PH4130CL,115 - NXP SEMICONDUCTORS

Important notice

Dear Customer,

On 7 February 2017 the former NXP Standard Product business became a new company with the

tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS

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1. Product proﬁle

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology.

1.2 Features

1.3 Applications

1.4 Quick reference data

2. Pinning information

PH4025L

N-channel TrenchMOS logic level FET

Rev. 01 — 22 August 2007 Product data sheet

nLogic level threshold nLead-free package

nOptimized for use in DC-to-DC

converters

nVery low switching and conduction

losses

n100 % RG tested n100 % ruggedness tested

nDC-to-DC converters nSwitched-mode power supplies

nVoltage regulators nPC Motherboards

nVDS ≤25 V nID≤99 A

nRDSon ≤4.0 mΩnQGD = 5 nC (typ)

Table 1. Pinning

Pin Description Simpliﬁed outline Symbol

1, 2, 3 source (S)

SOT669 (LFPAK)

4 gate (G)

mb mounting base; connected to drain (D)

1234

mbb076

Product data sheet Rev. 01 — 22 August 2007 2 of 12

NXP Semiconductors PH4025L

N-channel TrenchMOS logic level FET

3. Ordering information

4. Limiting values

Table 2. Ordering information

Type number Package

Name Description Version

PH4025L LFPAK plastic single-ended surface-mounted package (lfpak); 4 leads SOT669

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage 25 °C≤Tj≤150 °C - 25 V

VDGR drain-gate voltage (DC) 25 °C≤Tj≤150 °C; RGS =20kΩ-25V

VGS gate-source voltage - ±20 V

IDdrain current Tmb =25°C; VGS = 10 V; see Figure 2 and 3-99A

Tmb = 100 °C; VGS = 10 V; see Figure 2 - 67.5 A

IDM peak drain current Tmb =25°C; pulsed; tp≤10 µs; see Figure 3 - 300 A

Ptot total power dissipation Tmb =25°C; see Figure 1 - 46.4 W

Tstg storage temperature −55 +150 °C

Tjjunction temperature −55 +150 °C

Source-drain diode

ISsource current Tmb =25°C - 52 A

ISM peak source current Tmb =25°C; pulsed; tp≤10 µs - 208 A

Avalanche ruggedness

EDS(AL)S non-repetitive drain-source

avalanche energy unclamped inductive load; ID=56A;

tp= 0.16 ms; VDS ≤25 V; RGS =50Ω;

VGS = 10 V; starting at Tj=25°C

- 150 mJ

Product data sheet Rev. 01 — 22 August 2007 3 of 12

NXP Semiconductors PH4025L

N-channel TrenchMOS logic level FET

Fig 1. Normalized total power dissipation as a

function of mounting base temperature Fig 2. Normalized continuous drain current as a

function of mounting base temperature

Tmb =25°C

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

Tmb (°C)

0 20015050 100

003aab937

120

Pder

(%)

Tj (°C)

0 20015050 100

003aab555

120

Ider

(%)

Pder Ptot

Ptot 25°C()

------------------------100 %×=Ider ID

ID25°C()

-------------------- 100 %×=

003aab720

102

103

(A)

10−1

VDS (V)

10−1102

101

1 ms

Lim it RDSon = VDS/ID

10 ms

100 ms

100 µs

tp = 10 µs

Product data sheet Rev. 01 — 22 August 2007 4 of 12

NXP Semiconductors PH4025L

N-channel TrenchMOS logic level FET

5. Thermal characteristics

Table 4. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 --2K/W

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

Zth(j-mb)

(K/W)

003aab721

tp (s)

10−511010−1

10−2

10−410−3

10−1

10−2

tpT

δ =

single pulse

0.2

0.1

0.05

δ =0.5

0.02

Product data sheet Rev. 01 — 22 August 2007 5 of 12

NXP Semiconductors PH4025L

N-channel TrenchMOS logic level FET

6. Characteristics

Table 5. Characteristics

=25

C unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V(BR)DSS drain-source breakdown

voltage ID= 250 µA; VGS =0V

Tj=25°C 25--V

Tj=−55 °C 22.5 - - V

VGS(th) gate-source threshold voltage ID= 1 mA; VDS =V

GS; see Figure 9 and 10

Tj=25°C 1.3 1.7 2.15 V

Tj= 150 °C 0.8 - - V

Tj=−55 °C - - 2.6 V

IDSS drain leakage current VDS =25V; V

GS =0V

Tj=25°C --1µA

Tj= 150 °C - - 100 µA

IGSS gate leakage current VGS =±16 V; VDS = 0 V - - 100 nA

RGgate resistance f = 1 MHz - 0.48 - Ω

RDSon drain-source on-state

resistance VGS = 10 V; ID= 25 A; see Figure 6 and 8

Tj=25°C - 3.4 4.0 mΩ

Tj= 150 °C - 5.4 6.4 mΩ

VGS = 4.5 V; ID= 25 A; see Figure 6 and 8- 5.1 6.2 mΩ

Dynamic characteristics

QG(tot) total gate charge ID= 25 A; VDS =12V; V

GS = 4.5 V;

see Figure 11 and 12 - 21.3 - nC

QGS gate-source charge - 8.8 - nC

QGS1 pre-VGS(th) gate-source charge - 5.3 - nC

QGS2 post-VGS(th) gate-source charge - 3.4 - nC

QGD gate-drain charge - 5 - nC

VGS(pl) gate-source plateau voltage - 2.8 - V

QG(tot) total gate charge ID= 0 A; VDS =0V; V

GS = 4.5 V - 1.35 - nC

Ciss input capacitance VGS =0V; V

DS =12 V; f = 1 MHz;

see Figure 14 -2601-pF

Coss output capacitance - 645 - pF

Crss reverse transfer capacitance - 287 - pF

Ciss input capacitance VGS =0V; V

DS = 0 V; f = 1 MHz - 2973 - pF

td(on) turn-on delay time VDS =12 V; RL= 0.5 Ω; VGS = 4.5 V;

RG= 5.6 Ω- 28.3 - ns

trrise time -52-ns

td(off) turn-off delay time - 35 - ns

tffall time -24-ns

Source-drain diode

VSD source-drain voltage IS= 25 A; VGS = 0 V; see Figure 13 - 0.8 1.3 V

trr reverse recovery time IS= 25 A; dIS/dt = −100 A/µs; VGS =0V;

VR=20V -38-ns

Qrrecovered charge - 11 - nC

Product data sheet Rev. 01 — 22 August 2007 6 of 12

NXP Semiconductors PH4025L

N-channel TrenchMOS logic level FET

Tj=25°CT

j=25°C

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values Fig 6. Drain-source on-state resistance as a function

of drain current; typical values

Tj=25°C and 150 °C; VDS >I

D×RDSon

Fig 7. Transfer characteristics: drain current as a

function of gate-source voltage; typical values Fig 8. Normalized drain-source on-state resistance

factor as a function of junction temperature

VDS (V)

010.80.4 0.60.2

003aab722

(A)

VGS (V) = 10 4 3.5

2.5

4.5

ID (A)

0806020 40

003aab723

RDSon

(mΩ)

3.3

3.5

4.5

VGS (V) = 3

VGS (V)

04312

003aab724

(A)

VDS > ID × RDSon

Tj = 150 °C 25 °C

Tj (°C)

−60 180120060

003aab467

0.8

1.2

0.4

1.6

aRDSon

RDSon 25°C()

------------------------------

Product data sheet Rev. 01 — 22 August 2007 7 of 12

NXP Semiconductors PH4025L

N-channel TrenchMOS logic level FET

ID= 1 mA; VDS =V

GS Tj=25°C; VDS =5V

Fig 9. Gate-source threshold voltage as a function of

junction temperature Fig 10. Sub-threshold drain current as a function of

gate-source voltage

ID= 20 A; VDS =12V

Fig 11. Gate-source voltage as a function of gate

charge; typical values Fig 12. Gate charge waveform deﬁnitions

Tj (°C)

-60 180120060

003aab272

0.5

1.5

VGS(th)

(V)

max

typ

min

003aab938

VGS (V)

0321

10−4

10−5

10−2

10−3

10−1

(A)

10−6

maxtypmin

QG (nC)

05037.512.5 25

003aab725

VGS

(V)

VDS = 12 V

ID = 20 A

Tj = 25 °C

003aaa508

VGS

VGS(th)

QGS1 QGS2

QGD

VDS

QG(tot)

QGS

VGS(pl)

Product data sheet Rev. 01 — 22 August 2007 8 of 12

NXP Semiconductors PH4025L

N-channel TrenchMOS logic level FET

Tj=25°C and 150 °C; VGS =0V V

GS = 0 V; f = 1 MHz

Fig 13. Source current as a function of source-drain

voltage; typical values Fig 14. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

VSD (V)

0 1.20.90.3 0.6

003aab726

(A)

150 °C Tj = 25 °C

Tj (°C)

-60 180120060

003aab272

0.5

1.5

VGS(th)

(V)

max

typ

min

Product data sheet Rev. 01 — 22 August 2007 9 of 12

NXP Semiconductors PH4025L

N-channel TrenchMOS logic level FET

7. Package outline

Fig 15. Package outline SOT669 (LFPAK)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT669 MO-235 04-10-13

06-03-16

0 2.5 5 mm

scale

A2bcA e

UNIT

DIMENSIONS (mm are the original dimensions)

mm 1.10

0.95

0.15

0.00

1.20

1.01 0.50

0.35

4.41

3.62

2.2

2.0

0.9

0.7 0.25

0.19

0.30

0.24 4.10

3.80 6.2

5.8

1.3

0.8

0.85

0.40

1.3

0.8

8°

0°

D(1)

5.0

4.8

E(1)

3.3

3.1

E1(1)

D1(1)

max

0.25 4.20 1.27 0.25 0.1

1234

mounting

base

Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669

1/2 e

(A )

detail X

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

Product data sheet Rev. 01 — 22 August 2007 10 of 12

NXP Semiconductors PH4025L

N-channel TrenchMOS logic level FET

8. Revision history

Table 6. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PH4025L_1 20070822 Product data sheet - -

Product data sheet Rev. 01 — 22 August 2007 11 of 12

NXP Semiconductors PH4025L

N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

9.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

9.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

9.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

TrenchMOS — is a trademark of NXP B.V.

10. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PH4025L

N-channel TrenchMOS logic level FET

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 22 August 2007

Document identifier: PH4025L_1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

11. Contents

1 Product proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11

9.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

10 Contact information. . . . . . . . . . . . . . . . . . . . . 11

11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12