DESCRIPTION
The APS12205, APS12215, and APS12235 Hall-effect sensor
ICs are extremely temperature-stable and stress-resistant
devices especially suited for operation over extended junction
temperature ranges up to 175°C. Superior high-temperature
performance is made possible through dynamic offset
cancellation, which reduces the residual offset voltage normally
caused by device overmolding, temperature dependencies, and
thermal stress.
The single silicon chip includes: a Hall plate, small signal
amplifier, chopper stabilization, Schmitt trigger, and a short-
circuit-protected open-drain output. A south pole of sufficient
strength turns the output on; a north pole of sufficient strength
is necessary to turn the output off. For applications requiring
operation from greater than 5.5 V or operation directly from
a battery, refer to the A1220, A1221, or A1223.
Two package styles provide a choice of through-hole or surface
mounting. Package type LH is a modified 3-pin SOT23W
surface-mount package, while UA is a three-pin ultramini SIP
for through-hole mounting. Both packages are lead (Pb) free,
with 100% matte-tin-plated leadframes.
APS12205-15-35-DS, Rev. 4
MCO-0000479
FEATURES AND BENEFITS
• Optimized for applications with regulated power rails
□Operation from 2.8 to 5.5 V
• AEC-Q100 automotive qualified
• Operation up to 175°C junction temperature
• Dynamic offset cancellation
□Resistant to physical stress
□Superior temperature stability
• Symmetrical latch switchpoints
• Output short-circuit protection
• Solid-state reliability
• Industry-standard packages and pinouts
High-Temperature Hall-Effect Latches
for Low Voltage Applications
PACKAGES:
Functional Block Diagram
Not to scale
APS12205, APS12215,
and APS12235
3-pin SOT23W
(suffix LH)
3-pin SIP
(suffix UA)
June 18, 2019
GND
VCC
VOUT
Control
Current Limit
Dynamic Offset
Cancellation
Sample and Hold
To All Subcircuits
Amp
Low-Pass
Filter
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
RoHS
COMPLIANT
SELECTION GUIDE
Part Number Packing
[1] Mounting Branding Ambient, TABRP (Min) BOP (Max)
APS12205ELHALX 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A04 –40°C to 85°C
–40 G 40 G
APS12205ELHALT
[2] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A04
APS12205LLHALX 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A04
–40°C to 150°C
APS12205LLHALT
[2] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A04
APS12205LUAA Bulk, 500 pieces/bag 3-pin SIP through hole A18
APS12215LLHALX 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A01
–40°C to 150°C –90 G 90 G
APS12215LLHALT
[2] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A01
APS12215LUAA Bulk, 500 pieces/bag 3-pin SIP through hole A03
APS12235LLHALX 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A35
–40°C to 150°C –180 G 180 G
APS12235LLHALT
[2] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A35
APS12235LUAA Bulk, 500 pieces/bag 3-pin SIP through hole A36
[1] Contact Allegro for additional packing options.
[2] Available through authorized Allegro distributors only.
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Notes Rating Units
Forward Supply Voltage VCC 6 V
Reverse Supply Voltage VRCC –0.3 V
Output Off Voltage VOUT 6 V
Output Current IOUT Through short-circuit current limiting device. 60 mA
Maximum Junction Temperature TJ(max) 165 °C
For 1000 hours. 175 °C
Storage Temperature Tstg –65 to 170 °C
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
Terminal List
Name Description
Number
Package
LH
Package
UA
VCC Connects power supply to chip 1 1
VOUT Output from circuit 2 3
GND Ground 3 2
1
3
2
GND
VOUT
VCC
Package UA
Package LH
1
2
3
GND
VOUT
VCC
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ELECTRICAL CHARACTERISTICS: Valid over full operating voltage and ambient temperature range, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ.[1] Max. Unit
[2]
ELECTRICAL CHARACTERISTICS
Forward Supply Voltage VCC Operating, TJ < 175°C 2.8 – 5.5 V
Supply Current ICC VCC = 5.5 V – 2 4 mA
Output Leakage Current IOUTOFF VOUT = 5.5 V, B < BRP – – 10 µA
Output Saturation Voltage VOUT(SAT) IOUT = 5 mA, B > BOP – 50 500 mV
Output Current IOUT Recommended value used during characterization – 5 – mA
Output Short-Circuit Current Limit IOM B > BOP 30 – 60 mA
Power-On Time
[3] tON
VCC ≥ 2.8 V, B < BRP(min) – 10 G,
B > BOP(max) + 10 G – – 25 µs
Power-On State, Output
[3] POS VCC ≥ VCC(min), t < tON Low –
Chopping Frequency fC– 800 – kHz
Output Rise Time
[3][4] trRPULL-UP = 1 kΩ, CL = 20 pF – 0.2 2 µs
Output Fall Time
[3][4] tfRPULL-UP = 1 kΩ, CL = 20 pF – 0.1 2 µs
MAGNETIC CHARACTERISTICS
Operate Point BOP
APS12205 5 22 40 G
APS12215 15 50 90 G
APS12235 100 150 180 G
Release Point BRP
APS12205 –40 –22 –5 G
APS12215 –90 –50 –15 G
APS12235 –180 –150 –100 G
Hysteresis BHYS
APS12205
(BOP – BRP)
10 45 80 G
APS12215 30 100 180 G
APS12235 200 300 360 G
[1] Typical data are are at TA = 25°C and VCC = 5 V, and are for initial design estimations only.
[2] 1 G (gauss) = 0.1 mT (millitesla).
[3] Guaranteed by device design and characterization.
[4] CL = oscilloscope probe capacitance.
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions Value Units
Package Thermal Resistance RθJA
Package LH, 1-layer PCB with copper limited to solder pads 228 °C/W
Package LH, 2-layer PCB with 0.463 in.
2 of copper area each
side connected by thermal vias 110 °C/W
Package UA, 1-layer PCB with copper limited to solder pads 165 °C/W
2
3
4
5
6
25 45 65 85 105 125 145 165 185
Maximum Allowable VCC (V)
Temperature (°C)
Power Derating Curve
TJ(max) = 175°C; ICC = ICC(max), IOUT = 0 mA (Output Off)
VCC(max)
VCC(min)
Package UA, 1-layer PCB
(RθJA = 165 °C/W) (Center)
Package LH, 1-layer PCB
(RθJA = 228 °C/W) (Left)
Package LH, 2-layer PCB
(RθJA = 110 °C/W) (Right)
TJ(max)
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
20 40 60 80 100 120 140 160 180
Power Dissipation, PD(mW)
Temperature (°C)
Package Power Dissipation versus Ambient Temperature
Package LH, 2-layer PCB
(RθJA = 110°C/W)
Package UA, 1-layer PCB
(RθJA = 165°C/W)
Package LH, 1-layer PCB
(RθJA = 228°C/W)
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE
Electrical Characteristics
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-60 -40 -20 020 40 60 80 100 120 140 160
ICC (mA)
TA(°C)
Average Supply Current versus Ambient Temperature
2.8
5
5.5
VCC (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.5 33.5 44.5 55.5 6
ICC (mA)
VCC (V)
Average Supply Current versus Supply Voltage
-40
25
150
TA(°C)
0
50
100
150
200
250
300
350
400
450
500
-60 -40 -20 020 40 60 80 100 120 140 160
V
OUT(SAT)
(mV)
TA(°C)
Average Low Output Voltage versus Ambient Temperature for IOUT = 5 mA
2.8
5
5.5
VCC (V)
0
50
100
150
200
250
300
350
400
450
500
2.5 33.5 44.5 55.5 6
VOUT(SAT) (mV)
VCC (V)
Average Low Output Voltage versus Supply Voltage for IOUT = 5 mA
-40
25
150
TA(°C)
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE (continued)
APS12205 Magnetic Characteristics
5
10
15
20
25
30
35
40
-60 -40 -20 020 40 60 80 100 120 140 160
BOP (G)
TA(°C)
Average Operate Point versus Ambient Temperature
2.8
5
5.5
VCC (V)
5
10
15
20
25
30
35
40
2.5 33.5 44.5 55.5 6
BOP (G)
VCC (V)
Average Operate Point versus Supply Voltage
-40
25
150
TA(°C)
10
20
30
40
50
60
70
80
-60 -40 -20 020 40 60 80 100 120 140 160
BHYS (G)
TA(°C)
Average Switchpoint Hysteresis versus Ambient Temperature
2.8
5
5.5
VCC (V)
10
20
30
40
50
60
70
80
2.5 33.5 44.5 55.5 6
BHYS (G)
VCC (V)
Average Switchpoint Hysteresis versus Supply Voltage
-40
25
150
TA(°C)
-40
-35
-30
-25
-20
-15
-10
-5
-60 -40 -20 020 40 60 80 100 120 140 160
BRP (G)
TA(°C)
Average Release Point versus Ambient Temperature
2.8
5
5.5
VCC (V)
-40
-35
-30
-25
-20
-15
-10
-5
2.5 33.5 44.5 55.5 6
BRP (G)
VCC (V)
Average Release Point versus Supply Voltage
-40
25
150
TA(°C)
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE (continued)
APS12215 Magnetic Characteristics
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
-60 -40 -20 020 40 60 80 100 120 140 160
BOP (G)
Average Operate Point versus Ambient Temperature
2.8
5
5.5
VCC (V)
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
2.5 33.5 44.5 55.5 6
BOP (G)
VCC (V)
Average Operate Point versus Supply Voltage
-40
25
150
TA(°C)
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
-60 -40 -20 020 40 60 80 100 120 140 160
BHYS (G)
T
A
(°C)
Average Switchpoint Hysteresis versus Ambient Temperature
2.8
5
5.5
VCC (V)
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
2.5 33.5 44.5 55.5 6
BHYS (G)
VCC (V)
Average Switchpoint Hysteresis versus Supply Voltage
-40
25
150
TA(°C)
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-60 -40 -20 020 40 60 80 100 120 140 160
BRP (G)
Average Release Point versus Ambient Temperature
2.8
5
5.5
VCC (V)
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
2.5 33.5 44.5 55.5 6
BRP (G)
V
CC
(V)
Average Release Point versus Supply Voltage
-40
25
150
TA(°C)
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE (continued)
APS12235 Magnetic Characteristics
100
110
120
130
140
150
160
170
180
-60 -40 -20 020 40 60 80 100 120 140 160
BOP (G)
Average Operate Point versus Ambient Temperature
2.8
5
5.5
VCC (V)
100
110
120
130
140
150
160
170
180
2.5 33.5 44.5 55.5 6
BOP (G)
VCC (V)
Average Operate Point versus Supply Voltage
-40
25
150
TA(°C)
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
-60 -40 -20 020 40 60 80 100 120 140 160
BHYS (G)
T
A
(°C)
Average Switchpoint Hysteresis versus Ambient Temperature
2.8
5
5.5
VCC (V)
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
2.5 33.5 44.5 55.5 6
BHYS (G)
VCC (V)
Average Switchpoint Hysteresis versus Supply Voltage
-40
25
150
TA(°C)
-180
-170
-160
-150
-140
-130
-120
-110
-100
-60 -40 -20 020 40 60 80 100 120 140 160
BRP (G)
Average Release Point versus Ambient Temperature
2.8
5
5.5
VCC (V)
-180
-170
-160
-150
-140
-130
-120
-110
-100
2.5 33.5 44.5 55.5 6
BRP (G)
V
CC
(V)
Average Release Point versus Supply Voltage
-40
25
150
TA(°C)
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
10
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
OPERATION
The output of these devices switches low (turns on) when a mag-
netic field perpendicular to the Hall element exceeds the operate
point threshold, BOP (see Figure 1). After turn-on, the output volt-
age is VOUT(SAT)
. The output transistor is capable of continuously
sinking up to 30 mA. When the magnetic field is reduced below
the release point, BRP , the device output goes high (turns off).
The difference in the magnetic operate and release points is the
hysteresis, BHYS , of the device. This built-in hysteresis allows
clean switching of the output even in the presence of external
mechanical vibration and electrical noise.
Removal of the magnetic field will leave the device output
latched on if the last crossed switchpoint is BOP, or latched off if
the last crossed switch point is BRP.
POWER-ON BEHAVIOR
Device power-on occurs once tON has elapsed. During the
time prior to tON, and after VCC ≥ VCC(min), the output state is
VOUT(SAT) (Low). After tON has elapsed, the output will corre-
spond with the applied magnetic field for B > BOP or B < BRP.
See Figure 2 for an example.
Powering-on the device in the hysteresis range (less than BOP and
higher than BRP) will give an output state of VOUT(SAT). The cor-
rect state is attained after the first excursion beyond BOP or BRP
.
Figure 1: Switching Behavior of Latches
On the horizontal axis, the B+ direction indicates increasing
south polarity magnetic field strength, and the B– direction
indicates decreasing south polarity field strength (including the
case of increasing north polarity.
FUNCTIONAL DESCRIPTION
BOP
BRP
BHYS
VOUTOFF
VOUT
VOUT(SAT)
Switch to Low
Switch to High
B+
B–
V+
0
0
t
t
V
VCC(min)
tON
0
Output State
Undefined for
VCC
< VCC
(min) POS
VOUT(SAT )
VOUTOFF
V
VOUT
VCC
POS
B > BOP, BRP < B < BOP
B < BRP
Figure 2: Power-On Timing Diagram
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
11
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APPLICATIONS
It is strongly recommended that an external bypass capacitor be
connected (in close proximity to the Hall element) between the
supply and ground of the device to guarantee correct performance
under harsh environmental conditions and to reduce noise from
internal circuitry. As is shown in Figure 3, a 0.1 µF capacitor is
typical.
Extensive applications information on magnets and Hall-effect
sensors is available in:
• Hall-Effect IC Applications Guide, AN27701,
• Hall-Effect Devices: Guidelines for Designing Subassemblies
Using Hall-Effect Devices AN27703.1
• Soldering Methods for Allegro’s Products – SMD and
Through-Hole, AN26009
All are provided on the Allegro website:
www.allegromicro.com
CBYP
APS122xx
VOUT
GND
0.1 µF
VCC
Output
RPULL-UP
VS
Figure 3: Typical Application Circuit
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
12
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Amp
Clock/Logic
Hall Element
Sample and
Hold
Low-Pass
Filter
CHOPPER STABILIZATION
A limiting factor for switchpoint accuracy when using Hall-effect
technology is the small signal voltage developed across the Hall
plate. This voltage is proportionally small relative to the offset
that can be produced at the output of the Hall sensor. This makes
it difficult to process the signal and maintain an accurate, reliable
output over the specified temperature and voltage range. Chopper
stabilization is a proven approach used to minimize Hall offset.
The Allegro technique, dynamic quadrature offset cancellation,
removes key sources of the output drift induced by temperature
and package stress. This offset reduction technique is based on a
signal modulation-demodulation process. Figure 4 illustrates how
it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation. The
subsequent demodulation acts as a modulation process for the
offset, causing the magnetically induced signal to recover its orig-
inal spectrum at baseband while the DC offset becomes a high-
frequency signal. Then, using a low-pass filter, the signal passes
while the modulated DC offset is suppressed. Allegro’s innova-
tive chopper stabilization technique uses a high-frequency clock.
The high-frequency operation allows a greater sampling rate
that produces higher accuracy, reduced jitter, and faster signal
processing. Additionally, filtering is more effective and results in
a lower noise analog signal at the sensor output. Devices such as
the APS12205, APS12215, and APS12235 that use this approach
have an extremely stable quiescent Hall output voltage, are
immune to thermal stress, and have precise recoverability after
temperature cycling. This technique is made possible through the
use of a BiCMOS process which allows the use of low offset and
low noise amplifiers in combination with high-density logic and
sample-and-hold circuits.
Figure 4: Model of Chopper Stabilization
(Dynamic O󰀨set Cancellation)
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
13
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
POWER DERATING
The device must be operated below the maximum junction tem-
perature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems website.)
The Package Thermal Resistance, RθJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RθJC, is relatively
small component of RθJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
The resulting power dissipation capability directly reflects upon
the ability of the device to withstand extreme operating condi-
tions. The junction temperature mission profile specified in the
Absolute Maximum Ratings table designates a total operating life
capability based on qualification for the most extreme conditions,
where TJ may reach 175°C.
The silicon IC is heated internally when current is flowing into
the VCC terminal. When the output is on, current sinking into the
VOUT terminal generates additional heat. This may increase the
junction temperature, TJ, above the surrounding ambient tempe-
rature. The APS12205, APS12215, and APS12235 are permitted
to operate up to TJ = 175°C. As mentioned above, an operating
device will increase TJ according to equations 1, 2, and 3 below.
This allows an estimation of the maximum ambient operating
temperature.
PD = VIN × IIN (1)
ΔT = PD × RθJA (2)
TJ = TA + ΔT (3)
For example, given common conditions such as: TA= 25°C,
VCC = 5 V, ICC = 2.5 mA, VOUT = 185 mV, IOUT = 2 mA (output
on), and RθJA = 165°C/W, then:
PD = (VCC × ICC) + (VOUT × IOUT) =
(5 V × 2.5 mA) + (185 mV × 2 mA) =
12.5 mW + 0.4 mW = 12.9 mW
ΔT = PD × RθJA = 12.9 mW × 165°C/W = 2.1°C
TJ = TA + ΔT = 25°C + 2.1°C = 27.1°C
A worst-case estimate, PD(max), represents the maximum allow-
able power level (VCC(max), ICC(max)), without exceeding
TJ(max), at a selected RθJA.
For example, given the conditions RθJA = 228°C/W, TJ(max) =
175°C, VCC(max) = 5.5 V, ICC(max) = 4 mA, VOUT = 500 mV,
and IOUT = 5 mA (output on), the maximum allowable operating
ambient temperature can be determined.
The power dissipation required for the output is shown below:
PD(VOUT) = VOUT × IOUT = 500 mV × 5 mA = 2.5 mW
The power dissipation required for the IC supply is shown below:
PD(VCC) = VCC × ICC = 5.5 V × 4 mA = 22 mW
Next, by inverting using equation 2:
ΔT = PD × RθJA = [PD(VOUT) + PD(VCC)] × 228°C/W =
(2.5 mW + 22 mW) × 228°C/W =
24.5 mW × 228°C/W = 5.6°C
Finally, by inverting equation 3 with respect to voltage:
TA(est) = TJ(max) – ΔT = 175°C – 5.6°C = 169.4°C
In the above case there is only sufficient power dissipation
capability to operate up to TA(est). This particular result indicates
that, at TJ(max), the application and device can only dissipate
adequate amounts of heat at ambient temperatures ≤ TA(est);
the APS12205, APS12215, and APS12235 performance is not
guaranteed above TA = 150°C for the “L” temperature variant and
TA = 85°C for the “E” temperature variant.
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
14
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
0.55 REF
Gauge Plane
Seating Plane
0.25 BSC
0.95 BSC
0.95
1.00
0.70
2.40
2
1
AActive Area Depth, 0.28 ±0.04 mm
B
C
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Branding scale and appearance at supplier discretion
A
PCB Layout Reference View
Branded Face
CStandard Branding Reference View
APS12205ELHA and APS12205LLHA
1
A04
APS12215LLHA
1
A01
APS12235LLHA
1
A35
2.90 +0.10
–0.20
4°±4°
8 × 10° ±0.05
0.180+0.020
–0.053
0.05 +0.10
–0.05
0.25 MIN
1.91 +0.19
–0.06
2.98 +0.12
–0.08
1.00 ±0.13
0.40 ±0.10
For Reference Only; not for tooling use (reference DWG-0000628)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
DHall element, not to scale
D
D
D
1.49
0.96
3
Package LH, 3-Pin (SOT-23W)
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
15
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Package UA, 3-Pin SIP
2 31
1.27 NOM
1.02
MAX
45°
45°
C
1.52 ±0.05
B
A
E
E
1.44
2.04
E
Gate and tie bar burr area
A
B
C
Dambar removal protrusion (6×)
D
E
Active Area Depth, 0.50 ±0.08 mm
Branding scale and appearance at supplier discretion
Hall element (not to scale)
For Reference Only; not for tooling use (reference DWG-0000404, Rev. 1)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Mold Ejector
Pin Indent
DStandard Branding Reference View
A18
1
APS12205LUAA
A03
1
APS12215LUAA
A36
1
APS12235LUAA
0.41 +0.03
–0.06
0.43 +0.05
–0.07
14.99 ±0.25
4.09 +0.08
–0.05
3.02 +0.08
–0.05
0.79 REF
10°
Branded
Face
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
16
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Copyright 2019, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Number Date Description
– June 3, 2016 Initial release
1 June 20, 2016
Updated Functional Block Diagram (page 1);
Updated Selection Guide (page 2) and package outline drawing brand information (pages 14-
15).
2 September 23, 2016
Updated Title (all pages), Selection Guide (page 2), Absolute Maximum Ratings (page 2);
Electrical Characteristics (page 4); added Characteristic Performance Data (pages 6-9);
updated Functional Description (page 6), Chopper Stabilization (page 12), and Power
Derating sections (page 13).
3 July 5, 2018 Updated TJ(max) notes (page 2), Typical Application Circuit (page 11), Power Derating section
(page 13), Package Outline Drawings (pages 14-15), and other minor editorial updates.
4 June 18, 2019 Updated Selection Guide (page 2), Power Derating section (page 13), and Package Outline
Drawing branding (page 14).