Dual, Simultaneous Sampling, 16-Bit/14-Bit, 4 MSPS SAR ADCs, Differential Inputs AD7380/AD7381 Data Sheet FEATURES GENERAL DESCRIPTION 16-bit/14-bit ADC family Dual simultaneous sampling Fully differential analog inputs 4 MSPS throughput conversion rate SNR (typical) 92.5 dB, VREF = 3.3 V external at AD7380 (16-bit) 85.4 dB, VREF = 3.3 V external at AD7381 (14-bit) 101 dB with x16 OSR On-chip oversampling function Resolution boost function INL (maximum) 2.0 LSBs at 16-bit 1.0 LSB at 14-bit 2.5 V internal reference High speed serial interface -40C to +125C operation 16-lead LFCSP, 3 mm x 3 mm Wide common-mode range Alert function The AD7380/AD7381 are a 16-bit and 14-bit pin-compatible family of dual simultaneous sampling, high speed, low power, successive approximation register (SAR) analog-to-digital converters (ADCs) that operate from a 3.0 V to 3.6 V power supply and feature throughput rates up to 4 MSPS. The analog input type is differential, accepts a wide common-mode input voltage, and is sampled and converted on the falling edge of CS. An integrated on-chip oversampling block improves dynamic range and reduces noise at lower bandwidths. A buffered internal 2.5 V reference is included. Alternatively, an external reference up to 3.3 V can be used. APPLICATIONS PRODUCT HIGHLIGHTS Motor control position feedback Motor control current sense Sonar Power quality Data acquisition systems Erbium doped fiber amplifier (EDFA) applications I and Q demodulation 1. The conversion process and data acquisition use standard control inputs allowing simple interfacing to microprocessors or digital signal processors (DSPs). The device is compatible with 1.8 V, 2.5 V, and 3.3 V interfaces using the separate logic supply. The AD7380/AD7381 are available in a 16-lead lead frame chip scale package (LFCSP) with operation specified from -40C to +125C. Dual simultaneous sampling and conversion with two complete ADC functions. Pin-compatible product family. High 4 MSPS throughput rate. Space saving 3 mm x 3 mm LFCSP. An integrated oversampling block to increase dynamic range, reduce noise, and reduce SCLK speed requirements. Differential analog inputs with wide common-mode range. Small sampling capacitor reduces amplifier drive burden. 2. 3. 4. 5. 6. 7. FUNCTIONAL BLOCK DIAGRAM 3.3V (AINA+ AND AINA- ) VCC V REF V REF R C1 AINA+ R C2 AINA- C1 0V (AINB+ AND AINB- ) V REF SDOA REFIO GND 0V 1F OVERSAMPLING ADC A OSC REFCAP REGCAP V REF VLOGIC R C1 AINB+ R C2 AINB- REF CONTROL LOGIC LDO OVERSAMPLING ADC B C1 AD7380/AD7381 0V GND SCLK SDI CS DIGITAL CONTROLLER SDOB/ALERT 16871-001 0V 3.3V 1F Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7380/AD7381 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Resolution Boost ........................................................................ 20 Applications ....................................................................................... 1 Alert ............................................................................................. 20 General Description ......................................................................... 1 Power Modes ............................................................................... 21 Product Highlights ........................................................................... 1 Internal and External Reference ............................................... 21 Functional Block Diagram .............................................................. 1 Software Reset ............................................................................. 21 Revision History ............................................................................... 2 Diagnostic Self Test .................................................................... 21 Specifications..................................................................................... 3 Interface ........................................................................................... 22 Timing Specifications .................................................................. 6 Reading Conversion Results ..................................................... 22 Absolute Maximum Ratings............................................................ 8 Low Latency Readback .............................................................. 23 Thermal Resistance ...................................................................... 8 Reading from Device Registers ................................................ 24 ESD Caution .................................................................................. 8 Writing to Device Registers ...................................................... 24 Pin Configuration and Function Descriptions ............................. 9 CRC .............................................................................................. 25 Typical Performance Characteristics ........................................... 10 Registers ........................................................................................... 27 Terminology .................................................................................... 13 Addressing Registers .................................................................. 27 Theory of Operation ...................................................................... 14 CONFIGURATION1 Register ................................................. 28 Circuit Information .................................................................... 14 CONFIGURATION2 Register ................................................. 29 Converter Operation .................................................................. 14 ALERT Register .......................................................................... 29 Analog Input Structure .............................................................. 14 ALERT_LOW_THRESHOLD Register .................................. 30 ADC Transfer Function ............................................................. 15 ALERT_HIGH_THRESHOLD Register ................................. 30 Applications Information .............................................................. 16 Outline Dimensions ....................................................................... 31 Power Supply ............................................................................... 16 Ordering Guide .......................................................................... 31 Modes of Operation ....................................................................... 18 Oversampling .............................................................................. 18 REVISION HISTORY 11/2019--Rev. 0 to Rev. A Updated Title ..................................................................................... 1 Changes to Features Section, Applications Section, and Figure 1 ....................................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Aperture Delay Match Parameter, Table 3 and VREF Noise Parameter, Table 3 ......................................................... 5 Changes to Table 4 ............................................................................ 6 Change to Thermal Resistance Section ......................................... 8 Change to Pin 9 Description, Table 7 ............................................ 9 Changes to Figure 11 Caption....................................................... 10 Changes to Figure 15 Caption, Figure 18, Figure 19, and Figure 20 ................................................................................... 11 Changes to Terminology Section.................................................. 13 Change to ADC Transfer Function Section ................................ 15 Changes to Applications Information Section and Power Supply Section ..................................................................... 16 Added Table 9; Renumbered Sequentially .................................. 16 Changes to Figure 31 ...................................................................... 17 Changes to Normal Average Oversampling Section, Table 10, and Figure 32 .................................................................. 18 Changes to Rolling Average Oversampling Section and Figure 33................................................................................... 19 Changes to Resolution Boost Section .......................................... 20 Added Figure 36; Renumbered Sequentially .............................. 21 Change to Figure 37 and Table 12 ................................................ 22 Changes to Serial 2-Wire Mode Section, Resolution Boost Mode Section, Figure 38, and Figure 40 ...................................... 23 Changes to Figure 41 and Figure 42............................................. 24 Changes to Figure 43...................................................................... 26 Changes to Table 14 and Table 16 ................................................ 27 Change to CONFIGURATION1 Register Section and Table 17 .................................................................................... 28 Changes to CONFIGURATION2 Register Section and ALERT Register Section......................................................... 29 Changes to ALERT_LOW_THRESHOLD Register Section, Table 20, ALERT_HIGH_THRESHOLD Register Section, and Table 21 ................................................................................... 30 Changes to Ordering Guide .......................................................... 31 1/2019--Revision 0: Initial Version Rev. A | Page 2 of 31 Data Sheet AD7380/AD7381 SPECIFICATIONS VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, reference voltage (VREF) = 2.5 V internal, sampling frequency (fSAMPLE) = 4 MSPS, and TA = -40C to +125C, no oversampling enabled, unless otherwise noted. Table 1. AD7380 Parameter RESOLUTION THROUGHPUT Conversion Rate DC ACCURACY No Missing Codes Differential Nonlinearity (DNL) Error Integral Nonlinearity (INL) Error Gain Error Gain Error Temperature Drift Gain Error Match Zero Error Zero Error Drift Zero Error Matching AC ACCURACY Dynamic Range Oversampled Dynamic Range Signal-to-Noise Ratio (SNR) Test Conditions/Comments At 25C, VCC = 3.3 V Min 16 16 -1.0 -2.0 -0.015 -11 -0.01 -0.2 -0.5 -2 -0.5 Input frequency (fIN) = 1 kHz VREF = 3.3 V external Oversampling ratio (OSR) = 4 VREF = 3.3 V external 90 88.5 OSR = 8, RES = 1 OSR = 16, RES = 1 fIN = 100 kHz Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-(Noise + Distortion) (SINAD) fIN = 100 kHz VREF = 3.3 V external Channel to Channel Isolation POWER SUPPLIES VCC Current (IVCC) Normal Mode (Operational) Power Dissipation Total Power (PTOTAL) VCC Power (PVCC) Normal Mode (Operational) 1 89.5 88 Typ 0.7 0.75 0.002 1 0.002 0.01 0.5 0.1 Max Unit Bit 4 MSPS +1.0 +2.0 +0.015 +11 +0.01 +0.2 +0.5 +2 +0.5 Bits LSB LSB % FS1 ppm/C % FS mV mV V/C mV 93.3 91.8 95.2 92.5 91.1 98 101 89 -110 -113 -104 92.3 91 -110 dB dB dB dB dB dB dB dB dB dB dB dB dB dB 21.5 26 mA 83 107 mW 71 94 mW These specifications include full temperature range variation, but these specifications do not include the error contribution from the external reference. Rev. A | Page 3 of 31 AD7380/AD7381 Data Sheet VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V internal, fSAMPLE = 4 MSPS, and TA = -40C to +125C, no oversampling enabled, unless otherwise noted. Table 2. AD7381 Parameter RESOLUTION THROUGHPUT Conversion Rate DC ACCURACY No Missing Codes DNL Error INL Error Gain Error Gain Error Temperature Drift Gain Error Match Zero Error Zero Error Drift Zero Error Matching AC ACCURACY Dynamic Range Oversampled Dynamic Range SNR Test Conditions/Comments Min 14 14 -1.0 -1.0 -0.02 -20 -0.02 -2 +3 -1.5 0.5 0.3 0.002 1 0.002 0.25 0.5 0.25 Max Unit Bit 4 MSPS +1.0 +1.0 +0.02 +20 +0.02 +2 +3 +1.5 Bits LSB LSB % FS1 ppm/C % FS LSB V/C LSB fIN = 1 kHz OSR = 4 VREF = 3.3 V external SFDR OSR = 8, RES = 1 OSR = 16, RES = 1 fIN = 100 kHz VREF = 3.3 V THD VREF = 3.3 V 85 84.5 fIN = 100 kHz SINAD 84.5 84 Channel to Channel Isolation POWER SUPPLIES IVCC Normal Mode (Operational) Power Dissipation PTOTAL PVCC Normal Mode (Operational) 1 Typ 85.4 87 85.4 85 92.6 94.5 84.6 -108 -112 -107 -112 -101 85.3 84.9 -110 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 21.5 26 mA 83 107 mW 71 94 mW These specifications include full temperature range variation, but these specifications do not include the error contribution from the external reference. Rev. A | Page 4 of 31 Data Sheet AD7380/AD7381 Table 3. All Devices Parameter ANALOG INPUT Voltage Range Absolute Input Voltage Common-Mode Input Range Analog Input Common-Mode Rejection Ratio (CMRR) DC Leakage Current Input Capacitance SAMPLING DYNAMICS Input Bandwidth Aperture Delay Aperture Delay Match Aperture Jitter REFERENCE INPUT AND OUTPUT VREF Input Voltage Range VREF Input Current VREF Output Voltage VREF Temperature Coefficient VREF Line Regulation VREF Load Regulation VREF Noise DIGITAL INPUTS (SCLK, SDI, CS) Logic Levels Input Low Voltage (VIL) Input High Voltage (VIH) Input Low Current (IIL) Input High Current (IIH) DIGITAL OUTPUTS (SDOA, SDOB/ALERT) Output Coding Output Low Voltage (VOL) Output High Voltage (VOH) Test Conditions/Comments Min (AINx+) - (AINx-) AINx+, AINx- AINx+, AINx- -VREF -0.1 fIN = 500 kHz 0.2 to VREF - 0.2 -75 When in track mode When in hold mode 0.1 18 5 At -0.1 dB At -3 dB External reference External reference At 25C -40C to +125C 6 25 2 26 20 2.49 2.498 2.495 0.47 2.5 1 -38 -106 7 0.8 x VLOGIC -1 -1 Sink current (ISINK) = +300 A Source current (ISOURCE) = -300 A Max Unit +VREF VREF + 0.1 V V V dB 1 100 0.2 x VLOGIC V V A A +1 +1 VLOGIC - 0.3 3.0 3.2 1.65 MHz MHz ns ps ps V mA V V ppm/C ppm/V ppm/mA V rms Bits V V 1 A pF 3.3 3.3 3.6 3.6 3.6 V V V 2.3 100 2.8 200 mA A 10 3.5 10 200 3.7 200 nA mA nA 10 External reference = 3.3 V A pF pF 3.4 0.51 2.502 2.505 10 Twos complement 0.4 Floating State Leakage Current Floating State Output Capacitance POWER SUPPLIES VCC VLOGIC IVCC Normal Mode (Static) Shutdown Mode VLOGIC Current (IVLOGIC) Normal Mode (Static) Normal Mode (Operational) Shutdown Mode Typ SDOA and SDOB at 0x1FFF Rev. A | Page 5 of 31 AD7380/AD7381 Data Sheet Parameter Power Dissipation PVCC Normal Mode (Static) Shutdown Mode PVLOGIC Normal Mode (Static) Normal Mode (Operational) Shutdown Mode Test Conditions/Comments Min Typ Max Unit 7.6 330 10 720 mW W 33 11.5 33 720 13.3 720 nW mW nW SDOA and SDOB at 0x1FFF TIMING SPECIFICATIONS VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V internal, and TA = -40C to +125C, unless otherwise noted. Table 4.1, 2 Parameter tCYC tSCLKED Min 250 0.4 tSCLK tSCLKH tSCLKL tCSH 12.5 5 5 10 ns ns ns ns tQUIET tSDOEN 10 ns tSDOH Typ Max Unit ns ns Description Time between conversions CS falling edge to first SCLK falling edge SCLK period SCLK high time SCLK low time CS pulse width Interface quiet time prior to conversion CS low to SDOA and SDOB/ALERT enabled 5.5 8 ns ns ns VLOGIC 2.25 V 1.65 V VLOGIC < 2.25 V SCLK rising edge to SDOA and the SDOB/ALERT hold time 5.5 8 45 ns ns ns VLOGIC 2.25 V 1.65 V VLOGIC < 2.25 V CS rising edge to SDOA and the SDOB/ALERT high impedance ns ns ns 2 tSDOS SCLK rising edge to SDOA and the SDOB/ALERT setup time tSDOT tSDIS tSDIH tSCLKCS 1 1 0 tALERTC 12 ns SDI setup time prior to SCLK falling edge SDI hold time after SCLK falling edge SCLK rising edge to CS rising edge Conversion time Acquire time Valid time to start conversion after software reset (see Figure 36) Valid time to start conversion after soft reset Valid time to start conversion after hard reset Supply active to conversion First conversion allowed Settled to within 1% with internal reference Settled to within 1% with external reference Supply active to register read write access allowed Exiting power-down mode to conversion Settled to within 1% with internal reference Settled to within 1% with external reference Conversion start time for first sample in oversampling (OS) normal mode Conversion start time for xth sample in OS normal mode For AD7380 at 3 MSPS For AD7381 at 4 MSPS Time from CS to ALERT indication (see Figure 34) Time from CS to ALERT clear (see Figure 34) tCONVERT tACQUIRE tRESET 110 tALERTS_NOS 12 ns Time from internal conversion with exceeded threshold to ALERT indication (see Figure 34) 190 250 800 ns ns ns ns tPOWERUP tREGWRITE tSTARTUP tCONVERT02 tCONVERTx tALERTS 1 2 4 7 5 11 5 5 ms ms ms ms 11 10 10 ms s ns tCONVERT0 + (320 x (x - 1)) tCONVERT0 + (250 x (x - 1)) 200 ns ns ns All specifications are 10 pF load. Guaranteed by design. Rev. A | Page 6 of 31 Data Sheet AD7380/AD7381 tCYC tSCLKH tSCLK tSCLKED tCSH tSCLKL tQUIET tSCLKCS CS SDOA SDOB TRISTATE TRISTATE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DB15 DB14 DB13 DB12 DB11 DB10 DB 9 DB 8 DB 7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB15 DB14 DB13 DB12 DB11 DB10 DB 9 DB 8 DB 7 DB6 DB5 tSDOH DB4 DB3 tSDOS DB2 DB1 DB0 tSDOEN DB15 SDI DB14 DB13 DB12 DB11 DB10 DB9 DB8 tSDIS DB7 DB6 DB5 DB4 DB 3 TRISTATE TRISTATE tSDOT DB 2 DB 1 DB 0 16871-002 SCLK tSDIH Figure 2. Serial Interface Timing Diagram tCONVERT CS CONVERSION CONVERSION ACQUIRE 16871-003 ACQUIRE tACQUIRE Figure 3. Internal Conversion Acquire Timing tPOWERUP 16871-004 VCC CS Figure 4. Power-Up Time to Conversion tREGWRITE VCC SDI 16871-005 CS REG WRITE Figure 5. Power-Up Time to Register Read Write Access tSTARTUP SDI SHUTDOWN NORMAL POWERDOWN MODE NORMAL MODE ACCURATE CONVERSION 16871-006 CS Figure 6. Power-Down to Normal Mode Timing CS INTERNAL CONVERSION ACQUIRE CONVERSION ACQUIRE CONVERSION ACQUIRE CONVERSION ACQUIRE tCONVERT2 tCONVERT3 tCONVERT4 16871-007 tCONVERTx 1 1t CONVERTx STANDS FOR tCONVERT2, tCONVERT3, OR tCONVERT4 . Figure 7. Conversion Timing During OS Normal Mode Rev. A | Page 7 of 31 AD7380/AD7381 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter VCC to Ground (GND) VLOGIC to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Reference Input and Output (REFIO) Input to GND Input Current to Any Pin Except Supplies Operating Temperature Range Storage Temperature Range Junction Temperature Pb-Free Soldering Reflow Temperature Electrostatic Discharge (ESD) Ratings Human Body Model (HBM) Field Induced Charge Device Model (FICDM) Rating -0.3 V to +4 V -0.3 V to +4 V -0.3 V to VREF +0.3 V, VCC + 0.3 V, 4 V -0.3 V to VLOGIC + 0.3 V, 4 V -0.3 V to VLOGIC + 0.3 V, 4 V -0.3 V to VCC + 0.3 V, 4 V Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. Table 6. Thermal Resistance Package Type CP-16-451 10 mA -40C to +125C -65C to +150C 150C 260C 1 JA 55.4 JC 12.7 Unit C/W Test Condition 1: thermal impedance simulated values are based on JEDEC 2S2P thermal test board four thermal vias. See JEDEC JESD-51. ESD CAUTION 4 kV 1.25 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 8 of 31 Data Sheet AD7380/AD7381 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD7380/AD7381 13 SDOA 14 SDOB/ALERT 16 SCLK 15 SDI TOP VIEW (Not to Scale) GND 1 12 CS VLOGIC 2 11 REFIO 10 GND REGCAP 3 9 NOTES 1. EXPOSED PAD. FOR CORRECT OPERATION OF THE DEVICE, THE EXPOSED PAD MUST BE CONNECTED TO GROUND. 16871-008 AINA- 7 REFCAP AINA+ 8 AINB- 5 AINB+ 6 VCC 4 Figure 8. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1, 10 2 3 Mnemonic GND VLOGIC REGCAP 4 5, 6 7, 8 9 VCC AINB-, AINB+ AINA-, AINA+ REFCAP 11 REFIO 12 CS 13 SDOA 14 SDOB/ALERT 15 16 SDI SCLK EPAD Description Ground Reference Point. This pin is the ground reference point for all circuitry on the device. Logic Interface Supply Voltage, 1.65 V to 3.6 V. Decouple this pin to GND with a 1 F capacitor. Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this pin to GND with a 1 F capacitor. The voltage at this pin is 1.9 V typical. Power Supply Input Voltage, 3.0 V to 3.6 V. Decouple this pin to GND using a 1 F capacitor. Analog Inputs of ADC B. These analog inputs form a differential pair. Analog Inputs of ADC A. These analog inputs form a differential pair. Decoupling Capacitor Pin for Band Gap Reference. Decouple this pin to GND with a 0.1 F capacitor. The voltage at this pin is 2.5 V typical. Reference Input and Output. The on-chip reference of 2.5 V is available as an output on this pin for external use if the device is configured accordingly. Alternatively, an external reference of 2.5 V to 3.3 V can be input to this pin. Decoupling is required on this pin for both the internal and external reference options. A 1 F capacitor must be applied from this pin to GND. Chip Select Input. Active low, logic input. This input provides the dual function of initiating conversions on the AD7380 and the AD7381 and framing the serial data transfer. Serial Data Output A. This pin functions as a serial data output pin to access the ADC A or ADC B conversion results or data from any of the on-chip registers. Serial Data Output B/Alert Indication Output. This pin can operate as a serial data output pin or alert indication output. SDOB. This pin functions as a serial data output pin to access the ADC B conversion results. ALERT. This pin operates as an alert pin going low to indicate that a conversion result has exceeded a configured threshold. Serial Data Input. This input provides the data written to the on-chip control registers. Serial Clock Input. This serial clock input is for data transfers to and from the ADC. Exposed Pad. For correct operation of the device, the exposed pad must be connected to ground. Rev. A | Page 9 of 31 AD7380/AD7381 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VREF = 2.5 V internal, VCC = 3.6 V, VLOGIC = 3.3 V, fSAMPLE = 4 MSPS, fIN = 1 kHz, and TA = 25C, unless otherwise noted. 0 2.0 SNR = 90.92dB THD = -110.013dB SINAD = 90.86dB VREF = 2.5V INTERNAL -20 1.0 -60 DNL ERROR (LSB) -80 -100 -120 0.5 0 -0.5 -1.0 -140 -1.5 -160 32000 16871-112 2.0 0 SNR = 92.07dB THD = -104.40dB SINAD = 91.83dB VREF = 3.3V EXTERNAL -20 -40 1.5 1.0 INL ERROR (LSB) -60 -80 -100 -120 0.5 0 -0.5 100 8000 0 32000 80 CODE 16871-113 60 24000 40 FREQUENCY (kHz) 16000 20 -8000 0 -16000 -2.0 -180 -32000 -1.5 -160 -24000 -1.0 -140 16871-110 Figure 13. Typical INL Error Figure 10. FFT, VREF = 3.3 V External 1.0 0 SNR = 99.84dB THD = -104.45dB SINAD = 98.55dB VREF = 3.3V EXTERNAL ROLLING AVERAGE AT OSR = 8x RESOLUTION BOOST = ENABLED -40 0.8 0.6 LINEARITY ERROR (LSB) -20 -60 -80 -100 -120 -140 POSITIVE INL NEGATIVE INL 0.4 0.2 0 -0.2 -0.4 -0.6 -160 -180 0 20 40 60 80 FREQUENCY (kHz) 100 16871-111 -0.8 Figure 11. FFT with Oversampling, VREF = 3.3 V External -1.0 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C) Figure 14. Linearity Error vs. Temperature Rev. A | Page 10 of 31 110 125 16871-114 MAGNITUDE (dB) 0 CODE Figure 12. Typical DNL Error Figure 9. Fast Fourier Transform (FFT), VREF = 2.5 V Internal MAGNITUDE (dB) 24000 100 16000 80 8000 60 -8000 40 FREQUENCY (kHz) -16000 20 16871-109 0 -32000 -2.0 -180 -24000 MAGNITUDE (dB) -40 1.5 Data Sheet AD7380/AD7381 94.5 160000 146486 AINx + = AINx- = VREF / 2 262143 SAMPLES 140000 92.5 90.5 97997 80000 60000 88.5 EXTERNAL REFERENCE = 3.3V, R = 10 EXTERNAL REFERENCE = 3.3V, R = 33 EXTERNAL REFERENCE = 3.3V, R = 200 INTERNAL REFERENCE = 2.5V, R = 10 INTERNAL REFERENCE = 2.5V, R = 33 INTERNAL REFERENCE = 2.5V, R = 200 86.5 40000 84.5 20000 13558 -3 -2 -1 0 2 1 10 3 4 82.5 16871-115 4057 35 0 -4 5 CODE 1 100 1000 fIN (kHz) Figure 15. DC Histogram Codes at Code Center Figure 18. SNR vs. fIN (R Means Resistance) -70 -50 EXTERNAL REFERENCE = 3.3V INTERNAL REFERENCE = 2.5V EXTERNAL REFERENCE = 3.3V, R = 10 EXTERNAL REFERENCE = 3.3V, R = 33 EXTERNAL REFERENCE = 3.3V, R = 200 INTERNAL REFERENCE = 2.5V, R = 10 INTERNAL REFERENCE = 2.5V, R = 33 INTERNAL REFERENCE = 2.5V, R = 200 -60 -80 -70 THD (dB) -90 THD (dB) 10 16871-118 100000 SNR (dB) NUMBER OF HITS 120000 -100 -80 -90 -110 -100 -120 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) -120 1 10 100 1000 fIN (kHz) 16871-119 -25 16871-116 -130 -40 -110 Figure 19. THD vs. fIN Figure 16. THD vs. Temperature 94.5 98 EXTERNAL REFERENCE = 3.3V INTERNAL REFERENCE = 2.5V 96 92.5 94 90.5 SINAD (dB) 90 88 88.5 86.5 EXTERNAL REFERENCE = 3.3V, R = 10 EXTERNAL REFERENCE = 3.3V, R = 33 EXTERNAL REFERENCE = 3.3V, R = 200 INTERNAL REFERENCE = 2.5V, R = 10 INTERNAL REFERENCE = 2.5V, R = 33 INTERNAL REFERENCE = 2.5V, R = 200 84 84.5 82 80 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) 95 110 125 82.5 1 10 100 fIN (kHz) Figure 20. SINAD vs. fIN Figure 17. SNR vs. Temperature Rev. A | Page 11 of 31 1000 16871-120 86 16871-117 SNR (dB) 92 AD7380/AD7381 Data Sheet 106 50 104 IVCC (SINEWAVE INPUT) IVLOGIC (SINEWAVE INPUT) IVCC (POSITIVE FULL SCALE (PFS) INPUT) IVLOGIC (POSITIVE FULL SCALE (PFS) INPUT) 45 102 40 DYNAMIC CURRENT (mA) 100 98 94 92 90 NORMAL AVERAGE ROLLING AVERAGE NORMAL AVERAGE, RESOLUTION BOOST ENABLED ROLLING AVERAGE, RESOLUTION BOOST ENABLED 88 86 84 25 20 15 2 4 8 16 32 OVERSAMPLING RATIO 0 16871-121 0 Figure 21. SNR vs. Oversampling Ratio 0 1 2 3 4 THROUGHPUT RATE (MSPS) 16871-124 5 80 Figure 24. Dynamic Current at Different Input Signal vs. Throughput Rate 30 110 IVCC , INTERNAL REFERENCE = 2.5V IVCC , EXTERNAL REFERENCE = 3.3V 100 25 90 PSRR (dB) 20 15 80 70 10 60 5 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 40 100 Figure 22. Supply Current Dynamic vs.Temperature 1k 1k 100k 1M RIPPLE FREQUENCY (Hz) 16871-125 0 -40 50 16871-122 SUPPLY CURRENT DYNAMIC (mA) 30 10 82 Figure 25. Power Supply Rejection Ratio (PSRR) vs. Ripple Frequency 500 -40 450 -50 400 -60 350 CMRR (dB) 300 250 200 150 -70 -80 -90 100 -100 50 0 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C) 110 125 16871-123 SHUTDOWN CURRENT (A) 35 -110 100 1k 1k 100k RIPPLE FREQUENCY (Hz) Figure 26. CMRR vs. Ripple Frequency Figure 23. Shutdown Current vs. Temperature Rev. A | Page 12 of 31 1M 16871-126 SNR (dB) 96 Data Sheet AD7380/AD7381 TERMINOLOGY Differential Nonlinearity (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. DNL is often specified in terms of resolution for which no missing codes are guaranteed. Integral Nonlinearity (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Gain Error The first transition (from 100 ... 000 to 100 ... 001) occurs at a level 1/2 LSB above nominal negative full scale. The last transition (from 011 ... 110 to 011 ... 111) occurs for an analog voltage 11/2 LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Gain Error Temperature Drift The gain error drift is the gain error change due to a temperature change of 1C. Gain Error Match Gain error match is the difference in negative full-scale error between the input channels and the difference in positive fullscale error between the input channels. Zero Error Zero error is the difference between the ideal midscale voltage, 0 V, and the actual voltage producing the midscale output code, 0 LSB. Zero Error Drift The zero error drift is the zero error change due to a temperature change of 1C. Zero Error Matching Zero error matching is the difference in zero error between the input channels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels (dB). Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in dB, between the rms amplitude of the input signal and the peak spurious signal. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Signal-to-(Noise + Distortion) (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB. Analog Input Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of AINx+ and AINx- of frequency, f. CMRR (dB) = 10log(PADC_IN/PADC_OUT) where: PADC_IN is the common-mode power at the frequency, f, applied to the AINx+ and AINx- inputs. PADC_OUT is the power at the frequency, f, in the ADC output. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the falling edge of the CS input and when the input signal is held for a conversion. Aperture Delay Match Aperture delay match is the difference of the aperture delay between ADC A and ADC B. Aperture Jitter Aperture jitter is the variation in aperture delay. Rev. A | Page 13 of 31 AD7380/AD7381 Data Sheet THEORY OF OPERATION The AD7380/AD7381 are high speed, dual simultaneous sampling, fully differential 16-bit/14-bit, SAR ADCs. The AD7380/AD7381 operate from a 3.0 V to 3.6 V power supply and feature throughput rates up to 4 MSPS. The AD7380/AD7381 contain two SAR ADCs and a serial interface with two separate data output pins. The device is housed in a 16-lead LFCSP, offering the user considerable spacesaving advantages over alternative solutions. DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. The output impedances of the sources driving the AINX+ and AINX- pins must be matched. Otherwise, the two inputs have different settling times, resulting in errors. CAPACITIVE DAC Data is accessed from the device via the serial interface. The interface can operate with two or one serial outputs. The AD7380/AD7381 have an on-chip 2.5 V internal VREF. If an external reference is desired, the internal reference can be disabled, and a reference value ranging from 2.5 V to 3.3 V can be supplied. If the internal reference is used elsewhere in the system, buffer the reference output. The differential analog input range for the AD7380/AD7381 is the common-mode voltage (VCM) VREF/2. The AD7380/AD7381 feature an on-chip oversampling block to improve performance. Normal average and rolling average oversampling modes and power-down options that allow power saving between conversions are also available. Configuration of the device is implemented via the standard SPI (see the Interface section). CONVERTER OPERATION The AD7380/AD7381 have two SAR ADCs, each based around two capacitive digital-to-analog converters (DACs). Figure 27 and Figure 28 show simplified schematics of one of the ADCs in acquisition and conversion phases, respectively. The ADC comprises control logic, an SAR, and two capacitive DACs. In Figure 27 (the acquisition phase), SW3 is closed, SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor (CS) arrays can acquire the differential signal on the input. AINx- COMPARATOR CS B AINx+ A SW1 A SW2 B VREF CAPACITIVE DAC Figure 28. ADC Conversion Phase ANALOG INPUT STRUCTURE Figure 29 shows the equivalent circuit of the analog input structure of the AD7380/AD7381. The four diodes provide ESD protection for the analog inputs. Ensure that the analog input signals never exceed the supply rails by more than 300 mV. Exceeding the limit causes these diodes to become forward-biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the device. The C1 capacitors in Figure 29 are typically 3 pF and are primarily attributed to pin capacitance. The R1 resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 200 . The C2 capacitors are sampling capacitors of the ADC with a capacitance of 15 pF typically. VDD D AINx+ CAPACITIVE DAC CS B AINx+ AINx- SW2 C1 D COMPARATOR CS CONTROL LOGIC SW3 D AINx- B C1 R1 C2 D 16871-014 CAPACITIVE DAC 16871-012 VREF R1 C2 VDD A SW1 A CONTROL LOGIC SW3 CS 16871-013 CIRCUIT INFORMATION Figure 27. ADC Acquisition Phase When the ADC starts a conversion (see Figure 28), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected when the conversion begins. The control logic and charge redistribution Rev. A | Page 14 of 31 Figure 29. Equivalent Analog Input Circuit, Conversion Phase--Switches Open, Track Phase--Switches Closed Data Sheet AD7380/AD7381 ADC TRANSFER FUNCTION The conversion result is MSB first, twos complement. The LSB size is (2 x VREF)/2N, where N is the ADC resolution. The ADC resolution is determined by the resolution of the device chosen, and if resolution boost mode is enabled. Table 8 outlines the LSB size expressed in milivolts for different resolutions and reference voltages options. 011 ... 110 011 ... 101 100 ... 010 100 ... 001 100 ... 000 -FSR -FSR - 1LSB -FSR - 0.5LSB +FSR - 1LSB +FSR - 1.5LSB 16871-015 The ideal transfer characteristic for the AD7380/AD7381 is shown in Figure 30. 011 ... 111 ADC CODE (TWOS COMPLEMENT The AD7380/AD7381 can use a 2.5 V to 3.3 V VREF. The AD7380/AD7381 convert the differential voltage of the analog inputs (AINA+, AINA-, AINB+, and AINB-) into a digital output. Figure 30. ADC Ideal Transfer Function (FSR = Full-Scale Range) Table 8. LSB Size Resolution 14-bit 16-bit 18-bit Rev. A | Page 15 of 31 2.5 V Reference 305.2 76.3 19.1 3.3 V Reference 402.8 100.7 25.2 Unit V V V AD7380/AD7381 Data Sheet APPLICATIONS INFORMATION Figure 31 shows an example of a typical application circuit for the AD7380/AD7381. Decouple the VCC, VLOGIC, REGCAP, and REFIO pins with suitable decoupling capacitors as shown. The exposed pad is a ground reference point for circuitry on the device and must be connected to the board ground. Place a differential RC filter on the analog inputs to ensure optimal performance is achieved. On a typical application, it is recommended that R = 33 , C1 = 68 pF, and C2 = 330 pF. Figure 18 shows the SNR performance at different R values across the input frequency range. The performance of the AD7380/AD7381 devices may be impacted by noise on the digital interface. This impact depends on the on-board layout and design. Keep a minimal distance between the digital line and the digital interface, or place a 100 resistor in series and close to the SDOA pin and SDOB/ALERT pin to reduce noise from the digital interface coupling of the AD7380/AD7381. The two differential channels of the AD7380/AD7381 can accept an input voltage range from 0 V to VREF and has a wide common-mode range that allows the conversion of a variety of signals. These analog input pins can easily be driven with an amplifier. Table 9 lists the recommended driver amplifiers that best fit and add value to the application. The AD7380/AD7381 has an internal 2.5 V reference and can use an ultralow noise, high accuracy voltage reference as an external voltage source ranging from 2.5 V to 3.3 V such as the ADR4533 and ADR4525. POWER SUPPLY The typical application circuit in Figure 31 can be powered by a single 5 V (V+) voltage source that supplies the whole signal chain. The 5 V supply can come from a low noise, complementary metal-oxide semiconductor (CMOS) low dropout (LDO) regulator (ADP7105). The driver amplifier supply is provided by the+ 5 V (V+) and -2.5 V (V-), which is derived from the inverter, for example, the ADM660. The inverter then converts the +5 V to -5 V and supplies this voltage to the ADP7182 low noise voltage regulator to output the -2.5 V. The two independent supplies of the AD7380/AD7381, VCC and VLOGIC, that supply the analog circuitry and digital interface, respectively, can be supplied by a low quiescent current LDO regulator such as the ADP166. The ADP166 is a suitable supply with a fixed output voltage range from 1.2 V to 3.3 V for typical VCC and VLOGIC levels. Decouple both the VCC supply and the VLOGIC supply separately with a 1 F capacitor. Additionally, there is an internal LDO regulator that supplies the AD7380/AD7381. The on-chip regulator provides a 1.9 V supply for internal use on the device only. Decouple the REGCAP pin with a 1 F capacitor connected to GND. Power-Up The AD7380/AD7381 are robust to power supply sequencing. VCC and VLOGIC can be applied in any sequence. After VCC and VLOGIC are applied, an external reference must be applied. The AD7380/AD7381 require a tPOWERUP time from applying VCC and VLOGIC until the ADC conversion results are stable. Applying CS pulses, or interfacing with the AD7380/AD7381 prior to the setup time elapsing, does not have a negative impact on ADC operation. Conversion results are not guaranteed to meet data sheet specifications during this time, however, and must be ignored. Table 9. Signal Chain Components Companion Parts ADC Driver Part Name ADA4896-2 ADA4940-2 ADA4807-2 Description 1 nV/Hz, rail to rail output amplifier Ultralow power, full differential, low distortion 1 mA, rail-to-rail output amplifier Typical Application Precision, low noise, high frequency Precision, low density, low power Precision, low power, high frequency External Reference ADR4525 ADR4533 Ultralow noise, high accuracy 2.5 V voltage reference Ultralow noise, high accuracy 3.3 V voltage reference 2.5 V reference voltage 3.3 V reference voltage LDO Regulator ADP166 Low quiescent, 150 mA, LDO regulator 3.0 V to 3.6 V supply for VCC and VLOGIC ADP7104 Low noise, CMOS LDO regulator 5 V supply for driver amplifier ADP7182 Low noise line regulator -2.5 V supply for driver amplifier Rev. A | Page 16 of 31 Data Sheet AD7380/AD7381 V+ = 5V V+ VCM = REF/2 + - REF + - V+ LDO VREF = 2.5V TO 3.3V 10k LDO 3.0V TO 3.6V INVERTER 1.65V TO 3.6V 10k LDO 1F 1F V+ AINx+ - + V- = -2.5V C1 AINx- - + V- 1F C2 V+ VREF VCM 0V VLOGIC AD7380/AD7381 AINA- V- VCC REFIO AINA+ R SDI EXPOSED PAD R C1 SDOA SDOB/ALERT 100 100 DIGITAL HOST (MICROPROCESSOR/FPGA) SCLK CS AINB+ AINB- REGCAP REFCAP 1F GND 0.1F Figure 31. Typical Application Circuit Rev. A | Page 17 of 31 16871-016 VREF VCM 0V +5V TO -5V AD7380/AD7381 Data Sheet MODES OF OPERATION The AD7380/AD7381 have several on-chip configuration registers for controlling the operational mode of the device. OVERSAMPLING Oversampling is a common method used in analog electronics to improve the accuracy of the ADC result. Multiple samples of the analog input are captured and averaged to reduce the noise component from quantization noise and thermal noise (kTC) of the ADC. The AD7380/AD7381 offer an oversampling function on-chip and have two user configurable oversampling modes, normal average and rolling average. The oversampling functionality is configured by programming the OS_MODE bit and OSR bits in the CONFIGURATION1 register. Normal Average Oversampling Normal average oversampling mode can be used in applications where slower output data rates are allowable and where higher SNR or dynamic range is desirable. Normal average oversampling involves taking a number of samples, adding the samples together, and dividing the result by the number of samples taken. This result is then output from the device. The sample data is cleared after the process is completed. Normal average oversampling mode is configured by setting the OS_MODE bit to Logic 0 and having a valid nonzero value in the OSR bits. Writing to the OSR bits has a two cycle latency before the register gets updated. The oversampling ratio of the digital filter is controlled using the oversampling bits, OSR, which provides the oversampling bit decoding to select the different oversample rates. The output result is decimated to 16-bit resolution for the AD7380 and 14-bit resolution for the AD7381. If additional resolution is required, configure the resolution boost bit in the CONFIGURATION1 register. See the Resolution Boost section for further details. The number of samples, n, defined by the OSR bits are taken, added together, and the result is divided by n. The initial ADC conversion is initiated by the falling edge of CS, and the AD7380/AD7381 control all subsequent samples in the oversampling sequence internally. The sampling rate of the additional n samples is at 3 MSPS for the AD7380 and 4 MSPS for AD7381 in normal average oversampling mode. The oversampled conversion result is ready for read back on the next serial interface access. After the technique is applied, the sample data used in the calculation is discarded. This process is repeated every time the application needs a new conversion result and initiates at the falling edge of CS. As the output data rate is reduced by the oversampling ratio, the serial peripheral interface (SPI) SCLK frequency required to transmit the data is also reduced accordingly. Table 10. AD7380/AD7381 Normal Average Oversampling Performance Overview Oversampling Ratio Disabled 2 4 8 16 32 AD7380 SNR (dB typical) VREF = 2.5 V VREF = 3.3 V RES = 0 RES = 1 RES = 0 RES = 1 90.8 90.8 92.5 92.5 92.6 93.6 94.0 95.5 94.3 96.5 95.4 98.2 95.8 99.2 96.3 100.5 96.3 100.4 96.8 102.0 96.5 100.5 97.0 102.8 AD7381 SNR (dB typical) RES = 0 RES = 1 85.2 85.2 84.7 88 85.2 91.1 85.5 93 85.7 94.6 85.9 95.6 Output Data Rate (kSPS Maximum) 4000 1500 750 375 187.5 93.75 Output Data Rate (kSPS Maximum) 4000 2000 1000 500 250 125 CS S1 ACQ SDOA DON'T CARE SDOB/ALERT DON'T CARE S2 Sn ACQ S1 ACQ S2 Sn ACQ t0 RESULT t0 RESULT CONVERT START AT t1 Figure 32. Normal Average Oversampling Operation Rev. A | Page 18 of 31 16871-017 INTERNAL Data Sheet AD7380/AD7381 Rolling Average Oversampling In rolling average oversampling mode, all ADC conversions are controlled and initiated by the falling edge of CS. After a conversion is complete, the result is loaded into the FIFO. The FIFO length is 8, regardless of the oversampling ratio set. The FIFO is filled on the first conversion after a power-on reset, the first conversion after a software controlled hard or soft reset, or the first conversion after the REFSEL bit is toggled. A new conversion result is shifted into the FIFO on completion of every ADC conversion, regardless of the status of the OSR bits and the OS_MODE bit. This conversion allows a seamless transition from no oversampling to rolling average oversampling, or different rolling average oversampling ratios without waiting for the FIFO to fill. Rolling average oversampling mode can be used in applications where higher output data rates are required and where higher SNR or dynamic range is desirable. Rolling average oversampling involves taking a number of samples, adding the samples together, and dividing the result by the number of samples taken. This result is then output from the device. The sample data is not cleared after the process is completed. The rolling average oversampling mode uses a first in, first out (FIFO) buffer of the most recent samples in the averaging calculation, allowing the ADC throughput rate and output data rate to stay the same. Rolling average oversampling mode is configured by setting the OS_MODE bit to Logic 1 and having a valid nonzero value in the OSR bits. The oversampling ratio of the digital filter is controlled using the oversampling bits, OSR (see Table 11). The output result is decimated to 16-bit resolution for the AD7380 and 14-bit result for the AD7381. If additional resolution is required, this resolution can be achieved by configuring the resolution boost bit in the CONFIGURATION1 register. See the Resolution Boost section for further details. The number of samples, n, defined by the OSR bits are taken from the FIFO, added together, and the result is divided by n. The time between CS falling edges is the cycle time which can be controlled by the user, depending on the desired data output rate. Table 11. AD7380/AD7381 Rolling Averaging Oversampling Performance Overview AD7380 Oversampling Ratio Disabled 2 4 8 AD7381 SNR (dB typical) VREF = 2.5 V VREF = 3.3 V RES = 0 RES = 1 RES = 0 RES = 1 91 91 92.5 92.5 92 93 93.2 94.5 94 96 94.8 97.2 95.5 98.6 95.9 99.6 SNR (dB typical) RES = 0 RES = 1 85 85 84.5 87.7 85 91 85.5 93 Output Data Rate (kSPS Maximum) 4000 4000 4000 4000 Output Data Rate (kSPS Maximum) 4000 4000 4000 4000 VDD CS S1 ACQ SDI SDOA SDOB/ALERT S2 ACQ S3 ACQ S4 ACQ (FIFO1 + FIFO2 )/2 1 2 3 4 5 6 7 8 FIFO S1 - - - - - - - S1 1 2 3 4 5 6 7 8 ACQ S6 ACQ S7 ACQ ... ENABLE OS = 4 ENABLE OS = 2 DON'T CARE S5 (FIFO1 + FIFO2)/2 (FIFO1 + FIFO2)/2 (FIFO1 + FIFO2 + FIFO3 + FIFO4)/4 S2 FIFO S2 S1 - - - - - - 1 2 3 4 5 6 7 8 FIFO S3 S2 S1 - - - - - 1 2 3 4 5 6 7 8 FIFO S4 S3 S2 S1 - - - - 1 2 3 4 5 6 7 8 FIFO S5 S4 S3 S2 S1 - - - Figure 33. Rolling Average Oversampling Operation Rev. A | Page 19 of 31 1 2 3 4 5 6 7 8 FIFO S6 S5 S4 S3 S2 S1 - - 1 2 3 4 5 6 7 8 FIFO S7 S6 S5 S4 S3 S2 S1 - 16871-018 INTERNAL AD7380/AD7381 Data Sheet The register contains two status bits per ADC, one corresponding to the high limit, and the other to the low limit. A logical OR of alert signals for all ADCs creates a common alert value. This value can be configured to drive out on the ALERT function of the SDOB/ALERT pin. The SDOB/ALERT pin is configured as ALERT by configuring the following bits in the CONFIGURATION1 register and the CONFIGURATION2 register: RESOLUTION BOOST The default conversion result output data size for the AD7380 is 16 bits and for the AD7381 is 14 bits. When the on-chip oversampling function is enabled, the performance of the ADC can exceed the 16-bit level for the AD7380 or the 14-bit level for the AD7381. To accommodate the performance boost achievable, enable an additional two bits of resolution. If the RES bit in the CONFIGURATION1 register is set to Logic 1 and the AD7380/AD7381 are in a valid oversampling mode, the conversion result size for the AD7380 is 18 bits and for the AD7381 is 16 bits. In this mode, 18 SCLK cycles are required to propagate the data for the AD7380 and 16 SCLK cycles are required for the AD7381. Set the SDO bit to 1. Set the ALERT_EN bit to 1. In addition, set a valid value to the ALERT_HIGH_THRESHOLD register and the ALERT_LOW_THRESHOLD register. The alert indication function is available in oversampling, both rolling average and normal average, and in nonoversampling modes. ALERT The alert functionality is an out of range indicator and can be used as an early indicator of an out of bounds conversion result. An alert event triggers when the conversion result value register exceeds the alert high limit value in the ALERT_HIGH_ THRESHOLD register or falls below the alert low limit value in the ALERT_LOW_THRESHOLD register. The ALERT_HIGH_ THRESHOLD register and the ALERT_LOW_THRESHOLD register are common to all ADCs. When setting the threshold limits, the alert high threshold must always be greater than the alert low threshold. Detailed alert information is accessible in the ALERT register. The ALERT function of the SDOB/ALERT pin gets updated at the end of conversion. The alert indication status bits in the ALERT register get updated as well and must be read before the end of next conversion. The ALERT function of the SDOB/ALERT pin is cleared with a falling edge of CS. Issuing a software reset also clears the alert status in the ALERT register. tALERTS tALERTC CS SDOA NO OVERSAMPLING OR ROLLING AVARAGES OS INTERNAL CONV ACQ CONV ACQ CONV ACQ CONV ACQ ALERT EXCEEDS THRESHOLD CS SDOA NORMAL OVERSAMPLING INTERNAL C A C A C A C A C A C A C A C A C A C A C A C A C A C A C A C A EXCEEDS THRESHOLD tALERTS_NO Figure 34. Alert Operation Rev. A | Page 20 of 31 tALERTC 16871-019 ALERT Data Sheet AD7380/AD7381 POWER MODES The AD7380/AD7381 have two power modes that can be set in the CONFIGURATION1 register, normal mode and shutdown mode. These modes of operation provide flexible power management options, allowing optimization of the power dissipation and throughput rate ratio for different application requirements. Program the PMODE bit in the CONFIGURATION1 register to configure the power modes in the AD7380/AD7381. Set PMODE to Logic 0 for normal mode and Logic 1 for shutdown mode. Normal Mode Keep the AD7380/AD7381 in normal mode to achieve the fastest throughput rate. All blocks within the AD7380/AD7381 remain fully powered at all times, and an ADC conversion can be initiated by a falling edge of CS, when required. When the AD7380/AD7381 are not converting, the devices are in static mode, and power consumption is automatically reduced. Additional current is required to perform a conversion. Therefore, power consumption on the AD7380/AD7381 scales with throughput. Shutdown Mode When slower throughput rates and lower power consumption are required, use shutdown mode by either powering down the ADC between each conversion or by performing a series of conversions at a high throughput rate and then powering down the ADC for a relatively long duration between these burst conversions. When the AD7380/AD7381 are in shutdown mode, all analog circuitry powers down, including the internal reference, if enabled. The serial interface remains active during shutdown mode to allow the AD7380/AD7381 to exit shutdown mode. To enter shutdown mode, write to the PMODE bit in the CONFIGURATION1 register. The AD7380/AD7381 shuts down and current consumption reduces. To exit shutdown mode and return to normal mode, set the PMODE bit in the CONFIGURATION1 register to Logic 0. All register configuration settings remain unchanged entering or leaving shutdown mode. After exiting shutdown mode, allow sufficient time for the circuitry to turn on before starting a conversion. If the internal reference is enabled, allow the reference to settle for accurate conversions to happen. INTERNAL AND EXTERNAL REFERENCE The AD7380/AD7381 have a 2.5 V internal reference. Alternatively, if a more accurate reference or higher dynamic range is required, an external reference can be supplied. An externally supplied reference can be in the range of 2.5 V to 3.3 V. Reference selection, internal/external, is configured by the REFSEL bit in the CONFIGURATION1 register. If REFSEL is set to 0, the internal reference buffer is enabled. If an external reference is preferred, the REFSEL bit must be set to 1, and an external reference must be supplied to the REFIO pin. SOFTWARE RESET The AD7380/AD7381 have two reset modes, a soft reset and a hard reset. A reset is initiated by writing to the RESET bits, Bits[7:0], in the CONFIGURATION2 register. A soft reset maintains the contents of the configurable registers but refreshes the interface and the ADC blocks. Any internal state machines are reinitialized, and the oversampling block and FIFO are flushed. The ALERT register is cleared. The reference and LDO remain powered. A hard reset, in addition to the blocks reset by a soft reset, resets all user registers to the default status, resets the reference buffer, and resets the internal oscillator block. DIAGNOSTIC SELF TEST The AD7380/AD7381 run a diagnostic self test after a power-on reset (POR) or after a software hard reset to ensure correct configuration is loaded into the device. The result of the self test is displayed in the SETUP_F bit in the ALERT register. If the SETUP_F bit is set to Logic 1, the diagnostic self test fails. If the test fails, perform a software hard reset to reset the AD7380/AD7381 registers to the default status. tSTARTUP SDI SHUTDOWN NORMAL POWER-DOWN MODE NORMAL MODE ACCURATE CONVERSION Figure 35. Shutdown Mode Operation tRESET SDI SOFTWARE RESET Figure 36. Software Reset Operation Rev. A | Page 21 of 31 16871-136 CS 16871-020 CS AD7380/AD7381 Data Sheet INTERFACE The interface to the AD7380/AD7381 is via the SPI. The interface consists of a CS, SCLK, SDOA, SDOB/ALERT, and SDI pins. READING CONVERSION RESULTS The CS signal initiates the conversion process. A high to low transition on the CS signal initiates a simultaneous conversion of both ADCs, ADC A and ADC B. The AD7380/AD7381 have one cycle readback latency. Therefore, the conversion results are available on the next SPI access. Then, take the CS signal low, and the conversion result clocks out on the serial output pins. The next conversion also initiates at this point. The CS signal frames a serial data transfer and initiates an ADC conversion process. The falling edge of CS puts the track-andhold into hold mode, at which point, the analog input is sampled, and the bus is taken out of three-state. The SCLK signal synchronizes data in and out of the device via the SDOA, SDOB, and SDI signals. A minimum of 16 SCLK cycles are required for a write to or read from a register. The minimum numbers of SCLK pulses for a conversion read is dependent on the resolution of the device and the configuration settings, see Table 12. The conversion result shifts out of the device as a 16-bit result for the AD7380 and a 14-bit result for the AD7381. The MSB of the conversion result shifts out on the CS falling edge. The remaining data shifts out of the device under the control of the SCLK input. The data shifts out on the rising edge of the SCLK, and the data bits are valid on both the falling edge and the rising edge. After the final SCLK falling edge, take CS high again to return the SDOA and the SDOB/ALERT pins to a high impedance state. The ADC conversion operation is driven internally by an on-board oscillator and is independent of the SCLK signal. The AD7380/AD7381 have two serial output signals, SDOA and SDOB. To achieve the highest throughput of the device, use both SDOA and SDOB, 2-wire mode, to read the conversion results. If a reduced throughput is required or oversampling is used, it is possible to use 1-wire mode, SDOA signal only, for reading conversion results. Programming the SDO bit in the CONFIGURATION2 register configures 2-wire or 1-wire mode. The number of SCLK cycles to propagate the conversion results on the SDOA and the SDOB/ALERT pins is dependent on the serial mode of operation configured and if resolution boost mode is enabled, see Figure 37 and Table 12 for details. If CRC reading is enabled, this requires additional SCLK pulses to propagate the CRC information, see the CRC section for more details. Configuring the cyclic redundancy check (CRC) operation for SPI reads or SPI writes alters the operation of the interface. The relevant sections of this data sheet must be consulted to ensure correct operation. As the CS signal initiates a conversion, as well as framing the data, any data access must be completed within a single frame. CS 1 SDOA SDOB/ALERT 2 3 n-2 n-1 n1 CONVERSION RESULT 1 CONSULT TABLE 11 FOR n, THE NUMBER OF SCLK PULSES REQUIRED 16871-021 SCLK Figure 37. Reading Conversion Result Table 12. Number of SCLKs, n, Required for Reading Conversion Results Interface Configuration 2-Wire Resolution Boost Mode Disabled Enabled 1-Wire Disabled Enabled CRC Read Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Rev. A | Page 22 of 31 AD7380 16 24 18 26 32 40 36 44 Number of SCLK Pulses AD7381 14 22 16 24 28 36 32 40 Data Sheet AD7380/AD7381 Serial 2-Wire Mode performance. To accommodate the performance boost achievable, enable an additional two bits of resolution in the conversion output data. If the RES bit in the CONFIGURATION1 register is set to Logic 1 and the AD7380/AD7381 are in a valid oversampling mode, the conversion result size for the AD7380 is 18 bit and for the AD7381 is 16 bit. Configure 2-wire mode by setting the SDO bit in the CONFIGURATION2 register to 0. In 2-wire mode, the conversion result for ADC A is output on the SDOA pin, and the conversion result for ADC B is output on the SDOB/ALERT pin (see Figure 38). When the resolution boost mode is enabled, 18 SCLK cycles are required for the AD7380 and 16 SCLK cycles are required for the AD7381 to propagate the data. Serial 1-Wire Mode In applications where slower throughput rates are allowed, or normal average oversampling is used, the serial interface can operate in 1-wire mode. In 1-wire mode, the conversion results from ADC A and ADC B are output on the serial output, SDOA. Additional SCLK cycles are required to propagate all data. The ADC A data is output first, followed by the ADC B conversion results (see Figure 39). LOW LATENCY READBACK The interface on the AD7380/AD7381 has one cycle latency, as shown in Figure 40. For applications that operate at lower throughput rates, the latency of reading the conversion result can be reduced. When the conversion time elapses, tCONVERT, a second CS pulse after the initial CS pulse that initiates the conversion can readback the conversion result. This operation is shown in Figure 40. Resolution Boost Mode The default resolution and output data size for the AD7380 is 16 bits and for the AD7381 is 14 bits. Enabling the on-chip oversampling function reduces noise and improves the device S1 S0 S2 S3 SDOA DON'T CARE ADC A S0 ADC A S 1 SDOB/ALERT DON'T CARE ADC B S0 ADC B S 1 NOP NOP NOP SDI 16871-022 CS Figure 38. Reading Conversion Results for 2-Wire Mode S1 S0 S2 S3 SDOA SDI DON'T CARE NOP ADC A S0 ADC B S 0 NOP ADC A S 1 ADC B S 1 NOP 16871-023 CS Figure 39. Read Conversion Results for 1-Wire Mode CS SDOA SDOB/ALERT CNVn DON'T CARE ACQ CNV n+1 DON'T CARE ACQ RESULTn+1 RESULTn SCLK TARGET SAMPLE PERIOD Figure 40. Low Throughput Low Latency Rev. A | Page 23 of 31 16871-024 INTERNAL AD7380/AD7381 Data Sheet READING FROM DEVICE REGISTERS WRITING TO DEVICE REGISTERS All registers in the device can be read over the SPI. A register read is performed by issuing a register read command followed by an additional SPI command that can be either a valid command or no operation (NOP) command. The format for a read command is shown in Table 15. Bit D15 must be set to 0 to select a read command. Bits[D14:D12] contain the register address, and the subsequent twelve bits, Bits[D11:D0], are ignored. All the read and write registers in the AD7380/AD7381 can be written to over the SPI. The length of an SPI write access is determined by the CRC write function. An SPI access is 16 bit if CRC write is disabled and is 24 bit when CRC write is enabled. The format for a write command is shown in Table 15. Bit D15 must be set to 1 to select a write command. Bits[D14:D12] contain the register address, and the subsequent twelve bits, Bits[D11:D0], contain the data to be written to the selected register. S0 S1 S2 S3 S4 NOP READ REG 1 READ REG 2 NOP NOP SDOA INVALID RESULT S0 REG 1DATA REG 2DATA RESULT S3 SDOB/ALERT INVALID RESULT S0 SDI RESULT S3 Figure 41. Register Read S1 S0 S2 S3 SDI SDOA SDOB/ALERT NOP WRITE REG 1 WRITE REG 2 NOP INVALID RESULT S0 RESULT S1 RESULT S2 Figure 42. Register Write Rev. A | Page 24 of 31 16871-026 CS 16871-025 CS Data Sheet AD7380/AD7381 CRC CRC Polynomial The AD7380/AD7381 have CRC checksum modes that can be used to improve interface robustness by detecting errors in data transmissions. The CRC feature is independently selectable for SPI interface reads and SPI interface writes. For example, the CRC function for SPI writes can prevent unexpected changes to the device configuration but disabled on SPI reads, therefore maintaining a higher throughput rate. The CRC feature is controlled by the programming of the CRC_W and CRC_R bits in the CONFIGURATION1 register. For CRC checksum calculations, the following polynomial is always used: x8 + x2 + x + 1 CRC Read If enabled, a CRC is appended to the conversion result or register reads and consists of an 8-bit word. The CRC is calculated in the conversion result for ADC A and ADC B and is output on SDOA. A CRC is also calculated and appended to register read outputs. To generate the checksum, the 16-bit data conversion result of the two channels are combined to produce 32-bit data. The 8 MSBs of the 32-bit data are inverted and then left shifted by eight bits to create a number ending in eight logic zeros. The polynomial is aligned such that the MSB is adjacent to the leftmost Logic 1 of the data. An exclusive or (XOR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned such that the MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process repeats until the original data is reduced to a value less than the polynomial, which is the 8-bit checksum. The polynomial for this example is 100000111. CRC Write Let the original data of two channels be 0xAAAA and 0x5555, that is, 1010 1010 1010 1010 and 0101 0101 0101 0101. The data of the two channels is appended including eight zeros on the right, and then becomes 1010 1010 1010 1010 0101 0101 0101 0101 0000 0000. To enable the CRC write function, the CRC_W bit in the CONFIGURATION1 register must be set to 1. To set the CRC_W bit to 1 to enable the CRC feature, the request frame must have a valid CRC appended to the frame. Table 13 shows the CRC calculation of 16-bit two-channel data. In the final XOR operation, the reduced data is less than the polynomial. Therefore, the remainder is the CRC for the assumed data. After the CRC feature is enabled, all register write requests are ignored unless accompanied by a valid CRC command, requiring a valid CRC to both enable and disable the CRC write feature. The same process is followed for the AD7381, but instead of dealing with 32-bit data (combined result of two channels), it is 28-bit data. For reading data such as the registers, CRC computation is based on a 16-bit register data, and the same process is performed as described for a 32-bit data. The CRC read function can be used in 2-wire SPI mode, 1-wire SPI mode, and resolution boost mode. Rev. A | Page 25 of 31 AD7380/AD7381 Data Sheet Table 13. Example CRC Calculation for 2 16-Bit Data Data 1 0 1 0 1 Process Data 0 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x x x x x x x x 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 1 0 0 CRC 16 + 8 = 24 BITS 2-WIRE 16-BIT SDOA RESULT_A SDOB/ ALERT RESULT_B SDOA RESULT_A CRCA,B 16 + 16 + 8 = 40 BITS 1-WIRE 16-BIT RESULT_B CRC A,B 16 + 8 = 26 BITS 2-WIRE 18-BIT SDOA RESULT_A SDOB/ ALERT RESULT_B CRCA,B 18 + 18 + 8 = 44 BITS 1-WIRE 18-BIT SDOA RESULT_A RESULT_B CRC A,B 16 + 8 = 24 BITS REGISTER READ RESULT SDOA REGISTER X CRC REG X 16 + 8 = 24 BITS SDI REGISTER X CRC REG X 16 + 8 = 24 BITS REGISTER WRITE SDI WRITE REGISTER X CRC REG X Figure 43. CRC Operation Rev. A | Page 26 of 31 16871-027 REGISTER READ REQUEST 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 Data Sheet AD7380/AD7381 REGISTERS The AD7380/AD7381 have user programmable on-chip registers for configuring the device. Table 14 shows a complete overview of the registers available on the AD7380/AD7381. The registers are either read/write (R/W) or read only (R). Any read request to a write only register is ignored. Any write request to a read only register is ignored. Writes to any other register address are considered an NOP and are ignored. Any read request to a register address, other than those listed in Table 14, are considered an NOP, and the data transmitted in the next SPI frame are the conversion results. Table 14. Register Summary Hex. No. 0x1 Register Name CONFIGURATION1 Bits [15:8] [7:0] 0x2 CONFIGURATION2 [15:8] [7:0] 0x3 ALERT Bit 15 Bit 7 OSR[1:0] 0x5 ALERT_HIGH_THRESHOLD Bit 12 Bit 4 Bit 11 Bit 10 Bit 3 Bit 2 RESERVED ALERT_EN RES CRC_R Bit 9 Bit 1 OS_MODE REFSEL Bit 8 Bit 0 OSR[2] PMODE Reset 0x0000 R/W R/W SDO 0x0000 R/W 0x0000 R ALERT_LOW[11:8] 0x0800 R/W ALERT_HIGH[11:8] 0x07FF R/W RESERVED RESET [15:8] ALERT_LOW_THRESHOLD Bit 13 Bit 5 ADDRESSING CRC_W ADDRESSING ADDRESSING [7:0] 0x4 Bit 14 Bit 6 RESERVED AL_B_HIGH [15:8] [7:0] ADDRESSING [15:8] [7:0] ADDRESSING AL_B_LOW RESERVED CRCW_F SETUP_F RESERVED AL_A_HIGH AL_A_LOW ALERT_LOW[7:0] ALERT_HIGH[7:0] ADDRESSING REGISTERS A serial register transfer on the AD7380/AD7381 consists of 16 SCLK cycles. The four MSBs written to the device are decoded to determine which register is addressed. The four MSBs consist of the register address (REGADDR), Bits[2:0], and the read/write bit (WR). The register address bits determine which on-chip register is selected. The read/write bit determines if the remaining 12 bits of data on the SDI input are loaded into the addressed register, if the addressed register is a valid write register. If the WR bit is 1, the bits load into the register addressed by the register select bits. If the WR bit is 0, the command is seen as a read request. The addressed register data is available to be read during the next read operation. Table 15. Addressing Register Format MSB D15 WR D14 D13 D12 REGADDR[2:0] D11 D10 D9 D8 D7 D6 D5 DATA[11:0] D4 D3 D2 D1 LSB D0 Table 16. Bit Descriptions for Addressing Registers Bit D15 Mnemonic WR D14 to D12 REGADDR D11 to D0 DATA[11:0] Description If a 1 is written to this bit, Bits[D11:D0] of this register are written to the register specified by REGADDR, if it is a valid address. Alternatively, if a 0 is written, the next data sent out on the SDOA pin is a read from the designated register, if it is a valid address. When WR = 1, the contents of REGADDR determine the register for selection as outlined in Table 14. When WR = 0, and REGADDR contains a valid register address, the contents on the requested register are output on the SDOA pin during the next interface access. When WR = 0, and REGADDR contains 0x0, 0x6, or 0x7, the contents on the SDI line are ignored. The next interface access results in the conversion results being read back. These bits are written into the corresponding register specified by the REGADDR bits when the WR bit is equal to 1 and the REGADDR bits contain a valid address. Rev. A | Page 27 of 31 AD7380/AD7381 Data Sheet CONFIGURATION1 REGISTER Address: 0x1, Reset: 0x0000, Name: CONFIGURATION1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [15:12] ADDRESSING (R/W) Addressing [0] PMODE (R/W) Power-Down Mode. [11:10] RESERVED [1] REFSEL (R/W) Reference Select. [9] OS_MODE (R/W) Oversampling Mode. [2] RES (R/W) Resolution. [8:6] OSR (R/W) Oversampling Ratio. [3] ALERT_EN (R/W) Enable Alert Indicator Function. [5] CRC_W (R/W) CRC Write. [4] CRC_R (R/W) CRC Read. Table 17. Bit Descriptions for CONFIGURATION1 Bits [15:12] Bit Name ADDRESSING [11:10] 9 RESERVED OS_MODE [8:6] OSR 5 CRC_W 4 CRC_R 3 ALERT_EN 2 RES 1 REFSEL 0 PMODE Description Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers section for further details. Reserved. Oversampling Mode. Sets the oversampling mode of the ADC. 0: normal average. 1: rolling average. Oversampling Ratio. Sets the oversampling ratio for all the ADCs in the relevant mode. Normal average mode supports oversampling ratios of x2, x4, x8, x16, and x32. Rolling average mode supports oversampling ratios of x2, x4, and x8. 000: disabled. 001: 2x. 010: 4x. 011: 8x. 100: 16x. 101: 32x. 110: disabled. 111: disabled. CRC Write. Controls the CRC functionality for the SDI interface. When setting this bit from a 0 to a 1, the command must be followed by a valid CRC to set this configuration bit. If a valid CRC is not received, the entire frame is ignored. If the bit is set to 1, it requires a CRC to clear it to 0. 0: no CRC function. 1: CRC function. CRC Read. Controls the CRC functionality for the SDOA and SDOB/ALERT interface. 0: no CRC function. 1: CRC function. Enable Alert Indicator Function. This register functions when the SDO bit = 1. Otherwise, the ALERT_EN bit is ignored. 0: SDOB. 1: ALERT. Resolution. Sets the size of the conversion result data. If OSR = 0, these bits are ignored, and the resolution is set to default resolution. 0: normal resolution. 1: 2-bit higher resolution. Reference Select. Selects the ADC reference source. 0: selects internal reference. 1: selects external reference. Power-Down Mode. Sets the power modes. 0: normal mode. 1: power-down mode. Rev. A | Page 28 of 31 Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet AD7380/AD7381 CONFIGURATION2 REGISTER Address: 0x2, Reset: 0x0000, Name: CONFIGURATION2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [15:12] ADDRESSING (R/W) Addressing [7:0] RESET (R/W) Reset [11:9] RESERVED [8] SDO (R/W) SDO Table 18. Bit Descriptions for CONFIGURATION2 Bits [15:12] Bit Name ADDRESSING [11:9] 8 RESERVED SDO [7:0] RESET Description Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers section for further details. Reserved. SDO. Conversion results serial data output. 0: 2-wire, conversion data are output on both the SDOA and SDOB/ALERT pins. 1: 1-wire, conversion data are output on the SDOA pin only. Reset. Set to 0x3C to perform a soft reset, which refreshes some block and register contents remain unchanged. Clears ALERT register and flushes any oversampling stored variables or active state machine. Set to 0xFF to perform a hard reset, which resets all possible blocks in the device. Register contents are set to defaults. All other values are ignored. Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 R/W Reset 0x0 Access R 0x0 0x0 R R 0x0 R 0x0 R ALERT REGISTER Address: 0x3, Reset: 0x0000, Name: ALERT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [15:12] ADDRESSING (R) Addressing [0] AL_A_LOW (R) Alert A Low [11:10] RESERVED [1] AL_A_HIGH (R) Alert A High [9] CRCW_F (R) CRC Error [3:2] RESERVED [8] SETUP_F (R) Load Error [4] AL_B_LOW (R) Alert B Low [7:6] RESERVED [5] AL_B_HIGH (R) Alert B High Table 19. Bit Descriptions for ALERT Bits [15:12] Bit Name ADDRESSING [11:10] 9 RESERVED CRCW_F 8 SETUP_F [7:6] RESERVED Description Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers section for further details. Reserved. CRC Error. Indicates that a register write command failed due to a CRC error. This fault bit is sticky and remains set until the register is read. 0: no CRC error. 1: CRC error. Load Error. The SETUP_F bit indicates that the device configuration data did not load correctly on startup. This bit does not clear on an ALERT register read. A hard reset via the CONFIGURATION2 register is required to clear this bit and restart the device setup again. 0: no setup error. 1: setup error. Reserved. Rev. A | Page 29 of 31 AD7380/AD7381 Bits 5 Bit Name AL_B_HIGH 4 AL_B_LOW [3:2] 1 RESERVED AL_A_HIGH 0 AL_A_LOW Data Sheet Description Alert B High. The alert indication high bits indicate if a conversion result for the respective input channel exceeds the value set in the ALERT_HIGH_THRESHOLD register. This fault bit is sticky and remains set until the register is read. 0: no alert indication. 1: alert indication. Alert B Low. The alert indication low bits indicate if a conversion result for the respective input channel exceeds the value set in the ALERT_LOW_THRESHOLD register. This fault bit is sticky and remains set until the register is read. 0: no alert indication. 1: alert indication. Reserved. Alert A High. The alert indication high bits indicate if a conversion result for the respective input channel exceeds the value set in the ALERT_HIGH_THRESHOLD register. This fault bit is sticky and remains set until the register is read. 0: no alert indication. 1: alert indication. Alert A Low. The alert indication low bits indicate if a conversion result for the respective input channel exceeds the value set in the ALERT_LOW_THRESHOLD register. This fault bit is sticky and remains set until the register is read. 0: no alert indication. 1: alert indication. Reset 0x0 Access R 0x0 R 0x0 0x0 R R 0x0 R Reset 0x0 Access R/W 0x800 R/W Reset 0x0 Access R/W 0x7FF R/W ALERT_LOW_THRESHOLD REGISTER Address: 0x4, Reset: 0x0800, Name: ALERT_LOW_THRESHOLD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 [15:12] ADDRESSING (R/W) Addressing [11:0] ALERT_LOW (R/W) Alert Low Table 20. Bit Descriptions for ALERT_LOW_THRESHOLD Bits [15:12] Bit Name ADDRESSING [11:0] ALERT_LOW Description Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers section for further details. Alert Low. Data Bits[D11:D0] are the MSBs of the 16-bit internal alert low register. The remaining 4 bits are fixed at 0x0, which sets an alert when the conversion result is below the ALERT_LOW_THRESHOLD and disables when the conversion result is above the ALERT_LOW_THRESHOLD. ALERT_HIGH_THRESHOLD REGISTER Address: 0x5, Reset: 0x07FF, Name: ALERT_HIGH_THRESHOLD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 [15:12] ADDRESSING (R/W) Addressing [11:0] ALERT_HIGH (R/W) Alert High Table 21. Bit Descriptions for ALERT_HIGH_THRESHOLD Bits [15:12] Bit Name ADDRESSING [11:0] ALERT_HIGH Description Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers section for further details. Alert High. Data Bits[D11:D0] are the MSBs of the 16-bit internal ALERT_HIGH register. The remaining bits are fixed at 0xF, which sets an alert when the converter result is above the ALERT_HIGH_THRESHOLD and disables when the converter result is below the ALERT_HIGH_THRESHOLD. Rev. A | Page 30 of 31 Data Sheet AD7380/AD7381 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 P IN 1 IN D IC AT O R AR E A OP T IO N S (SEE DETAIL A) 16 13 12 1 0.50 BSC EXPOSED ED PAD 1.10 SQ 1.00 9 0.45 0.40 0.35 TOP VIEW 0.80 0.75 0.70 PKG-005000 4 5 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.15 REF SEATING PLANE 0.45 *1.20 0.55 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 08-29-2018-A PIN 1 INDICATOR AREA 3.10 3.00 SQ 2.90 *COMPLIANT TO JEDEC STANDARDS MO-220-WEED-4 WITH EXCEPTION TO THE EXPOSED PAD Figure 44. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-16-45) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 AD7380BCPZ-RL AD7380BCPZ-RL7 AD7380BCPZ-R2 AD7381BCPZ-RL AD7381BCPZ-RL7 EVAL-AD7380FMCZ EVAL-AD7381FMCZ 1 2 Resolution (Bit) 16 16 16 14 14 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP AD7380 Evaluation Board AD7381 Evaluation Board Package Option CP-16-45 CP-16-45 CP-16-45 CP-16-45 CP-16-45 Z = RoHS Compliant Part. The EVAL-AD7380FMCZ and the EVAL-AD7381FMCZ are compatible with the EVAL-SDP-CH1Z high speed controller board. (c)2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16871-0-11/19(A) Rev. A | Page 31 of 31 Marking Code C95 C95 C95 C93 C93