M34C02-RMN6TG - STMicroelectronics, Inc.

1/28August 2004

M34C02

2 Kbit Serial I²C Bus EEPROM

For DIMM Serial Presence Detec t

FEATURES SUMMARY

■Software Data Protection for lower 128 Bytes

■Two Wire I2C Se rial Interface

■100kHz and 400kHz Transfer Rat es

■Sin gle Supply Vo ltage:

– 2.5 t o 5.5V up to 400kHz for M34C02-W

– 2.2 t o 5.5V up to 400kHz for M34C02-L

– 1.8 t o 5.5V up to 100kHz for M34C02-R

– 1.7 t o 3.6V up to 100kHz for M34C02-F

■BYTE and P AG E WR ITE (up to 16 bytes)

■RANDOM and SEQ UENTIAL READ Modes

■Self-Timed Programming Cycle

■Automatic Address Incrementing

■Enh anced ESD/ Latch -Up Protection

■More than 1 Million Erase/Write Cycles

■More than 40 Yea r Data Retention

Table 1. Product List

Figure 1. Packages

Reference Part Number

M34C02

M34C02-W

M34C02-L

M34C02-R

M34C02-F

PDIP8 (BN)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

TSSOP8 (DS)

3x3mm² body size (MSO P)

UFDFPN8 (MB)

2x3mm² (MLP)

M34C02

2/28

TABLE OF CONTENTS

FEATUR ES SUMM ARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMM ARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. DIP, SO, TSSOP and MLP Conne ctions (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Power On Reset: VCC Lock-Out Write Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Serial Data (SDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chip Enable (E0, E1, E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. Maximum RL Value versus Bus Capacitance (CBUS ) for an I2C Bus . . . . . . . . . . . . . . . 5

Figure 5. I2C Bus Pro tocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Device Select Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Acknowledge B it (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Memo ry Add ressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. Setting the Write Protection Register (WC = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Setting the Software Write-Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 7. Result of Setting the Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 8. Write Mode Sequenc es in a Non Write-Protected Area . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Byte W rite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 9. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Minim izing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 10.Read M ode S equences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

R andom Add ress Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

C urre nt Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

USE WITHIN A DRAM DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3/28

M34C02

Programming the M34C02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. DRA M DIMM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 11.Serial Presence Detect Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Table 7. Operating Conditions (M34C02-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. Operating Conditions (M34C02-L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 9. Operating Conditions (M34C02-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 10. Op erating Conditions (M3 4C02-F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 11. AC Measurem ent Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 12. Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 13. DC Characteristics (M34C02-W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 14. DC Characteristics (M34C02-L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 15. DC Characteristics (M34C02-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 16. DC Characteristics (M34C02-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 17. AC Characteristics (M34C02 -W, M34C02-L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 18. AC Characteristics (M34C02 -R, M34C02-F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13.AC Wavefo rms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 14.P DIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outlin e . . . . . . . . . . . . . . . . . 21

Table 19. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package M echanical Data. . . . . . . . . . 21

Figure 15.S O8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 22

Table 20. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Mechan ical Data . . . . 22

Figure 16.UFDFPN8 (MLP8) 8-lead Ultra thin Fi ne pitch Dual Flat Package No lead 2x3mm ², Outline

Table 21. UF DFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data.

Figure 17.TSS OP 8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 24

Table 22. TSS OP8 – 8 lead Thin Shrink Sma ll Outline, Packag e Mechani cal Data . . . . . . . . . . . . 24

Figure 18.TSS OP 8 3x3m m² – 8 lead Thin Shrink Small Outline, 3x3mm ² body size, Outline . . . . 25

Table 23. TSS OP8 3x 3m m² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Data . . . . . . 25

PAR T NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 25. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7

M34C02

4/28

S UM MARY DESCRIP TION

The M34C02 is a 2Kbit serial EEPROM memory

able to lock permanently the data in its first half

(from location 00h to 7Fh). This facility has been

designed specifically for use in DRAM DIMMs (du-

al interli ne m emory modules) wi th Serial Presence

Detect. All the information concerning the DRAM

module configuration (such as its access speed,

its size, its organization) c an be kept write protect-

ed in the f irst half o f the memory.

This bottom half of the memory area can be write-

protected using a specially designed software

write protection mechanism. By sending the de-

vice a specific sequence, the first 128 Bytes of the

memory become permanently write protected.

Care must be t aken when using t his sequence as

its effect cannot be reversed. In addition, the de-

vice allows t he entire memory area to be write pro-

tected, using the W C input (for example by tieing

this input to V CC).

These I2C-compatible electrically erasable pro-

grammabl e memor y (EEPROM) devices are orga-

nized as 256x8 bit s.

Figure 2. Logic Diagram

I2C uses a two wire seria l interface, comprising a

bi-directional data line and a clock line. The device

carries a built-in 4-bit Device Type Identifier code

(1010) in accordance with the I2C bus definition to

access the memory area and a second Device

Type Identifier Code (0110) to access the Protec-

tion Register. These codes are used together wi th

three chip enabl e i nputs (E2, E1, E0) so that up to

eight 2Kbit devices m ay be attached to t he I²C bus

and selected individu ally.

The device behaves as a slave device in the I2C

protocol, with all memory operations sy nc hronized

by the serial clock. Read and Write operations are

initiated by a START cond ition, generated by the

bus master. T he START condition is followed by a

Device Select Code and RW bit (as described in

Table 3.), terminated by an acknowledge bit.

When w riting data to the memory , the mem ory in-

serts an acknowledge bit during the 9th bit time,

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledg es the receipt of the data byte

in t he same way. Data transfers are terminated by

a STOP c ondition after an Ack for WRITE, and af -

ter a NoAck for READ.

Figure 3. DI P, SO, TSSO P and MLP

Connections (To p View)

Not e: See PACKAGE MECHANICAL section for package dimen-

si ons, and how to i dentify pi n-1.

Table 2. Signal Names

Power On Reset: VCC Lock-Out Write Protec t

In order to prevent data corruption and inadvertent

Write operations during power up, a Power On Re-

set (POR) circuit is included. The intern al reset is

held active unt il VCC has reached the POR thresh-

old value, and all operations are disabled – the de-

vice will not respond to any command. In the same

way, when VCC drops from the operat ing voltage,

below the POR threshold value, all operations are

disabled and the device will not respond to any

command.

A stable and valid VCC (as defined in Table 7. to

Table 10.) must be applied before applying any

logic signal.

AI01931

E0-E2 SDA

VCC

M34C02

SCL

VSS

E0, E1, E2 Chip Enable

SDA Serial Data

SCL Serial Clock

WC Write Control

VCC Supply Volta ge

VSS Ground

SDAVSS SCL

WCE1

E0 VCC

AI01932C

M34C02

5/28

M34C02

SIGNAL DESCRIPTION

Serial Clock (SCL)

This input signal is u sed to strobe all data in and

out of the device. In applications where this signal

is used by slave devices to synchronize the bus to

a slower clock, the bus master must have an open

drain output, and a pull-up resistor can be con-

nected from Serial Clock (SCL) t o VCC. (Figure 4.

indicates how the valu e of the pull-up resist or can

be calculated). In most applications, though, this

method of synchronization is not employed, and

so the pull-up resistor is not necessary, provided

that the bus master has a push-pull (rather than

open drain) output.

Serial Data (SDA)

This bi-directional signal is used t o trans fer dat a i n

or out of the device. It is an open drain out put that

may be wi re-OR’ed with ot her op en drai n or open

collector signals on the bus. A pull up resistor must

be connected from Ser ial Data (SDA) to VCC. (Fig-

ure 4. indicates how the value of the pull-up resis-

tor can be cal culated).

Chip Enable (E0, E1, E2)

These input signals are used to set the value that

is to be looked f or on the three least signi ficant bits

(b3, b2, b1) of t he 7-bit Device Select Code. These

inputs mus t be tied t o VCC or VSS to e stablish the

Device Select Code.

Write Control (WC)

This input signal is provided for protecting the con-

tents of the whole memory from inadvertent write

operations. Write Control ( WC) is used to enable

(when driven Low) or disable (when driven High)

write instructions to the entire memory area or to

the P ro tect io n Regis ter.

When Write Control (WC) i s tied Low or left uncon-

nected, the write protection of the first half of the

memory is determined by t he status of the Protec-

ti on Regi ster.

Figure 4. Maximum RL Value versu s Bus Capacitance (CBUS) for an I2C Bus

AI01665

VCC

CBUS

SDA

MASTER

SCL CBUS

100

CBUS (pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc = 100kHz

M34C02

6/28

Figure 5. I2C Bus Protocol

Table 3. Device Select Code

Note: 1. The most significant bit, b7, is sent first.

2. E0 , E 1 and E2 are com pared against the respe ct i ve exte rnal pins on the memo ry device .

Device Type Identifier1Chip Enable Address2RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory Area Select

Code (two arrays) 1010E2E1E0RW

Protection Register

Select Code 0110E2E1E0RW

SCL

SDA

SCL

SDA

START

Condition

SDA

Input SDA

Change

AI00792B

STOP

Condition

123 789

MSB ACK

START

Condition

SCL 123 789

MSB ACK

STOP

Condition

7/28

M34C02

DEVICE OPERATION

The device supports the I2C protocol. T hi s i s sum -

mari ze d in Figure 5.. Any device that sends data

on to the bus is defined to be a transmitter, and

any device that reads the data to be a receiver.

The device that controls the data transfer is known

as the bus master, and the other as the slave de-

vice. A data transfer can only be initiated by the

bus master, which will also provide t he serial clock

for synchronization. The memory device is always

a slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data

(SDA) while Serial Clock (SCL) is stable in the

High state. A Start condition must precede any

data transfer command. The device continuously

monitors (except durin g a Write cycle) Serial Data

(SDA) and Serial Cloc k (SCL) for a Start condition,

and will not re spond unles s one is given.

Stop Condition

Stop is identified by a rising edge of Serial Data

(SDA) while Serial Clock (SCL) is stable and driv-

en High. A Stop condition terminat es comm unica-

tion between the device and the bus master. A

Read command that is followed by NoAc k can be

followed by a Stop condition to force the device

into the Stand-by mode. A Stop condition at the

end of a W rite command triggers the internal EE-

P R OM Write cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used t o indicate a success-

ful byte transfer. The bus transmitter, whether it be

bus master or slave device, releases Serial Data

(SDA) after sending eight bits of data. During the

9th clock pulse period, the receiver pulls Serial

Data (SDA) Low to acknowledge the receipt of the

eight data bits.

Data Input

During data input, the device samples Serial Data

(SDA) on the rising edge of Serial Clock (SCL).

For correct device operation, Serial Data (SDA)

must be stable during the rising edge of Serial

Clock (SCL), and the Serial Data (SDA) signal

must change only when Serial Clock (S CL) i s driv-

en Low.

Memory Addressing

To start communication between the bus master

and the slave device, the bus maste r must initiate

a Start condition. Following this, the bus master

sends the Device Select Code, shown in Table 3.

(on Serial Data (SDA ), most significant bit first).

The Device Select Code consists of a 4-bit Devi ce

Type Identifier, and a 3-bit Chip Enable “Add ress”

(E2, E1, E0). To address the memory array, t he 4-

bit Device Type Identifier is 1010b; to address the

Protection Register, it is 0110b.

Up to eight memory devices can be connec ted on

a single I 2C bus. Eac h one is given a unique 3-bit

code on the Chip Enable (E0, E1, E2) inputs.

When the Device Select Code i s received, the de-

vice only responds if the Chip Enable Address is

the same as the value on the Chip Enable ( E0, E1,

E2 ) in pu ts .

The 8th bit is the Read/Write bit (RW). This bit is

set to 1 fo r Read and 0 fo r Write operations.

If a match occurs on the Device Select code, the

corresponding device gives an acknowledgment

on Serial Data (SD A) du ring the 9 th bit time. If the

device does not match the Device Select code, it

deselects itself from the bus, and goes into Stand-

by mode.

Table 4. O peratin g Modes

No te: 1. X = VIH or VIL.

Mode RW bit WC 1 Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW = 1

Random Address Read 0X1START, Device Select, RW = 0, Address

1 X reSTART, Device Select, RW = 1

Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read

Byte Write 0 VIL 1 START, Device Select, RW = 0

Page Write 0 VIL ≤ 16 START, Device Select, RW = 0

M34C02

8/28

Figure 6. Setting the Write Protection Register (WC = 0)

Setting the Software Write-Protection

The M34C02 has a hardware write-protection fea-

ture, using the Write Contr ol (WC) signal. This sig-

nal can be driven High or Low, and must be held

constant for the whole instruction sequence.

When Write Control (WC) is held Low, the whole

memory array (addresses 00h to FFh) is write pro-

tected. When Wri te Control (WC) i s held High, the

write protection of the memory ar ray is dependent

on whether software write-protection has been

set.

Software write-protection allows the bottom half of

the memory area (addresses 00h to 7Fh) to be

permanently write protected irrespective of subse-

quent states of the Write Control (WC) signal.

The write protection feature is activated by writing

once to the Protection Register. The Protection

set to 0110b (as shown in Table 3.), and the E2,

E1 and E0 bits set according to the states being

applied on the E2, E1 and E0 signals. As for any

other write command, Write Control (WC) needs to

be held Low. Address and data bytes must be sent

with this command, but their values are all ignored,

and are treated as Don’t Care. Once the Protec-

tion Register has been writt en, the write protecti on

of the first 128 Bytes of the memory is enabled,

and it is not possible to unprotect these 128 Bytes,

even if the de vice is po wered off and on, and re-

gardless the state of Wri te Control (WC ).

When the Protection Register has been written,

the M34C02 no longer responds to the device type

identifier 0110b in either read or write mode.

Figu re 7. Re sult of Setti ng the Write P rot ection

START

SDA LINE

AI01935B

ACK

WORD

ADDRESS

VALUE

(DON'T CARE)

ACK

DATA

VALUE

(DON'T CARE)

STOP

ACK

CONTROL

BYTE

BUS ACTIVITY

MASTER

BUS ACTIVITY

Default EEPROM memory area

state before write access

to the Protect Register

AI01936C

Standard

Array

FFh

Standard

Array

80h

7Fh

00h

Standard

Array

FFh

Write

Protected

Array

80h

7Fh

00h

State of the EEPROM memory

area after write access

to the Protect Register

Memory

Area

9/28

M34C02

Figure 8. Write Mode Sequ ence s in a Non Write-Protected Area

Write Operations

Following a Start condition the b us master sends

a Device Select Code with the RW b it rese t to 0.

The device acknowledges t hi s, as shown in Figure

8., an d waits for an address byte. The device re-

sponds to the address byte with an acknowledge

bit, and th en w aits for the data byte.

When th e bus mast er generate s a Stop con dition

immediately af ter the Ack bi t (in the “10th bit” time

slot), either at the end of a Byte Write or a Page

Write, the internal memory Write cycle is triggered.

A Stop condition at any other time slot does not

trigger the internal Write cycle.

During the internal Write cycle, Seria l Da ta (SDA)

and Serial Clock (SCL) are ignored, and the de-

vice does not respond to any requests.

Byte Write

After the Device Select Code and the address

byte, the bus master sends one data byte. If the

addressed location is hardware write-protected,

the device repli es to the data byte with NoAck, and

the location is not modified. If, instead, the ad-

dressed location is not Write-protected, t he devi ce

replies with Ack. The bus master terminates the

transfer by generating a Stop condi tion, as shown

in Figur e 8..

Page Write

The Pag e Write m ode allows u p to 16 byt es to be

written in a single Write cycle, provided that they

are all located in the same page in the memory:

that is, the most significant memory address bits

are t he same. If more bytes are sent than will fit up

to the end of the pa ge, a c ond ition known as ‘ roll-

over’ occurs. This should be avoided, as data

starts to become overwrit ten in an implementation

dependent way.

The bus master sends f rom 1 to 16 b ytes of data,

each of which is acknowledged by the device if

Write Control (WC ) is Low. If the a ddressed loca-

tion is hardware write-protected, the device replies

to th e data byte with NoAc k, and the locations are

not modifi ed. A fter each byte is transferred, the in-

ternal byte address counter (the 4 least significant

address bits only) is in cremented. The transfer is

terminated by the bus master generating a Stop

condition.

STOP

START

BYTE WRITE DEV SEL BYTE ADDR DATA IN

START

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

AI01941

STOP

DATA IN N

ACK ACK ACK

R/W

ACK ACK ACK

R/W

ACK ACK

M34C02

10/28

Figu re 9. Wri t e C yc le Pol l in g Fl owchart usi n g A C K

Minimizing System Delays by Polling On ACK

During the internal Write cycle, the device discon-

nects itself from the bus, and writes a copy of the

data from its internal latches to the memory cells.

The maximum Write time (tw) is shown in Table

17. and Table 18., but the typical time is shorter.

To make use of this, a polling sequence can be

used by the bus master.

The sequence , as shown in Figure 9., is :

– Initial cond ition: a Write cyc le is in progress.

– Step 1: the bus master issues a Start condition

followed by a Device Select Code (the first

byte of the new instruction).

– Step 2: if the device is b usy with the internal

Wri te cycle, no Ack will be returned and the

bus master goes back to Step 1. If the device

has terminated the internal Write cy cle, it

respo nds with an Ack, indicating that the

devi ce is ready to receive t he second part of

the instruction (the first byte of this instruction

hav ing been sent during Step 1).

WRITE Cycle

in Progress

AI01847C

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

YESNO

ReSTART

STOP

DATA for the

WRITE Operation DEVICE SELECT

with RW = 1

Send Address

and Receive ACK

First byte of instruction

with RW = 0 already

decoded by the device

YESNO START

Condition

Continue the

WRITE Operation Continue the

Random READ Operation

11/28

M34C02

Figure 10. Read Mode Sequences

Note: 1. T he seven most significant bits of t he Device Sel ect Code of a Ra ndom Rea d (i n the 1st an d 3rd bytes ) m ust be ident i cal.

Read Operation s

Read operations are performed independently of

whether hardware or software prot ection has been

set.

The device has an internal address counter which

is incremented each time a byte is read.

Random Address Read

A dummy Write is first performed to load the ad-

dress into this address counter (as shown in Fig-

ure 10.) but without sending a Stop condition.

Then, the bus master sends another Start condi-

tion, and repeats the Device Select Code, wit h the

RW bit set to 1. The device acknowledges this,

and outputs the contents of the addressed byte.

The bus master must not acknowledge the byte,

and terminates the transfer with a Stop condition.

Current Address Read

For the Current Address Read operation, following

a Start condition, the bus master only sends a De-

vice Select Code with the RW bit set to 1. The de-

vice acknowledges this, and outputs the byte

addressed by the internal address counter. The

counter is then incremented. The bus master ter-

minates the transfer with a Stop condition, as

shown in Figure 10., without acknowledging the

byte.

START

DEV SEL * BYTE ADDR

START

DEV SEL DATA OUT 1

AI01942

DATA OUT N

STOP

START

CURRENT

ADDRESS

READ DEV SEL DATA OUT

RANDOM

ADDRESS

READ

STOP

START

DEV SEL * DATA OUT

SEQUENTIAL

CURRENT

READ

STOP

DATA OUT N

START

DEV SEL * BYTE ADDR

SEQUENTIAL

RANDOM

READ

START

DEV SEL * DATA OUT 1

STOP

ACK

R/W

NO ACK

ACK

R/W

ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

M34C02

12/28

Sequenti al Re ad

This operation can be used after a Current Ad-

dress Read or a Random Address Read. The bus

master does acknowledge the data byte output,

and sends additional clock pulses so that the de-

vice continues to output the next byte in sequence.

To terminate the stream of bytes, the bus master

must not acknowledge the last byte, and must

generate a Stop condition, as shown in Figur e 10..

The output data com es from consecutive address-

es, with the internal address counter automatically

incremented after each byte output. After the last

memory address, the address count er ‘rolls-over’,

and the device continues to output data from

memory address 00h.

Acknowledge in Read Mode

For all Read commands, the device waits, after

each byte read, f or an acknowledgment during the

9th bit time. If the bus master does not drive S erial

Data (SDA) Low during this time, the device termi-

nates the data transfer an d switches to its St and-

by mode.

USE WITHIN A DRAM DIM M

In the application, the M34C02 is soldered directly

in the printed circuit module. The 3 Chip Enable in-

puts (pins 1, 2 and 3) are wired at VCC or VSS

through the DIMM socket (see Table 5.). The pull-

up resistors needed for normal behavior of the I2C

bus are connected on the I2C bus of the mother-

board (as shown in Figure 11.).

The Write Control (WC) of the M34C02 can be left

unconnected. However, connecting it to VSS is

recommende d, to m aintain full read and write ac-

cess.

Programm ing the M34C02

When the M34C02 is delivered, full read and write

access is given to the whole memory array. It is

recommende d that the first st ep is to use th e test

equipment to write the module information (such

as its access speed, its size, its organization) to

the first half of the memory, starting from the first

memory location. When the data has been vali dat -

ed, the test equipment can send a Write command

to the Protection Register, using the de vice select

code ’01100000b’ followed by an address and

data byte (made up of Don’t Care values) as

shown in Figure 6.. The first 128 bytes of the mem-

ory area are then write-protected, and the M34C02

will no longer respond to the specific device select

code ’0110000xb’. I t is not possible to reverse this

sequence.

Table 5. DRA M DIMM Connections

INITIAL DELIVERY STATE

The device is delivered with the memory array

erased: all bits are set to 1 (each byte contains

FFh).

DIMM Position E2 E1 E0

0 VSS VSS VSS

1 VSS VSS VCC

2 VSS VCC VSS

3 VSS VCC VCC

4 VCC VSS VSS

5 VCC VSS VCC

6 VCC VCC VSS

7 VCC VCC VCC

13/28

M34C02

Figure 11. Serial Presence Detect Blo ck Diagram

Note: 1. E0, E1 and E 2 are wire d at e ach DIMM socket i n a bi nary sequenc e for a maxi m um of 8 devices.

2. Com m on clock and common da ta are s hared across all t he devices.

3. Pu ll-up re sisto rs ar e r equi red on all S DA a nd SCL b us li nes ( typic all y 4.7 k Ω) beca use t he se li nes ar e o pen dr ain w he n use d as

outputs.

R = 4.7kΩ

AI01937

DIMM Position 7 SDASCLE0E1E2

VCC

DIMM Position 6 SDASCLE0E1E2

DIMM Position 5 SDASCLE0E1E2

DIMM Position 4 SDASCLE0E1E2

DIMM Position 3 SDASCLE0E1E2

DIMM Position 2 SDASCLE0E1E2

VCC

DIMM Position 1 SDASCLE0E1E2

DIMM Position 0 SDASCLE0E1E2

VSS

VSS VCC

VSS

VSS VCC

VCC VSS

VCC

VCC VSS

VSS

VCC

SCL line SDA line

From the motherboard

I2C master controller

M34C02

14/28

MAXI MUM RAT IN G

Stressing the device ab ove t he rating listed in t he

Absolute Maximum Ratings" table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at t hese or

any other con ditions ab ove those i ndicated in t he

Operating sections of this specification is not im-

plied. Exposure to Absolute Max imum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 6. Absolute Maximum Ratings

Note : 1. Comp li ant wit h JED EC Std J- STD- 020 B (for small bod y, Sn-Pb or Pb asse mbl y), t he ST EC OPA CK ® 7191395 spec ification, an d

the Eu ropean di rectiv e on Restr i ct i ons on Haz ardous S ubstan ces (RoHS) 2002/ 95/EU.

2. JE DEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Min. Max. Unit

TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering 1See note1°C

VIO Input or Output Voltage –0.50 6.5 V

VCC Supply Voltage –0.50 6.5 V

VESD Electrostatic Discharge Voltage (Human Body model) 2–4000 4000 V

15/28

M34C02

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement condition s, and t he DC a nd AC charac-

teristics of the device. The parameters i n the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Des igners shoul d c heck that the operating

conditions in t heir circuit matc h the measurem ent

conditions when relying on the quoted parame-

ters.

Table 7. O per ating Conditions (M34 C02-W)

Table 8. O per ating Conditions (M34 C02-L)

Table 9. O per ating Conditions (M34C02-R)

Table 10. O per ating Conditions (M34C02-F)

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.5 5.5 V

TAAmb ient Operati ng Tem peratur e –40 85 °C

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.2 5.5 V

TAAmb ient Operati ng Tem peratur e –40 85 °C

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 1.8 5.5 V

TAAmb ient Operati ng Tem peratur e –40 85 °C

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 1.7 3.6 V

TAAmb ient Operati ng Tem peratur e 0 70 °C

M34C02

16/28

Table 11. AC Measurement Conditions

Figu re 12. AC Measure m e nt I/ O Wa veform

Table 12. Input Parameter s

Note: 1. TA = 25 ° C, f = 40 0 kHz

2. Sampled only, not 100% tested.

Symbol Parameter Min. Max. Unit

CLLoad Capacitance 100 pF

Input Rise and Fall Times 50 ns

Input Levels 0.2VCC to 0.8VCC V

Input and Output Timing Reference Levels 0.3VCC to 0.7VCC V

Symbol Parameter1,2 Test Condition Min.Max.Unit

CIN Input Capa citanc e (SDA) 8 pF

CIN Input Capacitance (other pins) 6 pF

ZWCL WC Input Impedance VIN < 0.5 V 5 20 kΩ

ZWCH WC Input Impedance VIN > 0.7VCC 500 kΩ

tNS Pulse width ignored

(Input Filter on SCL and SDA) Single glitch 100 500 ns

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

17/28

M34C02

Table 13. DC Characteristics (M34C02-W)

Table 14. DC Characteristics (M34C02-L)

Symbol Parameter Test Condition

(in addition to those in Table 7.)Min. Max. Unit

ILI Input Leaka ge Curren t

(SCL, SDA) VIN = VSS or VCC ± 2 µA

ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current VCC =5V, fc=40 0kHz (ris e/fall time < 30ns) 2mA

VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 1mA

ICC1 Stand -by Supply Current VIN = VSS or VCC , VCC = 5V 1 µA

VIN = VSS or VCC , VCC = 2.5V 0.5 µA

VIL

Input Low Voltage

(E2, E1, E0, SCL, SDA) –0.3 0.3VCC V

Input Low Voltage (WC) –0.3 0.5 V

VIH Input High Volta ge

(E2, E1, E0, SCL, SDA, WC)0.7VCC VCC+1 V

VOL Output Low Voltage IOL = 3mA, VCC = 5V 0.4 V

IOL = 2.1mA, VCC = 2.5V 0.4 V

Symbol Parameter Test Condition

(in addition to those in Table 8.)Min. Max. Unit

ILI Input Leaka ge Curren t

(SCL, SDA) VIN = VSS or VCC ± 2 µA

ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current

VCC =5V, fc=40 0kHz (ris e/fall time < 30ns) 2mA

VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 1mA

VCC =2.2V, fc=400kHz (rise/fall time < 30ns) 1mA

ICC1 Stand -by Supply Current VIN = VSS or VCC , VCC = 5 V 1 µA

VIN = VSS or VCC , 2.2V ≤ VCC < 2.5V 0.5 µA

VIL

Input Low Voltage

(E2, E1, E0, SCL, SDA) –0.3 0.3VCC V

Input Low Voltage (WC) –0.3 0.5 V

VIH Input High Volta ge

(E2, E1, E0, SCL, SDA, WC)0.7VCC VCC+1 V

VOL Output Low Voltage IOL = 3mA, VCC = 5V 0.4 V

IOL = 2.1mA, 2.2V ≤ VCC < 2.5V 0.4 V

M34C02

18/28

Table 15. DC Characteristics (M34C02-R)

Table 16. DC Characteristics (M34C02-F)

Note: 1. Preliminary Data.

Symbol Parameter Test Condition

(in addition to those in Table 9.)Min. Max. Unit

ILI Input Leaka ge Curren t

(SCL, SDA) VIN = VSS or VCC ± 2 µA

ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current VCC =1 . 8 V, f c=100kHz (rise/f all time < 30ns) 1mA

ICC1 Stand -by Supply Current VIN = VSS or VCC , VCC = 5V 1µA

VIN = VSS or VCC , 1.8V ≤ VCC < 2.5V 0.5 µA

VIL

Input Low Voltage

(E2, E1, E0, SCL, SDA) 2.5V ≤ VCC ≤ 5.5V – 0.3 0.3 VCC V

1.8V ≤ VCC < 2.5V – 0.3 0.25 VCC V

Input Low Voltage (WC) –0.3 0.5 V

VIH Input High Volta ge

(E2, E1, E0, SCL, SDA, WC)0.7VCC VCC+1 V

VOL Output Low Voltage

IOL = 3mA, VCC = 5V 0.4 V

IOL = 2.1mA, 2.2V ≤ VCC < 2.5V 0.4 V

IOL = 0.15mA, VCC = 1.8V 0.2 V

Symbol Parameter Test Condition

(in addition to those in Table 10.)Min.1Max.1Unit

ILI Input Leaka ge Curren t

(SCL, SDA) VIN = VSS or VCC ± 2 µA

ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current VCC =1 . 7 V, f c=100kHz (rise/f all time < 30ns) 1mA

ICC1 Stand -by Supply Current VIN = VSS or VCC , VCC = 3.6V 1 µA

VIN = VSS or VCC , 1.7V ≤ VCC < 2.5V 0.5 µA

VIL

Input Low Voltage

(E2, E1, E0, SCL, SDA) 2.5V ≤ VCC ≤ 3.6V – 0.3 0.3 VCC V

1.7V ≤ VCC < 2.5V – 0.3 0.25 VCC V

Input Low Voltage (WC) –0.3 0.5 V

VIH Input High Volta ge

(E2, E1, E0, SCL, SDA, WC)0.7VCC VCC+1 V

VOL Output Low Voltage IOL = 2.1mA, 2.2V ≤ VCC ≤ 3.6V 0.4 V

IOL = 0.15mA, VCC = 1.7V 0.2 V

19/28

M34C02

Table 17. AC Characteristics (M34C02-W, M34C02-L)

Note: 1. F or a reSTA RT condi tion, or fol l owing a Wr i te cycle .

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions , a minimum delay is placed between SCL=1 and the fal ling or rising edge of SDA.

Table 18. AC Characteristics (M34C02-R, M34C02-F )

Note: 1. F or a reSTA RT condi tion, or fol l owing a Wr i te cycle .

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions , a minimum delay is placed between SCL=1 and the fal ling or rising edge of SDA.

Test conditions specified in Table 11. and Table 7. or Table 8.

Symbol Alt. Parameter Min. Max. Unit

fCfSCL Clock Fre quenc y 400 kHz

tCHCL tHIGH Clock Pulse Width High 600 ns

tCLCH tLOW Clock Pulse Width Low 1300 ns

tDL1DL2 2tFSDA Fall Time 20 300 ns

tDXCX tSU:DAT Data In Set Up Time 100 ns

tCLDX tHD:DAT Data In Hold Time 0 ns

tCLQX tDH Data Out Hold Time 200 ns

tCLQV 3tAA Clock Low to Next Data Valid (Access Time) 200 900 ns

tCHDX 1tSU:STA Start Condition Set Up Time 600 ns

tDLCL tHD:STA Start Condition Hold Time 600 ns

tCHDH tSU:STO Stop Condition Set Up Time 600 ns

tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns

tWtWR Write Time 10 ms

Test conditions specified in Table 11. and Table 9. or Table 10.

Symbol Alt. Parameter Min. Max. Unit

fCfSCL Clock Fre quenc y 100 kHz

tCHCL tHIGH Clock Pulse Width High 4000 ns

tCLCH tLOW Clock Pulse Width Low 4700 ns

tDL1DL2 2tFSDA Fall Time 20 300 ns

tDXCX tSU:DAT Data In Set Up Time 250 ns

tCLDX tHD:DAT Data In Hold Time 0 ns

tCLQX tDH Data Out Hold Time 200 ns

tCLQV 3tAA Clock Low to Next Data Valid (Access Time) 200 3500 ns

tCHDX 1tSU:STA Start Condition Set Up Time 4700 ns

tDLCL tHD:STA Start Condition Hold Time 4000 ns

tCHDH tSU:STO Stop Condition Set Up Time 4000 ns

tDHDL tBUF Time between Stop Condition and Next Start Condition 4700 ns

tWtWR Write Time 10 ms

M34C02

20/28

Figure 13. AC Waveforms

SCL

SDA In

SCL

SDA Out

SCL

SDA In

tCHCL

tDLCL

tCHDX

START

Condition

tCLCH

tDXCXtCLDX

SDA

Input

SDA

Change tCHDH tDHDL

STOP

Condition

Data Valid

tCLQV tCLQX

tCHDH

STOP

Condition

tCHDX

START

Condition

Write Cycle

AI00795C

START

Condition

21/28

M34C02

P ACKAGE MECHANI CAL

Figure 14. PDIP8 – 8 pin Plastic DIP, 0.25mm lead fram e, Packag e Outline

No te : Drawi ng is not to sc al e.

Table 19. PDIP8 – 8 pin Plastic DIP, 0.25m m l ead frame, Package M ech anical Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 5.33 0.210

A1 0.38 0.015

A2 3.30 2.92 4.95 0.130 0.115 0.195

b 0.46 0.36 0.56 0.018 0.014 0.022

b2 1.52 1.14 1.78 0.060 0.045 0.070

c 0.25 0.20 0.36 0.010 0.008 0.014

D 9.27 9.02 10.16 0.365 0.355 0.400

E 7.87 7.62 8.26 0.310 0.300 0.325

E1 6.35 6.10 7.11 0.250 0.240 0.280

e2.54––0.100––

eA 7.62 – – 0.300 – –

eB 10.92 0.430

L 3.30 2.92 3.81 0.130 0.115 0.150

PDIP-B

M34C02

22/28

Figure 15. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width , Packag e Outline

No te : Drawi ng is not to sc al e.

Table 20. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body wi dth, Mechanical Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e1.27––0.050––

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

CP 0.10 0.004

SO-a

LA1 α

h x 45˚

23/28

M34C02

Figure 16. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline

Note: 1. Drawing is not to scale.

2. T he centr al pad ( the area E 2 by D2 in the above ill ustra tion) is pul l ed, internall y, to VSS. I t must not be allowed to be connect ed to

any ot her v ol tage or si gnal lin e on t he P CB, for ex am ple du ri ng t he s ol derin g process.

Table 21. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Pac kage No lead 2x3m m², Data

Symbol mm inches

Typ. Min. Max. Typ. Min. Max.

A 0.55 0.50 0.60 0.022 0.020 0.024

A1 0.00 0.05 0.000 0.002

b 0.25 0.20 0.30 0.010 0.008 0.012

D 2.00 0.079

D2 1.55 1.65 0.061 0.065

ddd 0.05 0.002

E 3.00 0.118

E2 0.15 0.25 0.006 0.010

e 0.50 – – 0.020 – –

L 0.45 0.40 0.50 0.018 0.016 0.020

L1 0.15 0.006

L3 0.30 0.012

N8 8

UFDFPN-01

A1 ddd

M34C02

24/28

Figure 17. TSS OP8 – 8 lead Thin Shrink S mall Outline, Packa ge Ou tline

No te : Drawi ng is not to sc al e.

Table 22. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechan ical Data

Symbol mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 1.000 0.800 1.050 0.0394 0.0315 0.0413

b 0.190 0.300 0.0075 0.0118

c 0.090 0.200 0.0035 0.0079

CP 0.100 0.0039

D 3.000 2.900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

E 6.400 6.200 6.600 0.2520 0.2441 0.2598

E1 4.400 4.300 4.500 0.1732 0.1693 0.1772

L 0.600 0.450 0.750 0.0236 0.0177 0.0295

L1 1.000 0.0394

α0° 8° 0° 8°

TSSOP8AM

EE1

A2A

25/28

M34C02

Figure 18. TSSOP 8 3x3mm ² – 8 lead Thin Shri nk Sm all Outline, 3x3m m ² body size, Outline

No te : Drawi ng is not to sc al e.

Table 23. TSSOP 8 3x3mm ² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Data

Symbol mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.100 0.0433

A1 0.050 0.150 0.0020 0.0059

A2 0.850 0.750 0.950 0.0335 0.0295 0.0374

b 0.250 0.400 0.0098 0.0157

c 0.130 0.230 0.0051 0.0091

D 3.000 2.900 3.100 0.1181 0.1142 0.1220

E 4.900 4.650 5.150 0.1929 0.1831 0.2028

E1 3.000 2.900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

CP 0.100 0.0039

L 0.550 0.400 0.700 0.0217 0.0157 0.0276

L1 0.950 0.0374

α0° 6° 0° 6°

TSSOP8BM

EE1

A2A

M34C02

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PART NUMBERING

Table 24. Ordering Information Scheme

Note: 1. Pa ckage av ai l able only on request.

For a list of available options (speed, package,

etc.) or for further i nf ormation on any aspect of this device, please c ontact your neares t ST Sales O f-

fice.

Example: M34C02 – W MN 6 T P

Device Type

M34 = ASSP I2C serial access EEPROM

Device Function

02 = 2 Kbit (256 x 8)

Operating Voltage

W = VCC = 2.5 to 5.5V (400kHz)

L = VCC = 2.2 to 5.5V (400kHz)

R = VCC = 1.8 to 5.5V (100kHz)

F = VCC = 1.7 to 3.6V (100kHz)

Package

BN1= PD IP8

MN = SO8 (150 mil width)

MB = UDFDFPN8 (MLP8)

DW = TSSOP8 (169 mil width)

DS = TSSOP8 (3x3mm² body size, MSOP8)

Device Grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

1 = Temperature range 0 to 70 °C.

Device tested with standard test flow

Option

blank = Standard Packing

T = Tape and Reel Packing

Plating Technology

blank = Standard SnPb plating

P = Lead-Free and RoHS compliant

G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free

27/28

M34C02

REVISION HISTORY

Table 25. Revision History

Date Rev. Description of Revision

27-Dec-1999 2.0 Adjustments to the formatting. 0 to 70°C temperature range removed from DC and AC tables.

No change to description of device, or parameters

07-Dec-2000 2.1 New definition of lead soldering temperature absolute rating for certain packages

13-Mar-2001 2.2 -R voltage range added

18-Jul-2002 2.3 TSSOP8 (3x3mm² body size) package (MSOP8) added

22-May-2002 2.4 VFDFPN8 package (MLP8) added

21-Jul-2003 3.0 Document reformatted. -F voltage range added.

17-Mar-2004 4.0 Table of Contents added. MLP package changed. Absolute Maximum Ratings for VIO(min)

and VCC(m in) change d. Solder ing tempe rature information clar ified for Ro HS complia nt

devices. Device grade information clarified

14-Apr-2004 5.0 Typos corrected in Ordering Information example

26-Aug-2004 6.0 Device Grade clarified. Product List summary table added

M34C02

28/28

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