®
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Rev. 03 — 2 July 2012 Product data sheet
1. General description
The ADC1206S040/055/070 are a family of BiCMOS 12-bit Analog-to-Digital Converters
(ADC) optimized for a wide range of applications such as cellular infrastructures,
professional telecommunications, imaging, and digital radio. It converts the analog input
signal into 12-bit binary coded digital words at a maximum sampling rate of 70 MHz. All
static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS
compatible and all outputs are CMOS compatible. A sine wave clock input signal can also
be used.
2. Features
12-bit resolution
Sampling rate up to 70 MHz
3 dB bandwidth of 245 MHz
5 V power supplies and 3.3 V output power supply
Binary or twos complement CMOS outputs
In-range CMOS compatible output
TTL and CMOS compatible static digital inputs
TTL and CMOS compatible digital outputs
Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible
Power dissipation 550 mW (typical)
Low analog input capacitance (typical 2 pF), no buffer amplifier required
Integrated sample and hold amplifier
Differential analog input
External amplitude range control
Voltage controlled regulator included
40 C to +85 C ambient temperature
3. Applications
High-speed analog-to-digital conversion for:
Cellular infrastructure
Professional telecommunication
Digital radio
Radar
Medical imaging
Fixed network
Cable modem
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 2 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Barcode scanner
Cable Modem Termination System (CMTS)/
Data Over Cable Service Interface Specification (DOCSIS)
4. Quick reference data
Table 1. Quick reference data
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V;
VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND
and DGND shorted together; Tamb =
40
C to 85
C; VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V;
Vref = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V and
VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VCCA analog supply voltage 4.75 5.0 5.25 V
VCCD digital supply voltage 4.75 5.0 5.25 V
VCCO output supply voltage 3.0 3.3 3.6 V
ICCA analog supply current -78 87 mA
ICCD digital supply current -27 30 mA
ICCO output supply current fclk = 20 MHz
fi = 400 kHz
- 3 4 mA
INL integral non-linearity fclk = 20 MHz
fi = 400 kHz
-2.6 4.5 LSB
DNL differential
non-linearity
fclk = 20 MHz
fi = 400 kHz
(no missing code
guaranteed)
-0.5 +1.1 0.95 LSB
fclk(max) maximum clock
frequency
ADC1206S040H 40 - - MHz
ADC1206S055H 55 - - MHz
ADC1206S070H 70 - - MHz
Ptot total power dissipation fclk = 55 MHz
fi = 20 MHz
-550 660 mW
5. Ordering information
Table 2. Ordering information
Type number Package Sampling
frequency
(MHz)
Name Description Version
ADC1206S040H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 10 1.75 mm
SOT307-2 40
ADC1206S055H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 10 1.75 mm
SOT307-2 55
ADC1206S070H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 10 1.75 mm
SOT307-2 70
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 3 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
6. Block diagram
4
18
OTC
23
20
VCCA1
27
26
25
24
28 D4
D5
D6
D7
D8
29
30
21
D3
D2
31 D1
32 D0
D11
OVERFLOW/UNDERFLOW
LATCH
CMOS
OUTPUTS
LATCHES
CLOCK DRIVER
014aaa385
36
CLK
VCCA3
19
CE
ADC1206S040/055/070
33 VCCO
44
AGND1 AGND3 OGND
3417
DGND2
data outputs
LSB
MSB
IR
40
AGND4
38
DGND1
23
22
D9
D10
15
VCCD2
37
VCCD1
41
VCCA4
35
CLKN
ANALOG - TO -
DIGITAL
CONVERTER
CMOS OUTPUT
Vref
REFERENCE
CMADC
REFERENCE
n.c.
FSREF
Vref
INN
IN
SH
CMADC
DEC
6 to 10,13,14,16
AMP
sample -
and - hold
43
11
12
42
39
1
5
Fig 1. Block diagram.
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 4 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
7. Pinning information
7.1 Pinning
ADC1206S070H
CMADC V
CCO
V
CCA1
D0
V
CCA3
D1
AGND3 D2
DEC D3
n.c. D4
n.c. D5
n.c. D6
n.c. D7
n.c. D8
V
ref
D9
FSREF AGND1
n.c. INN
n.c. IN
V
CCD2
V
CCA4
n.c. AGND4
DGND2 SH
OTC DGND1
CE V
CCD1
IR CLK
D11 CLKN
D10 OGND
014aaa383
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
Fig 2. Pin configuration
7.2 Pin description
Table 3. Pin description
Symbol Pin Description
CMADC 1regulator output common mode ADC input
VCCA1 2analog supply voltage 1 (5 V)
VCCA3 3analog supply voltage 3 (5 V)
AGND3 4analog ground 3
DEC 5decoupling node
n.c. 6not connected
n.c. 7not connected
n.c. 8not connected
n.c. 9not connected
n.c. 10 not connected
Vref 11 reference voltage input
FSREF 12 full-scale reference output
n.c. 13 not connected
n.c. 14 not connected
VCCD2 15 digital supply voltage 2 (5 V)
n.c. 16 not connected
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 5 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
8. Limiting values
DGND2 17 digital ground 2
OTC 18 control input twos complement output; active HIGH
CE 19 chip enable input (CMOS level; active LOW)
IR 20 in-range output
D11 21 data output; bit 11 (Most Significant Bit (MSB))
D10 22 data output; bit 10
D9 23 data output; bit 9
D8 24 data output; bit 8
D7 25 data output; bit 7
D6 26 data output; bit 6
D5 27 data output; bit 5
D4 28 data output; bit 4
D3 29 data output; bit 3
D2 30 data output; bit 2
D1 31 data output; bit 1
D0 32 data output; bit 0 (Least Significant Bit (LSB))
VCCO 33 output supply voltage (3.3 V)
OGND 34 output ground
CLKN 35 complementary clock input
CLK 36 clock input
VCCD1 37 digital supply voltage 1 (5 V)
DGND1 38 digital ground 1
SH 39 sample-and-hold enable input (CMOS level; active HIGH)
AGND4 40 analog ground 4
VCCA4 41 analog supply voltage 4 (5 V)
IN 42 analog input voltage
INN 43 complementary analog input voltage
AGND1 44 analog ground 1
Table 3. Pin description …continued
Symbol Pin Description
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCCA analog supply voltage [1] 0.3 +7.0 V
VCCD digital supply voltage [1] 0.3 +7.0 V
VCCO output supply voltage [1] 0.3 +7.0 V
VCC supply voltage difference VCCA VCCD 1.0 +1.0 V
VCCD VCCO 1.0 +4.0 V
VCCA VCCO 1.0 +4.0 V
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 6 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
[1] The supply voltages VCCA, VCCD and VCCO may have any value between 0.3 V and +7.0 V provided that
the supply voltage differences VCC are respected.
9. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction
to ambient
in free air 75 K/W
10. Characteristics
Vi(IN) input voltage on pin IN referenced to AGND 0.3 VCCA V
Vi(INN) input voltage on pin INN 0.3 VCCA V
Vi(clk)(p-p) peak-to-peak clock input
voltage
differential clock drive
at pins 35 and 36
- VCCD V
IOoutput current -10 mA
Tstg storage temperature 55 +150 C
Tamb ambient temperature 40 +85 C
Tjjunction temperature -150 C
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Table 6. Characteristics
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to 85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; Vref = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
Supplies
VCCA analog supply
voltage
4.75 5.0 5.25 V
VCCD digital supply
voltage
4.75 5.0 5.25 V
VCCO output supply
voltage
3.0 3.3 3.6 V
ICCA analog supply
current
I - 78 87 mA
ICCD digital supply
current
I - 27 30 mA
ICCO output supply
current
fclk = 20 MHz; fi = 400 kHz I - 3 4 mA
fclk = 40 MHz; fi = 4.43 MHz C - 6.2 9mA
fclk = 55 MHz; fi = 20 MHz I - 9.5 12 mA
Ptot total power
dissipation
fclk = 55 MHz fi = 20 MHz -550 660 mW
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 7 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Inputs
CLK and CLKN referenced to DGND[2]
VIL LOW-level
input voltage
PECL mode; VCCD = 5 V I 3.19 -3.52 V
TTL mode C 0 - 0.8 V
VIH HIGH-level
input voltage
PECL mode; VCCD = 5 V I 3.83 -4.12 V
TTL mode C2.0 - VCCD V
IIL LOW-level
input current
VCLK or VCLKN = 3.19 V C 10 - - A
IIH HIGH-level
input current
VCLK or VCLKN = 3.83 V C - - 10 A
Vi(dif)(p-p) peak-to-peak
differential
input voltage
AC driving mode;
DC voltage level = 2.5 V
C 1 1.5 2.0 V
Riinput resistance fclk = 55 MHz D 2 - - k
Ciinput
capacitance
fclk = 55 MHz D - - 2 pF
OTC, SH and CE (referenced to DGND); see Table 8 and 9
VIL LOW-level
input voltage
I 0 - 0.8 V
VIH HIGH-level
input voltage
I2.0 - VCCD V
IIL LOW-level
input current
VIL = 0.8 V I 20 - - A
IIH HIGH-level
input current
VIH = 2.0 V I - - 20 A
IN and INN (referenced to AGND); see Table 7, Vref = VCCA3 1.75 V
IIL LOW-level
input current
SH = HIGH C - 10 -A
IIH HIGH-level
input current
SH = HIGH C - 10 -A
Riinput resistance fi = 20 MHz D - 14 - M
Ciinput
capacitance
fi = 20 MHz D - 450 -pF
VI(cm) common-mode
input voltage
VI(IN) = VI(INN)
output code 2 047
C VCCA3 1.7 VCCA3 1.6 VCCA3 1.2 V
Voltage controlled regulator output CMADC
VO(cm) common-mode
output voltage
I - VCCA3 1.6 - V
Iload load current I - 1 2 mA
Table 6. Characteristics …continued
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to 85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; Vref = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 8 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Voltage input Vref[3]
Vref reference
voltage
full-scale fixed voltage;
fi = 20 MHz; fclk = 55 MHz
C - VCCA3 1.75 - V
Iref reference
current
C - 0.3 10 A
Vi(dif)(p-p) peak-to-peak
differential
input voltage
VI(IN)(p-p) VI(INN)(p-p);
Vref = VCCA3 1.75 V;
VI(cm) = VCCA3 1.6 V
C - 1.9 - V
Voltage controlled regulator output FSREF
VO(ref) reference
output voltage
VI(IN)(p-p) VI(INN)(p-p) = 1.9 V I - VCCA3 1.75 - V
Digital outputs D11 to D0 and IR (referenced to OGND)
VOL LOW-level
output voltage
IOL = 2 mA I 0 - 0.5 V
VOH HIGH-level
output voltage
IOH = 0.4 mA I VCCCO 0.5 - VCCO V
Iooutput current 3-state output level between
0.5 V and VCCO
I20 -+20 A
Switching characteristics; Clock frequency fclk; see Figure 3
fclk(min) minimum clock
frequency
SH = HIGH C - - 7 MHz
fclk(max) maximum clock
frequency
ADC1206S040H C40 - - MHz
ADC1206S055H I55 - - MHz
ADC1206S070H C70 - - MHz
tw(clk)H HIGH clock
pulse width
fi = 20 MHz C6.8 - - ns
tw(clk)L LOW clock
pulse width
fi = 20 MHz C6.8 - - ns
Analog signal processing; 50 % clock duty factor; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; Vref = VCCA3 1.75 V; see Table 7
Linearity
INL integral
non-linearity
fclk = 20 MHz; fi = 400 kHz I - 2.6 4.5 LSB
DNL differential
non-linearity
fclk = 20 MHz; fi = 400 kHz
(no missing code
guaranteed)
I - 0.5 +1.1 0.95 LSB
Eoffset offset error VCCA = VCCD = 5 V;
VCCO = 3.3 V; Tamb = 25 C;
output code = 2 047
C25 +5 +25 mV
EGgain error spread from device to
device; VCCA = VCCD = 5 V;
VCCO = 3.3 V; Tamb = 25 C
C7 - +7 %FS
Table 6. Characteristics …continued
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to 85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; Vref = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 9 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Bandwidth (fclk = 55 MHz)[4]
Bbandwidth 3 dB; full-scale input C220 245 -MHz
Harmonics
2H second
harmonic level
ADC1206S040H; (fclk = 40 MHz)
fi = 4.43 MHz C - 78 -dBFS
fi = 10 MHz C - 77 -dBFS
fi = 15 MHz C - 74 -dBFS
fi = 20 MHz C - 71 -dBFS
ADC1206S055H; (fclk = 55 MHz)
fi = 4.43 MHz C - 77 -dBFS
fi = 10 MHz C - 77 -dBFS
fi = 15 MHz C - 76 -dBFS
fi = 20 MHz I - 73 -dBFS
ADC1206S070H; (fclk = 70 MHz)
fi = 4.43 MHz C - 76 -dBFS
fi = 10 MHz C - 74 -dBFS
fi = 15 MHz C - 70 -dBFS
3H third harmonic
level
ADC1206S040H; (fclk = 40 MHz)
fi = 4.43 MHz C - 74 -dBFS
fi = 10 MHz C - 74 -dBFS
fi = 15 MHz C - 74 -dBFS
fi = 20 MHz C - 73 -dBFS
ADC1206S055H; (fclk = 55 MHz)
fi = 4.43 MHz C - 74 -dBFS
fi = 10 MHz C - 74 -dBFS
fi = 15 MHz C - 74 -dBFS
fi = 20 MHz I - 72 -dBFS
ADC1206S070H; (fclk = 70 MHz)
fi = 4.43 MHz C - 74 -dBFS
fi = 10 MHz C - 74 -dBFS
fi = 15 MHz C - 73 -dBFS
Table 6. Characteristics …continued
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to 85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; Vref = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 10 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Total harmonic distortion[5]
THD total harmonic
distortion
ADC1206S040H; (fclk = 40 MHz)
fi = 4.43 MHz C - 68 -dBFS
fi = 10 MHz C - 68 -dBFS
fi = 15 MHz C - 68 -dBFS
fi = 20 MHz C - 68 -dBFS
ADC1206S055H; (fclk = 55 MHz)
fi = 4.43 MHz C - 68 -dBFS
fi = 10 MHz C - 68 -dBFS
fi = 15 MHz C - 68 -dBFS
fi = 20 MHz I - 68 -dBFS
ADC1206S070H; (fclk = 70 MHz)
fi = 4.43 MHz C - 68 -dBFS
fi = 10 MHz C - 67 -dBFS
fi = 15 MHz C - 67 -dBFS
Thermal noise (fclk = 55 MHz)
Nth(RMS) RMS thermal
noise
shorted input; SH = HIGH;
fclk = 55 MHz
C - 0.45 -LSB
Signal-to-noise ratio[6]
S/N signal-to-noise
ratio
ADC1206S040H; (fclk = 40 MHz)
fi = 4.43 MHz C - 64 -dBFS
fi = 10 MHz C - 64 -dBFS
fi = 15 MHz C - 64 -dBFS
fi = 20 MHz C - 64 -dBFS
ADC1206S055H; (fclk = 55 MHz)
fi = 4.43 MHz C - 64 -dBFS
fi = 10 MHz C - 64 -dBFS
fi = 15 MHz C - 64 -dBFS
fi = 20 MHz I - 64 -dBFS
ADC1206S070H; (fclk = 70 MHz)
fi = 4.43 MHz C - 64 -dBFS
fi = 10 MHz C - 64 -dBFS
fi = 15 MHz C - 63 -dBFS
Table 6. Characteristics …continued
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to 85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; Vref = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 11 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Spurious free dynamic range; see Figure 7, 13 and 14
SFDR spurious free
dynamic range
ADC1206S040H; (fclk = 40 MHz)
fi = 4.43 MHz C - 72 -dBFS
fi = 10 MHz C - 71 -dBFS
fi = 15 MHz C - 71 -dBFS
fi = 20 MHz C - 69 -dBFS
ADC1206S055H; (fclk = 55 MHz)
fi = 4.43 MHz C - 72 -dBFS
fi = 10 MHz C - 71 -dBFS
fi = 15 MHz C - 71 -dBFS
fi = 20 MHz I - 69 -dBFS
ADC1206S070H; (fclk = 70 MHz)
fi = 4.43 MHz C - 70 -dBFS
fi = 10 MHz C - 69 -dBFS
fi = 15 MHz C - 69 -dBFS
Effective number of bits[7]
ENOB effective
number of bits
ADC1206S040H; (fclk = 40 MHz)
fi = 4.43 MHz C - 10.1 -bits
fi = 10 MHz C - 10.1 -bits
fi = 15 MHz C - 10.1 -bits
fi = 20 MHz C - 10 -bits
ADC1206S055H; (fclk = 55 MHz)
fi = 4.43 MHz C - 10.1 -bits
fi = 10 MHz C - 10.1 -bits
fi = 15 MHz C - 10 -bits
fi = 20 MHz I - 10 -bits
ADC1206S070H; (fclk = 70 MHz)
fi = 4.43 MHz C - 10 -bits
fi = 10 MHz C - 10 -bits
fi = 15 MHz C - 10 -bits
Two-tone Intermodulation; (fclk = 55 MHz; fi = 20 MHz)[8]
IM intermodulation
suppression
C - 68 -dB
IMD3 third-order
intermodulation
distortion
C - 70 -dB
Table 6. Characteristics …continued
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to 85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; Vref = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 12 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC level vary 1:1 with VCCD) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC level vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC level vary 1:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p - p) and with a DC
level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal,
sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a
100 nF capacitor.
e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.
In that case the CLKN pin has to be connected to the ground.
[3] The ADC input range can be adjusted with an external reference connected to Vref pin. This voltage has to be referenced to VCCA;
see Figure 12.
[4] The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[5] Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics:
THD 20 log
2H

23H

24H

25H

26H

2
++++
1H

2
----------------------------------------------------------------------------------------------------------------------------------------------
=
where 1H is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6.
[6] Signal-to-noise ratio (S/N) takes into account all harmonics above five and noise up to Nyquist frequency; see Figure 8.
Bit error rate (fclk = 55 MHz)
BER bit error rate fi = 20 MHz; VI = 16 LSB at
code 2 047
C - 1014 -times/sample
Timing (CL = 10 pF)[9]
td(s) sampling delay
time
C - 0.25 1ns
th(o) output hold
time
C 4 6.4 -ns
td(o) output delay
time
C - 9.0 13 ns
3-state output delay times; see Figure 4
tdZH float to active
HIGH delay
time
C - 5.1 9.0 ns
tdZL float to active
LOW delay
time
C - 7.0 11 ns
tdHZ active HIGH to
float delay time
C - 9.7 14 ns
tdLZ active LOW to
float delay time
C - 9.5 13 ns
Table 6. Characteristics …continued
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to 85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; Vref = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 13 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
[7] Effective number of bits are obtained via a fast Fourier transform (FFT). The calculation takes into account all harmonics and noise up to
half of the clock frequency (Nyquist frequency). Conversion to Single-to-noise-and-distortion-ratio (SINAD) is given by
SINAD = ENOB 6.02 + 1.76 dB; see Figure 5.
[8] Intermodulation measured relative to either tone with analog input frequencies of 20 and 20.1 MHz. The two input signals have the
same amplitude and the total amplitude of both signals provides full-scale to the converter (6 dB below full-scale for each input signal).
IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product.
[9] Output data acquisition: the output data is available after the maximum delay of td(o); see Figure 3.
11. Additional information relating to Table 6
Table 7. Output coding with differential inputs (typical values to AGND);
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V, Vref = VCCA3 1.75 V
Code VI(IN)(p-p)
(V)
VI(INN)(p-p) IR Binary outputs
D11 to D0
Twos complement
outputs D11 to D0
Underflow < 3.125 < 4.075 00000 0000 0000 10 0000 0000 00
03.125 4.075 10000 0000 0000 10 0000 0000 00
1 - - 1 0000 0000 0001 10 0000 0000 01
- -
2047 3.6 3.6 01 1111 1111 11 11 1111 1111 11
- -
4094 - - 1 1111 1111 1110 0111 1111 1110
4095 4.075 3.125 11111 1111 1111 0111 1111 1111
Overflow > 4.075 < 3.125 01111 1111 1111 0111 1111 1111
Table 8. Mode selection
OTC CE D0 to D11 and IR
0 0 binary; active
1 0 two’s complement; active
X[1] 1high-impedance
[1] X = don’t care.
Table 9. Sample-and-hold selection
SH Sample-and-hold
1active
0inactive; tracking mode
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 14 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
sample N + 1sample N
014aaa396
sample N + 2
sample N + 1sample N sample N + 2
t
w(clk)L
t
w(clk)H
HIGH
LOW
50 %
DATA
D0 T O D11
HIGH
DATA
N + 1
DATA
N
DATA
N − 1
DATA
N − 2
t
h(o)
t
d(o)
t
d(s)
CLK
IN
50 %
LOW
Fig 3. Timing diagram
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 15 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
LOW
HIGH
HIGH
LOW
ADC1206S
070
V
CCD
V
CCO
S1
CE
CE
output
data
output
data
10 %
50 %
50 %
90 %
50 %
t
dLZ
t
dZL
t
dHZ
t
dZH
15 pF
3.3 kΩ
S1
TEST
V
CCO
t
dLZ
V
CCO
t
dZL
OGND
t
dZH
t
dHZ
OGND
014aaa397
0 V
frequency on pin CE = 100 kHz
Fig 4. Timing diagram and test conditions of 3-state output delay time
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 16 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
fi (MHz)
1 10010
014aaa371
9.8
(2)
9.4
10.2
10.6
ENOB
(bits)
9
(3)
(1)
fi (MHz)
1 10010
014aaa372
−64
−68
−60
−56
THD
(dBFS)
−72
(1)
(3)
(2)
(1) 40 MHz
(2) 55 MHz
(3) 70 MHz
(1) 40 MHz
(2) 55 MHz
(3) 70 MHz
Fig 5. Effective Number Of Bits (ENOB) as a function
of input frequency (sample device).
Fig 6. Total Harmonic Distortion (THD) as a function
of input frequency (sample device).
fi (MHz)
1 10010
014aaa373
68
64
72
76
SFDR
(dBFS)
60
(1)
(2)
(3)
fi (MHz)
1 10010
014aaa374
64
63
65
66
SNR
(dBFS)
62
(3)
(1)
(2)
(1) 40 MHz
(2) 55 MHz
(3) 70 MHz
(1) 40 MHz
(2) 55 MHz
(3) 70 MHz
Fig 7. Spurious Free Dynamic Range (SFDR) as a
function of input frequency (sample device).
Fig 8. Signal-to-Noise ratio (S/N) as a function of input
frequency (sample device).
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 17 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
014aaa375
−80
−120
−40
0
power
spectrum
(dB)
−160
measured output range (MHz)
0 3020105 2515
Fig 9. Single-tone; fi = 20 MHz; fclk = 55 MHz.
014aaa376
−80
−120
−40
0
power
spectrum
(dB)
−160
measured output range (MHz)
0 3020105 2515
Fig 10. Two-tone; fi 1 = 20 MHz; fi 2 = 20.1 MHz; fclk = 55 MHz.
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 18 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
output code
0 4096307220481024
014aaa377
0
−1
1
2
output
range
(INL)
−2
Fig 11. Integral Non-Linearity (INL)
014aaa378
output code
0 4096307220481024
−0.2
0.2
0.6
DNL
(LSB)
−0.6
Fig 12. Differential Non-Linearity (DNL)
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 19 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Input amplitude (dBFS)
−60 0−20−40
014aaa379
40
60
80
SFDR
(dBFS)
20
(2)
(3)
(1)
(1) fi = 4.43 MHz
(2) fi = 20 MHz
(3) SFDR = 80 dB
Fig 13. SFDR as a function of input amplitude; VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; fclk = 40 MHz
Input amplitude (dBFS)
−60 0−20−40
014aaa380
40
60
80
SFDR
(dBFS)
20
(2)
(1)
(3)
(1) fi = 4.43 MHz
(2) fi = 20 MHz
(3) SFDR = 80 dB
Fig 14. SFDR as a function of input amplitude; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; fclk = 55 MHz
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 20 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
V
CCA
− V
ref
(V)
1.3 2.32.11.7 1.91.5
014aaa382
1.8
1.4
2.2
2.6
(V
i
− V
i
)
(p - p)
(V)
1
(1) S/N
(2) ENOB
(3) SFDR
Fig 15. ENOB, SFDR and S/R as a function of Vref;
fclk = 55 MHz; fi = 4.43 MHz
Fig 16. ADC full-scale; VI(IN)(p-p) VI(INN)(p-p) as a
function of VCCA Vref
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 21 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
12. Application information
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
6
7
6
9
10
1112 13 14 15 16 17 18 19 20 21 22
33
32
31
30
29
28
27
26
25
24
23
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9
ADC1206S070
100 nF
100 nF100 nF
220 nF
10 nf
100 nF
100 nF
100 nF
100 Ω100 Ω
5 V
CLK
5 VSH
mode
5 V
IN
INN
1:1
5 V
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c. n.c.
Vref
5 V
IR D10
D11
(MSB) chip select input
output format select
014aaa386
The analog, digital and output supplies should be separated and decoupled.
Fig 17. Application diagram
014aaa387
ADC1206S
070
TTL
input
MC 100
ELT20 CLK
270 Ω270 Ω
CLKN
PECL
D
014aaa388
ADC1206S
070
TTL
input CLK
CLKN
Fig 18. Application diagram for differential clock input
PECL compatible using a TTL to PECL
translator
Fig 19. Application diagram for TTL single-ended
clock
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 22 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
12.1 Demonstration board
IC2
ADC1206S070
014aaa370
34
35
36
37
38
39
40
41
42
43
44
OGND
CLKN
CLK
VCCD1
DGND1
SH
AGND4
VCCA4
IN
INN
AGND1
VCCA
VCCD
VCCA
VCC
VCCO
VCC
22
21
20
19
18
17
16
15
14
13
12
VCC
VCCA
VCC
VCCA
VCC
VCCO
VCCO
33 32 31 30 29 28 27 26 25 24 23
1234567891011
VCCO
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
IR
CE
OTC
DGND2
n.c.
VCCD2
n.c.
n.c.
FSREF
MC78MO5CDT
IN OUT
ICI
GND
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24 B8
23
B11
R4
50 Ω
R3
100 Ω
FL3
FL1
FL2
C13
100 nF
C6
330 nF
C15
10 nF
R1
100 Ω
5 kΩ
FL4
C8
10 nF
C17
10 nF
C19
C1
22 μF
(20 V)
C2
4.7 μF
(16 V)
C3
1 μF
T1
TP2
TM3
R5
4.7 kΩ
C4
1 μF
R2
62 Ω
R6
2.4 KΩ
1 kΩ
S2
S4
S3
B7
B5
1.2 kΩ
C11
100 nF
C18
10 nF C5
330 nF
C12
100 nF
C16
10 nF C10
100 nF
PMBT
2222A
D2
BZV55C3V6
C14
100 nF C7
330 nF
S1
S5
R9
100 Ω
J2
J3
J1
J4
J4
1
2
BYD17G
D3
CLK2
CLK1 CLK1
IN
C9
220 nF
P1
MCLT1_6T_KK81
TR1 CMADC
12 V13
GND
R8
750 Ω
D1
LGT679
330 nF
P2 R7
CMADC
VCCA1
VCCA3
AGDN3
DEC
n.c.
n.c.
n.c.
n.c.
n.c.
Vref
C8 = close to TR1 pin.
Fig 20. Demonstration board schematic.
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 23 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
014aaa391
J4
C4 C5
D2
TP2
P2
C3
D3
R2 R5
R7 R4
R6
C11
C10 C14
P1
R1
R3
J3
J2
J1
1
1
1
1
1
112 23
34
C12
S2
S5
S1
S3 S4
B7
B4
B5 B8
B11
C7
C9
R9
FL4
FL2
T1
TM3
TM2
TM1
C2
C1
IC1
IC2
TR1
R8
D1
12
Fig 21. Component placement (top side).
014aaa392
C6
FL1
FL3
C8
C13
C17
C15
C19 C16
C18
Fig 22. Component placement (underside).
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 24 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
014aaa393
Fig 23. PCB layout (top layer).
014aaa394
Fig 24. PCB layout (ground layer).
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 25 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
014aaa395
Fig 25. PCB layout (power plane).
12.2 Alternative parts
The following alternative parts are also available:
Table 10. Alternative parts
Type number Description Sampling frequency
ADC1006S055 Single 10 bits ADC [1] 55 MHz
ADC1006S070 Single 10 bits ADC [1] 70 MHz
[1] Pin to pin compatible
12.3 Recommended companion chip
The recommended companion chip is the TDA9901 wide band differential digital
controlled variable gain amplifier.
13. Support information
13.1 Non-linearities
13.1.1 Integral Non-Linearity (INL).
It is defined as the deviation of the transfer function from a best fit straight line (linear
regression computation). The INL of the code i is obtained from the equation:
INL i Vin i Vin ideal–
S
-----------------------------------------------
=
where
i02
n1–=
and
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 26 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
S = slope of the ideal straight line = code width; i = code value.
13.1.2 Differential Non-Linearity (DNL).
It is the deviation in code width from the value of 1 LSB.
DNL i Vin i1+Vin i–
S
-------------------------------------------- 1–=
where
i02
n2–=
13.2 Dynamic parameters (single tone)
Figure 26 shows the spectrum of a full-scale input sine wave with frequency ft, conforming
to coherent sampling (ft/fs = M/N, where M is the number of cycles and N is number of
samples, M and N being relatively prime), and digitized by the ADC under test.
measured output range fs/2
014aaa389
magnitude
SFDR
a1
a2a3ak
s
Fig 26. Spectrum of full-scale input sine wave with frequency ft.
Remark: in the following equations, Pnoise is the power of the terms which include the
effects of random noise, non-linearities, sampling time errors, and “quantization noise”.
13.2.1 Signal-to-noise and distortion (SINAD)
The ratio of the output signal power to the noise-plus-distortion power for a given sample
rate and input frequency, excluding the DC component:
SINAD db 10 Psignal
Pnoise distortion+
------------------------------------------
log=
13.2.2 Effective Number Of Bits (ENOB)
It is derived from SINAD and gives the theoretical resolution an ideal ADC would require
to obtain the same SINAD measured on the real ADC. A good approximation gives:
ENOB SINAD dB176–602=
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 27 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
13.2.3 Total Harmonic Distortion (THD)
The ratio of the power of the harmonics to the power of the fundamental. For k-1
harmonics the THD is:
THD dB 10 Pharmonics
Psignal
---------------------------
log=
where
Pharmonics 2
23
2k
2
++=
Psignal 1
2
=
The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics).
13.2.4 Signal-to-Noise ratio (S/N)
The ratio of the output signal power to the noise power, excluding the harmonics and the
DC component.
S/N dB 10 Psignal
Pnoise
-----------------
log=
13.2.5 Spurious Free Dynamic Range (SFDR)
The number SFDR specifies available signal range as the spectral distance between the
amplitude of the fundamental and the amplitude of the largest spurious (harmonic and
non-harmonic, excluding DC component).
SFDR dB 20 1
max s
------------------
log=
13.3 Intermodulation distortion
13.3.1 Spectral analysis (dual-tone)
014aaa384
−80
−120
−40
0
(dB)
−160
measured output range (HHz)
0 3020105 2515
IMD3
Fig 27. Spectral analysis (dual-tone)
From a dual-tone input sinusoid (ft 1 and ft 2, these frequencies being chosen according to
the coherence criterion), the intermodulation distortion products IMD2 and IMD3
(respectively, 2nd and 3rd order components) are defined, as follows.
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 28 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
13.3.2 IMD2 (IMD3)
The ratio of the RMS value of either tone to the RMS value of the worst second (third)
order intermodulation product.
The total intermodulation distortion IMD is given by
IMD dB 10 Pintermod
Psignal
-----------------------
log=
where,
Pintermod im
2ft1 ft2
–
im
2ft1 ft2
+
im
2ft1 2ft2
–
im
2ft1 2ft2
+
im
22ft1 ft2
–
im
22ft1 ft2
+++
+
+
–=
Psignal 2ft1

2ft2
+=
and
im
2ft

is the power in the intermodulation component at frequency ft.
13.4 Noise Power Ratio (NPR)
When using a notch-filtered broadband white-noise generator as the input to the ADC
under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the
in-notch power spectral density magnitudes for the FFT spectrum of the ADC output
sample set.
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 29 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
14. Package outline
UNIT A1A2A3bpcE
(1) eH
ELL
pZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.25
0.05 1.85
1.65 0.25 0.4
0.2 0.25
0.14 10.1
9.9 0.8 1.3
12.9
12.3 1.2
0.8 10
0
o
o
0.15 0.10.15
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.95
0.55
SOT307-2 97-08-01
03-02-25
D(1) (1)(1)
10.1
9.9
HD
12.9
12.3
E
Z
1.2
0.8
D
e
E
B
11
c
E
H
D
ZD
A
ZE
e
vMA
X
1
44
34 33 23 22
12
y
θ
A1
A
Lp
detail X
L
(A )
3
A2
pin 1 index
D
HvMB
bp
bp
wM
wM
0 2.5 5 mm
scale
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2
A
max.
2.1
Fig 28. SOT307-2 (QFP44)
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 30 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
15. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
ADC1206S040_055_070_3 20120702 Product data sheet -ADC1206S040_055_070_2
ADC1206S040_055_070_2 20080812 Product data sheet -ADC1206S040_055_070_1
Modifications: Corrections made to DNL value in Table
• 1.
Corrections made to several entries in Table
• 6.
Corrections made to note in Figure
• 4.
ADC1206S040_055_070_1 20080612 Product data sheet - -
16. Contact information
For more information or sales office addresses, please visit: http://www.idt.com
3ADC1206S040_055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 31 of 31
Integrated Device Technology
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
5 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Thermal characteristics . . . . . . . . . . . . . . . . . . 6
10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6
11 Additional information relating to Table 6 . . . 13
12 Application information. . . . . . . . . . . . . . . . . . 21
12.1 Demonstration board . . . . . . . . . . . . . . . . . . . 22
12.2 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 25
12.3 Recommended companion chip . . . . . . . . . . . 25
13 Support information . . . . . . . . . . . . . . . . . . . . 25
13.1 Non-linearities . . . . . . . . . . . . . . . . . . . . . . . . 25
13.1.1 Integral Non-Linearity (INL).. . . . . . . . . . . . . . 25
13.1.2 Differential Non-Linearity (DNL). . . . . . . . . . . 26
13.2 Dynamic parameters (single tone) . . . . . . . . . 26
13.2.1 Signal-to-noise and distortion (SINAD) . . . . . 26
13.2.2 Effective Number Of Bits (ENOB) . . . . . . . . . 26
13.2.3 Total Harmonic Distortion (THD) . . . . . . . . . . 27
13.2.4 Signal-to-Noise ratio (S/N) . . . . . . . . . . . . . . . 27
13.2.5 Spurious Free Dynamic Range (SFDR). . . . . 27
13.3 Intermodulation distortion. . . . . . . . . . . . . . . . 27
13.3.1 Spectral analysis (dual-tone) . . . . . . . . . . . . . 27
13.3.2 IMD2 (IMD3) . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.4 Noise Power Ratio (NPR) . . . . . . . . . . . . . . . 28
14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 29
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 30
16 Contact information . . . . . . . . . . . . . . . . . . . . 30
17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31