2018 Microchip Technology Inc. DS20005772B-page 1
24CW16X/24CW32X/24CW64X/24CW128X
Device Selection Table
Features
• 16/32/64/128-Kbit EEPROM:
- Internally organized as one
2048/4096/8192/16384 x 8 bit block
- Byte or page writes up to 32 bytes
- Byte or sequential reads within a block
- Self-timed write cycle (5 ms maximum)
• High-Speed I2C Interface:
- Industry standard: 1 MHz, 400 kHz and
100 kHz
- Output slope control to eliminate ground
bounce
- Schmitt trigger inputs for noise suppression
• Programmable Hardware Slave Address Bits:
- Configurable via the Hardware Address
Register (HAR)
• Versatile Data Protection Options:
- Software write protection via the Write
Protection Register (WPR)
• Operating Voltage Range of 1.6V to 5.5V
• Low-Power CMOS Technology:
- Write current: 1.0 mA maximum at 5.5V
- Read current: 1.0 mA maximum at 5.5V,
1MHz
- Standby Current: 1 µA at 5.5V
• High Reliability:
- More than one million erase/write cycles
- Data retention: >200 years
- ESD protection: >4000V
• RoHS Compliant
Packages
• 8-Lead SOIC, 8-Lead TSSOP, 8-Pad UDFN,
5-Lead SOT-23 and Two 4-Ball CSP options
Package Types (not to scale)
Pin Function Table
Part Number Density Page Size VCC Range Package Temp. Ranges
24CW16X 16-Kbit 32-byte 1.6-5.5 SN, OT, ST, MUY I
24CW32X 32-Kbit 32-byte 1.6-5.5 SN, OT, ST, MUY I
24CW64X 64-Kbit 32-byte 1.6-5.5 SN, OT, ST, MUY, CS0, CS1 I
24CW128X 128-Kbit 32-byte 1.6-5.5 SN, OT, ST, MUY, CS0, CS1 I
Note: ‘X’ in the part number refers to the preset hardware slave address. Refer to Table 3-2 for additional information.
Name Function
VSS Ground
SDA Serial Data Pin
SCL Serial Clock Input
VCC Supply Voltage
8-Pad UDFN
NC
NC
VSS
NC
SDA
VCC8
7
5
1
2
4
NC 3SCL
6
(Top View)
5-Lead SOT23
(Top View)
8-Lead SOIC/TSSOP
(Top View)
(Top View)
(Top View)
SCL
VSS
SDA
S
D
A
V
CC
V
CC
V
CC
V
CC
V
SS
SDA
SCL
SCL
NC
NC
NC
Vss
VCC
NC
SCL
SDA
1
2
3
4
8
7
6
5
1
2
3
5
4
SCL
VSS
SDA
NC
VCC
Note 1: CS0 CSP ball pitch is 0.4x0.4 mm.
2: CS1 CSP ball pitch is 0.5x0.4 mm.
4-Ball CSP (CS0)(1)4-Ball CSP (CS1)(2)
16K-128K I2C Serial EEPROM with Software Write
Protection Family Data Sheet
2018 Microchip Technology Inc. DS20005772B-page 2
24CW16X/24CW32X/24CW64X/24CW128X
Description
The 24CW16X/24CW32X/24CW64X/24CW128X
(24CW Series) devices provide 16-128 Kbits of Serial
EEPROM utilizing an I2C (2-wire) serial interface. The
24CW Series is organized as 2048/4096/8192/16384
bytes of 8 bits each (2-16 Kbytes). The 24CW Series is
optimized for use in consumer and industrial applica-
tions, where reliable and dependable nonvolatile mem-
ory storage is essential. The 24CW Series allows up to
eight devices to share a common I2C (2-wire) bus and is
capable of operation across a broad voltage range (1.6V
to 5.5V).
The 24CW Series contains a pair of programmable
Configuration registers which allow certain device
behaviors to be modified. These registers are the Write
Protection Register and the Hardware Address
Register.
The Write Protection Register (WPR) controls the valid
address ranges of the EEPROM array that can be writ-
ten. This allows the user to select the write protection
behavior to be configured for software write protection.
The Hardware Address Register (HAR) controls the
three hardware slave address bits. These bits deter-
mine which device addresses the 24CW Series will
Acknowledge. Because the 24CW Series is a 4-pin
device, the cascadable feature is controlled by the
HAR.
Once the desired software write protection and hardware
slave address bits are set, these Configuration registers
can be permanently locked, thereby preventing any
further changes to the device operation.
System Configuration Using Serial EEPROMs
I2C MCU
VCC
VCC
SCL
SDA
VSS
RPUP(max) = tR(max)
0.8473 CL
RPUP(min) = VCC – VOL(max)
IOL
Programmed
as Slave 0
24CWXXXX
VCC
SDA
SCL
Programmed
as Slave 1
24CWXXXX
VCC
SDA
SCL
Programmed
as Slave 7
24CWXXXX
VCC
SDA
SCL
VSS VSS
VSS
2018 Microchip Technology Inc. DS20005772B-page 3
24CW16X/24CW32X/24CW64X/24CW128X
Block Diagram
1 page
Start
Stop
Detector
VSS
Memory
System Control
Module
High-Voltage
Generation Circuit
Data & ACK
Input/Output Control
Address Register
and Counter
Write Protection
Register
DOUT
DIN
VCC
SCL
SDA
Power-on
Reset
Generator
EEPROM Array
Column Decoder
Row Decoder
Data Register
Hardware Address
Register
2018 Microchip Technology Inc. DS20005772B-page 4
24CW16X/24CW32X/24CW64X/24CW128X
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ................................................................................................................... -0.6V to 6.5V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias...............................................................................................................-40°C to +85°C
ESD protection on all pins........................................................................................................................................ >4 kV
† NOTICE: Stresses above those listed under ‘Maximum ratings’ may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended
period of time may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS
DC CHARACTERISTICS Electrical Characteristics:
Industrial (I): VCC = 1.6V to 5.5V TA= -40°C to +85°C
Param.
No. Symbol Characteristic Min. Max. Units Test Conditions
D1 VIH High-Level Input Voltage VCC X 0.7 VCC + 0.5 V
D2 VIL Low-Level Input Voltage -0.6 VCC X 0.3 V
D3 VOL Low-Level Output Voltage — 0.4 V IOL = 2.1 mA, VCC =3.0V
—0.2VIOL = 0.15 mA, VCC =1.8V
D4 ILI Input Leakage Current — ±1 µA VIN = VSS or VCC
D5 ILO Output Leakage Current — ±1 µA VOUT =VSS or VCC
D6 CINT Internal Capacitance
(all inputs and outputs)
—7pFTAMB =+25°C, FCLK = 1 MHz,
VCC =5.5V (Note 1)
D7 ICCREAD Operating Current — 0.3 mA VCC =1.8V, FCLK = 400 kHz
—1mAVCC =5.5V, FCLK =1MHz
D8 ICCWRITE Operating Current — 1 mA VCC =5.5V, FCLK =1MHz
D9 ICCS Standby Current — 0.5 µA SCL = SDA = VCC =1.8V
— 1.0 µA SCL = SDA = VCC =5.5V
Note 1: This parameter is not tested, but is ensured by characterization.
2018 Microchip Technology Inc. DS20005772B-page 5
24CW16X/24CW32X/24CW64X/24CW128X
FIGURE 1-1: BUS TIMING DATA
TABLE 1-3: EEPROM CELL PERFORMANCE CHARACTERISTICS
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Electrical Characteristics:
Industrial (I): VCC = 1.6V to 5.5V TA = -40°C to +85°C:
Param.
No. Symbol Characteristic Min. Max. Units Conditions
1F
CLK Clock Frequency — 1000 kHz 1.6V ≤VCC ≤5.5V
2THIGH Clock High Time 260 — ns 1.6V ≤VCC ≤5.5V
3T
LOW Clock Low Time 500 — ns 1.6V ≤VCC ≤5.5V
4T
RSDA and SCL Rise Time — 1000 ns 1.6V ≤VCC ≤5.5V (Note 1)
5TFSDA and SCL Fall Time — 300 ns 1.6V ≤VCC ≤5.5V (Note 1)
6T
HD:STA Start Condition Hold Time 260 — ns 1.6V ≤VCC ≤5.5V
7T
SU:STA Start Condition Setup Time 260 — ns 1.6V ≤VCC ≤5.5V
8THD:DAT Data Input Hold Time 0 — ns (Note 2)
9T
SU:DAT Data Input Setup Time 50 — ns 1.6V ≤VCC ≤5.5V
10 TSU:STO Stop Condition Setup Time 260 — ns 1.6V ≤VCC ≤5.5V
11 TAA Output Valid from Clock — 450 ns 1.6V ≤VCC ≤5.5V
12 TBUF Bus Free Time: Bus Time
must be Free before a New
Transmission can Start
500 — ns 1.6V ≤VCC ≤5.5V
13 TSP Input Filter Spike Suppression
(SDA and SCL pins)
—50ns(Note 3)
14 TWC Write Cycle Time
(byte or page)
—5ms
Note 1: The rise/fall times must be less than the specified maximums in order to achieve the maximum clock
frequencies specified for FCLK. Please refer to the I2C specification for applicable timings.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region of
the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: Not 100% tested. CB = total capacitance of one bus line in pF.
Operation Test Condition Min. Max. Units
Write Endurance(1)TA = 25°C, 1.6V VCC 5.5V 1,000,000 — Write Cycles
Data Retention(1)TA = 55°C 200 — Years
Note 1: Performance is determined through characterization and the qualification process.
SCL
SDA
In
SDA
Out
5
7
6
13
3
2
89
11
D4 4
10
12
2018 Microchip Technology Inc. DS20005772B-page 6
24CW16X/24CW32X/24CW64X/24CW128X
1.1 Power-up Requirements and
Reset Behavior
During a power-up sequence, the VCC supplied to the
24CW Series should monotonically rise from VSS to the
minimum VCC level, as specified in Ta b le 1 - 1, with a
slew rate no faster than 0.1V/µs.
1.1.1 DEVICE RESET
To prevent write operations or other spurious events
from happening during a power-up sequence, the
24CW Series includes a Power-on Reset (POR) circuit.
Upon power-up, the device will not respond to any
commands until the VCC level crosses the internal volt-
age threshold (VPOR) that brings the device out of
Reset and into Standby mode.
The system designer must ensure that instructions are
not sent to the device until the VCC supply has reached
a stable value greater than, or equal to, the minimum
VCC level. Additionally, once the VCC is greater than, or
equal to, the minimum VCC level, the master must wait
at least TPUP before sending the first command to the
device. See Ta bl e 1 -4 for the values associated with
these power-up parameters.
If an event occurs in the system where the VCC level
supplied to the 24CW Series drops below the maxi-
mum VPOR level specified, it is recommended that a
full-power cycle sequence be performed by first driving
the VCC pin to VSS, waiting at least the minimum TPOFF
time and then perform a new power-up sequence
in compliance with the requirements defined in
Section 1.1 “Power-up Requirements and Reset
Behavior”.
TABLE 1-4: POWER-UP CONDITIONS
Symbol Parameter Min. Max. Units
TPUP Time Required after VCC is Stable before the Device can Accept Commands 100 — µs
VPOR Power-on Reset Threshold Voltage — 1.5 V
TPOFF Minimum Time at VCC = 0V between Power Cycles 1 — ms
2018 Microchip Technology Inc. DS20005772B-page 7
24CW16X/24CW32X/24CW64X/24CW128X
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
2.1 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal, therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz and 2 kΩ for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2 Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
TABLE 2-1: PIN FUNCTION TABLE
Name 8-Lead
SOIC 8-Lead
TSSOP 5-Lead
SOT23 8-Lead
UDFN(1)4-Ball CSP
(CS0)(2)4-Ball CSP
(CS1)(3)Function
NC 1 1 — 1 — — No Connect
NC 2 2 — 2 — — No Connect
NC 3 3 — 3 — — No Connect
VSS 4424A2B2Ground
SDA5535B2B1Serial Data
SCL6616B1A2Serial Clock
NC7757——No Connect
VCC 8848A1A1Device Power Supply
Note 1: The exposed pad on this package can be connected to VSS or left floating.
2: CS0 CSP ball pitch is 0.4x0.4 mm.
3: CS1 CSP ball pitch is 0.5x0.4 mm.
2018 Microchip Technology Inc. DS20005772B-page 8
24CW16X/24CW32X/24CW64X/24CW128X
3.0 MEMORY ORGANIZATION
3.1 EEPROM Organization
The 24CW Series is internally organized as
64/128/256/512 pages of 32 bytes each, depending on
the density.
3.2 Device Configuration Registers
The 24CW Series contains two Configuration registers
that modulate device operation and/or report on the
current status of the device. These registers are:
• Write Protection Register (WPR)
• Hardware Address Register (HAR)
Once the device behavior is set as desired, the Config-
uration registers can be permanently locked (or set to
read-only), thereby preventing any subsequent
changes.
3.2.1 WRITE PROTECTION REGISTER
The Write Protection Register (WPR) allows for modifi-
cation of the device write protection behavior. Refer to
Section 8.2 “Write Prote ction Register” for additional
information of the WPR.
3.2.2 HARDWARE ADDRESS REGISTER
The Hardware Address Register (HAR) allows for
modification of the hardware slave address bits in the
device address byte that the device will Acknowledge.
Refer to Section 8.3 “Hardware Address Register”
for additional information on the HAR.
3.3 Device Addressing
Communication with the 24CW Series begins with an
8-bit device address byte, comprised of a 7-bit slave
address and a Read/Write Select (R/W) bit. Since
multiple slave devices can reside on the serial bus,
each slave device must have its own unique device
address, programmed in the HAR, so that the master
can access each device independently.
The 7-bit slave address is constructed using two
groups of bits. The first four bits contain the Device
Type Identifier, followed by three bits containing the
hardware slave address bits.
The 24CW Series will respond to only specific Device
Type Identifiers, as shown in Section 3.3.1 “Valid
Device Address Byte Inputs”.
The 3-bit hardware slave address is comprised of
bits A2, A1 and A0. These bits can be used to expand
the address space by allowing up to eight devices with
the same Device Type Identifiers on the bus. These
hardware slave address bits must correlate with the
values programmed in the HAR.
The device will respond to all valid device address byte
combinations that it receives.
3.3.1 VALID DEVICE ADDRESS BYTE
INPUTS
The 24CW Series will respond to the Device Type
Identifiers, as shown in Tab le 3- 1.
3.3.1.1 Preset Slave Addresses
The 24CW Series is preset with a specific slave
address. The preset slave address bits are embedded
in the base part number, as shown in Tab l e 3- 2 .
TABLE 3-1: TABLE OF VALID DEVICE ADDRESS BYTES
Access Region Device Type Identifier Hardware Slave Address Read/Write
Select
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EEPROM 1010A2 A1 A0 R/W
Configuration Registers 1010A2 A1 A0 R/W
Note: The access region is selected according to bit 7 of the first word address byte. Refer to Section 3.3.2
“Word Ad dre s s By te s ” for additional information.
2018 Microchip Technology Inc. DS20005772B-page 9
24CW16X/24CW32X/24CW64X/24CW128X
TABLE 3-2: DEVICE PRESET SLAVE
ADDRESS 3.3.1.2 Read/Write Select Bit
The eighth bit (bit 0) of the device address byte is the
Read/Write Select (R/W) bit. A read operation is
initiated if this bit is a logic ‘1’ and a write operation is
initiated if this bit is a logic ‘0’.
Upon the successful comparison of the device address
byte, the 24CW Series will respond. If a valid compari-
son is not made, the device will not respond and return
to a standby state.
3.3.2 WORD ADDRESS BYTES
Two 8-bit word address bytes are transmitted to the
device immediately following the device address byte.
The first word address byte contains the Most Signifi-
cant bits (MSbs) of the memory array word address to
specify which location in the EEPROM to start reading
or writing. Note that the number of word address bits
depends on the density. Refer to Ta b l e 3 - 3 for details.
When accessing the memory array, it is required that
bit 7 of the word address byte be set to a logic ‘0’.
When accessing the Configuration registers, it is
required that bit 7 of the first word address byte be set
to a logic ‘1’. Refer to Tab le 3- 3 for details.
Next, the second word address byte is sent to the device
which provides the remaining eight bits of the word
address (A7 through A0). Refer to Table 3-4 for details.
TABLE 3-3: FIRST WORD ADDRESS BYTE
TABLE 3-4: SECOND WORD ADDRESS BYTE
Part Number Series
24CWXXXX
Hardware Slave
Address Bits
A2 A1 A0
24CWXXX0(1)000
24CWXXX1(1,2)001
24CWXXX2(1,2)010
24CWXXX3(1,2)011
24CWXXX4(1,2)100
24CWXXX5(1,2)101
24CWXXX6(1,2)110
24CWXXX7(1,2)111
Note 1: ‘XXX’ in the part number varies depending
on the density.
2: Contact your local sales representative for
hardware slave address availability.
Memory Region Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
16-Kbit EEPROM 0xxxxA10 A9 A8
32-Kbit EEPROM 0xxxA11 A10 A9 A8
64-Kbit EEPROM 0xxA12 A11 A10 A9 A8
128-Kbit EEPROM 0xA13 A12 A11 A10 A9 A8
Configuration Registers 1xxxxxxx
Memory Region Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
16-Kbit EEPROM A7 A6 A5 A4 A3 A2 A1 A0
32-Kbit EEPROM A7 A6 A5 A4 A3 A2 A1 A0
64-Kbit EEPROM A7 A6 A5 A4 A3 A2 A1 A0
128-Kbit EEPROM A7 A6 A5 A4 A3 A2 A1 A0
Configuration Registers(1)xxxxxxxx
Note 1: When accessing the Configuration registers, the second word address byte must be transmitted to the
device despite containing only don’t care values.
2018 Microchip Technology Inc. DS20005772B-page 10
24CW16X/24CW32X/24CW64X/24CW128X
4.0 FUNCTIONAL DESCRIPTION
The 24CW Series supports a bidirectional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The bus must be
controlled by a master which generates the Serial
Clock (SCL), controls the bus access and generates
the Start and Stop conditions, while the 24CW Series
works as a slave. Both master and slave can operate
as a transmitter or receiver, but the master determines
which mode is activated.
5.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 5-1).
5.1 Bus Not Busy (A)
Both data and clock lines remain high.
5.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
5.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
5.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master.
5.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master must generate an extra clock
pulse, which is associated with this Acknowledge bit.
See Figure 5-2 for Acknowledge timing.
A device that Acknowledges must pull down the SDA
line during the Acknowledge clock pulse, in such a way,
that the SDA line is stable low during the high period of
the Acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During read
operations, the master must signal an end of data to the
slave by NOT generating an Acknowledge (NACK) bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24CW Series) will leave the data
line high to enable the master to generate the Stop
condition.
FIGURE 5-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note: The 24CW Series does not generate
any Acknowledge bits if an internal
programming cycle is in progress.
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCL
SDA
(A) (B) (D) (D) (C) (A)
2018 Microchip Technology Inc. DS20005772B-page 11
24CW16X/24CW32X/24CW64X/24CW128X
FIGURE 5-2: ACKNOWLEDGE TIMING
5.6 Standby Mode
The 24CW Series features a low-power Standby mode
which is enabled when any one of the following occurs:
• A valid power-up sequence is performed (see
Section 1.1 “Power-up Requirements and
Reset Behavior”).
• A Stop condition is received by the device unless
it initiates an internal write cycle (see Section 6.0
“Wri te Op erations”).
• At the completion of an internal write cycle (see
Section 6.0 “Write Operations”).
• An unsuccessful match of the Device Type Identi-
fier or hardware slave address in the device
address byte occurs (see Section 3.3 “Device
Addressing”).
• The master does not Acknowledge the receipt of
data read out from the device; instead, it sends a
NACK response.(see Se ction 7.0 “Read
Operations”).
5.7 Software Reset
After an interruption in protocol, power loss or system
Reset, any 2-wire device can be protocol reset by
clocking SCL until SDA is released by the EEPROM
and goes high. The number of clock cycles until SDA is
released by the EEPROM will vary. The Software Reset
sequence should not take more than nine dummy clock
cycles. Note that the Software Reset sequence will not
interrupt the internal write cycle and only resets the I2C
interface.
Once the Software Reset sequence is complete, new
protocol can be sent to the device by sending a Start
condition, followed by the protocol. Figure 5-3
illustrates the Software Reset sequence.
In the event that the device is still non-responsive, or
remains active on the SDA bus, a power cycle must be
used to reset the device (see Section 1.1.1 “Device
Reset”).
FIGURE 5-3: SOFTWARE RESET
SCL 987654321123
Transmitter must release the SDA line at this point,
allowing the receiver to pull the SDA line low, to
Acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point so the transmitter can
continue sending data.
Data from Transmitter
SDA
Acknowledge
Bit
Data from Transmitter
Dummy Clock Cycles
12389
SCL
SDA
SDA Released
by EEPROM Device is
Software Reset
2018 Microchip Technology Inc. DS20005772B-page 12
24CW16X/24CW32X/24CW64X/24CW128X
6.0 WRITE OPERATIONS
All write operations for the 24CW Series begin with the
master sending a Start condition, followed by a device
address byte with the R/W bit set to a logic ‘0’, and then
by the word address bytes. The data value(s) to be
written to the device immediately follows the word
address bytes.
6.1 Byte Write
The 24CW Series supports the writing of a single 8-bit
byte. Selecting a data byte in the 24CW Series requires
a two-byte word address with the MSb set to a logic ‘0’.
Note that some word address bits are ignored and the
number of ignored bits depends on the device density.
Upon receipt of the proper device address and word
address bytes, the EEPROM will send an Acknowl-
edge. The device will then be ready to receive the first
8-bit data byte. Following the receipt of the data byte,
the EEPROM will respond with an Acknowledge. The
addressing device, such as a master, must then termi-
nate the write operation with a Stop condition. At that
time, the EEPROM will enter an internally self-timed
write cycle, which will be completed within TWC, while
the data byte is being programmed into the nonvolatile
EEPROM. All inputs are disabled during this write cycle
and the EEPROM will not respond until the write
operation is complete.
If an attempt is made to write to a write-protected
portion of the array, no data will be written and the
device will immediately accept a new command.
FIGURE 6-1: BYTE WRITE
SCL
134567829
MSB
1 34567829
110
A2 A1 A0
00x
A12 A11 A10 A9 A8
0
A13
0
SDA
MSB
1 34567829134567829
A4 A3 A2 A1 A0 D7 D6 D4 D3 D2 D1 D0
0
D5
0
MSB
0
Note 1: The A13, A12 and A11 word address bits are don’t care bits on the 24CW16X.
2: The A13 and A12 word address bits are don’t care bits on the 24CW32X.
3: The A13 word address bit is a don’t care bit on the 24CW64X.
Device Address Byte Word Address – Byte 0
ACK
from
Slave
ACK
from
Slave
Start
by
Master
Word Address – Byte 1 Data Byte
ACK
from
Slave
A5A6A7
ACK
from
Slave
Stop
by
Master
MSB
2018 Microchip Technology Inc. DS20005772B-page 13
24CW16X/24CW32X/24CW64X/24CW128X
6.2 Page Write
A page write operation allows up to 32 bytes to be
written in the same write cycle, provided all bytes are in
the same page of the memory array. Partial page writes
of less than 32 bytes are also allowed.
A page write is initiated the same way as a byte write,
but the master does not send a Stop condition after the
first data byte is clocked in. Instead, after the EEPROM
Acknowledges receipt of the first data byte, the master
can transmit up to 31 additional data bytes. The
EEPROM will respond with an ACK after each data
byte is received.
Once all data to be written has been sent to the device,
the master must issue a Stop condition (see
Figure 6-2). Once the Stop condition is received, an
internal write cycle will begin.
If an attempt is made to write to a write-protected
portion of the array, no data will be written and the
device will immediately accept a new command.
The lower five bits of the word address are internally
incremented following the receipt of each data byte.
The higher order address bits are not incremented and
retain the memory page location.
When the incremented word address reaches the page
boundary, the address counter will roll over to the
beginning of the same page.
FIGURE 6-2: PAGE WRITE
Note: Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multiples
of the page buffer size (or ‘page size’) and
end at the addresses that are integer
multiples of [page size – 1]. If a page write
operation attempts to write across a physi-
cal page boundary, the result is that the
data wraps around to the beginning of the
current page (overwriting data previously
stored there), instead of being written to the
next page as might be expected. It is there-
fore necessary for the application software
to prevent page write operations that would
attempt to cross a page boundary.
SCL
MSBMSB MSB
MSBMSB MSB
Note 1: The A13, A12 and A11 word address bits are don’t care bits on the 24CW16X.
2: The A13 and A12 word address bits are don’t care bits on the 24CW32X.
3: The A13 word address bit is a don’t care bit on the 24CW64X.
SDA
123456789123456789
Device Address Byte Word Address – Byte 0
1010
A2 A1 A0
000x
A13 A12 A11 A10 A9 A8
0
ACK
from
Slave
ACK
from
Slave
Start by
Master
123456789123456789123456789
A7 A6 A5 A4 A3 A2 A1 A0
0
D7 D6 D5 D4 D3 D2 D1 D0
0
D7 D6 D5 D4 D3 D2 D1 D0
0
Data Byte (n+x), Max.
of 32 without Roll Over
Data Byte (n)Word Address – Byte 1
ACK
from
Slave
Stop by
Master
ACK
from
Slave
ACK
from
Slave
2018 Microchip Technology Inc. DS20005772B-page 14
24CW16X/24CW32X/24CW64X/24CW128X
6.3 Write Cycle Timing
The length of the self-timed write cycle, or TWC, is
defined as the amount of time from the Stop condition
that begins the internal write operation, to the Start con-
dition of the first device address byte sent to the 24CW
Series that it subsequently responds to with an ACK
(see Figure 6-3).
During the internally self-timed write cycle, any
attempts to read from, or write to, the memory array will
not be processed.
FIGURE 6-3: WRITE CYCLE TIMING
First Acknowledge from the device to
a valid device address sequence after
write cycle is initiated. The minimum
TWC can only be determined through
the use of an ACK polling routine.
SCL
SDA
89
D0 ACK ACK
9
Data Word n
Stop
Condition
Stop
Condition
Start
Condition
TWC
2018 Microchip Technology Inc. DS20005772B-page 15
24CW16X/24CW32X/24CW64X/24CW128X
6.4 Acknowledge Polling
Since the device will not Acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a write opera-
tion has been issued from the master, the device initiates
the internally timed write cycle. ACK polling can be
initiated immediately. This involves the master sending a
Start condition, followed by the device address byte for a
write operation (R/W = 0). If the device is still busy with
the write cycle, then a NACK will be returned. If a NACK
is returned, then the Start bit and device address byte
must be resent. If the cycle is complete, then the device
will return the ACK and the master can then proceed
with the next read or write operation. See Figure 6-4 for
the flow diagram.
FIGURE 6-4: AC KNOWLEDGE
POLLING FLOW
Note: If the user is polling after writing to the
Hardware Address Register (HAR), the
user must send the new hardware slave
address to determine whether the write
cycle is complete. If the 24CW Series
doesn’t ACK the new hardware slave
address after the maximum write cycle
time (TWC), the write to the HAR was not
successful.
Send
Write Operation
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Device Address
byte with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
2018 Microchip Technology Inc. DS20005772B-page 16
24CW16X/24CW32X/24CW64X/24CW128X
6.5 Write Protection
The 24CW Series write protection is controlled via the
Write Protection Register (WPR). The 24CW Series is
segmented into four different memory zones, which
allows the user to select which of the zones will be soft-
ware write-protected. The protection behavior can be
made permanent by locking the Configuration registers.
For additional information on the Write Protection
Register, see Section 8.2 “Write Protection Register”.
TABLE 6-1: 24CW SERIES SOFTWARE WRITE PROTECTION
Protection Level Protected Addres s Ran ge
24CW16X 24CW32X 24CW64X 24CW128X
Upper 1/4 0600h-07FFh 0C00h-0FFFh 1800h-1FFFh 3000h-3FFFh
Upper 1/2 0400h-07FFh 0800h-0FFFh 1000h-1FFFh 2000h-3FFFh
Upper 3/4 0200h-07FFh 0400h-0FFFh 0800h-1FFFh 1000h-3FFFh
Entire Array 0000h-07FFh 0000h-0FFFh 0000h-1FFFh 0000h-3FFFh
2018 Microchip Technology Inc. DS20005772B-page 17
24CW16X/24CW32X/24CW64X/24CW128X
7.0 READ OPERATIONS
Read operations are initiated the same way as write
operations, with the exception that the Read/Write
Select (R/W) bit in the device address byte must be a
logic ‘1’. There are three read operations:
• Current Address Read
• Random Address Read
• Sequential Read
7.1 Current Address Read
The 24CW Series contains an internal Address Pointer
that maintains the word address of the last byte
accessed, internally incremented by one. Therefore, if
the previous read access was to address ‘n’ (n is any
legal address), the next current address read operation
would access data from address n+1.
A current address read operation will output data
according to the location of the internal Address
Pointer. This is initiated with a Start condition, followed
by a valid device address byte with the R/W bit set to
logic ‘1’. The device will ACK this sequence and the
current address data byte is serially clocked out on the
SDA line. All types of read operations will be terminated
if the master does not respond with an ACK (it NACKs)
during the ninth clock cycle, which will force the device
into Standby mode. After the NACK response, the
master may send a Stop condition to complete the
protocol or it can send a Start condition to begin the
next sequence.
FIGURE 7-1: CURRENT ADDRESS READ
SCL
1 34567829134567829
SDA
MSB
110
A2 A1 A0
10
D7 D6 D4 D3 D2 D1 D0
1
D5
0
MSB
Data Byte (n)Device Address Byte
Start
by
Master
ACK
from
Slave
NACK
from
Master
Stop
by
Master
2018 Microchip Technology Inc. DS20005772B-page 18
24CW16X/24CW32X/24CW64X/24CW128X
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address, with
the MSb set to logic ‘0’, to the 24CW Series as part of
a write operation (R/W bit set to ‘0’). After the word
address is sent, the master generates a Start condition
following the Acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. Then, the master issues the device address byte
again, but with the R/W bit set to a ‘1’. The 24CW
Series will then issue an Acknowledge and transmit the
8-bit data byte. The master will not Acknowledge the
transfer, but does generate a Stop condition which
causes the 24CW Series to discontinue transmission
(Figure 7-2). After a random read operation, the
internal Address Pointer will point to the last word
address location, incremented by one.
FIGURE 7-2: RANDOM READ
MSB MSB
MSBMSB MSB
123456789123456789
Device Address Byte Data Byte n
1010
A2 A1 A0
10
D7 D6 D5 D4 D3 D2 D1 D0
1
NACK
from
Slave
ACK
from
Slave
Start by
Master
123456789123456789123456789
1010
A2 A1 A0
000x
A13 A12 A11 A10 A9 A8
0
A7 A6 A5 A4 A3 A2 A1 A0
0
Word Address – Byte 0Device Address Byte
ACK
from
Slave
Stop by
Master
ACK
from
Slave
ACK
from
Slave
SCL
SDA
Word Address – Byte 1
Start by
Master
Note 1: The A13, A12 and A11 word address bits are don’t care bits on the 24CW16X.
2: The A13, A12 word address bits are don’t care bits on the 24CW32X.
3: The A13 word address bit is a don’t care bit on the 24CW64X.
2018 Microchip Technology Inc. DS20005772B-page 19
24CW16X/24CW32X/24CW64X/24CW128X
7.3 Sequential Read
A sequential read is initiated by either a current
address read or a random read. After the master
receives a data byte, the master responds with an
Acknowledge. As long as the EEPROM receives an
ACK, it will continue to increment the word address and
serially clock out the sequential data byte. When the
maximum memory address is reached, the internal
Address Pointer will automatically roll over from the
end of the array to word address, 0000h, if the master
Acknowledges the byte received from the end of the
array.
All types of read operations will be terminated if the
master does not respond with an ACK (it NACKs)
during the ninth clock cycle, which will force the device
into Standby mode. After the NACK response, the
master may send a Stop condition to complete the
protocol or it can send a Start condition to begin the
next sequence.
FIGURE 7-3: SEQUENTIAL READ
MSBMSB MSB
123456789123456789123456789
1010
A2 A1 A0
000x
A13 A12 A11 A10
A9 A8
0
A7 A6 A5 A4 A3 A2 A1 A0
0
Word Address – Byte 0Device Address Byte
ACK
from
Slave
ACK
from
Slave
ACK
from
Slave
SCL
SDA
Word Address – Byte 1
Start by
Master
MSBMSB MSB
123456789123456789123456789
1010
A2 A1 A0
10
D7 D6 D5 D4 D3 D2 D1 D0
0
D7 D6 D5 D4 D3 D2 D1 D0
0
Data Byte (n)Device Address Byte
ACK
from
Master
ACK
from
Master
ACK
from
Slave
Data Byte (n+1)
Start by
Master
MSBMSB MSB
123456789123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
0
D7 D6 D5 D4 D3 D2 D1 D0
0
D7 D6 D5 D4 D3 D2 D1 D0
1
Data Byte (n+3)Device Byte (n+2)
NACK
from
Master
ACK
from
Master
ACK
from
Master
Data Byte (n+x)
Stop by
Master
Note 1: The A13, A12 and A11 word address bits are don’t care bits on the 24CW16X.
2: The A13 and A12 word address bit are don’t care bits on the 24CW32X.
3: The A13 word address bit is a don’t care bit on the 24CW64X.
2018 Microchip Technology Inc. DS20005772B-page 20
24CW16X/24CW32X/24CW64X/24CW128X
8.0 CONFIGURATION REGISTERS
The 24CW Series device contains a pair of 8-bit
Configuration registers which control software write
protection and the hardware slave address.
The Configuration registers are accessed sequentially
as Byte 0 and Byte 1, as shown in Table 8-1.
If desired, the Configuration registers can be locked so
that the registers are set to read-only and can no longer
be modified. This makes the current software write
protection and hardware slave address scheme
permanent.
TABLE 8-1: CONFIGURATION REGISTERS
8.1 Accessing the Configuration
Registers
The value of the Configuration registers can be deter-
mined by executing a random read sequence, as
shown in Section 8.5 “Reading the Configuration
Registers”. Changing the value of the Configuration
registers is accomplished with a byte write sequence
with the requirements outlined in Section 8.4 “Writing
to the Configuration Registers”.
Accessing these registers requires the use of ‘1010b’
(Ah) as the Device Type Identifier in the device address
byte. Following the Device Type Identifier is the hard-
ware slave address bits for which the values are deter-
mined by what is currently programmed in the HAR
(see Section 8.3 “Hardware Address Register”).
Finally, bit 0 is the Read/Write Select (R/W) bit, where
a logic ‘1’ is used for reading and logic ‘0’ is used for
writing. See Table 3-1 for additional information.
When accessing the Configuration registers, the word
address must be sent to the device. All bits in the word
address are ignored, except for the MSb which must be
set to logic ‘1’. Refer to Tab l e 3- 3 and Tab le 3- 4 for
additional information.
Memory Region Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write Protection Register 0 — WRTE CCLK — WPRE WPB1 WPB0 CRLB
Hardware Address Register 1 —HWREA0CK ——A2A1A0
Note: The hardware slave address bit values are
initially factory preset but can be changed
by the user. These bit values must match
the current device configuration to receive
an Acknowledge.
2018 Microchip Technology Inc. DS20005772B-page 21
24CW16X/24CW32X/24CW64X/24CW128X
8.2 Write Protection Register
The Write Protection Register (WPR) is Byte 0 of the
sequential Configuration registers. The Write Protection
Register format can be seen in Register 8-1.
Configuration Registers Write bit (WRTE): This bit
must be set to a logic ‘1’ in order to write to the Config-
uration registers. Failure to set the WRTE bit to a logic
‘1’ will cause the device to ignore the write operation.
When reading the WPR, the WRTE bit will always read
as logic ‘0’.
Configuration Registers Check Lock bit (CCLK): This
bit must match the CRLB bit when writing the Configura-
tion registers. If the CCLK bit does not match the CRLB,
the device will ignore the write operation. When reading
the WPR, the CCLK bit will always read as logic ‘0’.
Write Protection Register Enable bit (WPRE): This
bit is used to enable or disable the device software
write protection feature. A logic ‘0’ will disable the soft-
ware write protection feature and a logic ‘1’ will enable
software write protection.
Write-Protect Block bits (WPB<1:0>): These bits
allow four levels of protection for the memory array,
provided that the WPRE bit is set to a logic ‘1’. If the
WPRE bit is a logic ‘0’, the state of the WPB<1:0> bits
has no impact on device protection. The protected
address ranges can be found in Table 8-2.
Configuration Registers Lock bit (CRLB): This bit is
used to permanently lock the current state of the WPR
and HAR. A logic ‘0’ indicates that these registers can
be modified, whereas a logic ‘1’ indicates that the WPR
and HAR have been locked and can no longer be mod-
ified. To safeguard against accidental locking of these
registers, the CCLK bit must match the CRLB bit sent
to the device. If these bits do not match, the device will
ignore the write operation.
REGISTER 8-1: WR ITE PROTECTION REGISTER – BYTE 0
U-0 W-0 W-0 U-0 R/W R/W R/W R/W
— WRTE CCLK — WPRE WPB1 WPB0 CRLB
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 WRTE: Configuration Registers Write bit
1 = Configuration registers are writable
0 = Configuration register writes are ignored
bit 5 CCLK: Configuration Registers Check Lock bit
Must match the CRLB bit when writing to the Configuration registers.
bit 4 Unimplemented: Read as ‘0’
bit 3 WPRE: Write Protection Register Enable bit
1 = Write protection is set by the WPB<1:0> bits
0 = No software write protection is enabled (Default)
bit 2-1 WPB<1:0>: Write-Protect Block bits
If WPRE = 1:
11 = Entire EEPROM is write-protected
10 = Upper 3/4 of EEPROM is write-protected
01 = Upper 1/2 of EEPROM is write-protected
00 = Upper 1/4 of EEPROM is write-protected
If WPRE = 0:
Unused (Default).
bit 0 CRLB: Configuration Registers Lock bit
1 = Configuration registers will become permanently locked
0 = Configuration registers can be written to (Default)
Note: The Configuration registers cannot be
unlocked once they are locked.
2018 Microchip Technology Inc. DS20005772B-page 22
24CW16X/24CW32X/24CW64X/24CW128X
8.2.1 SOFTWARE WRITE PROTECTION
The EEPROM array in the 24CW Series will be pro-
tected from writing in accordance with the WPB<1:0>
bits value as long as the WPRE bit is set to logic ‘1’. If
the WPRE bit is set to logic ‘0’, the WPB<1:0> bits are
ignored and no portion of the EEPROM array will be
protected. The combination of these three bits creates
five possible levels of protection for the device, as seen
in Table 8-2.
TABLE 8-2: PROTECTED ADDRESS RANGE
Protection Level WPRE WPB1 WPB0 Protected Address Rang e
24CW16X 24CW32X 24CW64X 24CW128X
None 0xx None None None None
Upper 1/4 1000600h-07FFh 0C00h-0FFFh 1800h-1FFFh 3000h-3FFFh
Upper 1/2 1010400h-07FFh 0800h-0FFFh 1000h-1FFFh 2000h-3FFFh
Upper 3/4 1100200h-07FFh 0400h-0FFFh 0800h-1FFFh 1000h-3FFFh
Entire Array 1110000h-07FFh 0000h-0FFFh 0000h-1FFFh 0000h-3FFFh
2018 Microchip Technology Inc. DS20005772B-page 23
24CW16X/24CW32X/24CW64X/24CW128X
8.3 Hardware Address Register
The Hardware Address Register (HAR) is Byte 1 of the
sequential Configuration registers. The Hardware
Address Register format can be seen in Register 8-2.
HAR Write Enable bit (HWRE): When writing to the
HAR, this bit must be set to a logic ‘1’. Failure to set the
HWRE bit to a logic ‘1’ will cause the device to ignore
the write operation. When reading the HAR, the HWRE
bit will always read as logic ‘0’.
Hardware Slave Address Check A0 bit (A0CK): This
bit must match the A0 bit when writing to the Configura-
tion registers. If the A0CK bit does not match the A0 bit,
the device will ignore the write operation. When reading
the HAR, the A0CK bit will always read as logic ‘0’.
Hardware Slave Address bits (A2, A1, A0): The 3-bit
hardware slave address is contained in bits A2, A1 and
A0 of the HAR. These bits control the valid values in
bit 3 through bit 1 (A2, A1, A0) of the device address
byte. Details of the device address byte are found in
Section 3.3 “Device Addressin g” .
REGISTER 8-2: HARDWARE ADDRESS REGISTER – BYTE 1
U-0 W-0 W-0 U-0 U-0 R/W R/W R/W
—HWREA0CK——A2A1A0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 HWRE: HAR Write Enable bit
1 = Configuration registers are writable
0 = Configuration register writes are ignored
bit 5 A0CK: Hardware Slave Address Check A0 bit
Must match A0 bit when writing the Configuration registers.
bit 4-3 Unimplemented: Read as ‘0’
bit 2 A2: Hardware Slave Address A2 bit
1 = Hardware slave address bit A2 is set to a logic ‘1’
0 = Hardware slave address bit A2 is set to a logic ‘0’
bit 1 A1: Hardware Slave Address A1 bit
1 = Hardware slave address bit A1 is set to a logic ‘1’
0 = Hardware slave address bit A1 is set to a logic ‘0’
bit 0 A0: Hardware Slave Address A0 bit
1 = Hardware slave address bit A0 is set to a logic ‘1’
0 = Hardware slave address bit A0 is set to a logic ‘0’
Note: If multiple 24CW Series devices are on
the same bus, each device must have
unique hardware slave addresses to be
accessed individually, including program-
ming the HAR. Different preset hardware
slave addresses are available. Contact
your local sales representative for details.
2018 Microchip Technology Inc. DS20005772B-page 24
24CW16X/24CW32X/24CW64X/24CW128X
8.4 Writing to the Configuration
Registers
When writing to the Configuration registers, a byte write
sequence must be sent to the device (see Section 6.1
“Byte Write” for additional information). The MSb of
the word address must be set to logic ‘1’ in order to
write to the Configuration registers.
A valid WPR byte must be provided when writing to the
Configuration registers. If the WPR byte is invalid, the
operation will abort, the EEPROM will not Acknowledge
any data bytes and the device will not execute the inter-
nal write cycle. Refer to Section 8.2 “Write Protection
Register” for valid WPR byte values.
After sending a valid WPR byte, the HAR byte can
optionally be sent. If the HAR byte is invalid, the oper-
ation will abort, the EEPROM will not Acknowledge any
data bytes and the device will not execute the internal
write cycle. Refer to Section 8.3 “H ardware Address
Register” for valid HAR byte values.
Sending more than the WPR and HAR bytes to the
24CW Series will cause the write cycle to abort and the
contents of the WPR and HAR will not be changed.
FIGURE 8-1: CONFIGURATION REGISTERS WRITE SEQUENCE
Note: If a polling routine has been implemented
and the user writes new data values to the
HAR, the user must send the new hard-
ware slave address for the device to
Acknowledge.
MSB MSB
MSBMSB MSB
123456789123456789
WPR Byte HAR Byte
x1
D5
x
D3 D2 D1 D0
0x1
D5
xx
D2 D1 D0
0
ACK
from
Slave
ACK
from
Slave
123456789123456789123456789
1010
A2 A1 A0
001xxxxxxx0xxxxxxxx0
Word Address – Byte 0Device Address Byte
ACK
from
Slave
Stop by
Master
ACK
from
Slave
ACK
from
Slave
SCL
SDA
Word Address – Byte 1
Start by
Master
Optional
2018 Microchip Technology Inc. DS20005772B-page 25
24CW16X/24CW32X/24CW64X/24CW128X
8.5 Reading the Configuration
Registers
When reading the Configuration registers, a random
read sequence must be sent to the device (see
Section 7.2 “Random Read” for additional informa-
tion). The MSb of the word address must be set to
logic ‘1’ in order to read the Configuration registers.
It is not possible to read the contents of the Configuration
registers with a current address read sequence. Due to
the sequential nature of the Configuration registers, it is
not possible to read only the HAR contents.
FIGURE 8-2: CONFIGURATION REGISTERS READ SEQUENCE
Note: The 24CW Series will automatically roll
over from the HAR (Byte 1) back to the
WPR (Byte 0) if the master continues to
Acknowledge the data bytes during the
read operation.
MSBMSB MSB
123456789123456789123456789
1010
A2 A1 A0
001xxxxxxx0xxxxxxxx0
Word Address – Byte 0Device Address Byte
ACK
from
Slave
ACK
from
Slave
ACK
from
Slave
SCL
SDA
Word Address – Byte 1
Start by
Master
MSBMSB MSB
123456789123456789123456789
1010
A2 A1 A0
100000
D3 D2 D1 D0
000000
D2 D1 D0
1
WPR ContentsDevice Address Byte
NACK
from
Master
ACK
from
Master
ACK
from
Slave
HAR Contents
Start by
Master
Stop by
Master
Optional
2018 Microchip Technology Inc. DS20005772B-page 26
24CW16X/24CW32X/24CW64X/24CW128X
8.6 Locking the Configuration
Registers
The locking mechanism of the Configuration registers
is controlled through the CLRB bit found in the WPR
byte.
When locking the Configuration registers, a byte write
sequence must be sent to the device (see Section 6.1
“Byte Write” for additional information). The MSb of
the word address must be set to logic ‘1’ in order to
write to the Configuration registers.
A valid WPR byte with the CCLK and CRLB bits set to a
logic ‘1’ must be provided when locking the Configura-
tion registers. If the WPR byte is invalid, the operation
will abort, the EEPROM will not Acknowledge any
data bytes and the device will not execute the internal
write cycle. Refer to Section 8.2 “Write Protection
Register” for valid WPR byte values.
After sending a valid WPR byte, the HAR byte can
optionally be sent. If the HAR byte is invalid, the oper-
ation will abort, the EEPROM will not Acknowledge any
data bytes and the device will not execute the internal
write cycle. Refer to Section 8.3 “H ardware Address
Register” for valid HAR byte values.
It is possible to send only the WPR byte and lock the
Configuration registers by omitting the HAR byte and
sending a Stop condition after the WPR byte.
Sending more than the WPR and HAR bytes to the
24CW Series will cause the write cycle to abort and the
contents of the WPR and HAR will not be changed.
FIGURE 8-3: CONFIGURATION REGISTER LOCK SEQUENCE
Note: The Configuration registers cannot be
unlocked once they are locked.
Note: If the HAR byte is omitted, the hardware
slave address will be locked with its
current values.
MSB MSB
MSBMSB MSB
123456789123456789
WPR Byte HAR Byte
x11x
D3 D2 D1
10x1
D5
xx
D2 D1 D0
0
ACK
from
Slave
ACK
from
Slave
123456789123456789123456789
1010
A2 A1 A0
001xxxxxxx0xxxxxxxx0
Word Address – Byte 0Device Address Byte
ACK
from
Slave
Stop by
Master
ACK
from
Slave
ACK
from
Slave
SCL
SDA
Word Address – Byte 1
Start by
Master
Optional
2018 Microchip Technology Inc. DS20005772B-page 27
24CW16X/24CW32X/24CW64X/24CW128X
9.0 DEVICE DEFAULT CONDITION
The 24CW Series is delivered with the EEPROM array
set to logic ‘1’, resulting in FFh data in all locations of
the EEPROM memory array.
The Write Protection Register (WPR) is set to 00h and
the Hardware Address Register (HAR) is preset in
accordance with the ordering code selected. For fac-
tory preset hardware slave address bits, other than
‘000b’, contact your local sales representative.
2018 Microchip Technology Inc. DS20005772B-page 28
24CW16X/24CW32X/24CW64X/24CW128X
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
NNN
8-Lead 3.9 mm SOIC Example
24CW160
SN1751
017
5-Lead SOT-23 Example
8-Lead 4.4 mm TSSOP Example
AADJ
1751
017
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
*These packages are RoHs compliant. The JEDEC designator
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
AAER18
301A8
XXXX
YYWW
NNN
2018 Microchip Technology Inc. DS20005772B-page 29
24CW16X/24CW32X/24CW64X/24CW128X
Package Marking Information (Continued)
Part Number 1st Line Marking Codes
SOIC SOT-23 TSSOP UDFN CSP (CS0)(1)CSP (CS1)(2)
24CW16 Series 24CW160 AAEN AADJ ADG — —
24CW32 Series 24CW320 AAEP AADK ADH — —
24CW64 Series 24CW640 AAEQ AADL ADJ 6 6
24CW128 Series 24CW1280 AAER AADM ADK 7 7
Note 1: CS0 CSP ball pitch is 0.4x0.4 mm.
2: CS1 CSP ball pitch is 0.5x0.4 mm.
X
NN
4-Ball 0.4x0.4 mm CSP (CS0) Example
4-Ball 0.5x0.4 mm CSP (CS1) Example
8-Lead 2x3 mm UDFN Example
6
17
X
NN 7
1A
ADH
808
17
2018 Microchip Technology Inc. DS20005772B-page 30
24CW16X/24CW32X/24CW64X/24CW128X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018 Microchip Technology Inc. DS20005772B-page 31
24CW16X/24CW32X/24CW64X/24CW128X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018 Microchip Technology Inc. DS20005772B-page 32
24CW16X/24CW32X/24CW64X/24CW128X
!"#$%
& !"#$%&"'""($)%
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2018 Microchip Technology Inc. DS20005772B-page 33
24CW16X/24CW32X/24CW64X/24CW128X
0.15 C D
2X
NOTE 1 12
N
TOP VIEW
SIDE VIEW
Microchip Technology Drawing C04-028D [OT] Sheet 1 of
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
0.20 C
C
SEATING PLANE
AA2
A1
e
NX bB
0.20 C A-B D
e1
D
E1
E1/2
E/2
E
D
A
0.20 C2X
(DATUM D)
(DATUM A-B)
A
A
SEE SHEET 2
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
2018 Microchip Technology Inc. DS20005772B-page 34
24CW16X/24CW32X/24CW64X/24CW128X
Microchip Technology Drawing C04-091D [OT] Sheet 2 of
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
c
L
L1
T
VIEW A-A
SHEET 1
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
protrusions shall not exceed 0.25mm per side.
1.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2.
Foot Angle
Number of Pins
Pitch
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint
Lead Thickness
Lead Width
Notes:
L1
I
b
c
Dimension Limits
E
E1
D
L
e1
A
A2
A1
Units
N
e
0°
0.08
0.20 -
-
-
10°
0.26
0.51
MILLIMETERS
0.95 BSC
1.90 BSC
0.30
0.90
0.89
-
0.60 REF
2.90 BSC
-
2.80 BSC
1.60 BSC
-
-
-
MIN
6
NOM
1.45
1.30
0.15
0.60
MAX
REF: Reference Dimension, usually without tolerance, for information purposes only.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Dimensioning and tolerancing per ASME Y14.5M
2018 Microchip Technology Inc. DS20005772B-page 35
24CW16X/24CW32X/24CW64X/24CW128X
RECOMMENDED LAND PATTERN
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing No. C04-2091A [OT]
Dimension Limits
Contact Pad Length (X5)
Overall Width
Distance Between Pads
Contact Pad Width (X5)
Contact Pitch
Contact Pad Spacing
3.90
1.10
G
Z
Y
1.70
0.60
MAXMIN
C
X
E
Units
NOM
0.95 BSC
2.80
MILLIMETERS
Distance Between Pads GX 0.35
1
5
X
Y
ZC
E
GX
G
2
SILK SCREEN
2018 Microchip Technology Inc. DS20005772B-page 36
24CW16X/24CW32X/24CW64X/24CW128X
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2018 Microchip Technology Inc. DS20005772B-page 37
24CW16X/24CW32X/24CW64X/24CW128X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018 Microchip Technology Inc. DS20005772B-page 38
24CW16X/24CW32X/24CW64X/24CW128X
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2018 Microchip Technology Inc. DS20005772B-page 39
24CW16X/24CW32X/24CW64X/24CW128X
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%6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
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'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
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2018 Microchip Technology Inc. DS20005772B-page 44
24CW16X/24CW32X/24CW64X/24CW128X
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2018 Microchip Technology Inc. DS20005772B-page 45
24CW16X/24CW32X/24CW64X/24CW128X
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2018 Microchip Technology Inc. DS20005772B-page 46
24CW16X/24CW32X/24CW64X/24CW128X
APPENDIX A: REVISION HISTORY
Revision A (10/2017)
Initial release of this document.
Revision B (07/2018)
Added the 24CW128X device; Updated the CSP
package drawings; Changed the 8-pad UDFN package
code from MU to MUY; Added Data Retention test
conditions; Removed Preliminary status.
2018 Microchip Technology Inc. DS20005772B-page 47
24CW16X/24CW32X/24CW64X/24CW128X
THE MICROCHIP WEBSITE
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
•Product Support – Data sheets and errata, appli-
cation notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on “Cus-
tomer Change Notification” and follow the registration
instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representa-
tive or Field Application Engineer (FAE) for support.
Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the website
at: http://microchip.com/support
2018 Microchip Technology Inc. DS20005772B-page 48
24CW16X/24CW32X/24CW64X/24CW128X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device:
24CW16
=16-Kbit I
2C Compatible Serial EEPROM with
Software Write Protection
24CW32
=32-Kbit I
2C Compatible Serial EEPROM with
Software Write Protection
24CW64
= 64-Kbit I2C Compatible Serial EEPROM with
Software Write Protection
24CW128
= 128-Kbit I2C Compatible Serial EEPROM with
Software Write Protection
Slave Address:(1)0 = Hardware Slave Address ‘000b’
1 = Hardware Slave Address ‘001b’
2 = Hardware Slave Address ‘010b’
3 = Hardware Slave Address ‘011b’
4 = Hardware Slave Address ‘100b’
5 = Hardware Slave Address ‘101b’
6 = Hardware Slave Address ‘110b’
7 = Hardware Slave Address ‘111b’
Tape and Reel
Option: Blank = Standard Packaging (tube or tray)
T = Tape and Reel(1)
Temperature
Range: I=-40C to +85C (Industrial)
Package: SN = 8-Lead Plastic Small Outline – Narrow,
3.90 mm Body
OT = 5-Lead Plastic Small Outline Transistor
ST = 8-Lead Plastic Thin Shrink Small Outline –
4.4 mm Body
MUY = 8-Lead Plastic Dual Flat, No Lead Package –
2x3x0.5 mm
CS0668 = 4-Ball Extremely Thin Fine Pitch Wafer Level
Chip Scale Package – 0.4x0.4 mm Pitch
CS1668 = 4-Ball Extremely Thin Fine Pitch Wafer Level
Chip Scale Package – 0.5x0.4 mm Pitch
Examples:
a) 24CW160-I/SN = 16-Kbit, Slave Address 0,
Industrial Temp., SOIC Package.
b) 24CW320T-I/SN = 32-Kbit, Slave Address 0, Tape
and Reel, Industrial Temp., SOIC
Package.
c) 24CW640-I/SN = 64-Kbit, Slave Address 0,
Industrial Temp., SOIC Package.
d) 24CW1280T-I/SN = 128-Kbit, Slave Address 0, Tape
and Reel, Industrial Temp., SOIC
Package.
e) 24CW320-I/ST = 32-Kbit, Slave Address 0,
Industrial Temp., TSSOP
Package.
f) 24CW640T-I/ST = 64-Kbit, Slave Address 0, Tape
and Reel, Industrial Temp.,
TSSOP Package.
g) 24CW160T-I/OT = 16-Kbit, Slave Address 0, Tape
and Reel, Industrial Temp.,
SOT-23 Package.
h) 24CW320T-I/OT = 32-Kbit, Slave Address 0, Tape
and Reel, Industrial Temp.,
SOT-23 Package.
i) 24CW1280T-I/OT = 128-Kbit, Slave Address 0, Tape
and Reel, Industrial Temp.,
SOT-23 Package.
j) 24CW320T-I/MUY = 32-Kbit, Slave Address 0, Tape
and Reel, Industrial Temp., UDFN
Package.
k) 24CW640T-I/MUY = 64-Kbit, Slave Address 0, Tape
and Reel, Industrial Temp., UDFN
Package.
l) 24CW640T-I/CS0668 = 64-Kbit, Slave Address 0, Tape
and Reel, Industrial Temp., CS0
Package.
m) 24CW640T-I/CS1668 = 64-Kbit, Slave Address 0, Tape
and Reel, Industrial Temp., CS1
Package.
n) 24CW1280T-I/CS0668= 128-Kbit, Slave Address 0, Tape
and Reel, Industrial Temp., CS0
Package.
o) 24CW1280T-I/CS1668= 128-Kbit, Slave Address 0, Tape
and Reel, Industrial Temp., CS1
Package.
Note 1: Slave Address and Tape and Reel identifiers
only appear in the catalog part number
description. These identifiers are used for
ordering purposes and are not printed on the
device package. Check with your Microchip
Sales Office for availability.
[X]
Tape and Reel
Option
X
Slave
Address
(1)
(1)
2018 Microchip Technology Inc. DS20005772B-page 49
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT
logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,
Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK
MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST
logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32
logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are
registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-
Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,
MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,
RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial
Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,
Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3332-3
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’ s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, micro perip hera ls, n onvolat ile memory and
analog products . In add ition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
2018 Microchip Technology Inc. DS20005772B-page 50
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
ASIA/PACIFIC
Australia - Sydney
Tel: 61-2-9868-6733
China - Beijing
Tel: 86-10-8569-7000
China - Chengdu
Tel: 86-28-8665-5511
China - Chongqing
Tel: 86-23-8980-9588
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
China - Hong Kong SAR
Tel: 852-2943-5100
China - Nanjing
Tel: 86-25-8473-2460
China - Qingdao
Tel: 86-532-8502-7355
China - Shanghai
Tel: 86-21-3326-8000
China - Shenyang
Tel: 86-24-2334-2829
China - Shenzhen
Tel: 86-755-8864-2200
China - Suzhou
Tel: 86-186-6233-1526
China - Wuhan
Tel: 86-27-5980-5300
China - Xian
Tel: 86-29-8833-7252
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
India - New Delhi
Tel: 91-11-4160-8631
India - Pune
Tel: 91-20-4121-0141
Japan - Osaka
Tel: 81-6-6152-7160
Japan - Tokyo
Tel: 81-3-6880- 3770
Korea - Daegu
Tel: 82-53-744-4301
Korea - Seoul
Tel: 82-2-554-7200
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Malaysia - Penang
Tel: 60-4-227-8870
Philippines - Manila
Tel: 63-2-634-9065
Singapore
Tel: 65-6334-8870
Taiwan - Hsin Chu
Tel: 886-3-577-8366
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Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Thailand - Bangkok
Tel: 66-2-694-1351
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-67-3636
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7289-7561
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
10/25/17
