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FDB070AN06A0 N-Channel PowerTrench(R) MOSFET 60 V, 80 A, 7 m Features Applications * RDS(on) = 6.1 m ( Typ.) @ VGS = 10 V, ID = 80 A * Synchronous Rectification for ATX / Server / Telecom PSU * Qg(tot) = 51 nC ( Typ.) @ VGS = 10 V * Battery Protection Circuit * Low Miller Charge * Motor Drives and Uninterruptible Power Supplies * Low Qrr Body Diode * UIS Capability (Single Pulse and Repetitive Pulse) Formerly developmental type 82567 D D G G D2-PAK S S MOSFET Maximum Ratings TC = 25C unless otherwise noted Symbol Parameter FDB070AN06A0 Unit V DSS Drain to Source Voltage 60 V VGS Gate to Source Voltage 20 V 80 A 15 A Drain Current ID Continuous (TC < 97oC, VGS = 10V) o o Continuous (TA = 25 C, VGS = 10V, R JA = 43 C/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Figure 4 A 190 mJ 175 Derate above 25oC Operating and Storage Temperature W 1.17 W/oC -55 to 175 C o Thermal Characteristics RJC Thermal Resistance Junction to Case, Max. RJA Thermal Resistance Junction to Ambient, Max. (Note 2) RJA 0.86 Thermal Resistance Junction to Ambient, Max., (c)2003 Fairchild Semiconductor Corporation FDB070AN06A0 Rev. C2 1 1in2 copper pad area oC/W 62 o C/W 43 o C/W www.fairchildsemi.com FDB070AN06A0 -- N-Channel PowerTrench(R) MOSFET October 2013 Device Marking FDB070AN06A0 Device FDB070AN06A0 Package D2-PAK Reel Size 330 mm Tape Width 24 mm Quantity 800 units Electrical Characteristics TC = 25C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit V Off Characteristics B VDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250A, VGS = 0V 60 - - - - 1 - - 250 VGS = 20V - - 100 nA VGS = VDS, ID = 250A 2 - 4 V - 0.0061 0.007 ID = 80A, VGS = 10V, TJ = 175oC - 0.0127 0.015 - 3000 - - 510 - pF - 230 - pF 51 66 nC - 5.4 7 nC - 17 - nC - 11.6 - nC - 16 - nC V DS = 50V VGS = 0V TC = 150oC A On Characteristics VGS(TH) Gate to Source Threshold Voltage rDS(ON) Drain to Source On Resistance ID = 80A, VGS = 10V Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance V DS = 25V, VGS = 0V, f = 1MHz Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V Qg(TH) Threshold Gate Charge VGS = 0V to 2V Qgs Gate to Source Gate Charge Qgs2 Gate Charge Threshold to Plateau Qgd Gate to Drain "Miller" Charge VDD = 30V ID = 80A Ig = 1.0mA pF Switching Characteristics (VGS = 10V) tON Turn-On Time - - 256 ns Turn-On Delay Time - 12 - ns tr Rise Time - 159 - ns - 27 - ns tf Fall Time - 35 - ns Turn-Off Time - - 93 ns td(ON) td(OFF) Turn-Off Delay Time tOFF V DD = 30V, ID = 80A V GS = 10V, RGS = 5.6 Drain-Source Diode Characteristics ISD = 80A - - 1.25 V ISD = 40A - - 1.0 V Reverse Recovery Time ISD = 75A, dISD/dt = 100A/s - - 34 ns Reverse Recovered Charge ISD = 75A, dISD/dt = 100A/s - - 35 nC V SD Source to Drain Diode Voltage trr QRR Notes: 1: Starting TJ = 25C, L = 93H, I AS = 64A. 2: Pulse width = 100s. (c)2003 Fairchild Semiconductor Corporation FDB070AN06A0 Rev. C2 2 www.fairchildsemi.com FDB070AN06A0 -- N-Channel PowerTrench(R) MOSFET Package Marking and Ordering Information 1.2 120 1.0 100 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER CURRENT LIMITED BY PACKAGE 0.8 0.6 0.4 0.2 80 60 40 20 0 0 0 25 50 75 100 150 125 175 25 50 75 TC , CASE TEMPERATURE (o C) 100 125 TC, CASE TEMPERATURE Figure 1. Normalized Power Dissipation vs Ambient Temperature 150 175 (oC) Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 ZJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t , RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 2000 TC = 25oC FOR TEMPERATURES 1000 IDM, PEAK CURRENT (A) ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 VGS = 10V 150 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 100 50 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability (c)2003 Fairchild Semiconductor Corporation FDB070AN06A0 Rev. C2 3 www.fairchildsemi.com FDB070AN06A0 -- N-Channel PowerTrench(R) MOSFET Typical Characteristics TC = 25C unless otherwise noted 1000 500 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10s 100s 100 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 10ms DC 1 SINGLE PULSE TJ = MAX RATED TC = 25o C 100 STARTING TJ = 25oC 10 STARTING TJ = 150 oC 1 0.01 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 160 VGS = 10V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 100 Figure 6. Unclamped Inductive Switching Capability 120 80 TJ = 25 oC 40 TJ = VGS = 7V 120 VGS = 6V 80 TC = 25o C PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 40 -55oC VGS = 5V 0 0 4.0 4.5 5.0 5.5 6.0 6.5 VGS , GATE TO SOURCE VOLTAGE (V) 0 7.0 0.5 1.0 1.5 2.0 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics 16 2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE(m) 10 NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V TJ = 175oC 1 tAV, TIME IN AVALANCHE (ms) Figure 5. Forward Bias Safe Operating Area 160 0.1 14 12 VGS = 6V 10 8 VGS = 10V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 VGS = 10V, ID =80A 0.5 -80 6 0 20 40 60 ID, DRAIN CURRENT (A) 80 Figure 9. Drain to Source On Resistance vs Drain Current (c)2003 Fairchild Semiconductor Corporation FDB070AN06A0 Rev. C2 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (o C) 160 200 Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature 4 www.fairchildsemi.com FDB070AN06A0 -- N-Channel PowerTrench(R) MOSFET Typical Characteristics TC = 25C unless otherwise noted 1.2 1.10 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250A 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 1.05 1.00 0.95 0.90 -80 200 -40 TJ, JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 80 120 160 200 VGS , GATE TO SOURCE VOLTAGE (V) 10 CISS = C GS + CGD C, CAPACITANCE (pF) 40 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10000 COSS C DS + C GD 1000 CRSS = CGD VGS = 0V, f = 1MHz 100 0.1 0 TJ , JUNCTION TEMPERATURE (o C) 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 80A ID = 15A 2 0 0 60 10 20 30 40 50 60 Qg, GATE CHARGE (nC) Figure 13. Capacitance vs Drain to Source Voltage (c)2003 Fairchild Semiconductor Corporation FDB070AN06A0 Rev. C2 VDD = 30V Figure 14. Gate Charge Waveforms for Constant Gate Current 5 www.fairchildsemi.com FDB070AN06A0 -- N-Channel PowerTrench(R) MOSFET Typical Characteristics TC = 25C unless otherwise noted VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01 tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19. Switching Time Test Circuit (c)2003 Fairchild Semiconductor Corporation FDB070AN06A0 Rev. C2 90% + VGS RGS tf 50% 10% PULSE WIDTH 50% Figure 20. Switching Time Waveforms 6 www.fairchildsemi.com FDB070AN06A0 -- N-Channel PowerTrench(R) MOSFET Test Circuits and Waveforms The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RJA = 26.51+ 19.84/(0.262+Area) EQ.2 RJA = 26.51+ 128/(1.69+Area) EQ.3 60 RJA (o C/W) (T -T ) JM A P D M = ----------------------------R JA 80 (EQ. 1) 40 In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of P DM is complex and influenced by many factors: 20 0.1 1 10 (0.645) (6.45) AREA, TOP COPPER AREA in2 (cm2 ) (64.5) Figure 21. Thermal Resistance vs Mounting Pad Area 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. R JA 19.84 ( 0.262 + Area ) (EQ. 2) = 26.51 + ------------------------------------- Area in Inches Squared R JA 128 ( 1.69 + Area ) (EQ. 3) = 26.51 + ---------------------------------- Area in Centimeters Squared (c)2003 Fairchild Semiconductor Corporation FDB070AN06A0 Rev. C2 7 www.fairchildsemi.com FDB070AN06A0 -- N-Channel PowerTrench(R) MOSFET Thermal Resistance vs. Mounting Pad Area .SUBCKT FDB070AN06A0 2 1 3 ; rev March 2003 Ca 12 8 1.5e-9 Cb 15 14 1.5e-9 Cin 6 8 2.9e-9 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 5 51 ESLC EVTHRES + 19 8 + LGATE GATE 1 Lgate 1 9 4.8e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 3e-9 EVTEMP RGATE + 18 22 9 20 21 + 17 EBREAK 18 - 16 DBODY MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 7 SOURCE 3 RSOURCE RLSOURCE RLgate 1 9 48 RLdrain 2 5 10 RLsource 3 7 3 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD 11 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 62 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 DRAIN 2 5 S1A 12 S2A 13 8 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1.3e-3 Rgate 9 20 2.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 3.1e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD 5 8 EDS - 19 VBAT + IT 14 + + - 8 22 RVTHRES Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10))} .MODEL DbodyMOD D (IS=7.6E-12 N=1.04 RS=2.2e-3 TRS1=2.7e-3 TRS2=2e-7 + CJO=1.6e-9 M=0.55 TT=5e-12 XTI=3.9) .MODEL DbreakMOD D (RS=8e-1 TRS1=5e-4 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.05e-9 IS=1e-30 N=10 M=0.45) .MODEL MmedMOD NMOS (VTO=3.7 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.7) .MODEL MstroMOD NMOS (VTO=4.7 KP=100 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=3.01 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=27 RS=0.1) .MODEL RbreakMOD RES (TC1=7.1e-4 TC2=-5.5e-7) .MODEL RdrainMOD RES (TC1=1.7e-2 TC2=4e-5) .MODEL RSLCMOD RES (TC1=3e-3 TC2=1e-5) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-5.2e-3 TC2=-1.5e-5) .MODEL RvtempMOD RES (TC1=-3e-3 TC2=1.3e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1.5) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2003 Fairchild Semiconductor Corporation FDB070AN06A0 Rev. C2 8 www.fairchildsemi.com FDB070AN06A0 -- N-Channel PowerTrench(R) MOSFET PSPICE Electrical Model rev March 2003 template FDB070AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=7.6e-12,nl=1.04,rs=2.2e-3,trs1=2.7e-3,trs2=2e-7,cjo=1.6e-9,m=0.55,tt=5e-12,xti=3.9) dp..model dbreakmod = (rs=8e-1,trs1=5e-4,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.05e-9,isl=10e-30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=3.7,kp=10,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.7,kp=100,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.01,kp=0.03,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-2) DPLCAP 5 DRAIN sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4) 2 10 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=0.5) RLDRAIN sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1.5) RSLC1 51 c.ca n12 n8 = 1.5e-9 RSLC2 c.cb n15 n14 = 1.5e-9 ISCL c.cin n6 n8 = 2.9e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 62 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 DBREAK 50 - EVTEMP RGATE + 18 22 9 20 21 11 DBODY 16 MWEAK 6 EBREAK + 17 18 - MMED MSTRO RLGATE CIN 8 LSOURCE 7 SOURCE 3 RSOURCE i.it n8 n17 = 1 RLSOURCE S1A 12 l.lgate n1 n9 = 4.8e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 3e-9 res.rlgate n1 n9 = 48 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 3 S2A 13 8 15 14 13 S1B RBREAK 17 18 RVTEMP S2B 13 CA CB + 6 8 EGS - 19 IT 14 + VBAT 5 8 EDS - m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u + 8 22 RVTHRES res.rbreak n17 n18 = 1, tc1=7.1e-4,tc2=-5.5e-7 res.rdrain n50 n16 = 1.3e-3, tc1=1.7e-2,tc2=4e-5 res.rgate n9 n20 = 2.7 res.rslc1 n5 n51 = 1e-6, tc1=3e-3,tc2=1e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.1e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-5.2e-3,tc2=-1.5e-5 res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1.3e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10)) } } (c)2003 Fairchild Semiconductor Corporation FDB070AN06A0 Rev. C2 9 www.fairchildsemi.com FDB070AN06A0 -- N-Channel PowerTrench(R) MOSFET SABER Electrical Model th REV 23 March 2003 JUNCTION FDB070AN06A0T CTHERM1 TH 6 3.5e-3 CTHERM2 6 5 1.7e-2 CTHERM3 5 4 1.8e-2 CTHERM4 4 3 1.9e-2 CTHERM5 3 2 4.7e-2 CTHERM6 2 TL 7e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 2e-2 RTHERM2 6 5 7e-2 RTHERM3 5 4 1e-1 RTHERM4 4 3 1.5e-1 RTHERM5 3 2 1.6e-1 RTHERM6 2 TL 1.85e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDB070AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =3.5e-3 ctherm.ctherm2 6 5 =1.7e-2 ctherm.ctherm3 5 4 =1.8e-2 ctherm.ctherm4 4 3 =1.9e-2 ctherm.ctherm5 3 2 =4.7e-2 ctherm.ctherm6 2 tl =7e-2 RTHERM3 CTHERM3 4 RTHERM4 rtherm.rtherm1 th 6 =2e-2 rtherm.rtherm2 6 5 =7e-2 rtherm.rtherm3 5 4 =1e-1 rtherm.rtherm4 4 3 =1.5e-1 rtherm.rtherm5 3 2 =1.6e-1 rtherm.rtherm6 2 tl =1.85e-1 } CTHERM4 3 RTHERM5 CTHERM5 2 CTHERM6 RTHERM6 tl (c)2003 Fairchild Semiconductor Corporation FDB070AN06A0 Rev. C2 10 CASE www.fairchildsemi.com FDB070AN06A0 -- N-Channel PowerTrench(R) MOSFET SPICE Thermal Model FDB070AN06A0 -- N-Channel PowerTrench(R) MOSFET Mechanical Dimensions TO-263 2L (D2PAK) Figure 22. 2LD, TO263, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TT263-002 Dimension in Millimeters (c)2003 Fairchild Semiconductor Corporation FDB070AN06A0 Rev. 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