2015 Microchip Technology Inc. DS50002393A
EVB-LAN9353
Evaluation Board
User’s Guide
DS50002393A-page 2 2015 Microchip Technology Inc.
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MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and
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Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK,
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All other trademarks mentioned herein are property of their respective companies.
© 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-587-0
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• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
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Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
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and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
2015 Microchip Technology Inc. DS50002393A-page 3
EVB-LAN9353 Evaluation Board User’s Guide
Object of Declaration: EVB-LAN9353
2015 Microchip Technology Inc. DS50002393A-page 4
EVB-LAN9353 Evaluation Board User’s Guide
NOTES:
EVB-LAN9353
EVALUATION BOARD
USER’S GUIDE
2015 Microchip Technology Inc. DS50002393A-page 5
Table of Contents
Preface ........................................................................................................................... 7
Introduction............................................................................................................ 7
Document Layout .................................................................................................. 7
Conventions Used in this Guide ............................................................................ 8
The Microchip Web Site ........................................................................................ 9
Development Systems Customer Change Notification Service ............................ 9
Customer Support ................................................................................................. 9
Document Revision History ................................................................................. 10
Chapter 1. Overview
1.1 Introduction ................................................................................................... 11
1.1.1 References ................................................................................................ 13
1.1.2 Terms and Abbreviations .......................................................................... 14
Chapter 2. Board Details
2.1 Board Details ................................................................................................ 15
2.1.1 Power ........................................................................................................ 15
2.1.2 Power-on Reset ......................................................................................... 15
2.1.3 Clock .......................................................................................................... 16
Chapter 3. Board Configuration
3.1 Strap Options ............................................................................................... 17
3.1.1 Jumpers J4:J15 ......................................................................................... 17
3.1.1.1 GPIO/LED POL/LED Configurations ......................................... 18
3.1.1.2 Serial Management Mode Configuration ................................... 19
3.1.1.3 EEPROM Size Configuration ..................................................... 19
3.1.1.4 Energy-Efficient Ethernet Configuration .................................... 19
3.1.1.5 1588 Enable Configuration ........................................................ 20
3.1.1.6 PHY Address Configuration ....................................................... 20
3.1.2 GPIO 6 & GPIO 7 Input and Output Configurations .................................. 20
3.1.3 Jumper Settings for CONFIG 9 or CONFIG 10 ......................................... 21
3.1.4 Link Partner Duplex/Speed Configurations ............................................... 21
3.1.5 P0/P1 Configurations ................................................................................ 22
3.1.6 RMII RX Clock Configurations ................................................................... 24
3.1.7 GPIO Header ............................................................................................. 24
3.1.8 I2C Aardvark Header ................................................................................. 25
3.1.9 Copper and Fiber Mode Selections ........................................................... 25
3.1.9.1 Copper Mode ............................................................................. 25
3.1.9.2 Fiber Mode ................................................................................ 25
3.1.9.3 FX-LOS Fiber Mode Strap ......................................................... 26
3.2 LEDs ............................................................................................................. 26
3.3 Test Points ................................................................................................... 27
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 6 2015 Microchip Technology Inc.
3.4 Mechanicals ................................................................................................. 27
Appendix A. EVB-LAN9353 Evaluation Board
A.1 Introduction .................................................................................................. 28
Appendix B. EVB-LAN9353 Evaluation Board Schematics
B.1 Introduction .................................................................................................. 29
Appendix C. Bill of Materials (BOM)
C.1 Introduction .................................................................................................. 39
Wordwide Sales and Service ......................................................................................43
EVB-LAN9353
EVALUATION BOARD
USER’S GUIDE
2015 Microchip Technology Inc. DS50002393A-page 7
Preface
INTRODUCTION
This chapter contains general information that will be useful to know before using the
EVB-LAN9353. Items discussed in this chapter include:
•Document Layout
•Conventions Used in this Guide
•The Microchip Web Site
•Development Systems Customer Change Notification Service
•Customer Support
•Document Revision History
DOCUMENT LAYOUT
This document describes how to use the EVB-LAN9353 Evaluation Board as a
development tool for the LAN9353 three-port 10/100 managed Ethernet switch. The
manual layout is as follows:
•Chapter 1. “Overview” – Shows a brief description of the EVB-LAN9353 Evalua-
tion Board.
•Chapter 2. “Getting Started” – Includes instructions on how to get started with
the EVB-LAN9353 Evaluation Board.
•Chapter 3. “Board Configuration” – Provides information about the
EVB-LAN9353 Evaluation Board battery charging features.
•Appendix A. “EVB-LAN9353 Evaluation Board” – This appendix shows the
EVB-LAN9353 Evaluation Board.
•Appendix B. “EVB-LAN9353 Evaluation Board Schematics” – This appendix
shows the EVB-LAN9353 Evaluation Board schematics.
•Appendix C. “Bill of Materials (BOM)” – This appendix includes the
EVB-LAN9353 Evaluation Board Bill of Materials (BOM).
NOTICE TO CUSTOMERS
All documentation becomes dated, and this manual is no exception. Microchip tools and
documentation are constantly evolving to meet customer needs, so some actual dialogs
and/or tool descriptions may differ from those in this document. Please refer to our web site
(www.microchip.com) to obtain the latest documentation available.
Documents are identified with a “DS” number. This number is located on the bottom of each
page, in front of the page number. The numbering convention for the DS number is
“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the
document.
For the most up-to-date information on development tools, see the MPLAB® IDE online help.
Select the Help menu, and then Topics to open a list of available online help files.
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 8 2015 Microchip Technology Inc.
CONVENTIONS USED IN THIS GUIDE
This manual uses the following documentation conventions:
DOCUMENTATION CONVENTIONS
Description Represents Examples
Arial font:
Italic characters Referenced books MPLAB® IDE User’s Guide
Emphasized text ...is the only compiler...
Initial caps A window the Output window
A dialog the Settings dialog
A menu selection select Enable Programmer
Quotes A field name in a window or
dialog
“Save project before build”
Underlined, italic text with
right angle bracket
A menu path File>Save
Bold characters A dialog button Click OK
A tab Click the Power tab
N‘Rnnnn A number in verilog format,
where N is the total number of
digits, R is the radix and n is a
digit.
4‘b0010, 2‘hF1
Text in angle brackets < > A key on the keyboard Press <Enter>, <F1>
Courier New font:
Plain Courier New Sample source code #define START
Filenames autoexec.bat
File paths c:\mcc18\h
Keywords _asm, _endasm, static
Command-line options -Opa+, -Opa-
Bit values 0, 1
Constants 0xFF, ‘A’
Italic Courier New A variable argument file.o, where file can be
any valid filename
Square brackets [ ] Optional arguments mcc18 [options] file
[options]
Curly brackets and pipe
character: { | }
Choice of mutually exclusive
arguments; an OR selection
errorlevel {0|1}
Ellipses... Replaces repeated text var_name [,
var_name...]
Represents code supplied by
user
void main (void)
{ ...
}
Preface
2015 Microchip Technology Inc. DS50002393A-page 9
THE MICROCHIP WEB SITE
Microchip provides online support via our web site at www.microchip.com. This web
site is used as a means to make files and information easily available to customers.
Accessible by using your favorite Internet browser, the web site contains the following
information:
•Product Support – Data sheets and errata, application notes and sample
programs, design resources, user’s guides and hardware support documents,
latest software releases and archived software
•General Technical Support – Frequently Asked Questions (FAQs), technical
support requests, online discussion groups, Microchip consultant program
member listing
•Business of Microchip – Product selector and ordering guides, latest Microchip
press releases, listing of seminars and events, listings of Microchip sales offices,
distributors and factory representatives
DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip
products. Subscribers will receive e-mail notification whenever there are changes,
updates, revisions or errata related to a specified product family or development tool of
interest.
To register, access the Microchip web site at www.microchip.com, click on Customer
Change Notification and follow the registration instructions.
The Development Systems product group categories are:
•Compilers – The latest information on Microchip C compilers, assemblers, linkers
and other language tools. These include all MPLAB C compilers; all MPLAB
assemblers (including MPASM assembler); all MPLAB linkers (including MPLINK
object linker); and all MPLAB librarians (including MPLIB object librarian).
•Emulators – The latest information on Microchip in-circuit emulators.This
includes the MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators.
•In-Circuit Debuggers – The latest information on the Microchip in-circuit
debuggers. This includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug
express.
•MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows
Integrated Development Environment for development systems tools. This list is
focused on the MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and
MPLAB SIM simulator, as well as general editing and debugging features.
•Programmers – The latest information on Microchip programmers. These include
production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB
ICD 3 in-circuit debugger and MPLAB PM3 device programmers. Also included
are nonproduction development programmers such as PICSTART Plus and
PIC-kit 2 and 3.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 10 2015 Microchip Technology Inc.
Customers should contact their distributor, representative or field application engineer
(FAE) for support. Local sales offices are also available to help customers. A listing of
sales offices and locations is included in the back of this document.
Technical support is available through the web site at:
http://www.microchip.com/support
DOCUMENT REVISION HISTORY
Revision A (July 2015)
• Initial Release of this Document.
EVB-LAN9353
EVALUATION BOARD
USER’S GUIDE
2015 Microchip Technology Inc. DS50002393A-page 11
Chapter 1. Overview
1.1 INTRODUCTION
The LAN9353 is a fully featured, three-port 10/100 managed Ethernet switch designed
for industrial and embedded applications where performance, flexibility, ease of inte-
gration and system cost control are required.
The LAN9353 combines all the functions of a 10/100 switch system, including the
switch fabric, packet buffers, buffer manager, media access controllers (MACs), PHY
transceivers, and serial management. IEEE 1588v2 is supported via the integrated
IEEE 1588v2 hard-ware time stamp unit, which supports end-to-end and peer-to-peer
transparent clocks.
The LAN9353 complies with the IEEE 802.3 (full/half-duplex 10BASE-T and
100BASE-TX) Ethernet protocol, IEEE 802.3az Energy Efficient Ethernet (EEE)
(100Mbps only), and 802.1D/802.1Q management protocol specifications, enabling
compatibility with industry standard Ethernet and Fast Ethernet applications.
100BASE-FX is supported via an external fiber transceiver and cable diagnostics
(short, open and length) is included on the internal twisted pair copper interface.
The EVB-LAN9353 is an Evaluation Board (EVB) that utilizes the LAN9353 to provide
a fully-functional three-port Ethernet switch with Single MII/RMII/Turbo MII or Dual
RMII. The EVB-LAN9353 provides one fully integrated MAC/PHY internet port (Port 2)
via on-board RJ45 connectors. Port 0 and Port 1 provides two MII port connectors
which support the following:
• An external “Dual RMII –Capable or singleMII / RMII / Turbo MII”-Capable MAC
(with LAN9353 in PHY mode), via the on-board 40-pin male MII connector
• An external “Dual RMII –Capable or singleMII / RMII / Turbo MII”-Capable PHY
(with LAN9353 in MAC mode), via the on-board 40-pin female MII connector
Power is supplied to the board via a +5V external wall mount power supply.
The EVB-LAN9353 includes a 64K x 8 I2C EEPROM that may be used to automatically
load configuration settings from the EEPROM into the device at reset. An I2C host
adapter interface header (10-pin, 2x5) is provided to simplify I2C based configuration.
A simplified block diagram of the EVB LAN9353 can be seen in Error! Reference
source not found and LAN9353 supports for CONFIG 9 or CONFIG 10.
CONFIG 9: used to configure the LAN9353 in Dual RMII mode for external ports.
CONFIG 10: used to configure the LAN9353 in Single MII/RMII/TMII mode for external
port.
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 12 2015 Microchip Technology Inc.
FIGURE 1-1: EVB-LAN9353 BLOCK DIAGRAM (CONFIG 9)
Microchip
LAN9353
Straps
Jumpers
I2C EEPROM
Mode
Switch
Crystal
Reset
Power Supply
Module
Port 2
Port 1 Port 0
10/100
Ethernet
Magnetics &
RJ45
Fiber
Transceiver
(SFP)
40 pin MII
Connector
(Male)
40 pin MII
Connector
(Female)
40 pin MII
Connector
(Female)
40 pin MII
Connector
(Male)
RMII RMII
5V
To External
MAC
To External
PHY
To External
PHY
To External
MAC
Ethernet
2015 Microchip Technology Inc. DS50002393A-page 13
FIGURE 1-2: EVB-LAN9353 BLOCK DIAGRAM (CONFIG 10)
1.1.1 References
Concepts and material available in the following documents may be helpful when read-
ing this document. Visit www.microchip.com for the latest documentation.
Document Location
LAN9353 datasheet Visit www.microchip.com
AN8-13 Suggested Mag-
netics
http://www.microchip.com/wwwAp-
pNotes/AppNotes.aspx?appnote=en562793
EVB-LAN9353 Evalua-
tion Board Schematic
Visit www.microchip.com
Microchip
LAN9353
Straps
Jumpers
I2C EEPROM
Mode
Switch
Crystal
Reset
Power Supply
Module
Port 2
Port 0
10/100
Ethernet
Magnetics &
RJ45
Fiber
Transceiver
(SFP)
40 pin MII
Connector
(Female)
40 pin MII
Connector
(Male)
MII/RMII/TMII
5V
To External
PHY
To External
MAC
Ethernet
Fiber
Transceiver
(SFP)
10/100
Ethernet
Magnetics &
RJ45
Ethernet
Port 1
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 14 2015 Microchip Technology Inc.
1.1.2 Terms and Abbreviations
•EVB - Evaluation Board
•DNP - Do Not Populate
•100BASE-TX - 100 Mbps Fast Ethernet, IEEE802.3u Compliant
•GPIO - General Purpose I/O
•MII - Media Independent Interface
•RMII - Reduced Media Independent Interface
•EEE - Energy-Efficient Ethernet
•SFP - Small Form-factor Pluggable
•SFF - Small Form Factor
•SMI - Serial Management Interface
EVB-LAN9353
EVALUATION BOARD
USER’S GUIDE
2015 Microchip Technology Inc. DS50002393A-page 15
Chapter 2. Board Details
2.1 BOARD DETAILS
The following sections describe the various board features, including jumpers, LEDs,
test points, system connections, and switches. A top view of the EVB-LAN9353 is
shown in Figure 2-1.
FIGURE 2-1: LAN9353 BOARD REV-A
2.1.1 Power
DC 5V is applied through (J1) DC Socket, powered by a +5V external wall adapter.
switch (SW1) need to be ON position for the 5V to reach the 3.3V regulator. Glowing of
Green LED (D1) indicates successful generation of 3.3V o/p. This Power is supplied to
the LAN9353 and it has internal 1.2 V regulator which supplies power to the internal
core logic.
2.1.2 Power-on Reset
A power-on reset occurs whenever power is initially applied to the LAN9353 or if the
power is removed and reapplied to the LAN9353. This event resets all circuitry within
the LAN9353. After initial power-on, the LAN9353 can be reset by pressing the reset
switch (SW2). The reset LED D2 will assert (red) when the LAN9353 is in reset condi-
tion.
Port 1**
(with integrated
magnetics & LEDs)
Port 2
(with integrated
magnetics & LEDs)
ResetPowerMode SwitchStra
p
EEPROM
Port 1** (Female)
MII Connector
Port 1** (Male)
MII Connector
Microchip
LAN9353
Port 0 (Female)
MII Connector
Port 0 (Male)
MII Connector
Note: Config 10: Port 1 and Port 2 both are Internal, Port 0 External.
Config 9: Only Port 2 Internal, Port 0 and Port 1 are External.
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 16 2015 Microchip Technology Inc.
For stability, a delay of approximately 180ms is added from the +3.3V o/p to reset
release.
2.1.3 Clock
The LAN9353 requires a fixed-frequency 25 MHz clock (±50 ppm) source for use by
the internal clock oscillator and PLL. This is typically provided by attaching a 25 MHz
crystal to the OSCI and OSCO pins. Optionally, this clock can be provided by driving
the OSCI input pin with a single-ended 25 MHz clock source.
EVB-LAN9353
EVALUATION BOARD
USER’S GUIDE
2015 Microchip Technology Inc. DS50002393A-page 17
Chapter 3. Board Configuration
3.1 STRAP OPTIONS
The following tables describe the default settings and jumper descriptions for the
EVB-LAN9353. These defaults are the recommended configurations for evaluation of
the LAN9353. These settings may be changed as needed, however, any deviation from
the defaults settings should be approached with care and knowledge of the schematics
and datasheet. An incorrect jumper setting may disable the board.
3.1.1 Jumpers J4:J15
Jumpers J4 through J15 set various functions of the LAN9353. They can also be used
as GPIOs, LED drivers. When used as LED drivers, as they are on the EVB-LAN9353,
they are connected a specific way to set the strap value to a “1”, and another way to
set the strap value to a “0” Figure 3-1 illustrates the schematics connections with the
D3 circuit as a pull-up, and the D4 circuit as a pull-down. To illuminate D3, the LAN9353
will drive the cathode of the D3 low. To illuminate D4, the LAN9353 will drive the cath-
ode of the D4 high.
The J4 - J15 jumpers must be configured in pairs to identical settings in order to realize
the D3 circuit or the D4 circuit. The pairings are as follows:
-J4 & J7
-J6 & J9
-J5 & J8
- J11 & J14
- J10 & J13
- J12 & J15
The following subsections detail the jumper pair settings, their associated strap set-
tings, and the functional effects of setting the straps. All strap values are read during
power-up and on the rising edge of nRST signal. Once the strap value is set, the
LAN9353 will drive the LED’s high or low for illumination according the strap value. For
other designs which may use these pins as GPIOs refer to LAN9353 datasheet for
additional information. In those cases, internal default straps must be changed by an
I2C or SMI master or through EEPROM fields.
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 18 2015 Microchip Technology Inc.
FIGURE 3-1: LED STRAP CIRCUIT
3.1.1.1 GPIO/LED POL/LED CONFIGURATIONS:
GPIO/LED POL/LED configuration straps are used to configure the default polarity of
LEDs, GPIOs through jumpers as shown below in Table 3-1.
TABLE 3-1: GPIO/LED POL/LED CONFIGURATIONS
Header Pin Settings Signal Name Strap Value Description
J4 & J7 1-2(default) LEDPOL0
/GPIO0
/LED0
1 The LED (D3) is
set as active
LOW.
2 -3 0 The LED (D3) is
set as active
HIGH.
J5 & J8 1-2(default) LEDPOL1
/GPIO1
/LED1
1 The LED (D4) is
set as active
LOW.
2 -3 0 The LED (D4) is
set as active
HIGH.
J6 & J9 1-2(default) LEDPOL2
/GPIO2
/LED2
1 The LED (D5) is
set as active
LOW.
2 -3 0 The LED (D5) is
set as active
HIGH.
J10 & J13 1-2(default) LEDPOL3
/GPIO3
/LED3
1 The LED (D6) is
set as active
LOW.
2 -3 0 The LED (D6) is
set as active
HIGH.
2015 Microchip Technology Inc. DS50002393A-page 19
3.1.1.2 SERIAL MANAGEMENT MODE CONFIGURATION
Serial Management Mode selection strap (MNGT0) is used to configure the default
value of the Serial Management Mode Strap hard-strap (serial_mngt_mode_strap)
through jumpers as shown below in Table 3-2.
3.1.1.3 EEPROM SIZE CONFIGURATION:
The EEPROM size configuration strap (J6 & J9) determines the supported EEPROM
size range. A low selects 1Kbits (128 x 8) through 16Kbits (2K x 8)_24C16. A high
selects 32Kbits (4K x 8) through 512Kbits (64K x 8) or 4Mbits (512K x 8)_24C512 as
shown below in Table 3-3.
3.1.1.4 ENERGY-EFFICIENT ETHERNET CONFIGURATION
EEE_EN configuration strap is used to configure the default value of the EEE Enable
2-1 soft-straps (EEE_enable_strap_[2:1]) through jumpers as shown below in
Tab le 3 - 4.
J11 & J14 1-2(default) LEDPOL4
/GPIO4
/LED4
1 The LED (D7) is
set as active
LOW.
2 -3 0 The LED (D7) is
set as active
HIGH.
J12 & J15 1-2(default) LEDPOL5
/GPIO5
/LED5
1 The LED (D8) is
set as active
LOW.
2 -3 0 The LED (D8) is
set as active
HIGH.
TABLE 3-2: SERIAL MANAGEMENT MODE CONFIGURATION
Header Pin Settings serial_mngt_mode_
strap Description
J4 & J7 2-3 0 SMI Managed Mode
J4 & J7 1-2 (default) 1 I2C Managed Mode
TABLE 3-3: EEPROM SIZE CONFIGURATION
Header Pin Settings eeprom_size_strap
Value Description
J6 & J9 1-2 (default) 1 EEPROM size = 32K
bits (4k x 8) through
512K bits (64K x 8)
2 -3 0 EEPROM size = 1K
bits (128 x 8) through
16K bits (2K x 8)
TABLE 3-1: GPIO/LED POL/LED CONFIGURATIONS (CONTINUED)
Header Pin Settings Signal Name Strap Value Description
Note: “EEE_enable_strap_1” strap is used for the LAN9353 when in Port 1 inter-
nal PHY mode.
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 20 2015 Microchip Technology Inc.
3.1.1.5 1588 ENABLE CONFIGURATION
Energy Efficient Ethernet configuration strap is used to configure the default value of
the 1588 Enable soft-strap (1588_enable_strap) through jumpers as shown below in
Tab le 3 - 5.
3.1.1.6 PHY ADDRESS CONFIGURATION
PHY Address selection strap is used to configure the default value of the Switch PHY
Address Select soft-strap (phy_addr_sel_strap) through jumpers as shown below in
Tab le 3 - 6.
3.1.2 GPIO 6 & GPIO 7 Input and Output Configurations
GPIO 6 & 7 configuration straps are used to configure the default input value of the
GPIO 6 and 7 through jumpers as shown below in Table 3-7 and Table 3-8.
TABLE 3-4: EEE_EN CONFIGURATION
Header Pin Settings EEE_enable_strap_[
2:1] Value Description
J10 & J13 1-2(default) 1 EEE Enable
2 -3 0 EEE Disable
TABLE 3-5: 1588 ENABLE CONFIGURATION
Header Pin Settings 1588_enable_strap
Value Description
J11 & J14 1-2 (default) 1 1588 Enable
2 -3 0 1588 Disable
TABLE 3-6: PHY ADDRESSING
Header Pin
Settings
PHY_ADDR_SEL
_STRAP Value
VIRTUAL
PHY 0 AND 1
DEFAULT
ADDRESS
VALUE
PHY A
DEFAULT
ADDRESS
VALUE
PHY B
DEFAULT
ADDRESS
VALUE
J12 & J15 1-2 1 1 2 3
2-3 (default) 0 0 1 2
TABLE 3-7: GPIO 6 & 7 INPUT CONFIGURATION
Header Pin Settings Input Signal Name
J20 1-2 1 GPIO6
2-3 0
J21 1-2 1 GPIO7
2-3 0
TABLE 3-8: GPIO 6 & 7 OUTPUT CONFIGURATION
Header Pin Output Signal Name
J20 2 Push Pull GPIO6
J21 2 Push Pull GPIO7
Note: By default, the jumpers settings for J20 & J21 will be OPEN.
2015 Microchip Technology Inc. DS50002393A-page 21
3.1.3 Jumper Settings for CONFIG 9 or CONFIG 10
CONFIG 9: Used to configure the LAN9353 in Dual RMII mode by using jumpers as
shown below in Table 3-9.
Port 0: RMII PHY, RMII MAC modes
Port 1: RMII MAC, RMII PHY modes
Port 2: Internal PHY
CONFIG 10: Used to configure the LAN9353 in Single MII/RMII/TMII mode by using
jumpers as shown below in Table 8
Port 0: MII MAC, MII PHY, RMII PHY, RMII MAC, TMII MAC, TMII PHY modes
Port 1: Internal PHY
Port 2: Internal PHY
3.1.4 Link Partner Duplex/Speed Configurations
CONFIG 9 or CONFIG 10 must be configured before Link partner Duplex/Speed con-
figurations. For a detailed jumper settings for CONFIG 9 or CONFIG 10 refer to section
3.1.3.
The “duplex_strap_0” strap from J28 is used to determine the link partners duplex abil-
ity when in Port 0 MII MAC and RMII MAC modes as shown below in Table 3-10.
The “speed_strap_0” strap from J29 is used to determine the link partners speed ability
and to determine the parallel detect speed when in Port 0 “MII MAC and RMII MAC”
modes as shown below in Table 3-10.
TABLE 3-9: CONFIG 9 OR CONFIG 10 SETTINGS
SW11 SW12 SW13 SW14 SW15 SW16 SW17 SW18 Mode Configurations
1-3 1-3 1-3 1-3 1-3 1-3 1-3 1-3 2 RMII CONFIG 9
1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1xMII/RMII/T
MII
(DEFAULT)
CONFIG 10
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
TABLE 3-10: EMULATED LINK PARTNER DEFAULT ADVERTISED ABILITY
FOR PORT 0
J28
(P0_DUPLEX) J29 (P0_SPEED) duplex_strap_0 speed_strap_0
ADVERTISED
LINK PARTNER
ABILITY
1-2 2-3 1 0 10BASE-T
full-duplex
(0010)
1-2 1-2 1 1 100BASE-X
full-duplex
(1000)
2-3 2-3 0 0 10BASE-T
half-duplex
(0001)
2-3 1-2 0 1 100BASE-X
half-duplex
(0100)
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 22 2015 Microchip Technology Inc.
The “duplex_strap_1” strap from J30 is used to determine the link partners duplex abil-
ity when in Port 1 RMII MAC mode as shown below in Table 10.
The “speed_strap_1” strap from J31 is used to determine the link partners speed ability
and to determine the parallel detect speed when in Port 1 “RMII MAC” mode as shown
below in Table 3-11.
3.1.5 Port 0/Port 1 Mode Configurations
CONFIG 9 or CONFIG 10 must be configured before P0/P1 mode configurations. For
a detailed jumper settings for CONFIG 9 or CONFIG 10 refer to section 3.1.3
P0 Mode configuration straps (SW5, SW6, SW7 & SW8) are used to configure the
hard-straps such as Switch Port 0 Mode Strap (P0_mode_strap[1:0]), Switch Port 0
RMII Clock Direction Strap (P0_rmii_clock_dir_strap) and Switch Port 0 Clock Strength
Strap (P0_clock_strength_strap) as shown below in Table 3-12.
TABLE 3-11: EMULATED LINK PARTNER DEFAULT ADVERTISED ABILITY
FOR PORT 1
J30
(P1_DUPLEX) J31 (P1_SPEED) duplex_strap_1 speed_strap_1
ADVERTISED
LINK PARTNER
ABILITY
1-2 2-3 1 0 10BASE-T
full-duplex
(0010)
1-2 1-2 1 1 100BASE-X
full-duplex
(1000)
2-3 2-3 0 0 10BASE-T
half-duplex
(0001)
2-3 1-2 0 1 100BASE-X
half-duplex
(0100)
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
TABLE 3-12: PORT 0 MODE STRAP MAPPING
P1_
INTPHY
(J5 & J8)
P0_MODE3
(SW8)
P0_MODE2
(SW9)
P0_MODE1
(SW7)
P0_MODE0
(SW5) MODE
1-2 1-3 1-3 X X MII MAC
1-21-31-21-3 XMII PHY
1-2 1-3 1-2 1-2 1-3 Turbo MII PHY 12 ma
1-2 1-3 1-2 1-2 1-2 Turbo MII PHY 16 ma
2-3 X 1-3 1-3 X RMII MAC clock in
(default)
1-2 1-2
2-3 X 1-3 1-2 1-3 RMII MAC clock out
12ma
1-2 1-2
2-3 X 1-3 1-2 1-2 RMII MAC clock out
16ma
1-2 1-2
2-3 X 1-2 1-3 X RMII PHY clock in
1-2 1-2
2015 Microchip Technology Inc. DS50002393A-page 23
P1 Mode configuration straps (SW10, SW8, SW6 & J5/J8) are used to configure the
hard-straps such as Switch Port 1 Mode Strap (P1_mode_strap[1:0]), Switch Port 1
RMII Clock Direction Strap (P1_rmii_clock_dir_strap) and Switch Port 1 Clock Strength
Strap (P1_clock_strength_strap) as shown below in Table 3-13.
2-3 X 1-2 1-2 1-3 RMII PHY clock out 12ma
1-2 1-2
2-3 X 1-2 1-2 1-2 RMII PHY clock out 16ma
1-2 1-2
TABLE 3-12: PORT 0 MODE STRAP MAPPING (CONTINUED)
P1_
INTPHY
(J5 & J8)
P0_MODE3
(SW8)
P0_MODE2
(SW9)
P0_MODE1
(SW7)
P0_MODE0
(SW5) MODE
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
Note: SW8 will be used for Port 0 when LAN9353 is configured in Single
MII/TMII/RMII Mode and SW8 will be ignored when LAN9353 is in Dual
RMII mode.
TABLE 3-13: PORT 1 MODE STRAP MAPPING
P1_INTPHY
(J5 & J8)
P1_MODE2
(SW10)
P1_MODE1
(SW8)
P1_MODE0
(SW6) MODE
2-3 1-3 1-3 X RMII MAC clock in
(default)
2-3 1-3 1-2 1-3 RMII MAC clock out
12ma
2-3 1-3 1-2 1-2 RMII MAC clock out
16ma
2-3 1-2 1-3 X RMII PHY clock in
2-3 1-2 1-2 1-3 RMII PHY clock out 12ma
2-3 1-2 1-2 1-2 RMII PHY clock out 16ma
1-2 X X X Internal PHY
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
Note: SW8 will be used for Port 1 when LAN9353 is configured in Dual RMII Mode
and SW8 will be ignored when LAN9353 is in Single MII/TMII/RMII mode.
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 24 2015 Microchip Technology Inc.
3.1.6 RMII RX Clock Configurations
When LAN9353 is in MAC/PHY mode the reference clock routed either through TX or
RX Clock as shown in Table 3-14 for Port 0 and Table 3-15 for Port 1.
3.1.7 GPIO Header
J27 header is used for GPIO. Pin details are given below in Table 3-16.
TABLE 3-14: RX CLOCK CONFIGURATIONS FOR PORT 0
Switch Settings DESCRIPTION Mode
SW23 (1-3) (Default) TX Clock used as a Refer-
ence Clock
RMII MAC
SW23 (1-2) RX Clock used as a Refer-
ence Clock
RMII MAC
SW24 (1-3) (Default) Reference clock used as a TX
clock
RMII PHY
SW24 (1-2) Reference clock used as a RX
clock
RMII PHY
Note: When Port 0 configured in RMII mode, short Jumper J25 (1-2).
TABLE 3-15: RMII RX CLOCK CONFIGURATIONS FOR PORT 1
Switch Settings DESCRIPTION Mode
SW25 (1-3) (Default) TX Clock used as a Refer-
ence Clock
RMII MAC
SW25 (1-2) RX Clock used as a Refer-
ence Clock
RMII MAC
SW26 (1-3) (Default) Reference clock used as a TX
clock
RMII PHY
SW26 (1-2) Reference clock used as a RX
clock
RMII PHY
Note: External PHY considered LAN8742.
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
TABLE 3-16: PIN NAMES FOR GPIO HEADER
Signal Name Pin Number
GPIO0 J27.1
GPIO1 J27.2
GPIO2 J27.3
GPIO3 J27.4
GPIO4 J27.5
GPIO5 J27.6
GPIO6 J27.7
GPIO7 J27.8
2015 Microchip Technology Inc. DS50002393A-page 25
3.1.8 I2C Aardvark® Header
J16 connector is used for I2C Aardvark header. Respective pin details are given below
in Table 3-17.
3.1.9 Copper and Fiber Mode Selections
The LAN9353 supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) modes. In
100BASE-FX operation, the presence of the receive signal is indicated by the external
transceiver as either an open-drain, CMOS level, Loss of Signal (SFP) or a LVPECL
Signal Detect (SFF).
This EVB supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) in SFP mode. By
default Copper Mode is active. Fiber Mode is supported as an assembly option. To
select the Copper or Fiber Mode, the respective strap and signal routing resister
assembly options must to be configured.
3.1.9.1 COPPER MODE
The EVB-LAN9353 is set to Copper Mode by default. Table 3-18 details the required
strap resistors settings for Copper Mode operation.
Additionally, the signal routing resistors detailed in Table 3-19 must be assembled for
Copper Mode operation.
3.1.9.2 FIBER MODE
The LAN9353 supports SFP type 100BASE-FX mode. To enable Fiber Mode, the
respective strap and signal routing resisters must be configured.
TABLE 3-17: PIN NAMES FOR I2C AARDVARK HEADER
Signal Name Pin Number
I2C2_SCL J16.1
I2C2_SDA J16.3
GND J16.2 & J16.10
Note: Vendor part number for SFP Transceiver: Finisar/FTLF1217P2.
TABLE 3-18: COPPER MODE STRAP RESISTORS
Resistors Signal Names Description
R79 (10K) FXLOSEN Copper twisted pair for ports A and B further determined
by FXSDENA and FXSDENB
R76, R80 (10K) FXSDA/FXSDB Configures Port 0 and Port 1 to Copper Mode
Note: R75, R77, and R78 must not be populated (DNP).
TABLE 3-19: COPPER MODE SIGNAL ROUTING RESISTORS
Resistors Description
R17, R19, R21, R23 Port 0 Copper mode is Enabled
R31, R33, R35, R37 Port 1 Copper mode is Enabled
Note: R16, R18, R20, R22, R30, R32, R34, and R36 (0402 package) must not be
populated (DNP).
Note: Copper Mode related resistors must be DNP while Fiber Mode is active
(See Section 3.1.9.1 “Copper Mode”).
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 26 2015 Microchip Technology Inc.
Table 3-20 details the required strap resistor settings for Fiber Mode operation.
Additionally, the signal routing resistors detailed in Table 3-21 must be assembled for
Fiber Mode operation.
3.1.9.3 FX-LOS FIBER MODE STRAP
FX-LOS strap details are shown in Table 3-22. These strap settings determine if the
ports are to operate in FX-LOS Fiber Mode or FX-SD/Copper Mode.
3.2 LEDS
Table 3-23 describes the different LED references and their corresponding colors and
indications
TABLE 3-20: FIBER MODE STRAP RESISTORS
Resistors Description
R77 (10K) Configures Port 0 & 1 to FX_LOS Mode
R75, R78 (10K) Configures Port 0 & 1 to Fiber mode, respectively
Note: R76, R79, and R80 must not be populated (DNP).
TABLE 3-21: FIBER MODE SIGNAL ROUTING RESISTORS
Resistors Description
R16, R18, R20, R22 Port 0 Fiber mode Enabled
R30, R32, R34, R36 Port 1 Fiber mode Enabled
Note: R17, R19, R21, R23, R31, R33, R35, and R37 (0402 package) must not be
populated (DNP).
TABLE 3-22: FX-LOS MODE STRAP SETTINGS
R77 (10K) R79 (10K) Reference
Voltage (v) Function
Populate DNP 3.3 A level above 2V selects FX-LOS for Port 0 and Port 1
Populate Populate 1.5 A level of 1.5V selects FX-LOS for Port 0 and FX-SD /
Copper twisted pair for Port 1, further determined by
FXSDB
DNP Populate 0 (Default) A level of 0V selects FX-SD / Copper twisted pair for
Ports 0 and 1, further determined by FXSDA, FXSDB
Note: The above strap details describe the LAN9353 function. This EVB does not
support SFF Fiber Mode. Therefore, FX-SD related straps are not applica-
ble.
TABLE 3-23: LEDS
Reference Color Indication
D1 Green 3.3V Power active
D2 Red LAN9353 is in reset condition
D4 Green Full-duplex / Collision Port 1
D7 Green Full-duplex / Collision Port 2
Note: Assumes the LED_FUN field of the LED_CFG register is 00b.
2015 Microchip Technology Inc. DS50002393A-page 27
3.3 TEST POINTS
Table 3-24 describes the different test points and their corresponding connections.
3.4 MECHANICALS
Figure 3-2 displays details for EVB-LAN9353 mechanical dimensions. Dimension are
in mm.
FIGURE 3-2: LAN9353 EVB MECHANICAL DIMENSIONS
TABLE 3-24: TEST POINTS
Test Points Description Connection
TP1 Single pin populated 5V 5V_EXT
TP2 Single pin populated 3V3 3V3
TP3 Single pin unpopulated VDDCR VDDCR
TP4 Single pin unpopulated IRQ IRQ
TP5 Single pin unpopulated P0_MDC P0_MDC
TP6 Single pin unpopulated P0_MDIO P0_MDIO
TP7 Single pin unpopulated P1_MDC P1_MDC
TP8 Single pin unpopulated P1_MDIO P1_MDIO
TP9 Single pin populated GND GND
TP10 Single pin populated GND GND
2015 Microchip Technology Inc. DS50002393A-page 28
EVB-LAN9353
EVALUATION BOARD
USER’S GUIDE
Appendix A. EVB-LAN9353 Evaluation Board
A.1 INTRODUCTION
This appendix shows the EVB-LAN9353 Evaluation Board.
FIGURE A-1: EVB-LAN9353 EVALUATION BOARD
2015 Microchip Technology Inc. DS50002393A-page 29
EVB-LAN9353
EVALUATION BOARD
USER’S GUIDE
Appendix B. EVB-LAN9353 Evaluation Board Schematics
B.1 INTRODUCTION
This appendix shows the EVB-LAN9353 Evaluation Board Schematics.
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 30 2015 Microchip Technology Inc.
FIGURE B-1: EVB-LAN9353 EVALUATION BOARD SCHEMATIC 1
Mode
Switch
I2C
EEPROM/
Header
Straps
Jumpers
40 Pin MII
Connector
(Female)
40 Pin MII
Connector
(Male)
Power
Supply
Module
Reset
Switch
Crystal
10/100
Ethernet
Magnetics &
RJ45
10/100
Ethernet
Magnetics &
RJ45
Fiber
Trasnceiver-
(SFP) Port 1
Fiber
Trasnceiver-
(SFP) Port 2
Microchip
LAN9353
Port 0
Port 1 Port 2
EVB-LAN9353 Block Diagram (Config 10)
MII/RMII/TMII
Mode
Switch
I2C
EEPROM/
Header
Straps
Jumpers
40 Pin MII
Connector
(Female)
40 Pin MII
Connector
(Male)
Power
Supply
Module
Reset
Switch
Crystal
10/100
Ethernet
Magnetics &
RJ45
Fiber
Trasnceiver-
(SFP) Port 2
Microchip
LAN9353
Port 0
Port 2
EVB-LAN9353 Block Diagram (Config 9)
40 Pin MII
Connector
(Female)
40 Pin MII
Connector
(Male)
Port 1
RMII RMII
EVB-LAN9353 Evaluation Board User’s Guide
2015 Microchip Technology Inc. DS50002393A-page 31
FIGURE B-2: EVB-LAN9353 EVALUATION BOARD SCHEMATIC 2
Reset Generator
POWER SUPPLY
(Rb)(Ra)
OKR-T/3-W12-C
3 .3V REGULATOR, 3A
( 3V3 fixed when Rb=503e)
"3V3 Present"
"Reset"
3-$+
5V_SW
EN12_1
VOUT_3V3
5V_EXT
3V3
3V3
5V
3V3
3V3
3V3
3V3
RST#
TP9
BLACK
TP9
BLACK
TP1
RED
TP1
RED TP2
ORANGE
TP2
ORANGE
C3
0.1uF
C3
0.1uF
C6
0.1uF
C6
0.1uF
R8 1KR8 1K
U1
3_Amp
U1
3_Amp
GND 3
VIN
2
ENABLE
1TRIM 5
VOUT 4
R7
100
1/10W
1%
R7
100
1/10W
1%
1 2
R2
1K
R2
1K
R5
4.75K
1%
R5
4.75K
1%
Q1
NDS355AN_NMOS
Q1
NDS355AN_NMOS
1
G
3
S
2
D
U2
TPS3125
SOT23_5
Threshold = 2.64V
Delay = 180ms
U2
TPS3125
SOT23_5
Threshold = 2.64V
Delay = 180ms
RESET# 1
GND
2
RESET 3
MR#
4
VDD 5
SW1
P/N:1101M2S3CQE2
Switch, SPDT, Slide
SW1
P/N:1101M2S3CQE2
Switch, SPDT, Slide
2
3
1
C4
10uF
C4
10uF
C2
10uF
25V
C2
10uF
25V
D1
GRN
D1
GRN
1
A
2
C
R6
10.0K
1/10W
1%
R6
10.0K
1/10W
1%
12
C5
0.1uF
C5
0.1uF
U3
74LVC1G14
U3
74LVC1G14
2 4
53
1
SW2
sw_pb_2P
SW2
sw_pb_2P
D2
RED
D2
RED
1
A
2
C
R4
470E
1%
R4
470E
1%
R3
3.30K
1%
R3
3.30K
1%
C1
4.7uF
DNP
C1
4.7uF
DNP
R1
0
R1
0
TP10
BLACK
TP10
BLACK
R9
2.2K
R9
2.2K
R4A
33E
1%
R4A
33E
1%
FB1
2A/0.05DCR
FB1
2A/0.05DCR
J1J1
1
2
3
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 32 2015 Microchip Technology Inc.
FIGURE B-3: EVB-LAN9353 EVALUATION BOARD SCHEMATIC 3
Note:
OSCVSS need to connect to Chip gnd.
Power Supply Filtering
Low ESR
IRQ
REG_EN
RBIAS
VDD12TX1
VDD12TX2
VDD12TX2
VDD12TX1
OSCO
OSCI
3V3
VDD33TXRX1
VDD33TXRX2
VDDCR
VDD33TXRX1
VDD33TXRX2
3V3
3V3
3V3 3V3
3V3 VDDCR
FXSDA/FXLOSA
ATEST/FXLOSEN
RXPA
RXNA
TXNA
TXPA
TXNB
TXPB
RXNB
RXPB
FXSDB/FXLOSB
GPIO0
GPIO1
GPIO2
I2C2_SCL
I2C2_SDA
RST#
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
C14
0.1uF
C14
0.1uF
FB3 2A/0.05DCRFB3 2A/0.05DCR
R10 12.1K
1%
R10 12.1K
1%
C27 18pFC27 18pF
C25
0.1uF
C25
0.1uF
C17
0.1uF
C17
0.1uF
C11
0.1uF
C11
0.1uF
C210.1uF C210.1uF
POWER
INT PORT0INT PORT1
OSCI2C
OTHER
SIGNALS
U4A
LAN9353
POWER
INT PORT0INT PORT1
OSCI2C
OTHER
SIGNALS
U4A
LAN9353
OSCI
1
OSCO
2
OSCVDD12
3
OSCVSS
4
VDD33 5
VDDCR_1 6
REG_EN
7
ATEST/FXLOSEN
8
FXSDENA/FXSDA/FXLOSA 9
FXSDENB/FXSDB/FXLOSB 10
RST#
11
GPIO7
12 GPIO6
13
VDDIO_1 14
GPIO5/LED5/LEDPOL5/PHYADD
17 GPIO4/LED4/LEDPOL4/1588EN
18
VDDIO_2 20
VDDCR_2 24
VDDIO_3 32
GPIO3/LED3/LEDPOL3/EEEEN
34
VDDIO_4 37
VDDCR_3 38
TESTMODE
41
I2CSDA/EESDA/TMS
42 I2CSCL/EESCL/TCK
43
IRQ
44
GPIO2/LED2/LEDPOL2/E2PSIZE
45 GPIO1/LED1/TDI/LEDPOL1/P1_INTPHY
46
VDDIO_5 47
GPIO0/LED0/TDO/LEDPOL0/MNGT0
48
VDD33TXRX1 51
TXNA 52
TXPA 53
RXNA 54
RXPA 55
VDD12TX1 56
RBIAS
57
VDD33BIAS 58
VDD12TX2 59
RXPB 60
RXNB 61
TXPB 62
TXNB 63
VDD33TXRX2 64
GND
65
FB2 2A/0.05DCRFB2 2A/0.05DCR
C220.1uF C220.1uF
C15
0.1uF
C15
0.1uF
FB5
2A/0.05DCR
FB5
2A/0.05DCR
C24
0.1uF
C24
0.1uF
C23
1.0uF
DNP
C23
1.0uF
DNP
C13
0.1uF
C13
0.1uF
C8
0.1uF
C8
0.1uF
C20470pF C20470pF
C12
1.0uF DNP
C12
1.0uF DNP
C26 18pFC26 18pF
TP3
SMT
TP3
SMT
C16
0.1uF
C16
0.1uF
C9
1.0uF
DNP C9
1.0uF
DNP
C10
0.1uF
C10
0.1uF
C19
1uF
C19
1uF
C7
1.0uF
DNP
C7
1.0uF
DNP
TP4
WHITE
DNP
TP4
WHITE
DNP
Y1 25.000MHz
25ppm
Y1 25.000MHz
25ppm
1 2
FB4 2A/0.05DCR
BLM18EG221SN1D
FB4 2A/0.05DCR
BLM18EG221SN1D
C180.1uF C180.1uF
EVB-LAN9353 Evaluation Board User’s Guide
2015 Microchip Technology Inc. DS50002393A-page 33
FIGURE B-4: EVB-LAN9353 EVALUATION BOARD SCHEMATIC 4
Note:
Capacitors C10 through C13 are optional for EMI purposes
and are not populated on the LAN8740/41 evaluation board.
These capacitors are required for operation in an EMI
constrained environment.
LED1 (Green) = LINK/ACT
LED2 (Yellow) = SPEED
Note:
Capacitors C10 through C13 are optional for EMI purposes
and are not populated on the LAN8740/41 evaluation board.
These capacitors are required for operation in an EMI
constrained environment.
LED1 (Green) = LINK/ACT
LED2 (Yellow) = SPEED
/,1.$&7
63(('
/,1.$&7
63(('
3257
3257
'HIDXOWDVVHPEO\
1RWH)%DQG)%WREH]HURRKPV
COP-RXPA
COP-TXNA
COP-RXNA
COP-TXPA
COP-RXPB
COP-TXNB
COP-RXNB
COP-TXPB
VDD33TXRX1
VDD33TXRX2
FX_SFP-RXPA
FX_SFP-RXNA
TXPA
TXNA FX_SFP-TXNA
FX_SFP-TXPA
RXPA
RXNA
FX_SFP-RXPB
FX_SFP-RXNB
TXPB
TXNB FX_SFP-TXNB
FX_SFP-TXPB
RXPB
RXNB
LED2_CATHODE LED2_ANODE
LED0_CATHODE LED0_ANODE
LED5_ANODE
LED3_CATHODE LED3_ANODE
LED5_CATHODE
C34
10pF
50V
5%
DNP
C34
10pF
50V
5%
DNP
XMIT
RCV
75
75 75
1000 pF 2 kV
RJ45
1
4 & 5
2
3
7 & 8
6
75
GRN
YEL
T1
Pulse J0011D01BNL
XMIT
RCV
75
75 75
1000 pF 2 kV
RJ45
1
4 & 5
2
3
7 & 8
6
75
GRN
YEL
T1
Pulse J0011D01BNL
RD+
3
RXCT
5
RD-
6
TD+
1
TXCT
4
TD-
2
CHS GND
8
GND
13
GND1
14
MTG
15
MTG1
16
NC
7
C10
A9
C1
11
A1
12
FB6 0EFB6 0E
C28
10pF
50V
5%
DNP
C28
10pF
50V
5%
DNP
R103 330ER103 330E
C36
10pF
50V
5%
DNP
C36
10pF
50V
5%
DNP
R34 0
DNP
R34 0
DNP
R15
0
R15
0
R13
49.9
1/10W
1%
R13
49.9
1/10W
1%
R37 0R37 0
R28
49.9
1/10W
1%
R28
49.9
1/10W
1%
R36 0
DNP
R36 0
DNP
R21 0R21 0
R62 330ER62 330E
R17 0R17 0
R16 0
DNP
R16 0
DNP
C37
0.022uF
50V
10%
C37
0.022uF
50V
10%
R102 330ER102 330E
R33 0R33 0
R32 0
DNP
R32 0
DNP
R18 0
DNP
R18 0
DNP
C31
10pF
50V
5%
DNP
C31
10pF
50V
5%
DNP
R24 0
RES1210
R24 0
RES1210
R31 0R31 0
R61 330ER61 330E
XMIT
RCV
75
75 75
1000 pF 2 kV
RJ45
1
4 & 5
2
3
7 & 8
6
75
GRN
YEL
T2
Pulse J0011D01BNL
XMIT
RCV
75
75 75
1000 pF 2 kV
RJ45
1
4 & 5
2
3
7 & 8
6
75
GRN
YEL
T2
Pulse J0011D01BNL
RD+
3
RXCT
5
RD-
6
TD+
1
TXCT
4
TD-
2
CHS GND
8
GND
13
GND1
14
MTG
15
MTG1
16
NC
7
C10
A9
C1
11
A1
12
C30
10pF
50V
5%
DNP
C30
10pF
50V
5%
DNP
FB7 0EFB7 0E
R14
49.9
1/10W
1%
R14
49.9
1/10W
1%
C35
10pF
50V
5%
DNP
C35
10pF
50V
5%
DNP
R38 0
RES1210
R38 0
RES1210
R25
49.9
1/10W
1%
R25
49.9
1/10W
1%
R23 0R23 0
C29
10pF
50V
5%
DNP
C29
10pF
50V
5%
DNP
R20 0
DNP
R20 0
DNP
R22 0
DNP
R22 0
DNP
R12
49.9
1/10W
1%
R12
49.9
1/10W
1%
R35 0R35 0
R26
49.9
1/10W
1%
R26
49.9
1/10W
1%
C33
10pF
50V
5%
DNP
C33
10pF
50V
5%
DNP
R19 0R19 0
C32
0.022uF
50V
10%
C32
0.022uF
50V
10%
R29
0
R29
0
R11
49.9
1/10W
1%
R11
49.9
1/10W
1%
R27
49.9
1/10W
1%
R27
49.9
1/10W
1%
R30 0
DNP
R30 0
DNP
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 34 2015 Microchip Technology Inc.
FIGURE B-5: EVB-LAN9353 EVALUATION BOARD SCHEMATIC 5
Fiber Port 1 :SFP Interface Fiber Port 2 :SFP Interface
Note:Place
capacitors,
and resistors
close to FOT
Note:Place
resistors
close to
ASIC
Note:Place
capacitors,
and resistors
close to FOT
Note:Place
resistors
close to
ASIC
Assemble 0E at C38,C40,C42,C44 Assemble 0E at C39,C41,C43,C45
Note: Fiber mode related components are Not Populated on EVB (Default)
SFP_VCCT
SFP_VCCR
SFP_TD-
SFP_TD+
SFP_RD-
SFP_RD+
SFP_VCCT2
SFP_VCCR2
SFP_TD2-
SFP_TD2+
SFP_RD2-
SFP_RD2+
SFP_VCCT
SFP_VCCT2
3V3 3V3
3V3 3V3
FXSDA/FXLOSA FXSDB/FXLOSB
FX_SFP-TXPA
FX_SFP-RXNA
FX_SFP-RXPA
FX_SFP-TXNA
FX_SFP-RXNB
FX_SFP-RXPB
FX_SFP-TXPB
FX_SFP-TXNB
C53
0.1uF
C53
0.1uF
C49
0.1uF
C49
0.1uF
+
C48
10uF
16V
+
C48
10uF
16V
R40
82
R40
82
L2 1uHL2 1uH
C51
0.1uF
C51
0.1uF
L1 1uHL1 1uH
C39 0.1uFC39 0.1uF
C42
0.1uF
C42
0.1uF C43 0.1uFC43 0.1uF
R51
130
R51
130
J3
FTLF1217P2
J3
FTLF1217P2
VeeT
1
TXFault
2
TX Disable
3
MOD-DEF(2)
4
MOD-DEF (1)
5
MOD-DEF (0)
6
Rate Select
7
LOS
8
VeeR
9
VeeR1
10 VeeR3 11
VeeR2 14
RD- 12
RD+ 13
VccR 15
VccT 16
VeeT2 17
TD+ 18
TD- 19
VeeT1 20
21 21
22 22
23 23
24 24
25 25
26 26
27 27
28 28
29 29
30 30
31 31
R54
4.7K
R54
4.7K
R44
82
R44
82
R56
4.7K
R56
4.7K R59
4.7K
R59
4.7K
R49
130
R49
130
R41
49.9
R41
49.9
R48
100
DNP
R48
100
DNP
R57
4.7K
R57
4.7K
J2
FTLF1217P2
J2
FTLF1217P2
VeeT
1
TXFault
2
TX Disable
3
MOD-DEF(2)
4
MOD-DEF (1)
5
MOD-DEF (0)
6
Rate Select
7
LOS
8
VeeR
9
VeeR1
10 VeeR3 11
VeeR2 14
RD- 12
RD+ 13
VccR 15
VccT 16
VeeT2 17
TD+ 18
TD- 19
VeeT1 20
21 21
22 22
23 23
24 24
25 25
26 26
27 27
28 28
29 29
30 30
31 31
R45
49.9
R45
49.9
C47
0.1uF
C47
0.1uF
R39
82
R39
82
R47
100
DNP
R47
100
DNP
+
C52
10uF
16V
+
C52
10uF
16V
C41 0.1uFC41 0.1uF
R60
4.7K
R60
4.7K
+
C50
10uF
16V
DNP
+
C50
10uF
16V
DNP
C55
0.1uF
C55
0.1uF
+
C54
10uF
16V
+
C54
10uF
16V
R55
4.7K
R55
4.7K
C57
0.1uF
C57
0.1uF
+
C56
10uF
16V
+
C56
10uF
16V
R43
82
R43
82
R53
4.7K
R53
4.7K
C45 0.1uFC45 0.1uF
R50
130
R50
130
+
C46
10uF
16V
DNP
+
C46
10uF
16V
DNP
R42
49.9
R42
49.9
R58
4.7K
R58
4.7K
C44
0.1uF
C44
0.1uF
R52
130
R52
130
L4 1uHL4 1uH
L3 1uHL3 1uH
C38 0.1uFC38 0.1uF
R46
49.9
R46
49.9
C40 0.1uFC40 0.1uF
EVB-LAN9353 Evaluation Board User’s Guide
2015 Microchip Technology Inc. DS50002393A-page 35
FIGURE B-6: EVB-LAN9353 EVALUATION BOARD SCHEMATIC 6
GPIO [0:5] & LED_POL_Strap
FULL DUPLEX / Collision
LINK/ACT
SPEED
I2C EEPROM
FX_Los_Strap_1 & 2
FX_Mode_Strap_1 & 2
FULL DUPLEX / Collision
LINK/ACT
SPEED
Aardvark - I2C Connector
Note: U5: IC DIP Socket. Different sizes can be mounted
I2C EEPROM Lower size Below 16K(2K X 8)
I2C EEPROM Higher size
Above 16K(2K X 8)
[Default-512KBIT]
5 5 5HI9ROWDJH )XQFWLRQ
3RXSXODWH '13 9 $ERYH9VHOHFWV);/26IRUSRUWVDQG
3RXSXODWH 3RXSXODWH 9
/HYHORI9VHOHFWV);/26IRUSRUWDQG
);6'FRSSHUWZLVWHGSDLUIRUSRUW
IXUWKHUGHWHUPLQHGE\);6'%
3RXSXODWH
'HIDXOW
'13
'HIDXOW
'HIDXOW
/HYHORI96HOHFWV);6'FRSSHUWZLVWHGSDLU
IRUSRUWV$DQG%
IXUWKHUGHWHUPLQHGE\);6'$DQG);6'%
3257
&RSSHU
'HIDXOW
)LEHU
3RXSXODWH
3257
5
5
3257
02'(
)LEHU
5
5
&RSSHU
'HIDXOW
The LED is set as active high.
LED0/GPIO0/MNGT0
The LED is set as active low, 1
0
LED1/GPIO1
J4,J7 (1&2)
(Default)
ConnectorStrap Name
LED5/GPIO5/PHYADD
LED4/GPIO4/1588EN
LED3/GPIO3/EEEEN
LED2/GPIO2/E2PSIZE
Logic LED Polarity Strap
0
1
J5,J8 (2&3)
J5,J8 (1&2)
(Default)
J4,J7 (2&3)
J11,J14 (1&2)
(Default)
J10,J13 (2&3)
J10,J13 (1&2)
(Default)
J6,J9 (2&3)
J6,J9 (1&2)
(Default)
The LED is set as active low,
EEPROM Size=32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8) (LAN9252 only)
The LED is set as active high.
The LED is set as active low,
J12,J15 (2&3)
(Default)
J12,J15 (1&2)
J11,J14 (2&3)
The LED is set as active high.
EEE Disable
The LED is set as active low,
EEE Enable
1
0
The LED is set as active high.
EEPROM Size=1K bits (128 x 8) through 16K bits (2K x 8)
1
0The LED is set as active high.
1588 Disable
The LED is set as active low,
1588 Enable
1
1
0The LED is set as active high.
PHYADD=0,1,2
The LED is set as active low,
PHYADD =1,2,3
0
Port 1 LEDs Port 2 LEDs
LED2_ANODE
LED0_CATHODE
LED2_CATHODE
GPIO0
GPIO0 GPIO2
GPIO2
LED0_ANODE
LED0_ANODE
LED0_CATHODE
LED1_ANODE
LED1_CATHODE
LED2_ANODE
LED2_CATHODE
LED1_CATHODE
LED4_ANODE
LED4_CATHODE
GPIO4GPIO1
GPIO4GPIO1
LED1_ANODE
LED3_CATHODE
LED5_ANODE
LED5_CATHODE
GPIO3
GPIO5GPIO3
GPIO5
LED3_ANODE
LED3_ANODE
LED3_CATHODE
LED4_ANODE
LED4_CATHODE
LED5_ANODE
LED5_CATHODE
I2C2_SCL
I2C2_SDA
GPIO6
GPIO7
3V3 3V3
3V3 3V3
3V3
3V3
3V3
3V33V3 3V3 3V3
3V3
3V3
GPIO0
GPIO1
GPIO2
ATEST/FXLOSEN
FXSDA/FXLOSA
FXSDB/FXLOSB
GPIO3
GPIO4
GPIO5
LED0_ANODE
LED0_CATHODE
LED2_ANODE
LED2_CATHODE
LED3_ANODE
LED3_CATHODE
LED5_ANODE
LED5_CATHODE
I2C2_SCL
I2C2_SDA
GPIO6
GPIO7
R81
10.0K
R81
10.0K
12
J12J12
1
2
3
J7J7
1
2
3
D4
GRN
D4
GRN
1
A
2
C
R72
0E
R72
0E
D7
GRN
D7
GRN
1
A
2
C
J13J13
1
2
3
R78 10KDNPR78 10KDNP
J27
HEADER 8
J27
HEADER 8
1
2
3
4
5
6
7
8
R76 10KR76 10K
R77
10K
DNP
R77
10K
DNP
R82
10.0K
R82
10.0K
12
R85
0E
R85
0E
J10J10
1
2
3
C58
0.1uF
C58
0.1uF
R67
2K R67
2K
R84
1K
R84
1K
R73
0E
R73
0E
D8
GRN
DNP
D8
GRN
DNP
1
A
2
C
R100 10KR100 10K
R75 10KDNPR75 10KDNP
R74
1K
R74
1K
R66 4.7KR66 4.7K
D3
GRN
DNP
D3
GRN
DNP
1
A
2
C
R71
10.0K
R71
10.0K
12
R99 10KR99 10K
J11J11
1
2
3
J4J4
1
2
3
R86
0E
R86
0E
U5
24FC512-I/P
U5
24FC512-I/P
GND
4VCC 8
SDA 5
SCL 6
A0
1
A1
2
A2
3
WP
7
R83
10.0K
R83
10.0K
12
R80 10KR80 10K
J15J15
1
2
3
J14J14
1
2
3
R70
10.0K
R70
10.0K
12
J6J6
1
2
3
J21J21
1
2
3
J8J8
1
2
3
R69
10.0K
R69
10.0K
12
D6
GRN
DNP
D6
GRN
DNP
1
A
2
C
J9J9
1
2
3
R79
10K
R79
10K
D5
GRN
DNP
D5
GRN
DNP
1
A
2
C
J5J5
1
2
3
R68
2K R68
2K
J16
HEADER 5X2
J16
HEADER 5X2
2
4
6
8
10
1
3
5
7
9
J20J20
1
2
3
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 36 2015 Microchip Technology Inc.
FIGURE B-7: EVB-LAN9353 EVALUATION BOARD SCHEMATIC 7
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:ϱĂŶĚ:ϴ ^tϭϬ ^tϴ ^tϲ
ϬϬϬdž
^ŚŽƌƚϮͲϯ ^ŚŽƌƚϭͲϯ ^ŚŽƌƚϭͲϯ ŽƉĞŶ
ϬϬϭϬ
^ŚŽƌƚϮͲϯ ^ŚŽƌƚϭͲϯ ^ŚŽƌƚϭͲϮ ^ŚŽƌƚϭͲϯ
ϬϬϭϭ
^ŚŽƌƚϮͲϯ ^ŚŽƌƚϭͲϯ ^ŚŽƌƚϭͲϮ ^ŚŽƌƚϭͲϮ
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^ŚŽƌƚϮͲϯ ^ŚŽƌƚϭͲϮ ^ŚŽƌƚϭͲϯ ŽƉĞŶ
ϬϭϭϬ
^ŚŽƌƚϮͲϯ ^ŚŽƌƚϭͲϮ ^ŚŽƌƚϭͲϮ ^ŚŽƌƚϭͲϯ
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ϭdždždž
^ŚŽƌƚϭͲϮ ŽƉĞŶ ŽƉĞŶ ŽƉĞŶ
ZD//W,zĐůŽĐŬŽƵƚϭϮŵĂ
ZD//W,zĐůŽĐŬŽƵƚϭϲŵĂ
/ŶƚĞƌŶĂůW,z
WŽƌƚϭ;ZD//ͿDK^dZWDĂƉƉŝŶŐ
WŽƌƚϭDŽĚĞ
ZD//DĐůŽĐŬŝŶ
;ZD//ƉŝŶƌĞŵĂƉŵŽĚĞͿ
ZD//DĐůŽĐŬŽƵƚϭϮŵĂ
ZD//DĐůŽĐŬŽƵƚϭϲŵĂ
ZD//W,zĐůŽĐŬŝŶ
Wϭͺ/EdW,z WϬͺDKϯ WϬͺDKϮ WϬͺDKϭ WϬͺDKϬ
:ϱĂŶĚ:ϴ ^tϴ ^tϵ ^tϳ ^tϱ
ϭ ϬϬdždž
^ŚŽƌƚϭͲϮ ^ŚŽƌƚϭͲϯ ^ŚŽƌƚϭͲϯ E E
ϭ ϬϭϬdž
^ŚŽƌƚϭͲϮ ^ŚŽƌƚϭͲϯ ^ŚŽƌƚϭͲϮ ^ŚŽƌƚϭͲϯ E
ϭ ϬϭϭϬ
^ŚŽƌƚϭͲϮ ^ŚŽƌƚϭͲϯ ^ŚŽƌƚϭͲϮ ^ŚŽƌƚϭͲϮ ^ŚŽƌƚϭͲϯ
ϭ Ϭϭϭϭ
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ϭϭ
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ϭϭ
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ϭϭ
ϭϭŽ
ZD//W,zĐůŽĐŬŽƵƚϭϲŵĂ
ϭϭϬ
ZD//W,zĐůŽĐŬŽƵƚϭϮŵĂ
ϭϬdžZD//W,zĐůŽĐŬŝŶ
Ϭϭϭ
ZD//DĐůŽĐŬŽƵƚϭϲŵĂ
ϬϭϬ
ZD//DĐůŽĐŬŽƵƚϭϮŵĂ
ϬϬdžZD//DĐůŽĐŬŝŶ
dƵƌďŽD//W,zϭϲŵĂ
WŽƌƚϬDK^dZWDĂƉƉŝŶŐ
DK
D//D
D/ / W,z
dƵƌďŽD//W,zϭϮŵĂ
P1_MODE0
P0_MODE3 &
P1_MODE1
P1_MODE2
P0_MODE0
P0_MODE1
P0_MODE2
Config 10
Port 0 : External (MII/RMII/TMII)
Port 1 and Port 2 : Internal
Config 9 :
Port 0 and Port 1 : External (RMII) and
Port 2 : Internal
Note: CONFIG9 or CONFIG 10 must be configured before P0/P1 mode configurations
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa .
3V3
3V3
3V3
3V3
3V3
3V3
P1_REFCLK_MODE0/P0_INCLK
P1_OUTD1_MODE2/P0_OUTD3
P1_OUTD0_MODE1/P0_OUTD2_MODE3
P0_OUTD1_MODE2
P0_OUTD0_MODE1
P0_OUT/REF_CLK_MODE0
P0_OUT/REF_CLK_MODE0
P0_OUTD0_MODE1
P0_OUTD1_MODE2
P1_REFCLK_MODE0/P0_INCLK
P1_OUTD0_MODE1/P0_OUTD2_MODE3
P1_OUTD1_MODE2/P0_OUTD3
R108 10.0KR108 10.0K
R104 10.0KR104 10.0K
R109 10.0KR109 10.0K
R105 10.0KR105 10.0K
SW8
JS102011CQN
SW8
JS102011CQN
1
2
3
R107 10.0KR107 10.0K
SW5
JS102011CQN
SW5
JS102011CQN
1
2
3
R106 10.0KR106 10.0K
SW6
JS102011CQN
SW6
JS102011CQN
1
2
3
SW10
JS102011CQN
SW10
JS102011CQN
1
2
3
SW7
JS102011CQN
SW7
JS102011CQN
1
2
3
SW9
JS102011CQN
SW9
JS102011CQN
1
2
3
EVB-LAN9353 Evaluation Board User’s Guide
2015 Microchip Technology Inc. DS50002393A-page 37
FIGURE B-8: EVB-LAN9353 EVALUATION BOARD SCHEMATIC 8
CONFIG9[CONFIG10]
CONFIG9 = 2RMII
CONFIG10 = 1 MII/RMII(Default)
Default -Open
8 Jumpers
Config9(2RMII) = 2-3 Short (1-2 - open)
Config10 = 1-2 Short (2-3 - open) (Default)
Default (1-2)
Jumper settings for CONFIG 9 or CONFIG 10
Note: For Switches to short 1-3, Knob Position should be
at 1-2 and vice versa .
Emulated Link Partner Default Advertised
Ability for Port 0
Emulated Link Partner Default Advertised
Ability for Port 1
J30
(P1_DUPLEX)
J31
(P1_SPEED)
Duplex
Strap_1
ADVERTISED LINK PARTNER ABILITY
(Bits 8,7,6,5)
1-2
1-2 1-2
1-2
2-3
2-3 2-3
2-3
1
11
1
0
00
0
Speed
Strap_1
10BASE-T full-duplex (0010)
100BASE-X full-duplex (1000)
10BASE-T half-duplex (0001)
100BASE-X half-duplex (0100)
J28
(P0_DUPLEX)
J29
(P0_SPEED)
Duplex
Strap_0
ADVERTISED LINK PARTNER ABILITY
(Bits 8,7,6,5)
1-2
1-2 1-2
1-2
2-3
2-3 2-3
2-3
1
11
1
0
00
0
Speed
Strap_0
10BASE-T full-duplex (0010)
100BASE-X full-duplex (1000) (Default)
10BASE-T half-duplex (0001)
100BASE-X half-duplex (0100)
SW12SW11
1-2
1-3
SW15SW13 SW14 SW16 SW17 SW18 Mode
1-3
1-2
1-3
1-2
1-3
1-2
1-3
1-2
1-3
1-2
1-3
1-2
1-3
1-2
2 RMII
1 MII/RMII/TMII
(Default)
Configuration
CONFIG 9
CONFIG 10
Default -Open
Default (1-2)
P1_INDV/P0_INER
P1_OUTDV
P1_MDC_DUPLEX/P0_CRS
P1_MDIO_SPEED/P0_COL
P0_IND1
P0_IND0
P0_INDV
P0_OUTD1_MODE2
P0_OUTD0_MODE1
P0_OUTDV
P0_DUPLEX
P0_OUTER_SPEED
P0_OUT/REF_CLK_MODE0
P0_MDC
P0_MDIO
P1_REFCLK_MODE0
P1_IND1
P1_INDV
P1_OUTD1_MODE2
P1_OUTD0_MODE1
P1_IND0
P1_MDC_DUPLEX
P1_MDIO_SPEED
P0_INCLK
P0_IND3
P0_INER
P0_OUTD3
P0_OUTD2
P0_CRS
P0_COL
P0_IND2
P1_REFCLK_MODE0/P0_INCLK
P1_IND1/P0_IND3
P1_IND0/P0_IND2
P1_OUTD1_MODE2/P0_OUTD3
P1_OUTD0_MODE1/P0_OUTD2_MODE3
P0_DUPLEX
P0_OUTER_SPEED
P1_MDC_DUPLEX/P0_CRS
P1_MDIO_SPEED/P0_COL
3V3
3V3
3V3
3V3
P1_REFCLK_MODE0/P0_INCLK
P1_OUTD1_MODE2/P0_OUTD3
P1_OUTD0_MODE1/P0_OUTD2_MODE3
P0_OUTD1_MODE2
P0_OUTD0_MODE1
P0_OUT/REF_CLK_MODE0
P0_MDIO
P0_MDC
P0_COL
P0_CRS
P0_IND3
P0_IND2
P0_IND0
P0_INDV
P0_INCLK
P0_INER
P0_OUTER_SPEED
P0_OUT/REF_CLK_MODE0
P0_OUTDV
P0_OUTD0_MODE1
P0_OUTD1_MODE2
P0_OUTD2
P0_OUTD3
P0_IND1
P1_IND0
P1_INDV
P1_REFCLK_MODE0
P1_OUTDV
P1_OUTD0_MODE1
P1_OUTD1_MODE2
P1_MDIO_SPEED
P1_MDC_DUPLEX
P1_IND1
R116
33
R116
33
SW11
JS102011CQN
SW11
JS102011CQN
1
2
3
J28J28
1
2
3
SW16
JS102011CQN
SW16
JS102011CQN
1
2
3
SW18
JS102011CQN
SW18
JS102011CQN
1
2
3
J31J31
1
2
3
U4B
LAN9353 U4B
LAN9353
P1_OUTDV[RESERVED]
35
P1_INDV[P0_INER]
33
P1_OUTD0/P1_MODE1[P0_OUTD2/P0_MODE3]
16
P1_DUPLEX/P1_MDC[P0_CRS]
49
P1_OUTD1/P1_MODE2[P0_OUTD3]
15
P1_SPEED/P1_MDIO[P0_COL]
50
P0_OUTDV 23
P0_OUTD0/P0_MODE1 22
P0_OUTD1/P0_MODE2 21
P0_SPEED[P0_OUTER/P0_SPEED] 19
P0_REFCLK/P0_MODE0[P0_OUTCLK/P0_REFCLK/P0_MODE0] 25
P0_INDV 26
P0_IND0 27
P0_IND1 28
P1_REFCLK/P1_MODE0[P0_INCLK]
29
P1_IND0[P0_IND2]
30 P1_IND1[P0_IND3]
31
P0_DUPLEX 36
P0_MDC 39
P0_MDIO 40
R125 33R125 33
R145 33R145 33 R123 33R123 33
J30J30
1
2
3
R146 33
R146 33 R124 33R124 33
R117 33R117 33
SW13
JS102011CQN
SW13
JS102011CQN
1
2
3
J29J29
1
2
3
SW14
JS102011CQN
SW14
JS102011CQN
1
2
3
R122 33R122 33
R120 10.0KR120 10.0K
SW15
JS102011CQN
SW15
JS102011CQN
1
2
3
SW17
JS102011CQN
SW17
JS102011CQN
1
2
3
R119 10.0KR119 10.0K
R121 10.0KR121 10.0K
J22J22
1 2
R144 33R144 33
SW12
JS102011CQN
SW12
JS102011CQN
1
2
3
R118 10.0KR118 10.0K
R147 33R147 33
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 38 2015 Microchip Technology Inc.
FIGURE B-9: EVB-LAN9353 EVALUATION BOARD SCHEMATIC 9
J26 = Default open
MII Male for External MAC Board
MII Female for External PHY Board
Pullup for MDIO(common for all PHY) signal
Short option for RXDV & CRS
for RMII mode
J28 = Default open
Short for RMII mode
Default (1-3)
Default Short 2-3
PORT 0
PORT 1
MII Male for External MAC Board
MII Female for External PHY Board
Pullup for MDIO(common for all PHY) signal
Default Short 2-3
For RMII
Default (1-3)
Switch
Settings Description Mode
SW23 (1-3)
Default
SW23 (1-2)
SW24 (1-3)
Default
SW24 (1-2)
TX Clock used as a Reference Clock
RX Clock used as a Reference Clock
Reference clock used as a TX clock
Reference clock used as a RX clock
RMII MAC
RMII MAC
RMII PHY
RMII PHY
Note: 1. For Switches to short 1-3, Knob Position should be
at 1-2 and vice versa .
2. External PHY considered LAN8742
Switch
Settings Description Mode
SW25 (1-3)
Default
SW25 (1-2)
SW26 (1-3)
Default
SW26 (1-2)
TX Clock used as a Reference Clock
RX Clock used as a Reference Clock
Reference clock used as a TX clock
Reference clock used as a RX clock
RMII MAC
RMII MAC
RMII PHY
RMII PHY
Note: 1. For Switches to short 1-3, Knob Position should be
at 1-2 and vice versa .
2. External PHY considered LAN8742
Port 0 - RMII RX Clock Configurations
Port 1 - RMII RX Clock Configurations
MAC_TXCLK0
MAC_RXCLK0
P0_MDIO
P0_IND1
P0_OUTD3
P0_INER
P0_IND3
P0_OUTDV
P0_MDC
P0_IND0
P0_OUTD2
PHY_RXCLK0
P0_OUTD1_MODE2
P0_CRS
P0_COL
P0_INDV
P0_IND2
PHY_TXCLK0
TXER0
P0_OUTD0_MODE1
P0_INDV P0_CRS
P0_OUTDV
TXER0
P0_MDIO
P0_MDC
P0_OUTER_SPEED
P0_INCLK
P0_OUT/REF_CLK_MODE0
MAC_RXCLK0
PHY_RXCLK0
MAC_TXCLK0
PHY_TXCLK0
P1_CRS
MAC_TXCLK1
MAC_RXCLK1
P1_OUTDV
P1_MDIO_SPEED
P1_MDC_DUPLEX
MAC_RXCLK1
PHY_RXCLK1
MAC_TXCLK1
PHY_TXCLK1
P1_INDV P1_CRS
P1_MDIO_SPEED
P1_IND1
P1_OUTDV
P1_MDC_DUPLEX
P1_IND0
P1_OUTD1_MODE2
P1_CRS
P1_INDV
P1_OUTD0_MODE1
PHY_TXCLK1
PHY_RXCLK1P1_REFCLK_MODE0
5V
3V3
3V3
5V
5V
3V3 3V3
5V
P0_MDIO
P0_MDC
P0_COL
P0_CRS
P0_IND3
P0_IND2
P0_IND0
P0_INDV
P0_INCLK
P0_INER
P0_OUTER_SPEED
P0_OUT/REF_CLK_MODE0
P0_OUTDV
P0_OUTD0_MODE1
P0_OUTD1_MODE2
P0_OUTD2
P0_OUTD3
P0_IND1
P1_INDV
P1_REFCLK_MODE0
P1_OUTDV
P1_OUTD0_MODE1
P1_OUTD1_MODE2
P1_MDIO_SPEED
P1_MDC_DUPLEX
P1_IND1
P1_IND0
R13210K DNPR13210K DNP
SW24
JS102011CQN
SW24
JS102011CQN
1
2
3
R130 0ER130 0E
J25J25
1 2
R127 0ER127 0E
R134 49.9K
DNP
R134 49.9K
DNP
J18
MII_RA
AMP - 6-5174218-2
J18
MII_RA
AMP - 6-5174218-2
+5V[3]
1
MDIO
2
MDC
3
RXD3
4
RXD2
5
RXD1
6
RXD0
7
RX_DV
8
RX_CLK
9
RX_ER
10
TX_ER
11
TX_CLK
12
TX_EN
13
TXD0
14
TXD1
15
TXD2
16
TXD3
17
COL
18
CRS
19
+5V[4]
20 +5V[2] 21
COMMON[18] 22
COMMON[17] 23
COMMON[16] 24
COMMON[15] 25
COMMON[14] 26
COMMON[13] 27
COMMON[12] 28
COMMON[11] 29
COMMON[10] 30
COMMON[9] 31
COMMON[8] 32
COMMON[7] 33
COMMON[6] 34
COMMON[5] 35
COMMON[4] 36
COMMON[3] 37
COMMON[2] 38
COMMON[1] 39
+5V[1] 40
C640.1uF C640.1uF
R1371.5K R1371.5K
C66 0.1uFC66 0.1uF
J26J26
12
C5910uF C5910uF
J23
MII_RA
AMP - 6-5174218-2
J23
MII_RA
AMP - 6-5174218-2
+5V[3]
1
MDIO
2
MDC
3
RXD3
4
RXD2
5
RXD1
6
RXD0
7
RX_DV
8
RX_CLK
9
RX_ER
10
TX_ER
11
TX_CLK
12
TX_EN
13
TXD0
14
TXD1
15
TXD2
16
TXD3
17
COL
18
CRS
19
+5V[4]
20 +5V[2] 21
COMMON[18] 22
COMMON[17] 23
COMMON[16] 24
COMMON[15] 25
COMMON[14] 26
COMMON[13] 27
COMMON[12] 28
COMMON[11] 29
COMMON[10] 30
COMMON[9] 31
COMMON[8] 32
COMMON[7] 33
COMMON[6] 34
COMMON[5] 35
COMMON[4] 36
COMMON[3] 37
COMMON[2] 38
COMMON[1] 39
+5V[1] 40
C60 10uFC60 10uF
R1311.5K R1311.5K
R129 0EDNP R129 0EDNP
C65 10uFC65 10uF
TP7TP7 TP6TP6
SW25
JS102011CQN
SW25
JS102011CQN
1
2
3
TP8TP8
SW26
JS102011CQN
SW26
JS102011CQN
1
2
3
J19
FEMALE MII CONN
AMP - 749069-4
J19
FEMALE MII CONN
AMP - 749069-4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Chassis1
Chassis2
R139 10KR139 10K
SW23
JS102011CQN
SW23
JS102011CQN
1
2
3
R133 10KR133 10K
R136 0ER136 0E
C6310uF C6310uF
R135 0ER135 0E
R128 0ER128 0E
J24
FEMALE MII CONN
AMP - 749069-4
J24
FEMALE MII CONN
AMP - 749069-4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Chassis1
Chassis2
R126 0ER126 0E
C62 0.1uFC62 0.1uF
TP5TP5
R13810K R13810K
C610.1uF C610.1uF
2015 Microchip Technology Inc. DS50002393A-page 39
EVB-LAN9353
EVALUATION BOARD
USER’S GUIDE
Appendix C. Bill of Materials (BOM)
C.1 INTRODUCTION
This appendix includes the EVB-LAN9353 Evaluation Board Bill of Materials (BOM).
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 40 2015 Microchip Technology Inc.
Configuration: Config 10: Two internal copper mode with higher size EEPROM (24FC512)
TABLE C-1: EVB-LAN9353 EVALUATION BOARD BILL OF MATERIALS
Item Qty Reference Designator(s) Part PCB Footprint Manufacturer Manufacturer Part Number
1 2 C2,C4 10uF CAP0805 Murata GRM21BR61E106KA73L
2 21 C3,C5,C6,C8,C10,C11,C13,C14,C15,C16,C17
,C18,C21,C22,C24,C25,C58,C61,C62,C64,C6
6
0.1uF CAP0603 Murata GRM155R61E104KA7D
3 1 C19 1uF CAP0603 Murata GRM188R61C105KA93D
4 1 C20 470pF CAP0603 Murata GRM033R71E471KA01D
5 2 C26,C27 18pF CAP0603 Murata GRM1885C1H180JA01D
6 2 C32,C37 0.022uF CAP0603 Kemet C0603C223K5RACTU
7 4 C59,C60,C63,C65 10uF CAP0603 TDK C1608X5R0J106K080AB
8 3 D1,D4,D7 GRN LED0603 Wurth electronics 150 060 GS7 500 0
9 1 D2 RED LED0603 Wurth electronics 150 060 RS7 500 0
10 5 FB1,FB2,FB3,FB4,FB5 2A/0.05DCR RES0603 Murata BLM18EG221SN1D
11 1 J1 SKT_P-
WR_2R0mm_4A_THRU_R
A
th_conn_pwrjack_dc-210_rt Cui Stack PJ-002AH
12 18 J4,J5,J6,J7,J8,J9,J10,J11,J12,J13,J14,J15,J2
0,J21,J28,J29,J30,J31
HDR_1x3 TH_CONN_1X3P FCI 68000-103HLF
13 1 J16 HEADER 5X2 th_conn_2x5p_BOX FCI 67997-210HLF
14 2 J18,J23 MII_RA TH_CON-
N_TE-5173278_40P
TE 5173278-2-ND
15 2 J19,J24 FEMALE MII CONN TH_CONN_MII-749069-4 TE 749069-4-ND
16 3 J22,J25,J26 CONN_2P th_conn_1x2p FCI 68000-102HLF
17 1 J27 CONN_8P th_conn_1x8p FCI 68000-108HLF
18 1 Q1 NDS355AN_NMOS sot23-NDS Fairchild NDS355AN
19 15 R1,R15,R29,R126,R127,R128,R130,R135,R1
36,FB6,FB7,R72,R73,R85,R86
0E RES0603 Panasonic ERJ-3GEY0R00V
20 4 R2,R8,R74,R84 1K RES0603 Panasonic ERJ-3GEYJ102V
21 1 R3 3.30K RES0603 Yageo America 9C06031A3301FKHFT
22 1 R4 470E RES0603 BOURNS CR0603-FX-4700ELF
23 1 R4A 33E RES0603 BOURNS CR0603-FX-33R0ELF
24 1 R5 4.75K RES0603 Panasonic ERJ-3EKF4751V
25 25 R6,R69,R70,R71,R81,R82,R83,R76,R79,R80,
R99,R100,R133,R138,R139,R104,R105,R106
,R107,R108,R109,R118,R119,R120,R121
10.0K RES0603 Panasonic ERJ-3EKF1002V
2015 Microchip Technology Inc. DS50002393A-page 41
26 1 R7 100E RES0603 Panasonic ERJ-3EKF1000V
27 1 R9 2.2K RES0603 Panasonic ERJ-3GEYJ222V
28 1 R10 12.1K RES0603 Rohm MCR01MZPF1202
29 8 R11,R12,R13,R14,R25,R26,R27,R28 49.9E RES0603 Yageo America 9C06031A49R9FKHFT
30 8 R17,R19,R21,R23,R31,R33,R35,R37 0 RES0402 Panasonic ERJ-2GE0R00X
31 2 R24,R38 0 RES1210 Vishay CRCW12100000Z0EA
32 4 R61,R62,R102,R103 330E RES0603 Panasonic ERJ-3GEYJ331V
33 2 R67,R68 2K RES0603 Panasonic ERJ-3GEYJ202V
34 10 R116,R117,R122,R123,R124,R125,R144,R14
5,R146,R147
33E RES0603 BOURNS CR0603-FX-33R0ELF
35 2 R131,R137 1.5K RES0603 Panasonic ERJ-3GEYJ152V
36 1 SW1 SW-SPDT-SLIDE sw_ck_1101m2s3cqe2 C&K 1101M2S3CQE2
37 1 SW2 sw_pb_2P sw_pb_2P Panasonic EVQ-PJU04K
38 18 SW5,SW6,SW7,SW8,SW9,SW10,SW11,SW1
2,SW13,SW14,SW15,SW16,SW17,SW18,SW
23,SW24,SW25,SW26
450301014042 TH_SW_SPST_3P_10x2p5 Wurth electronics 450301014042
39 1 TP1 RED TH_TP_60D40 Keystone 5000
40 1 TP2 ORANGE TH_TP_60D40 Keystone 5003
41 TP9,TP10 BLACK TH_TP_60D40 Keystone 5001
42 2 T1,T2 Pulse - J0011D01BNL th_conn_pulse_rj45_j0026 Pulse Electronics 553-1483-ND
43 1 U1 3_Amp TH_DC-DC_VERT_5PIN_P
67
Murata OKR-T/3-W12-C
44 1 U2 TPS3125 SOT23_5 TI TPS3125L30DBVR
45 1 U3 74LVC1G14 SOT23_5 TI SN74LVC1G14DCKR
46 1 U4 LAN9353 IC_QFN64 Microchip LAN9353
47 1 U5 Round Base IC_DIP8_300 Assmann AR08-HZL-TT-R
48 1 U5 24FC512 IC_DIP8_300 Microchip 24FC512-I/P
49 4 D3,D5,D6,D8 GRN LED0603 Wurth electronics 150 060 GS7 500 0
50 1 Y1 25.000MHz XTAL_HCM49 Cardinal Components
Inc.
CSM1Z-A5B2C5-40-25.0D18-F
TABLE C-1: EVB-LAN9353 EVALUATION BOARD BILL OF MATERIALS (CONTINUED)
Item Qty Reference Designator(s) Part PCB Footprint Manufacturer Manufacturer Part Number
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 42 2015 Microchip Technology Inc.
NOTES:
DS50002393A-page 43 2015 Microchip Technology Inc.
AMERICAS
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Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
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Web Address:
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Tel: 678-957-9614
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Fax: 86-28-8665-7889
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Fax: 86-25-8473-2470
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Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
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Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
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Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
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Tel: 86-592-2388138
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Tel: 86-756-3210040
Fax: 86-756-3210049
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Tel: 91-80-3090-4444
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India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
01/27/15
