ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 1 -
FEATURES
The AK5355 is a low voltage 16bit A/D converter for digital audio systems. The AK5355 also includes an
Input Gain Amplifier, making it suitable for microphone applications or low-input signal levels. The analog
signal input of the AK5355 is single-ended, eliminating the need for external filters. The AK5355 is housed
in a space-saving 16pin TSSOP or 20pin QFN pac kage.
FEATURES
1. Resolution: 16bits
2. Recording Functions
• Gain Amplifier (0dB / +15dB)
• Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
3. ADC Characteristics
• Single-ended Input
• Input Level: 1.8Vpp@VA=3.0V (= 0.6 x VA)
• S/(N+D): 85dB
• DR, S/N: 91dB
4. Master Clock: 256fs/384fs/512fs
5. Audio Data Format: MSB First, 2’s compliment
• 16bit MSB justified or I2S
8. Power Supply
• VA, VD: 2.1 ∼ 3.6V (typ. 3.0V)
9. Powe r Supply Current: 5mA
10. Ta = -40 ∼ 85°C
11. Package: 16pin TSSOP
20pin QFN (4.2mm x 4.2mm, 0.5mm pitch)
LIN
VCOM
VA
VSS
MCLK
SDTO
BCLK
LRCK
VD
A
DC HPF
A
udio I/F
Controller
Clock Divider
PDN
RIN
DIFSEL
Low Power 16bit ∆Σ ADC
AK5355
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 2 -
Ordering Guide
AK5355VT -40 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AK5355VN -40 ∼ +85°C 20pin QFN (0.5mm pitch)
AKD5355 Evaluation Board for AK5355VT
Pin Layout (AK5355VT)
1VCOM
RIN
VSS
LIN
VA
VD
SEL
NC
Top
View
2
3
4
5
6
7
8
TST1
NC
BCLK
MCLK
LRCK
SDTO
16
15
14
13
12
11
10
9
DIF
PDN
Pin Layout (AK5355VN)
NC
TST1
NC
NC
VCOM
DIF
PDN
BCLK
MCLK
LRCK
RIN
LIN
VSS
VA
VD
SDTO
NC
NC
NC
SEL
Top View
16
17
18
19
20
15
14
13
1
10
9
8
7
6
2
3
4
5
12
11
A
K5355
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 3 -
PIN/FUNCTION (AK5355VT)
No. Pin Name I/O Function
1 VCOM O ADC Common Voltage Output Pin
2 RIN I Rch Input Pin
3 LIN I Lch Input Pin
4 VSS - Ground Pin
5 VA - Analog Power Supply Pin, +3.0V
6 VD - Digital Power Supply Pin, +3.0V
7 SEL I Input Gain Select Pin
“L”: 0dB, “H”: +15dB
8 NC - NC Pin (No internal bonding)
9 SDTO O Audio Serial Data Output Pin
10 LRCK I Input/Output Channel Clock Pin
11 MCLK I Master Clock Input Pin
12 BCLK I Audio Serial Data Clock Pin
13 PDN I Reset & Power Down Pin
“L” : Reset & Power down, “H” : Normal opera tion
14 DIF I Audio Data Format Select Pin
“L”: MSB justified, “H”: I2S
15 NC - NC Pin (No internal bonding)
16 TST1 I TEST pin (Pull-down Pin)
This pin should be left floating or connected to VSS
Note: All digital input pins should not be left floating.
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 4 -
PIN/FUNCTION (AK5355VN)
No. Pin Name I/O Function
1 RIN I Rch Input Pin
2 LIN I Lch Input Pin
3 VSS - Ground Pin
4 VA - Analog Power Supply Pin, +3.0V
5 VD - Digital Power Supply Pin, +3.0V
6 SEL I
Input Gain Select Pin
“L”: 0dB, “H”: +15dB
7 NC -
NC Pin (No internal bonding)
This pin should be left floating.
8 NC -
NC Pin (No internal bonding)
This pin should be left floating.
9 NC -
NC Pin (No internal bonding)
This pin should be left floating.
10 SDTO O Audio Serial Data Output Pin
11 LRCK I Input/Output Channel Cl ock Pin
12 MCLK I Master Clock Input Pin
13 BCLK I Audio Serial Data Cl ock Pin
14 PDN I Reset & Power Down Pin
“L”: Reset & Power down, “H”: Normal operation
15 DIF I Audio Data Format Select Pin
“L”: MSB justified, “H”: I2S
16 NC - NC Pin (No internal bonding)
This pin should be left floating.
17 TST1 I TEST pin (Pull-down Pin)
This pin should be left floating or connected to VSS
18 NC - NC Pin (No internal bonding)
This pin should be left floating.
19 NC - NC Pin (No internal bonding)
This pin should be left floating.
20 VCOM O ADC Common Voltage Output Pin
Note: All digital input pins should not be left floating.
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 5 -
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter Symbol Min max Units
Power Supply
Analog
Digital VA
VD -0.3
-0.3 4.6
4.6 V
V
Input Current (Any Pin Except Supplies) IIN - ±10 mA
Analog Input Voltage (LIN, RIN pins) VINA -0.3 VA+0.3 V
Digital Input Voltage VIND -0.3 VD+0.3 V
Ambient Temperature (power applied) Ta -40 85 °C
Storage Temperature Tstg -65 150 °C
Note 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter Symbol min typ max Units
Power Supply
Analog (VA pin)
Digital (VD pin) VA
VD 2.1
2.1 3.0
3.0 3.6
VA V
V
Note 1. All voltages with respect to ground.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 6 -
ANALOG CH AR AC TE RI S T I C S
(Ta=25°C; VA, VD=3.0V; fs= 44.1kHz; Signal Frequency=1kHz; M easurement frequency=10Hz ∼ 20kHz;
unless otherwise specified)
Parameter min typ max Units
Resolution 16 bits
Input PGA Characteristics (IPGA): Gain = 0dB 1.65 1.8 1.95 Vpp
Input Voltage (Note 2) Gain = +15dB 0.29 0.32 0.35 Vpp
Gain = 0dB 27 40 kΩ
Input Impedance Gain = +15dB 20 30 kΩ
ADC Analog Input Characteristics: (Note 3) Gain = 0dB 75 85 dB
S/(N+D) (-0.5dBFS Output) Gain = +15dB 70 80 dB
Gain = 0dB 84 91 dB
D-Range (-60dBFS Output, A-weight) Gain = +15dB 76 84 dB
Gain = 0dB 84 91 dB
S/N (A-weight) Gain = +15dB 76 84 dB
Gain = 0dB 90 100 dB
Interchannel Isolat ion Gain = +15dB 80 90 dB
Gain = 0dB 0.2 0.5 dB
Interchannel Gain Mismatch Gain = +15dB 0.2 1.0 dB
Power Supplies
Power Supply Current: VA+VD
Normal Operation (PDN=“H”) 5 7.5 mA
AK5355VT 10 100 µA
Power Down (PDN=“L”) (Note 4)
AK5355VN 10 20 µA
Note 2. Analog input voltage (full-scale voltage) scales with VA.
Gain = 0dB; 0.6 x VA
Gain = +15dB; 0.107 x VA
Note 3. ADC measurements are input from LIN/RIN and routed through input gain amplifier.
The internal HPF cancels the offset of input gain amplifier and ADC.
Note 4. In case of power-down mode, all digital input pins including clocks pins (MCLK, BCLK and LRCK) are held at
VD or VSS. PDN pin is held at VSS.
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 7 -
FILTER CHARACTERISTICS
(Ta=25°C; VA, VD=2.1 ∼ 3.6V; fs=44.1kHz)
Parameter Symbol min typ max Units
ADC Digital Filter (Decimation LPF):
Passband (Note 5)
±0.1dB
-1.0dB
-3.0dB
PB
0
20.0
21.1
17.4
kHz
kHz
kHz
Stopband (Note 5) SB 27.0 kHz
Passband Ripple PR ±0.1 dB
Stopband Attenuation SA 65 dB
Group Delay (Note 6) GD 17.0 1/fs
Group Delay Distortion ∆GD 0
µs
ADC Digital Filter (HPF):
Frequency Response (Note 5)
-3dB
-0.5dB
-0.1dB
FR
3.4
10
22
Hz
Hz
Hz
Note 5. The passband and stopband frequencies scale with fs (sampling frequency).
For exampl es, PB=0.454 x fs(@ADC: -1.0dB).
Note 6. The calcula ted de lay tim e cause d by di gital fi ltering. Thi s tim e is from t he input of an analog signal to sett ing the
16bit data of both channels to the output register of the ADC and includes the group delay of the HPF.
DC CHARACTERISTICS
(Ta=25°C; VA, VD=2.1 ∼ 3.6V)
Parameter Symbol min typ max Units
High-Level Input Voltage (Except for TST1
pin)
Low-Level Input Voltage (Except for TST1 pi n)
VIH
VIL 75%VD
- -
- -
25%VD V
V
High-Level Output Voltage (Iout=-80µA)
Low-Level Output Voltage (Iout=80µA) VOH
VOL VD-0.4
- - -
0.4 V
V
Input Leakage Current (Note 7) Iin - - ± 10 µA
Note 7. TST1 pin is pulled-down internally (typ. 100kΩ)
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 8 -
SWITCHING CHARACTERISTICS
(Ta=25°C; VA, VD=2.1 ∼ 3.6V; CL=20pF)
Parameter Symbol min typ max Units
Control Clock Frequency
Master Clock (MCLK)
256fs: Frequency
Pulse Width Low
Pulse Width High
384fs: Frequency
Pulse Width Low
Pulse Width High
512fs: Frequency
Pulse Width Low
Pulse Width High
Channel Clock (LRCK) Frequency
Duty Cycle
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
duty
2.048
28
28
3.072
23
23
4.096
16
16
8
45
11.2896
16.9344
22.5792
44.1
12.8
19.2
25.6
50
55
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
kHz
%
Audio Interface Timing
BCLK Period
BCLK Pulse Width Low
Pulse Width High
BCLK “↓” to LRC K
LRCK Edge to SDTO (MSB)
BCLK “↓” to SD TO
tBLK
tBLKL
tBLKH
tBLR
tDLR
tDSS
312.5
130
130
-tBLKH+50
tBLKL-50
80
80
ns
ns
ns
ns
ns
ns
Reset / Init ia lizing Timing
PDN Pulse Width
PDN “↑” to SDTO (Note 8)
tPW
tPWV
150
4128
ns
1/fs
Note 8. This is the number of LRCK rising after the PDN pin is pulled high.
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 9 -
Timing Diagram
MCLK
1/fCLK
tCLKH tCLKL
VIH
VIL
LRCK
1/fs
VIH
VIL
BCLK
tBLK
VIH
VIL
tBLKH tBLKL
Figure 1. Clock Timing
VIH
LRCK
VIL
VIH
BCLK
tBLR
VIL
tDLR tDSS
SDTO 50%VDD15 (MSB)
Figure 2. Audio Data Input/Output Timing (Audio I/F = No.0)
PDN
SDTO
VIL
tPWV
tPW
50%VD
Figure 3. Reset Timing
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 10 -
OPERATION OVERVIEW
System Clock
The clocks require d to operate are MCLK (256fs/384fs/512fs), LRCK (fs) and BC LK (32fs∼). The master clock (M CLK)
should be synchronized with LRCK. The phase between these clocks does not matter. The frequency of MCLK can be
input as 256fs, 384fs or 512fs. When the 384fs or 512fs is input, the internal master clock is divided into 2/3 or 1/2
automatically.
*fs is sampling frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever the ADC is in operation. If these
clocks are not provided, the AK5355 may draw excess current and will not operate properly because it utilizes these
clocks for internal dynamic refresh of regist ers. If the external clocks are not present, the AK5355 should be placed in
power-down mode.
Audio Data I/F Format
The SDTO, BCLK and LRCK pins are connected to an external controller. The audio data format has two modes,
MSB-first and 2’s complim ent. The data format is set using the DIF pin.
No. DIF pin SDTO (ADC) LRCK BCLK Figure
0 L 16bit MSB justified Lch: “H”, Rch: “L” ≥ 32fs Figure 4
1 H I2S Com patible Lch: “L”, Rch: “H” ≥ 32fs Figure 5
Table 1. Audio Data Forma t
LRCK
BCLK
(
32fs
)
SDTO(o)
012 8910 1213 15012 8910 1213 150
15
1
14 4876 032
11 14
15 15 14 4876 03215
1411
15
13
BCLK
(
64fs
)
SDTO
(
o
)
0 1 2 3 14 15 17 18 31 0 1 2 14 15 17 18 31 0
15
1
14 015 14 1 2 1 15
15:MSB, 0:LSB Lch Data Rch Data
2113
16
0
163
13
3
13 13
3
Figure 4. Audio Data Timi ng (No.0)
LRCK
BCLK
(
32fs
)
SDTO(o)
0 1 2 4 9 10 12 13 15 0 1 2 4 9 10 12 13 15 0
0
1
15 513 7 7 143
11 14
26 0 15 513 7 7 14326
1411
0
13
BCLK(64fs)
SDTO
(
o
)
0 1 2 3 14 15 17 18 31 0 1 2 4 14 15 17 18 31 0 1
15 015 13 2 1
15:MSB, 0:LSB Lch Data Rch Data
2114
16
0
163
14
14
3
2
14
3
4
Figure 5. Audio Data Timing (No. 1)
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 11 -
Digital High Pass Filter
The AK5355 has a Digital High Pass Filter (HPF) to cancel DC-offset in both the ADC and input gain amplifier. The
cut-off frequency of the HPF is 3.4Hz at fs=44.1kHz. This cut-off frequency scales with the sampling frequency (fs).
Input Gain Amplifier
The AK5355 includes an input gain amplifier. The gain can be changed to 0dB or +15dB by using the SEL pin. Input
impedance is 40kΩ typically.
SEL pin Gain
L 0dB
H +15dB
Table 2. Input Gain Amplifier
Power down
The AK5355 is placed in t he power-down mode by bringing PDN “L”. The di gital filter is also rese t at the same time. This
reset should alway s be done after powe r-up. An analog i nitial izati on cycle st arts a fter exit ing the power-down m ode. The
output data SDTO becomes available after 4128 cycles of LRCK clock. During initialization, the ADC digital data
outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle to the data corresponding to the
input signals at the end of initialization (Settling time equals the group delay time approximately).
Normal Operation
Internal
State
PDN
Power-down Initialize Normal Operation
4128/fs(93.6ms@fs=44.1kHz)
Idle N o is e
GD GD
“0”data
A
/D In
(Analog)
A
/D Out
(Digital)
Clock In
MCLK,LRCK,BCLK
(1)
(2)
(3)
“0”data Idle Nois e
Notes:
(1) Digital output corresponding to the analog input is delayed by the Group Delay amount (GD).
(2) A/D output is “0” data in the power-down state.
(3) When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5355 should be placed in the
power-down state.
Figure 6. Power-down/up sequence example
System Reset
The AK5355 should be reset once by bringing PDN ”L” upon power-up. The AK5355 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK5355 is in the
power-down mode until MCLK and LRCK are input.
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
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SYSTEM DESIGN (AK5355VT)
Figure 7 shows the system connection diagram. An evaluation board [AKD5355] is available which demonstrates the
application circuit, optimum layout, power supply arrangements and measurement results.
VCOM1
RIN2
LIN3
VSS4
VA5
VD6
SEL7
NC8
16
15
14
13
12
11
10
9
TST1
NC
PDN
BCLK
MCLK
LRCK
SDTO
Top View
0.1µ
+
+
Rch In
Lch In
Analog Supply 10µ +
Controller
Sy stem GroundAnalog Ground
DIF
Reset
+0.1µ2.2µ
Mode
Setting
2.1 ∼ 3.6V
0.1µ
10µ +
Digital Supply
2.1 ∼ 3.6V
Figure 7. System Connection Diagram Example (AK5355VT)
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 13 -
SYSTEM DESIGN (AK5355VN)
Figure 8 shows the system connection diagram. An evaluation board [AKD5355] is available which demonstrates the
application circuit, optimum layout, power supply arrangements and measurement results.
0.1µ
+
+
Rch In
Lch In
Analog Supply 10µ +
Controller
System Grou
n
Analog Ground
Reset
+0.1µ
2.2µ
Mode
Setting
2.1 ∼ 3.6V
0.1µ
10µ +
Digital Supply
2.1 ∼ 3.6V
RIN
LIN
VSS
VA
VD
VCOM
NC
NC
TST1
NC
DIF
PDN
BCLK
MCLK
LRCK
SEL
NC
NC
NC
SDTO
Top View
1
2
3
4
5
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
Figure 8. System Connection Diagram Example (AK5355VN)
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 14 -
MIC Device Connection Example
Figure 9 and Figure 10 show the connection example of MIC Device. In this case, a mono microphone is connected to
LIN pin the AK5355. Unused R IN pi n c an be open. The power supply for the microphone is provided via 4.4kΩ (2.2kΩ
+ 2.2kΩ) from anal og power supply. The power supply noise provided to the microphone should be care because the
microphone gain is usually high, around 40dB. In Figure 9, 1st order LPF by 2.2kΩ and 10µF is inserted betw ee n th e
power supply and the microphone.
The AK5355 has a gain of +15dB in analog stage. However, as the usual application needs a gain of around 40dB or
50dB, the shortage of gain, 25dB or 35dB, should be covered by digital processing like DSP.
The total S/N in ea ch gain level is shown in Table 3
Analog Gain Digi tal Gain S/N
+15dB 0dB 83dB
+15dB +25dB 58dB
+15dB +35dB 48dB
Table 3. S/N of each gain level
VCOM1
RIN2
LIN3
VSS4
VA5
VD6
SEL7
NC8
16
15
14
13
12
11
10
9
TST1
NC
PDN
BCLK
MCLK
LRCK
SDTO
Top View
0.1µ
Analog Supply 10µ +
Controller
Sy stem GroundAnalog Ground
DIF
Reset
+0.1µ2.2µ
Mode
Setting
2.1 ∼ 3.6V
0.1µ
10µ +
Digital Supply
2.1 ∼ 3.6V
MIC
10µ +
2.2k
2.2k
0.1µ
Figure 9. MIC Device Connection Example (AK5355VT)
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
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0.1µ Analog Supply 10µ +
Controller
System Grou
Analog Ground
Reset
+0.1µ
2.2µ
Mode
Setting
2.1 ∼ 3.6V
0.1µ
10µ +
Digital Supply
2.1 ∼ 3.6V
RIN
LIN
VSS
VA
VD
VCOM
NC
NC
TST1
NC
DIF
PDN
BCLK
MCLK
LRCK
SEL
NC
NC
NC
SDTO
Top View
1
2
3
4
5
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
MIC
10µ +
2.2k
2.2k
0.1µ
Figure 10. MIC Device Connection Example (AK5355VN)
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 16 -
1. Grounding and Power Supply Decoupling
The AK5355 requires careful att e ntion to power supply and grounding arrangements. VA is usually supplied from the
analog supply in the system. VD is a power supply pin to interface with the external ICs and is supplied from the digital
supply in the system. VSS of the AK5355 should be connected to the analog ground plane. System analog ground and
digital ground should be connected together near to where the supplies are brought onto the printed circuit board.
Decoupling capacitors should be as near to the AK5355 as possible, with the small value ceramic capacitor being the
nearest.
2. Voltage Reference
The input to VA Voltage sets the a nalog input range. A 0.1µF ceramic capacitor and a 10µF electrolytic capacitor are
normally connected to VA and VSS pins. VCOM is a signal ground of this chip. An electroly tic 2.2µF in para lle l with a
0.1µF ceramic capacitor atta ched to these pins eliminates the effects of high frequency noise. No load current may be
drawn from the VCOM pin. All signa ls, especially cloc k, should be kept away from the VA, VD and VCOM pi ns in order
to avoid unwanted coupling int o the AK5355.
3. Analog Inputs
The analog inputs are single-ended and the input resistance is 40kΩ (typ). The input signal range scales with nom inally
(0.6 x VA) Vpp (typ) @ GAIN = 0dB centered around the internal common voltage (typ. 0.45 x VA). Usually, the input
signal cuts DC with a capa citor. The cut-off frequency is fc=(1/2πRC). The ADC output data format is 2’s complement.
The DC offset including the ADC’s own DC offset is removed by the internal HPF (fc=3.4Hz@fs=44.1kHz).
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 17 -
PACKAGE (AK5355VT)
0-10°
Detail A
Seating Plane 0.10
0.17
±
0.05
0.22±0.1 0.65
*5.0±0.1 1.05±0.05
A
18
916
16
p
in TSSOP
(
Unit: mm
)
*4.4±0.1
6.4±0.2
0.5±0.2
0.1±0.1
NOTE: Dimension "*" does not include mold flash.
0.13 M
Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 18 -
PACKAGE (AK5355VN)
20pin QFN (Unit: mm)
4.20 ± 0.10
4.20 ± 0.10
0.22 ± 0.05
4.00 ± 0.05
4.00 ± 0.05
0.50
0.05 M
0.05
1.00
SAB
1.00
C0.7
0.22 ± 0.05
45.0° 45.0°
3 - 0.69 ± 0.11
0.35 ± 0.11
0.50
B
A
3 - C0.2
0.60 ± 0.10 S
+ 0.03
- 0.05
0.22
S
0.02TYP
0.005MIN 0.04MAX
0.90 ± 0.05
Note: The black parts of back package should be open.
Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 19 -
MARKING (AK5355VT)
AKM
5355VT
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX : Lot#
YYY : Date Code
3) Marketing Code : 5355VT
4) Asahi Kasei Logo
ASAHI KASEI [AK5355]
MS0113-E-01 2005/01
- 20 -
MARKING (AK5355VT)
5355
X
XXX
1
XXXX : Date code identifier (4 digits)
Revision History
Date (YY/MM/DD) Revision Reason Page Contents
01/08/27 00 First Edition
05/01/20 01 Spec addition 2 20pin QFN package is added.
6 Power supply current (Power-down m ode, 20QFN):
20µA(max)
IMPORTAN T NOTICE
• These products and their specifications are sub ject to ch ange withou t notice. Before considering a ny use or
application, consu lt the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning th eir current status.
• AKM assumes no liability for infr ingement of any patent, intellectual prop erty, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchan ge, or strategic materials.
• AKM products are neither intende d nor autho rized fo r use as critical c omponents in any safety, life su ppo rt,
or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except
with the expr ess written consent of the Re presentative Director of AK M. As used here:
a. A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function
or perform may reasonably be expected to result in loss of life or in significant injury or damage to person
or property.
b. A critical component is one whose failure to function or perfo rm may reasonably be ex pected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefo re meet very high standards of per formance and reliability.
• It is the responsibility of the b uyer or distributor of an AKM product who distributes, disp oses of, or
otherwise places the pr oduct with a third party to notify that party in advance of th e above content and
conditions, a nd the buyer or distributor agrees to assume an y an d all responsibility and liability fo r and hold
AKM harmless from any and all claims arising f rom the use of said product in th e absence of such
notification.