RT/SD
FB
VIN
SW
RTN
BST
6V - 95V
Input
LM5009A
SHUTDOWN RCL
VCC
VIN
GND
RCL
RT
C1 C3
C4 L1
D1 RFB2
RFB1
R3
C2
GND
VOUT
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LM5009A
SNVS608H –JUNE 2009–REVISED SEPTEMBER 2016
LM5009A 100-V, 150-mA Constant ON-Time Buck Switching Regulator
1
1 Features
1• Operating Input Voltage Range: 6 V to 95 V
• Integrated 100-V, N-Channel Buck Switch
• Internal Start-Up Regulator
• No Loop Compensation Required
• Ultra-Fast Transient Response
• ON Time Varies Inversely With Input Voltage
• Operating Frequency Remains Constant With
Varying Line Voltage and Load Current
• Adjustable Output Voltage From 2.5 V
• Highly Efficient Operation
• Precision Internal Reference
• Low Bias Current
• Intelligent Current Limit
• Thermal Shutdown
• 8-Pin VSSOP and 8-Pin WSON (4 mm × 4 mm)
Packages
2 Applications
• Non-Isolated Telecommunication Buck Regulator
• Secondary High-Voltage Post Regulator
• 42-V Automotive Systems
3 Description
The LM5009A is a functional variant of the LM5009
COT buck switching regulator. The functional
differences of the LM5009A are: The minimum input
operating voltage is 6 V, the ON-time equation is
slightly different, and the requirement for a minimum
load current is removed.
The LM5009A step-down switching regulator features
all of the functions required to implement a low cost,
efficient, buck bias regulator. This high voltage
regulator contains an 100-V N-channel buck switch.
The device is easy to implement and is provided in
the 8-pin VSSOP and the thermally enhanced 8-pin
WSON packages. The regulator is based on a control
scheme using an ON time inversely proportional to
VIN. This feature allows the operating frequency to
remain relatively constant. The control scheme
requires no loop compensation. An intelligent current
limit is implemented with forced OFF time, which is
inversely proportional to VOUT. This scheme ensures
short-circuit control while providing minimum
foldback. Other features include: thermal shutdown,
undervoltage lockout (VCC), gate drive undervoltage
lockout, max duty cycle limiter, and a precharge
switch.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LM5009A VSSOP (8) 4.00 mm × 4.00 mm
WSON (8) 4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application, Basic Step-Down Regulator
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
7 Detailed Description.............................................. 8
7.1 Overview................................................................... 8
7.2 Functional Block Diagram......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes........................................ 12
8 Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application.................................................. 13
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support................. 19
11.1 Documentation Support ........................................ 19
11.2 Receiving Notification of Documentation Updates 19
11.3 Community Resources.......................................... 19
11.4 Trademarks........................................................... 19
11.5 Electrostatic Discharge Caution............................ 19
11.6 Glossary................................................................ 19
12 Mechanical, Packaging, and Orderable
Information........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (February 2013) to Revision H Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
• Changed values in the Thermal Information table from 200 to 157.7 (DGK) and from 40 to 42.8 (NGU)............................. 4
Changes from Revision F (February 2013) to Revision G Page
• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
1SW 8 VIN
2BST 7 VCC
3RCL 6 RT /SD
4RTN 5 FB
Not to scale
EP
1SW 8 VIN
2BST 7 VCC
3RCL 6 RT /SD
4RTN 5 FB
Not to scale
3
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5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View NGU Package
8-Pin WSON
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
SW 1 O Switching node: power switching node. Connect to the output inductor, recirculating diode, and
bootstrap capacitor.
BST 2 I Boost pin (bootstrap capacitor input): an external capacitor is required between the BST and the SW
pins. A 0.01-µF ceramic capacitor is recommended. An internal diode charges the capacitor from VCC
during each OFF time.
RCL 3 I Current limit OFF-time set pin: a resistor between this pin and RTN sets the OFF time when current limit
is detected. The OFF time is preset to 35 µs if FB = 0 V.
RTN 4 — Ground pin: ground for the entire circuit.
FB 5 I Feedback input from regulated output: this pin is connected to the inverting input of the internal
regulation comparator. The regulation threshold is 2.5 V.
RT/SD 6 I On time set pin: a resistor between this pin and VIN sets the switch on time as a function of VIN. The
minimum recommended on time is 400 ns at the maximum input voltage. This pin is used for remote
shutdown.
VCC 7 O Output from the internal high voltage series pass regulator: this regulated voltage provides gate drive
power for the internal Buck switch. An internal diode is provided between this pin and the BST pin. A
local 0.47-µF decoupling capacitor is required. The series pass regulator is current limited to 9 mA.
VIN 8 I Input voltage: input operating range of 6 V to 95 V.
EP — — Exposed pad: the exposed pad has no electrical contact. Connect to system ground plane for reduced
thermal resistance.
4
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN to GND –0.3 100 V
BST to GND –0.3 114 V
SW to GND (steady state) –1 V
BST to VCC 100 V
BST to SW 14 V
VCC to GND 14 V
All other inputs to GND –0.3 7 V
Storage temperature, Tstg –55 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIN Input voltage 6 95 V
TJOperating junction temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1) LM5009A
UNITDGK (VSSOP) NGU (WSON)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 157.7 42.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50.2 41.5 °C/W
RθJB Junction-to-board thermal resistance 77.9 20.1 °C/W
ψJT Junction-to-top characterization parameter 4.5 0.4 °C/W
ψJB Junction-to-board characterization parameter 76.5 20.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 4.5 °C/W
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(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applying statistical process control. The junction temperature (TJin °C) is calculated from the ambient temperature (TAin °C) and power
dissipation (PDin Watts) as follows: TJ= TA+ (PD• RθJA ) where RθJA (in ° C/W) is the package thermal impedance provided in the
Thermal Information section.
(2) The VCC output is intended as a self bias for the internal gate drive power and control circuits. Device thermal limitations limit external
loading.
6.5 Electrical Characteristics
Typical values correspond to TJ= 25 ° C. Minimum and maximum limits apply over TJ= –40°C to 125°C for LM5009A. Unless
otherwise stated, VIN = 48 V(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC SUPPLY
VCC Reg VCC regulator output(2) VIN = 48 V 6.6 7 7.4 V
VIN – VCC 6 V < VIN < 8.5 V 100 mV
VCC bypass threshold VIN increasing 8.5 V
VCC bypass hysteresis 300 mV
VCC output impedance VIN = 6 V 100 Ω
VIN = 10 V 8.8 Ω
VIN = 48 V 0.8 Ω
VCC current limit VIN = 48 V 9.2 mA
VCC UVLO VCC increasing 5.3 V
VCC UVLO hysteresis 190 mV
VCC UVLO filter delay 3 µs
Iin operating current FB = 3 V, VIN = 48 V 550 750 µA
Iin shutdown current RT/SD = 0 V 110 176 µA
CURRENT LIMIT
Current limit threshold 0.24 0.3 0.36 A
Current limit response time Iswitch overdrive = 0.1 A, time to switch off 350 ns
TOFF-1 OFF-time generator FB = 0 V, RCL = 100 K 35 µs
TOFF-2 OFF-time generator FB = 2.3 V, RCL = 100 K 2.56 µs
ON TIME GENERATOR
TON-1 ON-time generator VIN = 10 V, RON = 200 K 2.15 2.77 3.5 µs
TON-2 ON-time generator VIN = 95 V, RON = 200 K 200 300 420 ns
RT/SD Remote shutdown threshold Rising 0.4 0.7 1.05 V
RT/SD(HYS) Remote shutdown hysteresis 35 mV
MINIMUM OFF TIME
Minimum off timer FB = 0 V 300 ns
REGULATION AND OV COMPARATORS
FB reference threshold Internal reference, trip point for switch ON 2.445 2.5 2.55 V
FB overvoltage threshold Trip point for switch OFF 2.875 V
FB bias current 100 nA
THERMAL SHUTDOWN
TSD Thermal shutdown temperature 165 °C
Thermal shutdown hysteresis 25 °C
6
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(1) For devices procured in the 8-pin WSON package, the Rds(on) limits are specified by design characterization data only.
6.6 Switching Characteristics
Typical values correspond to TJ= 25 °C. Minimum and maximum limits apply over TJ= –40°C to 125°C for LM5009A. Unless
otherwise stated, VIN = 48 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Buck switch RDS(ON)(1) Itest = 200 mA 2.2 4.6 Ω
Gate drive UVLO Vbst – Vsw rising 2.8 3.8 4.8 V
Gate drive UVLO hysteresis 490 mV
Precharge switch voltage At 1 mA 0.8 V
Precharge switch ON time 150 ns
0 0.5 1.0 1.5 2.0 2.5
0
5
10
15
20
25
30
35
CURRENT LIMIT OFF TIME (Ps)
VFB (V)
300k RCL = 500k
100k
50k
7
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6.7 Typical Characteristics
Figure 1. Efficiency vs Load Current and VIN
(Circuit of Figure 10)Figure 2. VCC vs VIN
Figure 3. ON Time vs Input Voltage and RTFigure 4. Current Limit OFF Time vs VFB and RCL
Figure 5. Maximum Frequency vs VOUT and VIN Figure 6. ICC Current vs Applied VCC Voltage
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7 Detailed Description
7.1 Overview
The LM5009A device is a step-down switching regulator featuring all of the functions required to implement a
low-cost, efficient, buck bias power converter. This high-voltage regulator contains a 100-V, N-channel buck
switch, is easy to implement, and is provided in the 8-pin VSSOP and the thermally-enhanced, 8-pin WSON
packages. The regulator is based on a control scheme using an ON time inversely proportional to VIN. The
control scheme requires no loop compensation. Current limit is implemented with forced OFF time, which is
inversely proportional to VOUT. This scheme ensures short circuit control while providing minimum foldback.
The LM5009A is applied in numerous applications to efficiently regulate down higher voltages. This regulator is
well suited for 48-V Telecom and the new 42-V Automotive power bus ranges.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Control Circuit Overview
The LM5009A is a buck DC-DC regulator that uses a control scheme in which the ON time varies inversely with
line voltage (VIN). Control is based on a comparator and the ON-time one-shot, with the output voltage feedback
(FB) compared to an internal reference (2.5 V). If the FB level is below the reference the buck switch is turned on
for a fixed time determined by the line voltage and a programming resistor (RT). Following the ON period the
switch remains off for at least the minimum off-timer period of 300 ns. If FB is still below the reference at that
time, the switch turns on again for another ON-time period. This continues until regulation is achieved.
FB
SW
L1
C2
RFB2
VOUT2
R3
LM5009A
RFB1
Copyright © 2016, Texas Instruments Incorporated
F = VOUT
1.385 x 10-10 x RT
F = VOUT2 x L x 1.04 x 1020
RL x (RT)2
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Feature Description (continued)
The LM5009A operates in discontinuous conduction mode at light load currents, and continuous conduction
mode at heavy load current. In discontinuous conduction mode, current through the output inductor starts at zero
and ramps up to a peak during the ON time, then ramps back to zero before the end of the OFF time. The next
ON-time period starts when the voltage at FB falls below the internal reference; until then, the inductor current
remains zero. In this mode, the operating frequency is lower than in continuous conduction mode, and varies with
load current. Therefore, at light loads the conversion efficiency is maintained, because the switching losses
reduce with the reduction in load and frequency. The discontinuous operating frequency is calculated with
Equation 1.
where
• RL= the load resistance (1)
In continuous conduction mode, current flows continuously through the inductor and never ramps down to zero.
In this mode the operating frequency is greater than the discontinuous mode frequency and remains relatively
constant with load and line variations. The approximate continuous mode operating frequency is calculated with
Equation 2.
(2)
The output voltage (VOUT) is programmed by two external resistors as shown in Functional Block Diagram. The
regulation point is calculated with Equation 3.
VOUT = 2.5 × (RFB1 + RFB2) / RFB1 (3)
The LM5009A regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor C2. A minimum of 25 mV to 50 mV of ripple voltage at the feedback pin
(FB) is required for the LM5009A. In cases where the capacitor ESR is too small, additional series resistance
may be required (R3 in Functional Block Diagram).
For applications where lower output voltage ripple is required, the output is taken directly from a low-ESR output
capacitor, as shown in Figure 7. However, R3 slightly degrades the load regulation.
Figure 7. Low Ripple Output Configuration
UVLO 7 V
SW Pin
Inductor
Current
Vin
t2
ILIM
VCC
VIN t1
t3
IO
VOUT
0 V
10
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Feature Description (continued)
7.3.2 Start-Up Regulator (VCC)
The high-voltage bias regulator is integrated within the LM5009A. The input pin (VIN) is connected directly to line
voltages between 6 V and 95 V, with transient capability to 100 V. Referring to Functional Block Diagram and
Figure 2, when VIN is between 6 V and the bypass threshold (nominally 8.5 V), the bypass switch (Q2) is on, and
VCC tracks VIN within 100 mV to 150 mV. The bypass switch on-resistance is approximately 100 Ω, with inherent
current limiting at approximately 100 mA. When VIN is above the bypass threshold Q2 is turned off, and VCC is
regulated at 7 V. The VCC regulator output current is limited at approximately 9.2 mA. When the LM5009A is
shutdown using the RT/SD pin, the VCC bypass switch is shut off regardless of the voltage at VIN.
When VIN exceeds the bypass threshold, the time required for Q2 to shut off is approximately 2 µs to 3 µs. The
capacitor at VCC (C3) must be a minimum of 0.47 µF to prevent the voltage at VCC from rising above the absolute
maximum rating in response to a step input applied at VIN. C3 must be placed as close as possible to the VCC
and RTN pins. In applications with a relatively high input voltage, power dissipation in the bias regulator is a
concern. An auxiliary voltage of between 7.5 V and 14 V is diode connected to the VCC pin to shut off the VCC
regulator, thereby reducing internal power dissipation. The current required into the VCC pin is shown in Figure 6.
Internally a diode connects VCC to VIN requiring that the auxiliary voltage be less than VIN.
The turnon sequence is shown in Figure 8. During the initial delay (t1) VCC ramps up at a rate determined by the
current limit and C3 while internal circuitry stabilizes. When VCC reaches UVLO (typically 5.3 V) the buck switch
is enabled. The inductor current increases to the current limit threshold (ILIM) and during t2 VOUT increases as the
output capacitor charges up. When VOUT reaches the intended voltage, the average inductor current decreases
(t3) to the nominal load current (IO).
Figure 8. Start-Up Sequence
TOFF = VFB
(6.35 x 10-6 x RCL)
0.285 +
10-5
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Feature Description (continued)
7.3.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 2.5-V reference. In normal operation (the output voltage is
regulated), an ON-time period is initiated when the voltage at FB falls below 2.5 V. The buck switch stays on for
the ON time, causing the FB voltage to rise above 2.5 V. After the ON-time period, the buck switch stays off until
the FB voltage again falls below 2.5 V. During start-up, the FB voltage is below 2.5 V at the end of each ON
time, resulting in the minimum OFF-time of 300 ns. Bias current at the FB pin is nominally 100 nA.
7.3.4 Overvoltage Comparator
The feedback voltage at FB is compared to an internal 2.875-V reference. If the voltage at FB rises above
2.875 V, the ON-time pulse is immediately terminated. This condition can occur if the input voltage or the output
load change suddenly. The buck switch does not turn on again until the voltage at FB falls below 2.5 V.
7.3.5 ON-Time Generator and Shutdown
The ON time for the LM5009A is determined by the RTresistor, and is inversely proportional to the input voltage
(VIN). This results in a nearly constant frequency as VIN is varied over the VIN range. The ON-time equation for
the LM5009A is calculated with Equation 4.
TON = 1.385 × 10–10 × RT/ VIN (4)
RTmust be selected for a minimum ON time (at maximum VIN) greater than 400 ns, for proper current limit
operation. This requirement limits the maximum frequency for each application, depending on VIN and VOUT.
7.3.6 Current Limit
The LM5009A contains an intelligent current limit OFF timer. If the current in the Buck switch exceeds 0.3 A, the
present cycle is immediately terminated, and a non-resetable OFF timer is initiated. The length of OFF time is
controlled by an external resistor (RCL) and the FB voltage (see Figure 4). When FB = 0 V, a maximum OFF time
is required, and the time is preset to 35 µs. This condition occurs when the output is shorted, and during the
initial part of start-up. This amount of time ensures safe short circuit operation up to the maximum input voltage
of
95 V. In cases of overload where the FB voltage is above 0 V (not a short circuit), the current limit OFF time is
less than 35 µs. Reducing the OFF time during less severe overloads reduces the amount of foldback, recovery
time, and the start-up time. The OFF time is calculated with Equation 5.
(5)
The current limit sensing circuit is blanked for the first 50 ns to 70 ns of each ON time, so it is not falsely tripped
by the current surge which occurs at turnon. The current surge is required by the recirculating diode (D1) for the
turnoff recovery.
7.3.7 N-Channel Buck Switch and Driver
The LM5009A integrates an N-channel Buck switch and associated floating high-voltage gate driver. The gate
driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A
0.01-µF ceramic capacitor (C4) connected between the BST pin and SW pin provides the voltage to the driver
during the ON time.
During each OFF time, the SW pin is at approximately 0 V, and the bootstrap capacitor charges from VCC
through the internal diode. The minimum OFF timer, set to 300 ns, ensures a minimum time each cycle to
recharge the bootstrap capacitor.
STOP
RUN
RTLM5009A
RT/SD
VIN
Input
Voltage
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Feature Description (continued)
The internal precharge switch at the SW pin is turned on for approximately 150 ns during the minimum OFF-time
period, ensuring sufficient voltage exists across the bootstrap capacitor for the ON time. This feature helps
prevent operating problems which can occur during very light-load conditions, involving a long OFF time, during
which the voltage across the bootstrap capacitor could otherwise reduce below the gate drive UVLO threshold.
The precharge switch also helps prevent start-up problems which can occur if the output voltage is precharged
prior to turnon. After current limit detection, the precharge switch is turned on for the entire duration of the forced
OFF time.
7.3.8 Thermal Protection
The LM5009A must be operated so the junction temperature does not exceed 125°C during normal operation. An
internal thermal shutdown circuit is provided to shutdown the LM5009A in the event of a higher than normal
junction temperature. When activated, typically at 165°C, the controller is forced into a low power reset state by
disabling the buck switch. This feature prevents catastrophic failures from accidental device overheating. When
the junction temperature reduces below 140°C, normal operation is resumed (typical hysteresis = 25°C).
7.4 Device Functional Modes
The LM5009A is remotely disabled by taking the RT/SD pin to ground, as shown in Figure 9. The voltage at the
RT/SD pin is between 1.5 V and 3 V, depending on VIN and the value of the RTresistor.
Figure 9. Shutdown Implementation
FB
VIN
SW
RTN
BST
LM5009A
8
6
5
3
4
1
2
7
SHUTDOWN
VCC
RCL
RT/SD
12V - 90V
Input
309k
C1
1.0 PF
RT
RCL
316k RFB1
1.0k
RFB2
3.01k R3
3.3
GND
C2
22 PF
VOUT
10.0V
L1
220 PH
C3
0.47 PF
C4
0.01 PF
D1
C5
0.1 PF
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5009A is a nonsynchronous buck regulator designed to operate over a wide input voltage range and
output current. Spreadsheet-based quick-start calculation tools and the on-line WEBENCH®software can be
used to create a buck design along with the bill of materials, estimated efficiency, and the complete solution cost.
8.2 Typical Application
The final circuit is shown in Figure 10. The circuit was tested, and the resulting performance is shown in
Figure 11 and Figure 12.
Figure 10. LM5009A Example Circuit
8.2.1 Design Requirements
A guide for determining the component values is illustrated with a design example. See Functional Block
Diagram and the Bill of Materials listed in Table 2.
Table 1. Design Parameters
PARAMETER VALUE
Input voltage range 12 V to 90 V
Output voltage 10 V
Load current range 100 mA to 150 mA
L1 = VOUT x (VIN - VOUT)
IOR x Fs x VIN
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8.2.2 Detailed Design Procedure
Table 2. Bill of Materials
ITEM DESCRIPTION PART NUMBER VALUE
C1 Ceramic capacitor TDK C4532X7R2A105M 1 µF, 100 V
C2 Ceramic capacitor TDK C4532X7R1E226M 22 µF, 25 V
C3 Ceramic capacitor Kemet C1206C474K5RAC 0.47 µF, 50 V
C4 Ceramic capacitor Kemet C1206C103K5RAC 0.01 µF, 50 V
C5 Ceramic capacitor TDK C3216X7R2A104M 0.1 µF, 100 V
D1 Schottky power diode Diodes Inc. DFLS1100 100 V, 1 A
L1 Power inductor COILTRONICS DR125-221-R or
TDK SLF10145T-221MR65 220 µH
RFB2 Resistor Vishay CRCW12063011F 3.01 kΩ
RFB1 Resistor Vishay CRCW12061001F 1 kΩ
R3 Resistor Vishay CRCW12063R30F 3.3 Ω
RTResistor Vishay CRCW12063093F 309 kΩ
RCL Resistor Vishay CRCW12063163F 316 kΩ
U1 Switching regulator Texas Instruments LM5009A —
8.2.2.1 RFB1 and RFB2
VOUT = VFB × (RFB1 + RFB2) / RFB1 (6)
Because VFB = 2.5 V, the ratio of RFB2 to RFB1 calculates as 3:1. Standard values of 3.01 kΩand 1 kΩare
chosen. Other values could be used as long as the 3:1 ratio is maintained.
8.2.2.2 Fsand RT
The recommended operating frequency range for the LM5009A is 50 kHz to 1.1 MHz. Unless the application
requires a specific frequency, the choice of frequency is generally a compromise, because it affects the size of
L1 and C2, and the switching losses. The maximum allowed frequency, based on a minimum ON time of 400 ns,
is calculated with Equation 7.
FMAX = VOUT / (VINMAX × 400 ns) (7)
For this exercise, FMAX = 277 kHz. From Equation 2, RTcalculates to 260 kΩ. A standard value, 309-kΩresistor
is used to allow for tolerances in Equation 2, resulting in a frequency of 234 kHz.
8.2.2.3 L1
The main parameter affected by the inductor is the output current ripple amplitude. The choice of inductor value
therefore depends on both the minimum and maximum load currents, keeping in mind that the maximum ripple
current occurs at maximum VIN.
8.2.2.3.1 Minimum Load Current
To maintain continuous conduction at minimum IO(100 mA), the ripple amplitude (IOR) must be less than 200 mA
peak-to-peak so the lower peak of the waveform does not reach zero. L1 is calculated using Equation 8.
(8)
At VIN = 90 V, L1(min) calculates to 190 µH. The next larger standard value (220 µH) is chosen and with this
value IOR calculates to 173 mA peak-to-peak at VIN = 90 V, and 32 mA peak-to-peak at VIN = 12 V.
15
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8.2.2.3.2 Maximum Load Current
At a load current of 150 mA, the peak of the ripple waveform must not reach the minimum value of the
LM5009A’s current limit threshold (240 mA). Therefore, the ripple amplitude must be less than 180 mA peak-to-
peak, which is already satisfied in the above calculation. With L1 = 220 µH, at maximum VIN and IO, the peak of
the ripple is 236 mA. While L1 must carry this peak current without saturating or exceeding the temperature
rating, it also must be capable of carrying the maximum value of the LM5009A’s current limit threshold (360 mA)
without saturating, because the current limit is reached during startup.
The DC resistance of the inductor must be as low as possible to minimize the power loss.
8.2.2.4 C3
The capacitor on the VCC output provides not only noise filtering and stability, but the primary purpose is to
prevent false triggering of the VCC UVLO at the buck switch on and off transitions. C3 must be no smaller than
0.47 µF.
8.2.2.5 C2 and R3
When selecting the output filter capacitor C2, the items to consider are ripple voltage due to the ESR, ripple
voltage due to the capacitance, and the nature of the load.
8.2.2.6 ESR and R3
A low ESR for C2 is generally desirable so as to minimize power losses and heating within the capacitor.
However, the regulator requires a minimum amount of ripple voltage at the feedback input for proper loop
operation. For the LM5009A, the minimum ripple required at pin 5 is 25 mV peak-to-peak, requiring a minimum
ripple at VOUT of 100 mV. Because the minimum ripple current (at minimum VIN) is 32 mA peak-to-peak, the
minimum ESR required at VOUT is 100 mV / 32 mA = 3.12 Ω. Because quality capacitors for SMPS applications
have an ESR considerably less than this, R3 is inserted as shown in Functional Block Diagram. R3’s value,
along with C2’s ESR, must result in at least 25 mV peak-to-peak ripple at pin 5. Generally, R3 is 0.5 Ωto 4 Ω.
8.2.2.7 C2
C2 must generally be no smaller than 3.3 µF. Typically, the value is 10 µF to 20 µF with the optimum value
determined by the load. If the load current is fairly constant, a small value suffices for C2. If the load current
includes significant transients, a larger value is necessary. For each application, experimentation is required to
determine the optimum values for R3 and C2.
8.2.2.8 RCL
When current limit is detected, the minimum OFF-time set by this resistor must be greater than the maximum
normal OFF time, which occurs at maximum input voltage. Using Equation 4, the minimum ON time is 476 ns,
yielding an OFF time of 3.8 µs (at 234 kHz). Due to the 25% tolerance on the ON time, the OFF-time tolerance is
also 25%, yielding a maximum OFF time of 4.75 µs. Allowing for the response time of the current limit detection
circuit (350 ns) increases the maximum OFF time to 5.1 µs. This is increased an additional 25% to 6.4 µs to
allow for the tolerances of Equation 5. Using Equation 5, RCL calculates to 310 kΩat VFB = 2.5 V. A standard
value 316-kΩresistor is used.
8.2.2.9 D1
The important parameters are reverse recovery time and forward voltage. The reverse recovery time determines
how long the reverse current surge lasts each time the buck switch is turned on. The forward voltage drop is
significant in the event the output is short-circuited as it is only this diode’s voltage which forces the inductor
current to reduce during the forced OFF time. For this reason, a higher voltage is better, although that affects
efficiency. A good choice is a Schottky power diode, such as the DFLS1100. The reverse voltage rating of D1
must be at least as great as the maximum VIN, and the current rating must be greater than the maximum current
limit threshold (360 mA).
C1 = I x tON
'V0.15A x 3.57 Ps
2.0V
== 0.268 PF
16
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8.2.2.10 C1
C1 supplies most of the switch current during the ON time, and limit the voltage ripple at VIN, on the assumption
that the voltage source feeding VIN has an output impedance greater than zero. At maximum load current, when
the buck switch turns on, the current into pin 8 suddenly increases to the lower peak of the output current
waveform, ramp up to the peak value, then drop to zero at turnoff. The average input current during this ON time
is the load current (150 mA). For a worst-case calculation, C1 must supply this average load current during the
maximum ON time. To keep the input voltage ripple to less than 2 V (for this exercise), C1 is calculated with
Equation 9.
(9)
Quality ceramic capacitors in this value have a low ESR, which adds only a few millivolts to the ripple. It is the
capacitance which is dominant in this case. To allow for the capacitor’s tolerance, temperature effects, and
voltage effects, a 1-µF, 100-V X7R capacitor is used.
8.2.2.11 C4
The recommended value for C4 is 0.01 µF, as this is appropriate in the majority of applications. A high-quality
ceramic capacitor, with low ESR is recommended as C4 supplies the surge current to charge the buck switch
gate at turnon. A low ESR also ensures a quick recharge during each OFF time. At minimum VIN, when the ON
time is at maximum, it is possible during start-up that C4 does not fully re-charge during each 300 ns OFF time.
The circuit is not able to complete the start-up, and achieve output regulation. This can occur when the frequency
is intended to be low (for example, RT= 500 K). In this case, C4 must be increased so it can maintain sufficient
voltage across the buck switch driver during each ON time.
8.2.2.12 C5
This capacitor helps avoid supply voltage transients and ringing due to long lead inductance at VIN. TI
recommends placing a low-ESR, 0.1-µF ceramic chip capacitor close to the LM5009A.
8.2.2.13 Ripple Configuration
The LM5009A uses a constant-ON-time (COT) control scheme where the ON time is terminated by a one-shot
and the OFF time is terminated by the feedback voltage (VFB) falling below the reference voltage. Therefore, for
stable operation, the feedback voltage must decrease monotonically in phase with the inductor current during the
OFF time. Furthermore, this change in feedback voltage (VFB) during OFF time must be large enough to
dominate any noise present at the feedback node.
Table 3 presents three different methods for generating appropriate voltage ripple at the feedback node. Type 1
and type 2 ripple circuits couple the ripple from the output of the converter to the feedback node (FB). The output
voltage ripple has two components:
1. Capacitive ripple caused by the inductor current ripple charging or discharging the output capacitor.
2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor and
R3.
The capacitive ripple is out of phase with the inductor current. As a result, the capacitive ripple does not
decrease monotonically during the OFF time. The resistive ripple is in phase with the inductor current and
decreases monotonically during the OFF time. The resistive ripple must exceed the capacitive ripple at output
(VOUT) for stable operation. If this condition is not satisfied, then unstable switching behavior is observed in COT
converters with multiple ON-time bursts in close succession followed by a long OFF time.
The type 3 ripple method uses a ripple injection circuit with RA, CA, and the switch node (SW) voltage to generate
a triangular ramp. This triangular ramp is then ac-coupled into the feedback node (FB) using the capacitor CB.
This circuit is suited for applications where low output voltage ripple is imperative because this circuit does not
use the output voltage ripple.
ff SW FB2 FB1
3L1,min
5
CF (R IIR )
25 mV
RI
t
u
t
'
u
t
u '
O
3REF L1,min
25 mV V
RV I
IN,min
IN,min O ON(@V )
A A (V V ) T
R C 25mV
u
d
GND
To FB
L1
COUT
RFB2
RFB1
VOUT
R3
GND
To FB
L1
COUT
RFB2
RFB1
VOUT
R3
Cff
COUT
VOUT
GND
RA
CB
CA
To FB
RFB2
RFB1
L1
17
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Table 3. Ripple Configuration
TYPE 1 TYPE 2 TYPE 3
Lowest cost Reduced ripple Minimum ripple
(10) (11) (12)
See AN-1481 Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT)
Regulator Designs (SNVA166) for more details on each ripple generation method.
8.2.3 Application Curves
Figure 11. Efficiency vs Load Current and VIN Figure 12. Efficiency vs VIN
GND
CBST
RFB1
VLINE
SW
Cbyp
VOUT
LIND
RFB2
CB
RON
COUT
CIN
Via to Ground Plane
CVCC
CA
RA
SW
BST
RCL
RTN FB
RON
VCC
VIN
LM5009A
GND
D1
Exp Thermal
Pad
Copyright © 2016, Texas Instruments Incorporated
18
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9 Power Supply Recommendations
The LM5009A is designed to operate with an input power supply capable of supplying a voltage range from 6 V
to 95 V. The input power supply must be well regulated and capable of supplying sufficient current to the
regulator during peak load operation. Also, like in all applications, the power-supply source impedance must be
small compared to the module input impedance to maintain the stability of the converter.
10 Layout
10.1 Layout Guidelines
The LM5009A regulation and overvoltage comparators are very fast, and as such respond to short duration noise
pulses. Therefore, layout considerations are critical for optimum performance. The components at pins 1, 2, 3, 5,
and 6 must be as physically close as possible to the IC, thereby minimizing noise pickup in the PC tracks. The
current loop formed by D1, L1, and C2 must be as small as possible. The ground connection from D1 to C1 must
be as short and direct as possible.
If the internal dissipation of the LM5009A produces excessive junction temperatures during normal operation,
good use of the PCB ground plane can help to dissipate heat. The exposed pad on the bottom of the 8-pin
WSON package is soldered to a ground plane on the PCB, and that plane must extend out from beneath the IC
to help dissipate the heat. Additionally, the use of wide PCB traces, where possible, can also help conduct heat
away from the IC. Judicious positioning of the PCB within the end product, along with use of any available air
flow (forced or natural convection) can help reduce the junction temperatures.
10.2 Layout Example
Figure 13. LM5009A Buck Layout Example With the WSON Package
19
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
AN-1481 Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator
Designs (SNVA166)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5009AMM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SLLA
LM5009AMMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SLLA
LM5009ASD/NOPB ACTIVE WSON NGU 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5009ASD
LM5009ASDX/NOPB ACTIVE WSON NGU 8 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5009ASD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5009AMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5009AMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5009ASD/NOPB WSON NGU 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5009ASDX/NOPB WSON NGU 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5009AMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM5009AMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LM5009ASD/NOPB WSON NGU 8 1000 210.0 185.0 35.0
LM5009ASDX/NOPB WSON NGU 8 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2019
Pack Materials-Page 2
MECHANICAL DATA
NGU0008B
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SDC08B (Rev A)
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