DATA SH EET
Product specification
Supersedes data of 2003 Nov 26 2004 Jul 05
INTEGRATED CIRCUITS
TDA9965A
12-bit, 5.0 V, 40 Msps
analog-to-digital interface for CCD
cameras
2004 Jul 05 2
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
FEATURES
•Clamp and Track/Hold (CTH) circuit with adjustable
bandwidth, Programmable Gain Amplifier (PGA), 12-bit
Analog-to-Digital Converter (ADC) and reference
regulator
•Fully programmable via a 3-wire serial interface
•Sampling frequency up to 40 MHz
•PGA gain from 0 to 36 dB (in 0.05 dB steps)
•CTH programmable bandwidth from 35 to 284 MHz
typical
•Standby mode (20 mW typical)
•Low power consumption of only 425 mW typical
•5 V operation and 3 to 5.25 V operation for the digital
outputs
•TTL compatible inputs; TTL and CMOS compatible
outputs.
APPLICATIONS
•CCD camera systems.
GENERAL DESCRIPTION
The TDA9965A is a 12-bit analog-to-digital interface for a
CCD camera. The device includes a CTH circuit, PGA and
a low-power 12-bit ADC, together with its reference
voltage regulator.
The CTH has a bandwidth circuit controlled by on-chip
DACs via a serial interface.
A 10-bit digital clamp controls the ADC input clamp level.
QUICK REFERENCE DATA
Note
1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB.
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VCCA analog supply voltage 4.75 5.0 5.25 V
VCCD digital supply voltage 4.75 5.0 5.25 V
VCCO digital output supply voltage 3.0 3.3 5.25 V
ICCA analog supply current with internal regulator −65 −mA
ICCD digital supply current with internal regulator −19 −mA
ICCO digital output supply current fpix = 40 MHz; CL= 10 pF on all
data outputs; ramp input −1−mA
ADCres ADC resolution −12 −bits
Vi(IN)(p-p) CTH input voltage
(peak-to-peak value) −2−V
GCTH CTH output amplifier gain −0−dB
PGAdyn PGA dynamic range −36 −dB
fpix(max) maximum pixel frequency code fco(CTH) = 0000 40 −−MHz
Ntot(rms) total noise from CTH input to
ADC output (RMS value) GPGA = 0 dB;
code fco(CTH) = 0000 −0.85 −LSB
Vn(i)(eq)(rms) equivalent input noise
(RMS value) GPGA = 30 dB;
code fco(CTH) = 0000; note 1 −90 −µV
Ptot total power consumption −425 −mW
TYPE
NUMBER PACKAGE
NAME DESCRIPTION VERSION
TDA9965AHL LQFP48 plastic low profile quad flat package; 48 leads; body 7 ×7×1.4 mm SOT313-2
2004 Jul 05 3
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
BLOCK DIAGRAM
handbook, full pagewidth
MGU713
REGULATOR
12-BIT ADC
CLAMP
CLAMP
SERIAL
INTERFACE
INIT-ON-
POWER
OUTPUT
BUFFER
7
6
9
8
10
11
14
13 15 16 17 18 20 21 22 23
19 24
25
26
27
28
29
30
31
32
33
34
35
37
383940
41
4243
44
45
48 46
47
DGND2
AGND4
IN
SHD SHP CLPADC
CLPOB CLKADC
DGND1
VCCD2
D8
D7
D6
VCCO2
OGND2
VCCO1
OGND1
D5
D4
D3
D2
REGEN SEN D1
D0
SCLKSDATA
DEC REF32
VRT
VRB VCCA3
AGND3
ADCIN
Vref
VCCA1
VCCA2
AGND2 TDA9965A
36 D9
D11
STDBY
VCCD1 D10
1
3
4
5
2
AGND5
AGND1
12
n.c.
STGE
PGAOUT REF = 3.2 V
10
12
TRACK AND HOLD CLOCK
4-BIT DAC
10-BIT DAC
PGA
Fig.1 Block diagram.
2004 Jul 05 4
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
PINNING
SYMBOL PIN DESCRIPTION
AGND4 1 analog ground 4
IN 2 data input signal from CCD
AGND5 3 analog ground 5
STGE 4 clamp storage capacitor pin
AGND1 5 analog ground 1
VCCA1 6 analog supply voltage 1
AGND2 7 analog ground 2
VCCA2 8 analog supply voltage 2
Vref 9 ADC clamp reference voltage input; short-circuited to ground via a capacitor
PGAOUT 10 PGA amplifier signal output
ADCIN 11 ADC analog signal input; externally connected to pin PGAOUT
n.c. 12 not connected
REGEN 13 regulator enable input (active HIGH)
VRB 14 regulator reference voltage bottom
VRT 15 regulator reference voltage top
DEC 16 regulator decoupling; decoupled to ground via a capacitor
REF32 17 internal reference voltage; decoupled to ground via a capacitor
VCCA3 18 analog supply voltage 3
AGND3 19 analog ground 3
SEN 20 enable input for the serial interface shift register (active LOW)
SCLK 21 serial clock input for the serial interface
SDATA 22 serial data input: 10-bit PGA gain, 4-bit DAC for the frequency cut-off, 10 low significant bits for
the digital ADC clamp and edge pulse control
D0 23 ADC digital output 0 (LSB)
D1 24 ADC digital output 1
D2 25 ADC digital output 2
D3 26 ADC digital output 3
D4 27 ADC digital output 4
D5 28 ADC digital output 5
OGND1 29 digital output ground 1
VCCO1 30 digital output supply voltage 1
OGND2 31 digital output ground 2
VCCO2 32 digital output supply voltage 2
D6 33 ADC digital output 6
D7 34 ADC digital output 7
D8 35 ADC digital output 8
D9 36 ADC digital output 9
D10 37 ADC digital output 10
D11 38 ADC digital output 11 (MSB)
STDBY 39 standby control input (active HIGH); all output bits are logic 0 when standby is enabled
2004 Jul 05 5
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
VCCD1 40 digital supply voltage 1
DGND1 41 digital ground 1
CLKADC 42 ADC clock input
CLPADC 43 clamp control pulse input for ADC analog input signal
CLPOB 44 clamp control pulse input at optical black
SHP 45 preset sample and hold pulse input
SHD 46 data sample and hold pulse input
VCCD2 47 digital supply voltage 2
DGND2 48 digital ground 2
SYMBOL PIN DESCRIPTION
handbook, full pagewidth
TDA9965AHL
MGU715
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
DGND2
VCCD2
SHD
SHP
CLPOB
CLPADC
CLKADC
DGND1
VCCD1
STDBY
D11
D10
REGEN
VRB
VRT
DEC
REF32
VCCA3
AGND3
SEN
SCLK
SDATA
D0
D1
AGND4
IN
AGND5
STGE
AGND1
VCCA1
VCCA2
AGND2
Vref
PGAOUT
ADCIN
n.c.
D9
D8
D7
D6
VCCO2
OGND2
VCCO1
OGND1
D5
D4
D3
D2
Fig.2 Pin configuration.
2004 Jul 05 6
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Note
1. All supplies are connected together.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCCA analog supply voltage note 1 −0.3 +7.0 V
VCCD digital supply voltage note 1 −0.3 +7.0 V
VCCO digital output supply voltage note 1 −0.3 +7.0 V
∆VCC supply voltage difference
between VCCA and VCCD −1.0 +1.0 V
between VCCD and VCCO −1.0 +4.0 V
Viinput voltage referenced to AGND −0.3 +7.0 V
Iooutput current −10 +10 mA
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −20 +75 °C
Tjjunction temperature −150 °C
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air 76 K/W
2004 Jul 05 7
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
CHARACTERISTICS
VCCA =V
CCD =5V; V
CCO = 3.0 V; fpix = 40 MHz; Tamb =−20 to +75 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VCCA analog supply voltage 4.75 5.0 5.25 V
VCCD digital supply voltage 4.75 5.0 5.25 V
VCCO digital output supply
voltage 3.0 3.3 5.25 V
ICCA analog supply current with internal regulator −65 −mA
ICCD digital supply current with internal regulator −19 −mA
ICCO digital output supply
current fpix = 40 MHz; CL=10pF
on all data outputs; ramp
input
−1−mA
Digital inputs
CLOCK INPUT:PIN CLKADC (REFERENCED TO DGND)
VIL LOW-level input voltage 0 −0.8 V
VIH HIGH-level input voltage 2.0 −VCCD V
IIL LOW-level input current VCLKADC = 0.8 V −1−+1 µA
IIH HIGH-level input current VCLKADC = 2.0 V −−20 µA
Ziinput impedance −63 −kΩ
Ciinput capacitance −1−pF
CONTROL INPUTS:PINS SEN, SCLK, SDATA, STDBY, CLPOB, CLPADC AND REGEN
VIL LOW-level input voltage 0 −0.8 V
VIH HIGH-level input voltage 2.0 −VCCD V
Iiinput current −2−+2 µA
SAMPLE AND HOLD INPUTS:PINS SHP AND SHD
VIL LOW-level input voltage 0 −0.8 V
VIH HIGH-level input voltage 2.0 −VCCD V
Iiinput current −10 −+10 µA
Clamp and Track/Hold (CTH) circuit: pins IN, SHD and SHP
Vi(IN)(p-p) CTH input voltage
(peak-to-peak value) −2−V
Ii(IN) input current −3−+3 µA
tW(SHP) SHP pulse width Vi(IN) = 1000 mV;
transition (98.5%) in 1 pixel;
code fco(CTH) = 0000;
see Fig.5
8−−ns
2004 Jul 05 8
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
tW(SHD) SHD pulse width Vi(IN) =1000mV;
transition (98.5%) in 1 pixel;
code fco(CTH) = 0000;
see Fig.5
8−−ns
code fco(CTH)
0000 −7−ns
0001 −12 −ns
0010 −16 −ns
0100 −22 −ns
1000 −32 −ns
1111 −49 −ns
th(IN-SHP) CTH input hold time
compared to control pulse
SHP
see Fig.5 −3−ns
th(IN-SHD) CTH input hold time
compared to control pulse
SHD
see Fig.5 −3−ns
Programmable Gain Amplifier (PGA) output: pin PGAOUT
VPGAOUT(p-p) PGA output amplifier
dynamic voltage level
(peak-to-peak value)
−2000 −mV
VPGAOUT(b) PGAoutput amplifierblack
level voltage code C(CLP) =0 −1.475 −V
ZPGAOUT PGA output amplifier
output impedance fpix at 10 kHz for minimum
and maximum values −5−Ω
IPGAOUT PGA output current drive static −−1mA
GPGA(min) minimum gain of PGA
circuit code GPGA =0 −0−dB
GPGA(max) maximum gain of PGA
circuit code GPGA ≥767 −36 −dB
Analog-to-Digital Converter (ADC)
fpix(max) maximum pixel frequency 40 −−MHz
tW(CLKADC)H CLKADC pulse width
HIGH Vi(IN) = 1000 mV;
transition (99.5%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128; see Fig.5
11 −−ns
tW(CLKADC)L CLKADC pulse width
LOW Vi(IN) = 1000 mV;
transition (99.5%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128
11 −−ns
SRCLKADC CLKADC input slew rate rising and falling edges;
10% to 90% 0.5 −−V/ns
Vi(ADCIN)(p-p) ADC input voltage
(peak-to-peak value) with internal regulator −2−V
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2004 Jul 05 9
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
Note
1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB.
Ii(ADCIN) ADC input current −2−+120 µA
VRB ADC reference voltage
bottom −1.30 −V
VRT ADC reference voltage top −3.65 −V
DNL differential non-linearity ramp input; fpix =30MHz −±0.5 ±0.9 LSB
td(s) sampling delay see Fig.5 −−5ns
Total chain characteristics (CTH + PGA + ADC)
td(SHD-CLKADC) delay between
SHD and CLKADC Vi(IN) = 1000 mV;
transition (95%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128; see Fig.5
−15 −ns
th(SHD-CLKADC) SHD hold time compared
to CLKADC Vi(IN) =32mV;
transition (95%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128; see Fig.5
−0−ns
Ntot(rms) total noise from CTH input
to ADC output
(RMS value)
GPGA = 0 dB;
code fco(CTH) = 0000 −0.85 −LSB
GPGA = 30 dB;
code fco(CTH) = 0000; note 1 −6−LSB
OCCD(max) maximum offset voltage
between CCD floating
level and CCD dark pixel
level
see Fig.11 −200 −+200 mV
Vn(i)(eq)(rms) equivalent input noise
(RMS value) GPGA = 30 dB;
code fco(CTH) = 0000; note 1 −90 −µV
Digital outputs (fpix = 40 MHz; CL=10pF)
VOH HIGH-level output voltage IOH =−1mA V
CCO −0.5 −VCCO V
VOL LOW-level output voltage IOL =1mA 0 −0.5 V
th(o) output hold time see Fig.5 10 −−ns
td(o) output delay VCCO = 5.25 V −20 25 ns
VCCO =3V −26 31 ns
Serial interface
fSCLK(max) maximum clock frequency
of serial interface 5−−MHz
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2004 Jul 05 10
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
handbook, full pagewidth
PGA GAIN
LATCHES FREQUENCY
LATCHES
LATCH
SELECTION
SD0
LSB MSB
SDATA
SCLK
SEN
10-bit LSB
ADC clamp
FCE709
PGA control frequency
control CTH edge control
clocks
SD1 SD2 SD3 SD4 SD5
10
SD6
SHIFT REGISTER
SD7 SD8 SD9 A0 A1
(SD0 to SD9)
(SD0 to SD3)
(SD0 to SD2)
(SD0 to SD9)
EDGE
CONTROL
LATCHES
CLAMP
ADC
LATCHES
Fig.3 Serial interface block diagram.
handbook, full pagewidth
MGU158
SDATA
SCLK
SEN
A1 A0 SD9 SD7 SD6 SD5 SD4 SD3
MSB LSB
SD2 SD1 SD0
th2
tsu3
tsu1
th1
tsu2
SD8
Fig.4 Loading sequence of control DACs input data via the serial interface.
tsu1 =t
su2 = tsu3 = 4 ns (minimum);
th1 =t
h2 = 4 ns (minimum).
2004 Jul 05 11
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
Table 1 Serial interface programming
Notes
1. PGA gain register must always be refreshed after clamp code register content has been changed.
2. When pin CLPADC = HIGH (SD1 = 1; serial interface), the ADC input is clamped to the voltage level of Vref. Pin Vref
is connected to ground via a capacitor.
When the power supplies increase from zero to VCC, the init-on-power block initializes the circuit as follows:
•Cut-off frequency of the CTH circuit is set to: code fco(CTH) =0
•PGA gain control is set to: code GPGA =0
•Clamp code of the ADC is set to: code ADCCLP =0
•SHP and SHD sample on HIGH level; CLKADC activated with rising edge
•CLPOB and CLPADC activated on HIGH level.
Table 2 Standby selection
Note
1. If an external regulator is used it has to be switched off in standby mode in order to avoid extra power consumption
by the TDA9965A.
ADDRESS BITS SDATA BITS SD0 to SD9
A1 A0
0 0 clamp reference of ADC (SD0 to SD9); note 1
0 1 cut-off frequency of CTH (SD0 to SD3)
1 0 PGA gain control (SD0 to SD9)
1 1 edge control for pulses SHP, SHD, CLPOB, CLPADC and CLKADC (note 2):
SD0 = 1, SHP and SHD sample on LOW level
SD1 = 1, CLPADC and CLPOB activated on HIGH level
SD2 = 1, CLKADC activated with rising edge
PIN STDBY DATA BITS SD9 to SD0 ICCA +I
CCD
HIGH logic 0 4 mA (typical); note 1
LOW active 84 mA (typical)
2004 Jul 05 12
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
handbook, full pagewidth
MGU389
N
IN
from
CCD
SHP
SHD
ADCIN
CLKADC
DATA
N + 1 N + 2
N − 1 N − 2 N − 3 N
N − 1 N
N + 3
N + 2 N + 1
td(o)
td(s)
tW(CLKADC)H
td(SHD-CLKADC) th(SHD-CLKADC)
th(IN-SHP)
tW(SHD)
2.0 V
0.8 V
tW(SHP)
th(o)
50%
10%
90%
th(IN-SHD)
2.0 V
0.8 V
2.0 V
0.8 V
Fig.5 Pixel frequency timing diagram.
The polarities used in this case are:
- SHP and SHD sample on HIGH level
- CLKADC activated with rising edge.
2004 Jul 05 13
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
handbook, full pagewidth
MGU861
CLPADC
(active HIGH)
CLPOB
(active HIGH)
OPTICAL BLACK HORIZONTAL FLYBLACK DUMMY VIDEOVIDEOPGAOUT
CLPOB
WINDOW
CLPADC
WINDOW
1 pixel
CLPADC
WINDOW
1 pixel
Fig.6 Line frequency timing diagram.
handbook, halfpage
0 256 512 1024
PGA control DAC input code
GPGA
(dB)
48
12
24
0
36
768
FCE775
Fig.7 PGA gain as a function of PGA control DAC
input code.
handbook, halfpage
0000 0010 0100 CTH control code
BW
(MHz)
300
100
0
200
1000 1111
FCE758
Fig.8 CTH bandwidth as a function of CTH
control code.
2004 Jul 05 14
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
handbook, halfpage
MGU862
0
I
(µA)
V (V)
70 mV
2.4
600
−600
Fig.9 Typical clamp current as a function of
voltage on pin STGE.
handbook, halfpage
FCE689
I
(µA)
50
−400
400
0
−50
(1)
VOVO + 64 LSBVO − 64 LSB V (V)
Fig.10 Typical clamp current as a function of
voltage on pin Vref.
(1) VO depends on the clamp code.
handbook, halfpage
FCE688
−200 mV
+200 mV
Fig.11 Maximum offset voltage between CCD
floating and dark pixel level.
2004 Jul 05 15
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
APPLICATION INFORMATION
handbook, full pagewidth
MGU714
1
2
3
4
5
6
7
8
9
10
11
36
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16
5.0 V
17 18 19 20 21 22 23 24
35
34
33
32
31 (2)
(2)
30
29
28
27
26
12 25
TDA9965A
D9
D8
D7
D5
D4
D3
D2
OGND2
VCCO2
OGND1
VCCO1
AGND4
IN
AGND5
STGE
AGND1
VCCA1
VCCA2
Vref
n.c.
D6
VCCD2
SHD
SHP
CLPOB
CLPADC
CLKADC
VCCD1
D11
D10
DGND2
DGND1
STDBY
AGND2
PGAOUT
ADCIN
VRB
VRT
DEC
REF32
VCCA3
AGND3
SEN
SDATA
D0
D1
REGEN
SCLK
from timing
generator
serial
interface
5.0 V
5.0 V
CCD
(2)
5.0 V
(2)
33 pF
47 nF
100 nF
(2)
(3)
(3)
5.0 V (2)
(2)
(1)
1 nF
1
nF 1
µF
2.2
nF
Fig.12 Application diagram.
(1) The clamp level of the signal input at pin ADCIN can be tuned from code 0 to code 1023 in one LSB step of the ADC via the serial interface (clamp
ADC activated).
(2) All supply pins must be decoupled with 100 nF capacitors mounted as closely as possible to the device.
(3) The capacitors on pins STGE and Vref have typical values, performing a typical device start-up time of 300 µs from standby to active (supplies on).
2004 Jul 05 16
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
handbook, full pagewidth
1
2
3
4
5
6
7
8
9
10
11
36
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16
5.0 V
17 18 19 20 21 22 23 24
35
34
33
32
31
(2)
(2)
30
29
28
27
26
12 25
TDA9965A
D9
D8
D7
D5
D4
D3
D2
OGND2
VCCO2
OGND1
VCCO1
AGND4
IN
AGND5
STGE
AGND1
VCCA1
VCCA2
Vref
n.c.
D6
VCCD2
SHD
SHP
CLPOB
CLPADC
CLKADC
VCCD1
D11
D10
DGND2
DGND1
STDBY
AGND2
PGAOUT
ADCIN
VRB
VRT
DEC
REF32
VCCA3
AGND3
SEN
SDATA
D0
D1
REGEN
SCLK
from timing
generator
serial
interface
5.0 V
5.0 V
CCD1
(2)
5.0 V
(2)
33 pF
47 nF
100 nF
(2)
(3)
(3)
5.0 V
(2)
(2)
(1)
1 nF
1
nF 1
nF 1
µF
1
nF 1
µF
2.2
nF
MGU716
1
2
3
4
5
6
7
8
9
10
11
36
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16
5.0 V
17 18 19 20 21 22 23 24
35
34
33
32
31
(2)
(2)
30
29
28
27
26
12 25
TDA9965A
D9
D8
D7
D5
D4
D3
D2
OGND2
VCCO2
OGND1
VCCO1
AGND4
IN
AGND5
STGE
AGND1
VCCA1
VCCA2
Vref
n.c.
D6
VCCD2
SHD
SHP
CLPOB
CLPADC
CLKADC
VCCD1
D11
D10
DGND2
DGND1
STDBY
AGND2
PGAOUT
ADCIN
VRB
VRT
DEC
REF32
VCCA3
AGND3
SEN
SDATA
D0
D1
REGEN
SCLK
from timing
generator
serial
interface
5.0 V
5.0 V
CCD2
(2)
5.0 V
(2)
33 pF
47 nF
100 nF
(2)
(3)
(3)
5.0 V
(2)
(2)
(1)
2.2
nF
Fig.13 Application diagram with two CCDs.
For notes (1), (2) and (3) see Fig.12
2004 Jul 05 17
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
Power and grounding recommendations
Care should be taken to minimize the noise when
designing a printed-circuit board for applications such as
PC cameras, surveillance cameras, camcorders, and
digital still cameras.
For the front-end integrated circuit, the basic rules of
printed-circuit board design and implementation of analog
components (such as classical operational amplifiers)
must be taken into account, particularly with respect to
power and ground connections.
The connections between the CCD interface and the CTH
input should be as short as possible and a ground ring
protection around these connections can be beneficial.
Separate analog and digital supplies provide the best
performance. If it is not possible to do this on the board
then the analog supply pins must be decoupled effectively
from the digital supply pins. The decoupling capacitors
must be placed as close as possible to the IC package.
In a two-ground system, in order to minimize the noise
through the package and die parasitics, the following
recommendation must be implemented:
•The ground pin associated with the digital outputs must
be connected to the digital ground plane and special
care should be taken to avoid feedthrough in the analog
ground plane. The analog and digital ground planes
must be connected together with an inductor as closely
as possible to the IC in order for them to have the same
DC voltage.
•The digital output pins and their associated lines should
be shielded by the digital ground plane which can then
be used as a return path for the digital signals.
2004 Jul 05 18
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
PACKAGE OUTLINE
UNIT A
max. A
1
A
2
A
3
b
p
cE
(1)
eH
E
LL
p
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.6 0.20
0.05 1.45
1.35 0.25 0.27
0.17 0.18
0.12 7.1
6.9 0.5 9.15
8.85 0.95
0.55 7
0
o
o
0.12 0.10.21
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT313-2 MS-026136E05 00-01-19
03-02-25
D
(1) (1)(1)
7.1
6.9
H
D
9.15
8.85
E
Z
0.95
0.55
D
b
p
e
E
B
12
D
H
b
p
E
H
v
M
B
D
ZD
A
ZE
e
v
M
A
1
48
37
36 25
24
13
θ
A
1
A
L
p
detail X
L
(A )
3
A
2
X
y
c
w
M
w
M
0 2.5 5 mm
scale
pin 1 index
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
2004 Jul 05 19
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
SOLDERING
Introduction to soldering surface mount packages
Thistextgives averybrief insighttoa complextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemountICs, butitisnot suitableforfinepitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuitboard byscreen printing,stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
•below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
– for all BGA, HTSSON-T and SSOP-T packages
– for packages with a thickness ≥2.5 mm
– for packages with a thickness < 2.5 mm and a
volume ≥350 mm3 so called thick/large packages.
•below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices (SMDs)orprinted-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswithleads onfoursides,the footprintmust
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2004 Jul 05 20
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. Formore detailedinformation onthe BGApackagesrefer tothe
“(LF)BGAApplication Note
”(AN01026); ordera copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C±10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar or manual soldering is suitable for PMFP packages.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
USON, VFBGA not suitable suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable(4) suitable
PLCC(5), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(5)(6) suitable
SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable
CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable not suitable
2004 Jul 05 21
Philips Semiconductors Product specification
12-bit, 5.0 V, 40 Msps analog-to-digital
interface for CCD cameras TDA9965A
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor atany otherconditionsabove thosegivenin the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuch applicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
© Koninklijke Philips Electronics N.V. 2004 SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a world wide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands R78/03/pp22 Date of release: 2004 Jul 05 Document order number: 9397 750 13312
