IS61C1024 IS61C1024L_ 128K x 8 HIGH-SPEED CMOS FEATURES High-speed access time: 12, 15, 20, 25 ns Low active power: 600 mW (typical) Low standby power: 500 LW (typical) CMOS standby Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications Fully static operation: no clock or refresh required TTL compatible inputs and outputs Single 5V (410%) power supply Low power version available: |IS61C1024L Commercial and industrial temperature ranges available FUNCTIONAL BLOCK DIAGRAM STATIC RAM NOVEMBER 1998 DESCRIPTION The JSST 1S61C1024 and 1S61C1024L are very high-speed, low power, 131,072-word by 8-bit CMOS static RAMs. They are fabricated using /SS/'s high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The 186101024 and 1S61C1024L are available in 32-pin 300-mil plastic DIP, STSOP (8 x 13.4), 300-mil SOJ, and TSOP (Type I) packages. AO-A16 vCcc > GND > VO DATA CIRCUIT 1/00-1/07 DECODER CE2 CONTROL OE CIRCUIT WE 512 x 2048 MEMORY ARRAY COLUMN I/O ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 1998, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. 1-800-379-4774 SRO28-1J 11/03/98IS61C1024 1IS61C1024L PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOJ 32-Pin TSOP (Type 1) (T) and STSOP (Type 1) (H) Ne [1 ~ 321] vec Ai1 [11 32{_] OE Ai6 []2 31] A15 Ag CL] 2 31{_] A1o Ai4 3 30[] CE2 As C13 30{_] CE1 Ai2 [4 20] WE A1i3 (4 29{_] 07 A7 5 28[] A13 WE (15 98[_] 1/06 a6 [6 27[] As cE2 C16 97|-] 1/05 as 7 26[] A9 Ais C17 96 [-] 1/04 a4 Qe 251] Att vec E48 25(-] 1/03 as 9 24] OF Nc C19 o4{] GND a2 Y] 10 23f] A10 Ai6 C4 10 93[_] 02 nS : o Zp von Ai4 O11 22] 01 A12 [1] 12 211] 1/00 voo TJ 13 201] vo6 a7 E113 20] ao vo1 [] 14 19] VO5 vo2 TJ 15 18] o4 a6 L} 14 19 At GND [] 16 171] vos " = 'e re re PIN DESCRIPTIONS A0-A16 Address Inputs CET Chip Enable 1 Input CE2 Chip Enable 2 Input OE Output Enable Input WE Write Enable Input 1/00-I/O7 Input/Output Vcc Power GND Ground OPERATING RANGE Range Ambient Temperature Vcc Commercial 0C to +70C 5V + 10% Industrial 40C to +85C 5V + 10% TRUTH TABLE Mode WE CET CE2 OE W/OOperation Vcc Current Not Selected Xx H Xx Xx High-2 IsB1, IsB2 (Power-down) xX xX L xX High-2 IsB1, IsB2 Output Disabled H L H H High-Z Icc1, lec2 Read H L H L DouTt Icc1, Icc2 Write L L H Xx DIN Icc1, Icc2 2 Integrated Silicon Solution, Inc. 1-800-379-4774 SRO28-1J 11/03/98IS61C1024 IS61C1024L ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND 0.5 to +7.0 Vv TBIAS Temperature Under Bias 55 to +125 C TsTG Storage Temperature 65 to +150 C Pr Power Dissipation 1.5 Ww lout DC Output Current (LOW) 20 mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE) Symbol Parameter Conditions Max. Unit CIN Input Capacitance Vin = OV 5 pF Cout Output Capacitance Vout = OV 7 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25C, f = 1 MHz, Vee = 5.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VoH Output HIGH Voltage Vcc = Min., loy = -4.0 mA 2.4 _ Vv VoL Output LOW Voltage Vcc = Min., lo. = 8.0 mA _ 0.4 Vv Viq Input HIGH Voltage 2.2 Veco + 0.5 Vv VIL Input LOW Voltage -0.3 0.8 Vv lu Input Leakage GND < Vin Vcc Com. -2 2 LA Ind. -5 5 ILo Output Leakage GND < Vout < Vcc Com. -2 2 LA Outputs Disabled Ind. 5 5 Note: 1. Vit = -3.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. 1-800-379-4774 3 SRO28-1J 11/03/98IS61C1024 IS61C1024L 1S61C1024 POWER SUPPLY CHARACTERISTICS (Over Operating Range) -12 ns -15ns -20 ns -25 ns Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit Icct Vcc Operating Vcc = Max., CE= Vit Com. 140 140 140 140 mA Supply Current lour =0 mA, f=0 Ind. 140 140 140 140 Icc2 Vcc Dynamic Operating Vcc = Max., CE= VIL Com. 220 200 170 150 mA Supply Current lout = 0 mA, f = fax Ind. 220 200 170 150 IsBt TTL Standby Current Vcc = Max., Com. 40 40 40 40 mA (TTL Inputs) Vin = Vin or Vi Ind. 60 60 60 60 CH > Vin, f=0or CE2< Vi, f=0 Isp2 CMOS Standby Voc = Max., Com. 30 30 8 8 mA Current (CMOS Inputs) CE1<Vcc-0.2V, Ind. 40 40 40 40 CE2 <0.2V Vin > Voc - 0.2V, or Vin <0.2V, f=0 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 1IS61C1024L POWER SUPPLY CHARACTERISTICS (Over Operating Range) -15 ns -20 ns -25 ns Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit lect Vcc Operating Vcc = Max., CE= Vit Com. 85 85 85 mA Supply Current lour =0 mA, f=0 Ind. 110 110 110 Icc2 Vcc Dynamic Operating Vcc = Max., CE= VIL Com. _ 160 150 150 mA Supply Current lout = 0 mA, f = fax Ind. 160 150 150 IsBt TTL Standby Current Vcc = Max., Com. 40 40 40 mA (TTL Inputs) Vin = Vin or Vi Ind. 60 60 60 CH > Vin, f=0or CE2< Vi, f=0 Isp2 CMOS Standby Vcc = Max., Com. _ 500 500 500 A Current (CMOS Inputs) CEI <Vcc-0.2V, Ind. 750 750 750 CE2 <0.2V Vin > Voc 0.2V, or Vin <0.2V, f=0 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 Integrated Silicon Solution, Inc. 1-800-379-4774 SRO28-1J 11/03/98IS61C1024 IS61C1024L READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -12?) -15 ns -20 ns -25 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit trc Read Cycle Time 12 15 20 25 ns TAA Address Access Time _ 12 15 _ 20 _ 25 ns toHa Output Hold Time 3 3 3 3 ns tacet CET Access Time 12 15 20 2 ns tace2 CE2 Access Time 12 _ 15 20 25 ns tooe + OE Access Time 6 7 9 9 ns tizoe + OE to Low-Z Output 0 0 0 0 ns tuzoe OE to High-Z Output 0 6 0 6 0 7 0 10 ns tizce1 CET to Low-Z Output 2 2 3 3 ns tizce2) CE2 to Low-Z Output 2 _ 2 _ 3 _ 3 _ ns tuzce CET or CE2 to High-Z Output 0 7 0 8 0 9 0 10 ns teu) CET or CE2 to Power-Up 0 0 0 0 ns tev CET or CE2 to Power-Down 12 12 18 2 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. -12 ns device for |S61C1024 only. 3. Tested with the load in Figure 2. Transition is measured +500 mV from steady-state voltage. Not 100% tested. 4. Not 100% tested. AC TEST CONDITIONS Parameter Unit Input Pulse Level OV to 3.0V Input Rise and Fall Times 3ns Input and Output Timing 1.5V and Reference Level Output Load See Figures 1 and 2 AC TEST LOADS 480 5V OUTPUT 30 pF 255 Q Including jig and scope = Figure 1 480 5V OUTPUT 5 pF 255 Q Including jig and scope = = Figure 2 Integrated Silicon Solution, Inc. 1-800-379-4774 SRO28-1J 11/03/98IS61C1024 1IS61C1024L AC WAVEFORMS READ CYCLE NO. 1) o tRC > ADDRESS x i tAA tOHA t LOHA DOUT DATA VALID READ CYCLE NO. 2) t tRC a ADDRESS tAA at-LOHA > OE {DOE tHZOE m CF N 4 CE1 \ tLZOE- 7 et tACE1/tACE2 a N CE2 Ho x bw tLZCE1/ALZCE2 Lt tH7CE > DOUT HIGH-Z KK DATA VALID >_- laa tPU Lt tPD _____| [cc A N S U P P LY 50% 50% CURRENT VL Notes: 1. WE is HIGH for a Read Cycle. ee 2. The device is continuously selected. OE, CE1 = ViL, CE2 = Vin. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. 6 Integrated Silicon Solution, Inc. 1-800-379-4774 SRO28-1J 11/03/98IS61C1024 IS61C1024L WRITE CYCLE SWITCHING CHARACTERISTICS) (Over Operating Range, Standard and Low Power) -12 ns@) -15 ns -20ns -25ns Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit twe Write Cycle Time 12 15 20 25 ns tscet CET to Write End 10 120 15 = 2CO ns tsce2 CE2 to Write End 10 _ 12 _ 15 _ 20 ns taw Address Setup Time to Write End 10 _ 12 _ 15 _ 20 _ ns tHA Address Hold from Write End 0 _ 0 _ 0 0 ns tsa Address Setup Time 0 0 0 0 ns tewe WE Pulse Width 10 _ 10 _ 12 _ 15 _ ns tsp Data Setup to Write End 7 8 10 12 ns tHD Data Hold from Write End 0 0 _ 0 0 ns tuzwe WELOW to High-Z Output _ 7 _ 7 _ 10 _ 12 ns tzwe WEHIGH to Low-Z Output 2 2 2 2 ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. __ __ 2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. -12 ns device for |S61C1024 only. Tested with OE HIGH. Tested with the load in Figure 2. Transition is measured +500 mV from steady-state voltage. Not 100% tested. ok Integrated Silicon Solution, Inc. 1-800-379-4774 7 SRO28-1J 11/03/98IS61C1024 IS61C1024L AC WAVEFORMS WRITE CYCLE NO. 1?) (WE Controlled) La twc ADDRESS mK tSCE1 ple tHA CE oo x tSCE2 > CE2 7H K at tAw > WE tPWE 5 VA ~<t-tSA eu t tLZWE DOUuT DATA UNDEFINED QV J tSD m~ tHD DIN DATA-IN VALID WRITE CYCLE NO. 2) (CE1, CE2 Controlled) Lat twc at ADDRESS mK tS A tSCE1. /- tHA Cet S x tSCE2. ->} CE2 VA N _ tAw |S aE __e tPWE " JS |< tHZWE >} e tLZWE | DouT DATA UNDEFINED a {SD m{e tHD m| DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CET LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = Vin. Integrated Silicon Solution, Inc. 1-800-379-4774 SRO28-1J 11/03/98IS61C1024 IS61C1024L 1IS61C1024 STANDARD VERSION ORDERING INFORMATION Commercial Range: 0C to +70C 1IS61C1024 STANDARD VERSION ORDERING INFORMATION Industrial Range: 40C to +85C Speed (ns) Order Part No. Package Speed (ns) Order Part No. Package 12 IS61C01024-12J 300-mil Plastic SOJ 12 1S61C01024-12JI 300-mil Plastic SOJ 12 1S61C01024-12N 300-mil Plastic DIP 12 1S61C1024-12NI_ 300-mil Plastic DIP 12 1S61C01024-12K 400-mil Plastic SOJ 12 IS61C1024-12KI 400-mil Plastic SOJ 12 IS6101024-12H STSOP (Type 1) 12 IS6101024-12HI = STSOP (Type |) 12 IS61C01024-12T TSOP (Type 1) 12 IS61C1024-12TI| = TSOP (Type |) 15 1IS6101024-15J 300-mil Plastic SOJ 15 1S6101024-15JI 300-mil Plastic SOJ 15 IS6101024-15N 300-mil Plastic DIP 15 IS61C1024-15NI = 300-mil Plastic DIP 15 IS6101024-15K 400-mil Plastic SOJ 15 IS61C1024-15KI 400-mil Plastic SOJ 15 IS6101024-15H STSOP (Type 1) 15 IS61C1024-15HI = STSOP (Type 1) 15 IS6101024-15T TSOP (Type 1) 15 IS61C1024-15TIl = TSOP (Type |) 20 1IS6101024-20J 300-mil Plastic SOJ 20 IS6101024-20JI 300-mil Plastic SOJ 20 IS6101024-20N 300-mil Plastic DIP 20 IS61C1024-20NI 300-mil Plastic DIP 20 IS6101024-20K 400-mil Plastic SOJ 20 IS61C1024-20KI 400-mil Plastic SOJ 20 IS6101024-20H STSOP (Type 1) 20 IS61C1024-20HI = STSOP (Type 1) 20 1S6101024-20T TSOP (Type 1) 20 IS6101024-20TI TSOP (Type |) 25 IS6101024-25J 300-mil Plastic SOJ 25 1S6101024-25JI 300-mil Plastic SOJ 25 IS6101024-25N 300-mil Plastic DIP 25 IS61C1024-25NI 300-mil Plastic DIP 25 IS6101024-25K 400-mil Plastic SOJ 25 IS61C1024-25KI 400-mil Plastic SOJ 25 1S6101024-25H STSOP (Type 1) 25 IS61C1024-25HI = STSOP (Type 1) 25 IS61C01024-25T TSOP (Type 1) 25 IS61C1024-25TI| = TSOP (Type |) 1IS61C1024L LOW POWER VERSION ORDERING INFORMATION Commercial Range: 0C to +70C IS61C1024L LOW POWER VERSION ORDERING INFORMATION Industrial Range: 40C to +85C Speed (ns) Order Part No. Package 15 IS61C1024L-15J 300-mil Plastic SOJ IS61C1024L-15N 300-mil Plastic DIP IS61C1024L-15K 400-mil Plastic SOJ IS61C1024L-15H STSOP (Type 1) IS6101024L-15T | TSOP (Type 1) 20 IS61C1024L-20J 300-mil Plastic SOJ IS61C1024L-20N 300-mil Plastic DIP IS61C1024L-20K 400-mil Plastic SOJ IS61C1024L-20H STSOP (Type 1) IS6101024L-20T TSOP (Type 1) 25 IS61C1024L-25J 300-mil Plastic SOJ IS61C1024L-25N 300-mil Plastic DIP IS61C1024L-25K 400-mil Plastic SOJ IS61C1024L-25H STSOP (Type |) IS6101024L-25T TSOP (Type 1) Speed (ns) Order Part No. Package 15 IS61C1024L-15JI 300-mil Plastic SOJ 1S61C1024L-15NI 300-mil Plastic DIP IS61C1024L-15KI 400-mil Plastic SOJ 1S61C1024L-12HRI STSOP (Type 1) IS6101024L-15TI TSOP (Type 1) 20 IS61C1024L-20JI 300-mil Plastic SOJ IS61C1024L-20NI 300-mil Plastic DIP IS61C1024L-20KI 400-mil Plastic SOJ 1S6101024L-12HRI STSOP (Type 1) IS61C1024L-20T] TSOP (Type 1) 25 IS61C1024L-25JI 300-mil Plastic SOJ IS61C1024L-25NI 300-mil Plastic DIP IS61C1024L-25KI 400-mil Plastic SOJ 1S6101024L-12HRI STSOP (Type 1) IS6101024L-25T| TSOP (Type 1) Integrated Silicon Solution, Inc. 1-800-379-4774 SRO28-1J 11/03/98IS61C1024 IS61C1024L NOTICE Integrated Silicon Solution, Inc., reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. Integrated Silicon Solution, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, Integrated Silicon Solution, Inc. shall not be liable for any damages arising as a result of any error or omission. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of Integrated Silicon Solution, Inc. is adequately protected under the circumstances. Copyright 1998 Integrated Silicon Solution, Inc. Reproduction in whole or in part, without the prior written consent of Integrated Silicon Solution, Inc., is prohibited. Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Fax: (408) 588-0806 Toll Free: 1-800-379-4774 E-mail: sales@issi.com http://www.issi.com 10 Integrated Silicon Solution, Inc. 1-800-379-4774 SRO28-1J 11/03/98