COM20020I3V-DZD - SMSC Corporation

SMSC COM20020I 3.3V 1 Revision 12-06-06

DATASHEET

COM20020I 3.3V

5Mbps ARCNET (ANSI

878.1) Controller with

2K x 8 On-Chip RAM

Datasheet

Product Features

 New Features:

- Data Rates up to 5 Mbps

- Programmable Reconfiguration Times

 28 Pin PLCC and 48 Pin TQFP Packages;

Lead-free RoHS Compliant P ackages also

available

 Ideal for Industrial/Factory/Building Automation

and Transportation Applicati ons

 Deterministic, (ANSI 878.1), Token Passing

ARCNET Protocol

 Minimal Microcontroller and Medi a Interface

Logic Required

 Flexible Interface For Use With All

Microcontrollers or Microproc essors

 Automatically Detects Type of Microcontroller

Interface

 2Kx8 On-Chip Dual Port RAM

 Command Chaining for Packet Queuing

 Sequential Access to Internal RAM

 Software Programmable Node ID

 Eight, 256 Byte Pages Allow Four Pages TX and

RX Plus Scratch-Pad Memory

 Next ID Readable

 Internal Clock Scaler and Clock Multiplier for

Adjusting Network Speed

 Operating Temperature Ra nge of -40oC to +85oC

 Self-Reconfiguration Protocol

 Supports up to 255 Nodes

 Supports Various Network Topologies (Star, Tree,

Bus...)

 CMOS, Single +3.3V Supply

 Duplicate Node ID Detection

 Powerful Diagnostics

 Receive All Packets Mode

 Flexible Media Interface:

- Traditional Hybrid Interface For Long

Distances up to Four Miles at 2.5Mbps

- RS485 Differential Driver Interface For Low

Cost, Low Power, High Reliability

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

ORDERING INFORMATION

Order Numbers:

COM20020I3VLJP for 28 p in PLCC package

COM20020I3V-DZ D for 28 pin PLCC package lead-free RoHS compliant package

COM20020I3V-HD for 48 p in TQFP package

COM20020I3V-HT for 48 pin TQFP lead-free RoHS compliant package

80 Arkay Drive

Hauppauge, NY 11788

(631) 435-6000

FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete

information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no

responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without

notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does

not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC

or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard

Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.

SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause

or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further

testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale

Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems

Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMIT ATION ANY AND ALL IMPLIED WARRANTIES

OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND

ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY

DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR

REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC

OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO

HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH

DAMAGES.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 3 Revision 12-06-06

DATASHEET

TABLE OF CONTENTS

2.0 GENERAL DESCRIPTION..............................................................................................................................5

3.0 PIN CONFIGURATIONS.................................................................................................................................6

4.0 DESCRIPTION OF PIN FUNCTIONS FOR TQFP ..........................................................................................8

5.0 PROTOCOL DESCRIPTION.........................................................................................................................11

5.1 NETWORK PROTOCOL ..................................................................................................................................11

5.2 DATA RATES ...............................................................................................................................................11

5.3 NETWORK RECONFIGURATION.......................................................................................................................12

5.4 BROADCAST MESSAGES...............................................................................................................................12

5.5 EXTENDED TIMEOUT FUNCTION.....................................................................................................................12

5.6 LINE PROTOCOL ..........................................................................................................................................13

6.0 SYSTEM DESCRIPTION...............................................................................................................................15

6.1 MICROCONTROLLER INTERFACE ....................................................................................................................15

6.2 TRANSMISSION MEDIA INTERFACE .................................................................................................................19

7.0 FUNCTIONAL DESCRIPTION......................................................................................................................24

7.1 MICROSEQUENCER ......................................................................................................................................24

7.2 INTERNAL REGISTERS...........................................................................................................................25

7.3 INTERNAL RAM ............................................................................................................................................35

7.4 COMMAND CHAINING....................................................................................................................................40

7.5 INITIALIZATION SEQUENCE ............................................................................................................................42

7.6 IMPROVED DIAGNOSTICS ..............................................................................................................................42

8.0 OPERATIONAL DESCRIPTION ...................................................................................................................45

8.1 MAXIMUM GUARANTEED RATINGS*................................................................................................................45

8.2 DC ELECTRICAL CHARACTERISTICS ...............................................................................................................45

9.0 TIMING DIAGRAMS......................................................................................................................................48

10.0 PACKAGE OUTLINES..................................................................................................................................60

11.0 APPENDIX A.................................................................................................................................................62

12.0 APPENDIX B.................................................................................................................................................65

12.1 SOFTWARE IDENTIFICATION OF THE COM20020I REV B, REV C AND REV D.....................................................65

LIST OF FIGURES

Figure 1 - COM20020I OPERATION ...........................................................................................................................10

Figure 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERF ACE...............................................16

Figure 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE......................................17

Figure 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE...............................................................................18

Figure 5 - COM20020I NETW ORK USING R S-48 5 D I F F ERENTI A L TR A N S CE I V E R S................................................20

Figure 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0.............................................................................................20

Figure 7 - INTERNAL BLOCK DIAGRAM....................................................................................................................22

Figure 8 – SEQUENTIAL ACCESS OPERATION........................................................................................................35

Figure 9 – RAM BUFFER PACKET CONFIGURATION ..............................................................................................38

Figure 10 - COMMAND CHAINING S TATU S RE G I S T E R QUEU E...............................................................................40

Figure 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE..................................................48

Figure 12 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE..................................................49

Figure 13 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................50

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

Figure 14 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................51

Figure 15 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE.........................................52

Figure 16 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE.........................................53

Figure 17 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE.........................................54

Figure 18 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE.........................................55

Figure 19 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE .......................................56

Figure 20 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE .......................................57

Figure 21 – NORMAL MODE TRANSMIT OR RECEIVE TIMING...............................................................................58

Figure 22 – BACKPLANE MODE TRANSMIT OR RECEIVE TIMING.........................................................................58

Figure 23 – TTL INPUT TIMING ON XTAL1 PIN.........................................................................................................59

Figure 24 – RESET AND INTERRUPT TIMING...........................................................................................................59

Figure 25 - 28 PIN PLCC PACKAGE DIMENSIONS ...................................................................................................60

Figure 26 - 48 PIN TQFP PACKAGE OUTLINE...........................................................................................................61

Figure 27 - EFFECT OF THE EF BIT ON THE TA/RI BIT ...........................................................................................63

LIST OF TABLES

Table 1 - Typica l Medi a ................................................................................................................................................23

Table 2 - Read Register Summary...............................................................................................................................24

Table 3 - Write Register Summary...............................................................................................................................25

Table 4 - Status R e g is te r...................................................................................................... ........................................28

Table 5 - Diagnostic Statu s Registe r.............................................................................................................................29

Table 6 - Comman d Re giste r........................................................................................................................................30

Table 7 - Address Pointer High Reg ister.......................................................................................................................31

Table 8 - Address Pointer Low Register........................................................................................................................31

Table 9 - Sub Add r ess R e giste r................................................................................................ ...................................31

Table 10 - Configuration Register ................................................................................................................................31

Table 11 - Setup 1 R egister..........................................................................................................................................33

Table 12 - Setup 2 R egister..........................................................................................................................................34

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 5 Revision 12-06-06

DATASHEET

2.0 General Description

SMSC's COM20020I is a member of the family of Embedded ARCNET Controllers from Standard Microsystems

Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent

peripherals in industrial, automotive, and embedded control environments using an ARCNET protocol engine. The

flexible microcontroller and media interfaces, eight-page message support, and extended temperature range of the

COM20020I make it the only true network controller optimized for use in industrial, embedded, and automotive

applications. Using an ARCNET protocol engine is the ideal solution for embedded control applications because it

provides a deterministic t oken-passing pr otocol, a hig hly reliable an d proven net working scheme, an d a data rate of up

to 5 Mbps when using the COM20020I.

A token-passing protocol provides predictable response times because each network event occurs within a

predetermined time interval, based upon the number of nodes on the network. The deterministic nature of ARCNET is

essentia l in real time applicatio ns. The integration of t he 2Kx8 RAM buffer on-chip, the Command Chaining feature, the

5 Mbps maximum data rate, and the internal diagnostics make the COM20020I the highest performance embedded

communications device available. With only one COM20020I and one microcontroller, a complete communicatio ns node

may be implemented.

For more details on the ARCNET protocol engine and traditional dipulse signaling schemes, please refer

to the ARCNET Local Area Network Standard, available from Standard Microsystems Corporation or the

ARCNET Desig ner 's Handboo k, av ailabl e from Data point Corpora tion.

For more detai led informatio n on cabling opti ons including RS 485, transform er-coupled RS -485 and Fiber

Optic interfaces, please refer to the following technical note which is available from Standard

Microsystem s Corpo rat ion: Techni cal Not e 7-5 - C abling Guidel ines for the COM2 002 0I ULA NC.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

3.0 PIN CONFIGURATIONS

nRD/nDS

nWR/DIR

nCS

nINTR

nRESET IN

nTXEN

RXIN

nPULSE2

nPULSE1

XTAL2

XTAL1

VDD

25 24 23 22 21 20 19

nCS

nINTR

nRESET IN

VSS

nTXEN

RXIN

nPULSE2

567891011

AD1

VSS

AD2

nPULSE 1

XTAL2

XTAL1

VDD

VSS

N/C

A0/nMUX

A2/ALE

AD0

AD1

AD2

VSS

nWR/DIR

nRD/nDS

VDD

A2/ALE

AD0

A0/nMUX

Packages: 24-Pin DIP or 28-Pin PLCC

Ordering Information:

COM20019

PACKAGE TYPE: P = Plastic, LJP = PLCC

TEMP RANGE: (Blank) = Commercial: 0°C to +70°C

I = Industrial: -40°C to +85°C

DEVICE TYPE: 20019 = Univ ersal Local Area Network Controller

(with 2K x 8 RAM)

Package: 28-Pin PLCC

Ordering Information:

COM20020 I P

PACKAGE TYPE: P = Plastic, LJP = PLCC

TEMP RANGE: 1 = Industrial: -40° C to 75° C

DEVICE TYPE: 20020 = Universal Local Area Network

(with 2K x 8 RAM)

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 7 Revision 12-06-06

DATASHEET

N/C

A2/ALE

A0/nMUX

VDD

N/C

VSS

N/C

nRD/nDS

VDD

nWR/DIR

N/C

VSS

N/C

VDD

XTAL1

XTAL2

VSS

nPULSE1

AD0

AD1

N/C

AD2

N/C

VSS

VDD

VSS

nCS

VDD

nINTR

N/C

VDD

nRESET

VSS

nTXEN

RXIN

N/C

BUSTMG

nPULSE2

COM20020I

48 PIN TQFP

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

4.0 DESCRIPTION OF PIN FUNCTIONS FOR TQFP

PIN NO NAME SYMBOL I/O DESCRIPTION

MICROCONTROLLER INTERFACE

44, 45,

46 Address

0-2 A0/nMUX

A2/ALE

On a non-multiplexed mode, A0-A2 are address

input bits. (A0 is the LSB) On a multiplexed

address/data bus, nMUX tied Low, A1 is left open,

and ALE is tied to the Address Latch Enable signal.

A1 is connected to an internal pull-up resistor.

1, 2, 4,

7, 9, 10,

12, 13

Data 0-7 AD0-AD2,

D3-D7 I/O On a non-multiplexed bus, these signals are used as

the lower byte data bus lines. On a multiplexed

address/data bus, AD0-AD2 act as the address lines

(latched by ALE) and as the low data lines. D3-D7

are always used for data only. T hese signals are

connected to internal pull-up r esistors.

47, 48,

3, 5,

14-17

N/C N/C I/O Non-connection

37 nWrite/

Direction nWR/DIR IN

nWR is for 80xx CPU, nWR is Write signal input.

Active Low.

DIR is for 68xx CPU, DIR is Bus Direction signal

input. (Low: Write, High: Read.)

39 nRead/

nData

Strobe

nRD/nDS IN

nRD is for 80xx CPU, nRD is Read signal in put.

Active Low.

nDS is for 68xx CPU, nDS is Data Strobe signal

input. Active Low.

31 nReset In nRESET IN Hardware reset signal. Active Low.

34 nInterrupt nINTR OUT Interrupt signal output. Active Lo w.

36 nChip

Select nCS IN Chip Select input. Active Low.

42 N/C N/C OUT Non-connection

26 Read/Write

Bus Timing

Select

BUSTMG IN

Read and Write Bus Access Timing mode selecting

signal. Status of this signal effects CPU and DMA

Timing.

L: High speed timing mo de (only for non-multiplexed

bus)

H: Normal timing mode

This signal is connected to internal pull-up registers.

33 N/C N/C OUT

35 Power

Supply VDD PWR

38 Power

Supply VDD PWR +3.3 volts power supply pins.

40 N/C N/C Non-connection

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 9 Revision 12-06-06

DATASHEET

PIN NO NAME SYMBOL I/O DESCRIPTION

TRANSMISSION MEDIA INTERFACE

nPulse 1

nPulse 2

nPULSE1

nPULSE2

OUT

I/O

In Normal Mode, these active low signals carry the

transmit data information, encoded in pulse format as

DIPULSE waveform. In Backplane Mode, the

nPULSE1 signal driver is pro grammable (push/pull or

open-drain), while the nPULSE2 signal provides a

clock with frequency of doubl ed data rate. nPULSE1

is connected to a weak internal pull-up resistor on

the open/drain driver in backp lane mode.

28 Receive In RXIN IN

This signal carries the receive data information from

the line transceiver.

29 nTransmit

Enable nTXEN OUT

Transmission Enable sig na l. Active polarity is

programmable through the nPULSE2 pin.

nPULSE2 floating before power-up;

nTXEN active lo w

nPULSE2 grounded before power-up;

nTXEN active high (this opti on is only availa ble in

Back Plane mode)

22 Crystal

Oscillator XTAL1

XTAL2 IN

OUT An external crystal should be connected to these

pins. Oscillation frequency range is from 10 MHz to

20 MHz. If an external TTL clock is used instead, it

must be connected to XTAL1 with a 390ohm pull-up

resistor, and XTAL2 should be left floating.

8, 20,

32, 35,

38, 43

Power

Supply VDD PWR +5 Volt power supply pins.

6, 11,

18, 23,

30, 41

Ground VSS PWR Ground pins.

3, 5,

14-17,

19, 27,

33, 40,

42, 48

N/C N/C Non-connection

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

FIGURE 1 - COM20020I OPERATION

Invitation

to Transmit to

this ID?

Free Buffer

Enquiry to

this ID? SOH?

RI?

Wr it e S ID

to Buffer

DID

=0?

DID

=ID?

Wr i te B uff er

with Packet

CRC

OK?

LENGTH

OK?

DID

=0?

DID

=ID?

SEND ACK

Broadcast

Enabled? N

No Activity

for 41

uS?

Set NI D=ID

Start Timer:

T=(255-ID)

Activity

On Line? Y

T=0?

Set RI

RI?

Transmit

NAK

Transmit

ACK

Set NID=I D

Write ID to

RAM Buffer

Send

Reconfigure

Burst

Power O n

Reconfigure

Timer has

Timed Out

Start

Reconfiguration

Timer (420 mS)*

TA?

Broadcast? Transmit

Free Buffer

Enquiry No

Activity

Pass the

Token

Set TA

ACK?

NAK?

Activity NY

Increment

NID

Send

Packet

Was Packet

Broadcast?

Activity

ACK? Set TMA

Set TA

x 73 us

for 37.4

us?

for 37 .4

us?

for 37.4

us?

Read Node ID

ID refers to th e i dent i ficat ion number of the ID assigned to this node.

NID refers to the next identification number that receives t he token

after this ID passes it.

SID refers to the source identific ation.

DID refers to the destination identification.

SOH refers to the start of header character; preceeds all data packets.

* Reconfig ti mer is pro gr ammable via setup2 register bit s 1, 0 .

Note - All time values are valid for 5 Mbps.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 11 Revision 12-06-06

DATASHEET

5.0 PROTOCOL DESCRIPTION

5.1 Network Protocol

Communication on the network is based on a token passing protocol. Establishment of the network configuration and

management of the network protocol are handled entirely by the COM20020I's internal microcoded sequencer. A

processor or intelligent peripheral transmits data by simply loading a data packet and its destination ID into the

COM20020I's internal RAM buffer, and issuing a command to enable the transmitter. When the COM20020I next

receives the token, it verifies that the receiving node is ready by first transmitting a FREE BUFFER ENQUIRY message.

If the receiving node transmits an ACKnowledge message, the data packet is transmitted followed by a 16-bit CRC. If

the receiving node cannot accept the packet (typically its receiver is inhibited), it transmits a Negative AcKnowledge

message and the transmitter passes the token. Once it has been established that the receiving node can accept the

packet and t ransmission is complet e, the receiving no de verifies the packet . If the packet is receiv ed successfully, th e

receiving node transmits an ACKnowledge message (or nothing if it is not received successfully) allowing the transmitter

to set the appropriate status bits to indicate successful or unsuccessful delivery of the packet. An interrupt mask permits

the COM20020I to generate an interrupt to the processor when selected status bits become true. Figure 1 is a flow

chart illustra ting the internal ope ration of the COM20020I connected to a 20 MH z crystal oscillator .

5.2 Data Rates

The COM20020I is capable of supporting data rates from 156.25 Kbps to 5 Mbps. The following protocol description

assumes a 5 Mbps data rate. To attain the faster data rates, the clock frequency may be doubled by the internal clock

multiplier (see next section). For slower data rates, an internal clock divider scales down the clock frequency. Thus all

timeout values are scaled a s shown in the follow ing table:

Example: IDLE L INE Timeout @ 5 Mbps = 41 μs. IDLE LINE Timeout for 156.2 Kb ps is 41 μs * 32 = 1.3 ms

INTERNAL

CLOCK

FREQUENCY

CLOCK

PRESCALER

DATA RATE

TIMEOUT SCALING

FACTOR (MULTIPLY BY)

40 MHz Div. by 8 5 Mbps 1

20 MHz Div. by 8

Div. by 16

Div. by 32

Div. by 64

Div. by 128

2.5 Mbps

1.25 Mbps

625 Kbps

312.5 Kbps

156.25 Kbps

Selecting Clock Frequencies Above 2.5 Mbps

To realize a 5 Mbps n et work, an external 40 MHz clock mus t be input. H owever, since 40 MHz is near t he frequenc y

of FM radio band, it is not practical for use for noise emission reasons. Therefore, higher frequency clocks are

generated from the 20 MHz crystal as selected through two bits in the Setup2 register, CKUP[1,0] as shown below.

The selected clock is supplied to the ARCNET controller.

CKUP1 CKUP0 CLOCK FREQUENCY (DATA RATE)

0 0 20 MHz (Up to 2.5Mbps) Default (Bypass)

0 1 40 MHz (Up to 5Mbps)

1 0 Reserved

1 1 Reserved

This clock multiplier is powered-down (bypassed) on default. After changing the CKUP1 and CKUP0 bits, the

ARCNET core operation is stopped and the internal PLL in the clock generator is awakened and it starts to generat e

the 40 MHz. The lock out time of the inter nal PLL is 8uSec typically. After more than 8 μs ec (this wait time is defi ned

as 1 msec in this data sheet), it is necessary to write command data '18H' to the command register to re-start the

ARCNET core operation. T his clock generator is called “clock multiplier”.

Changing the CKUP1 and C KUP0 bits must be one time or less after releasing hardware reset.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

The EF bit in the SETUP2 register must be set when the data rate is over 5 Mbps.

5.3 Network Reconfiguration

A significant advantage of the COM20020I i s its ability to adapt to change s on the net work. Whenever a ne w node is

activated or deactivated, a NETWORK RECONFIGURATION is performed. When a new COM20020I is turned on

(creating a new active node on the network), or if the COM20020I has not received an INVITATION TO TRANSMIT

for 420mS, or if a software reset occurs, the COM20020I causes a NETWORK RECONFIGURATION by sending a

RECONFIGURE BURST consisting of eight marks and one space repeat ed 765 tim es. The pur pose of this burst is to

terminate all activity on the network. Since this burst is longer than any other type of transmission, the burst will

interfere with the next INVITATION TO TRANSMIT, destroy the token and keep any other node from assuming

control of the line.

When any COM20020I senses an idle line for greater than 41μS, which occurs only when the token Is lost, each

COM20020I starts an inter nal timeout equal to 73μs times t he quantit y 255 minus its own ID. The CO M20020I starts

network reconfiguration b y sending an invitation to transm it first to itself and then to all ot her nodes by decrementing

the destination Node ID. If the timeout expires with no line activity, the COM20020I starts sending INVITATION TO

TRANSMIT with the Destination ID (DID) equal to the currently stored NID. Within a given network, only one

COM20020I will timeout (the one with the highest ID number). After sending the INVITATION TO TRANSMIT, the

COM20020I waits for activity on the line. If there is n o activity for 37.4μS, the COM20020I increments the NID value

and transmits another INVITATION TO TRANSMIT using the NID equal to the DID. If activity appears before the

37.4μS timeout expires, the COM20020I releases control of the line. During NETWORK RECONFIGURATION,

INVITATIONS TO TRANSMIT are sent to all NIDs (1-255).

Each COM20020I on the network will finally have saved a NID value equal to the ID of the COM20020I that it

released control to. At this point, control is passed directly from one node to the next with no wasted INVITATIONS

TO TRANSMIT being sent to ID's not on the network, until the ne xt NETWORK RECONFIGURATION occurs. Whe n

a node is powered off, the previous node attempts to pass the token to it by issuing an INVITATION TO TRANSMIT.

Since this node does not res pond, the previ ous node tim es out an d transmits another IN VITAT ION TO T RANSMIT to

an incremented ID and eventually a response will be rece ived.

The NETWORK RECONFIGURATION time depends on the number of nodes in the network, the propagation delay

between nodes, and the highest ID number on the network, but is typically within the range of 12 to 30.5 mS.

5.4 Broadcast Messages

Broadcasting gives a particu lar node the abili ty to transmit a data packet to all nodes on the network simultaneousl y.

ID zero is reserved for this feature a nd no node on the network can be a ssigned ID zero. To broadcast a message,

the transmitting node's processor simply loads the RAM buffer with the data packet and sets the DID equal to zero.

Figure 4 illustrates the position of each byte in the packet with the DID residing at address 0X01 or

Hex of the current page selected in the "Enable Transmit from Page fnn" command. Each individual node has the

ability to ignore bro adcast m essages b y setting th e most significa nt bit of th e "E nable Rec eive to Pa ge fn n" comm and

to a logic "0".

5.5 Extended Timeout Function

There are three timeouts associated with the COM20020I operation. The values of these timeouts are

controlled by bits 3 and 4 of the Configuration Register and bit 5 of the Setup 1 Register.

Response Time

The Response Time determines the maximum propagation delay allowed between any two nodes, and should be

chosen to be larger than the round trip propagation delay between the two furthest nodes on the network plus the

maximum turn around time (the time it takes a particular COM20020I to start sending a message in response to a

received message) which is approximately 6.4 μS. The round trip propagation delay is a function of the transmission

media and network topology. For a typical system using RG62 coax in a baseband system, a one way cable

propagation delay of 15.5 μS translates to a distance of about 2 miles. The flow chart in Figu re 1 uses a value of 37.4

S (15.5 + 15.5 + 6 .4) to determine if any node w ill re spon d.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 13 Revision 12-06-06

DATASHEET

Idle Time

The Idle Time is associated with a NETWORK RECONFIGURATION. Figure 1 illustrates that during a NETWORK

RECONFIGURATION one node will continually transmit INVITATIONS TO TRANSMIT until it encounters an active

node. All other nodes on the network must distinguish between this operation and an entirely idle line. During

NETWORK RECONFIGURATION, activity will appear on the line every 41 μS. This 41 μS is equal to the Response

Time of 37.4 μS plus the time it takes the COM20020I to start retransmitting another message (usually another

INVITATION TO TRANSMIT).

Reconfiguration Time

If any node does not receive the token within the Reconfiguration Time, the node will initiate a NETWORK

RECONFIGURATION. The ET2 and ET1 bits of the Configuration Register allow the network to operate over longer

distances than the 2 miles stated earlier. The logic levels on these bits control the maximum distances over which the

COM20020I can operate by controlling the three timeout values described above. For proper network operation, all

COM20020I's connected to the same network must have the same Response Time, Idle Time, and Reconfiguration

Time.

5.6 Line Protocol

The ARCNET line protocol is considered isochronous because each byte is preceded by a start interval and ended with

a stop interval. Unlike asynchronous protocols, there is a constant amount of time separating each data byte. On a 5

Mbps network, each byte takes exactly 11 clock intervals of 200ns each. As a result, one byte is transmitted every 2.2

S and th e time to tr ansmit a mes sag e ca n be pre cise ly d eterm ine d. The line i dles i n a sp acing ( log ic " 0") cond it ion. A

logic "0" is defined as no line activity and a logic "1" is defined as a negative pulse of 100nS duration. A transmission

starts with an ALERT BURST consisting of 6 unit intervals of mark (logic "1"). Eight bit data characters are then sent,

with each character preceded by 2 unit intervals of mark and one unit interval of space. Five types of transmission can

be performed as described below :

Invitations To Transmit

An Invitation To Transmit is used to pass the token from one node to another and is sent by the following sequence:

 An ALERT BURST

 An EOT (End Of Transmission: ASCII code 04H)

 Two (repeated) D ID (Destination ID) characters

ALERT

BURST EOT DID DID

Free Buffer Enquiries

A Free Buffer Enquiry is used to ask another node if it is able to accept a packet of data. It is sent by the following

sequence:

 An ALERT BURST

 An ENQ (ENQuiry: ASCII code 85H)

 Two (repeated) D ID (Destination ID) characters

ALERT

BURST ENQ DID DID

Data Packe ts

A Data Packet consists of the actual data being sent to another node. It is sent by the following sequence:

 An ALERT BURST

 An SOH (Start Of Header--ASCII code 01H)

 An SID (Source ID) character

 Two (repeated) D ID (Destination ID) characters

 A single COUNT character which is the 2's complement of the number of data bytes to follow if a short packet is

sent, or 00H followed by a COUNT character if a long packet is sent.

 N data bytes where COUNT = 25 6-N (or 512 -N for a long packet)

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

 Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X16 + X15 + X2 + 1.

Acknowledgements

An Acknowledgement is used to acknowledge reception of a packet or as an affirmative response to FREE BUFFER

ENQUIRIES and is sent by the follow ing se quence :

 An ALERT BURST

 An ACK (ACKnowledgemen t--ASC II code 86H) chara c te r

ALERT BURST ACK

Negative Acknowledgements

A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the

following sequen ce :

 An ALERT BURST

 A NAK (Negative Acknowledgemen t--ASCII cod e 15H) cha racter

ALERT BURST NAK

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 15 Revision 12-06-06

DATASHEET

6.0 SYSTEM DESCRIPTION

6.1 Microcontroller Interface

The top hal ves of Fi gur e 2 and Fi gur e 3 illustrate t ypical COM20020I interfaces to t he microcontr ollers. The i nterfaces

consist of a 8-bit data bu s, an address bus an d a control bus. In order to support a wide range of microcontrolle rs w ith out

requiring glue logic and without increasing the number of pins, the COM20020I automatically detects and adapts to the

type of microcontroller being used. Upon hardware reset, the COM20020I first determines whether the read and write

control signals are separate READ and WRITE signals (like the 80XX) or DIRECTION and DATA STROBE (like the

68XX). To determine the type of control signals, the device requires the software to execute at least one write access to

external m emor y bef o re attemp ting t o ac ce ss t he COM 2 002 0I . The device defaults to 80XX-like signals. Once the type

of control signals are determined, the COM20020I remains in this interface mode until the next hardware reset occurs.

The second determination the COM20020I makes is whether the bus is multiplexed or non-multiplexed. To determine

the type of bus, the device requires the software to write to an odd memory location followed by a read from an odd

location before attempting to access the COM20020I. The signal on the A0 pin during the odd location access tells the

COM20020I the type of bus. Since multiplexed operation requires A0 to be active low, activity on the A0 line tells the

COM20020I that the bus is non-multiplexed. The device defaults to multiplexed operation. Both determinations may be

made simultaneously by performing a WRITE followed by a READ operation to an odd location within the COM20020I

Address space 20020D registers. Once the type of bus is determined, the COM20020I remains in this interface mode

until hardware reset oc curs.

Whenever nCS and nRD are activated, the preset determinations are assumed as final and will not be changed until

hardware reset. Re fer to DESCRIPTION OF PIN FUNCTIONS FOR TQFP section for detai l s on the related signal s. All

accesse s to the internal RAM and the internal reg isters are controlled by the COM20020I. The internal RAM is accessed

via a pointer-based sche me (refer to the Sequential Access Memory section) , and the internal regi sters are accessed via

direct addressing. Many peripherals are not fast enough to take advantage of high-speed microcontrollers. Since

microcontrollers do not typically have READY inputs, standard peripherals cannot extend cycles to extend the access

time. The access time of the COM20020I, on the other hand, is so fast that it does not need to limit the speed of the

microcontroller. The C OM20020 I is desig ned to be flexi ble so that it i s i ndependent of the microcon trol ler speed.

The COM20020I provides for no wait state arbitration via direct addressing to its internal registers and a pointer based

addressing scheme to access its internal RAM. The pointer may be used in auto-increment mode for typical sequential

buffer emptying or loading, or it can be taken out of auto-increment mode to perform random accesses to the RAM. The

data within the RAM is accessed through the data register. Data being read is prefetched from memory and placed into

the data register for the microcontroller to read. It is important to notice that only by writing a new address pointer

(writing to an address pointer low), one obtains the contents of COM20020I internal RAM. Performing only read from the

Data Register does not load new data from the internal RAM. During a write operation, the data is stored in the data

prefetched to prepare for the first read operation .

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

FIGURE 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE

RXIN

nPULSE

TXEN

GND

+3.3V

100

BACKPLANE

FIGURE A

RXIN

nPULSE

FIGURE B

Receive

HFD3212-

+5V

Transmitte

HFE4211-

+5V

2 Fiber

(ST

NOTE: COM20020 must be in backplane mode

D0-

nINT1

RESET

nRD

nWR

D0-AD2, D3-

nCS

nRESET

nRD/nD

nWR/DI

nINTR

2/BAL

XTAL1

XTAL2

GND

RXIN

nPULSE

nTXEN

8051

COM20020I

Differential

Configuratio

Media

may be

with Figure A, B or

LTC1480 or

Equiv.

0/nMU

27 pF 27 pF

XTAL2

XTAL1

20 MH z

XTAL

3.3V-5V Converter

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 17 Revision 12-06-06

DATASHEET

FIGURE 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE

D0-D7

nIRQ1

nRES

nIOS

R/nW

D0-D7

0/nMU

XTAL1

XTAL2

nCS

nRESET

nRD/nDS

nWR/nDIR

nINTR

2/BALE

RXIN

nPULSE1

nPULSE2

TXEN

GND

Differential Driver

Configuration

6801

COM2002

Media Interface

may be replaced

with Figure A, B or C.

LTC1480 or

Equiv.

XTAL1 XTAL2

27 pF 27 pF

20MHz

XTAL

RXIN

nPULSE1

nPULSE2

nTXEN

GND

Traditional Hybrid

Configuration

RXIN

nPULSE1

nPULSE2

17, 19,

4, 13, 14

5.6K

1/2W

5.6K

1/2W

0.01 uF

1KV

-5V

0.47

uF 10

0.47

+5V

FIGURE C

HYC9088

HYC9068 or

N/C

*Valid for 2.5 Mbps only.

3.3V-5V Converter

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

High Speed CPU Bus Timing Support

High speed CPU bus support was added to the COM20 020I. The reasoning behind this is as follows: With the Host

interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable before the read signal is

active and remain after the read signal is inactive. But the High Speed CPU bus timing doesn't adhere to these

timings. For example, a RISC type single chi p microcontroller (like the HITACHI SuperH series) ch anges I/O address

at the same time as the read signal. Therefore, several external logic ICs would be required to connect to this

microcontroller.

In addition, the Diagnostic St atus (DIAG) register is cle ared automatic ally by reading itself. T he internal DIAG register

read signal is gen erated by decoding the Address (A 2-A0), Chip Select (nCS) and Read (nRD) signals. The decoder

will generate a noise spike at t he above tight timing. The DIAG register is cleared by the spike signa l without readin g

itself. This is unexpected operation. Reading the internal RAM and Next Id Register have the same mechanism as

reading the DIAG register.

Therefore, the address decode and host interface mode blocks were modified to fit the above CPU interface to

support high speed CPU bus timing. In Intel CPU mode (nRD, nWR mode), 3 bit I/O address (A2-A0) and Chip

Select (nCS) are sam pled internally b y Flip-Flops on the fa lling edge of the i nternal delayed nRD signal. The internal

real read signal is the more delayed nRD signal. But the rising edge of nRD doesn't delay. By this modification, the

internal real address and Chip Select are stable while the internal real read signa l is active. Refer to Figure 4 below.

FIGURE 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE

The I/O address and Chip S elect signals, which are supplied to the data output lo gic, are not sampled. Also, the nRD

signal is not delayed, because the above sampling and delaying paths decrease the data access time of the read

cycle.

The above sampling and delaying signals are supplied to the Read Pulse Generation logic which generates the

clearing pulse f or the Diagnostic register and gen erates the starting pulse of the RAM Ar bitration. Typical delay tim e

between nRD and nRD1 is ar ound 15nS and between nRD1 and nRD2 is around 10nS.

Longer pulse widths are needed due to these dela ys on nRD signal. However, the CP U can insert some wait cycles

to extend the width without any impact on performance.

The RBUSTMG bit was added to Disable/E nable the High Speed CPU Read functi on. It is defined as: RBUSTMG=0,

Disabled (Default); RBUSTMG=1, Enabled.

A2-A0, nCS

nRD

Delayed nRD

(nRD1)

Sampled A2-A0, nCS

More delayed nRD

(nRD2)

VALID

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 19 Revision 12-06-06

DATASHEET

In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply.

RBUSTMG BIT BUS TIMING MODE

0 Normal Speed CPU Read and Write

1 High Speed CPU Read and Normal Speed CPU Write

6.2 Transmission Media Interface

The bottom halves of Figure 2 and Figure 3 illustrate the COM20020I interface to the transmission media used to

connect the node to the network. TABLE 1 - TYPICAL MEDIA lists different types of cable which are suitable for

ARCNET applications. The user may interface to the cable of choice in one of three ways:

Traditional Hybrid Interface

The Traditional Hybrid Interface is that which is used with previous ARCNET devices. The Hybrid Interface is

recommended if the node is to be placed in a network with other Hybrid-Interfaced nodes. The Traditional Hybrid

Interface is for use with nodes operating at 2.5 Mbps only. The transformer coupling of the Hybrid offers isol ation for the

safety of the system and offers high Common Mode Rejection. The Traditional Hybrid Interface uses circuits like

SMSC's HYC9068 or HYC9088 to transfer the pulse-encoded data between the cable and the COM20020I. The

COM20020I transmits a logic "1" by generating two 100nS non-overlapping negative pulses, nPULSE1 and nPULSE2.

Lack of pulses indic ates a logic "0". T he nPU LSE 1 and nP UL SE2 sig nals ar e sent t o the H ybrid, whic h creat es a 20 0nS

dipulse signal on th e media.

A logic "0" is transmitted by the absence of the dipulse. During reception, the 200nS dipulse appearing on the media is

coupled through the RF transformer of the LAN Driver, which produces a positive pulse at the RXIN pin of the

COM20020I. The pulse on the RXIN pin represents a logic "1". Lack of pulse represents a logic "0". Typically, RXIN

pulses occur at multiples of 400nS. The COM20020I can tolerate distortion of plus or minus 100nS and still correctly

capture and convert the RXIN pulses to NRZ format. Figure 5 illustrates the events which occur in transmission or

reception of data consisting of 1, 1, 0.

Please refer to TN7-5 – Cabling Guidelines for the COM20020I ULANC, available from SMSC, for recommended

cabling distance, termination, and node count for ARCNET nodes.

Backplane Configuration

The Backplane Open Drain Configuration is recommended for cost-sensitive, short-distance applications like backplanes

and instrumentation. This mode is advantageous because it saves components, cost, and power.

Since the Back plane Configur ation encodes data diffe rently than the tradit ional Hybrid Conf iguration, n odes utilizing th e

Backplane Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid Configuration. The

Backplane Configuration does not isolate the node from the media nor protects it from Common Mode noise, but

Common Mode N oi se i s less of a proble m in short distan ce s.

The COM20020I supplies a programmable output driver for Backplane Mode operation. A push/pull or open drain driver

can be selected by programming the P1MODE bit of the Setup 1 Register (see register descriptions for details). The

COM20020I defau lts to an open drain o utput.

The Backplane Configuration provides for direct connection between the COM20020I and the media. Only one pull-up

resistor (in open drain configuration of the output driver) is required somewhere on the media (not on each individual

node). The nPULSE1 signal, in this mode, is an open drain or push/pull driver and is used to directly drive the media. It

issues a 200nS negative pulse to transmit a logic "1". Note that when used in the open-drain mode, the COM20020I

does not have a fail/safe input on the RXIN pin. The nPULSE1 signal actually contains a weak pull-up resistor. This

pull-up should not take the place of th e resistor required on the media for open drain mo de.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

FIGURE 5 - COM20020I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS

FIGURE 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0

COM2002

+3.3V

RBIAS

+3.3V +3.3V

RBIAS RBIAS

RT RT

LTC1480 or

Equiv.

COM2002 COM2002

20MHZ

CLOCK

(FOR R E F.

ONLY)

nPULSE1

nPULSE2

DIPULSE

RXIN

100ns

200ns

400ns

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 21 Revision 12-06-06

DATASHEET

In typical applications, the serial backplane is terminated at both ends and a bias is provided by the external pull-up

resistor.

The RXIN signal is directly connected to the cable via an internal Schmitt trigger. A negative pulse on this input

indicates a logic "1". Lack of pulse indicates a logic "0". For typical single-ended backplane applications, RXIN is

connected to nPULSE1 to make the serial backplane data line. A ground line (from the coax or twisted pair) should run

in parallel with the signal. For applications requiring different treatment of the receive signal (like filtering or squelching),

nPULSE1 and RXIN re mai n as independent pins. External differential drivers/receive rs for increased range and co mmon

mode noise reje cti on, fo r example, would requ ire the si gnals to be inde pende nt of one another.

When the device is in Backplane Mode, the clock provided by the nPULSE2 signal may be used for encoding the data

into a different encoding scheme o r o th er synchronous operations needed on the serial da ta stream.

Differential Driver Configuration

The Differential Driver Configuration is a special case of the Backplane Mode. It is a dc coupled configuration

recommended for applications like car-area networks or other cost-sensitive applications which do not require direct

compatibility w ith existing ARCN ET nodes and do no t requi re isola tion.

The Differential Driver Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid

Configurat i on. Like the Back pla ne Conf igur atio n, the Differ e ntia l Driv er Conf ig urati on does n ot isol ate t he node fr om the

media.

The Differential Driver interface includes a RS485 Driver/Receiver to transfer the data between the cable and the

COM20020I. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is active. The nPULSE1

signal issues a 200nS (at 2.5Mbps) negative pulse to transmit a logic "1". Lack of pulse indicates a logic "0". The RXIN

signal receives the data, the transmitter portion of the COM20020I is disabled during reset and the nPULSE1, nPULSE2

and nTXEN pins are inactive.

Programmable TXEN Polarity

To accommodate transceivers with active high ENABLE pins, the COM20020I contains a programmable TXEN output.

To program the TXEN pin for an active high pulse, the nPULSE2 pin should be connected to ground. To retain the

normal active low polarity, nPULSE2 should be left open. The polarity determination is made at power on reset and is

valid only for Backplane Mode operation. The nPULSE2 pin should remain grounded at all times if an active high

polarity is de sired.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

FIGURE 7 - INTERNAL BLOCK DIAGRAM

MICRO-

SEQUENCER

AND

WORKING

REGISTERS

STATUS/

COMMAND

RESET

LOGIC

RECONFIGURATION

TIMER NODE ID

LOGIC

OSCILLATOR

TX/RX

LOGIC

ADDITIONAL

REGISTERS

ADDRESS

DECODING

CIRCUITRY 2K x 8

AD0-AD2,

BUS

ARBITRATION

CIRCUITRY

nPULSE1

nPULSE2

nTXEN

nINTR

nRESET

RAM

A0/nMUX

A2/BALE

nRD/nDS

nWR/DIR

nCS

D3-D7

RXIN

XTAL1

XTAL2

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 23 Revision 12-06-06

DATASHEET

Table 1 - Typica l Media

CABLE TYPE NOMINAL

IMPEDANCE A TTENUATION PER 1000 FT.

AT 5 MHz

RG-62 Be lden #86262 93Ω 5.5dB

RG-59/U Belden #8910 8 75Ω 7.0dB

RG-11/U Belden #8910 8 75Ω 5.5dB

IBM Type 1* Belden #89688 150Ω 7.0dB

IBM Type 3* Telephone Twisted

Pair Belden #1155A

100Ω

17.9dB

COMCODE 26 AWG Twisted

Pair Part #105-064-703

105Ω

16.0dB

*Non-plenu m-rated cables of th is ty pe are also availa ble.

Note: For more detailed information on Cabling options including RS-485, transformer-coupled RS-485 and Fiber Optic

interfaces, please refer to TN7-5 – Cabling Guidelines for the COM20020I ULANC, available from Standard

Microsystems Corporation.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

7.0 FUNCTIONAL DESCRIPTION

7.1 Microsequencer

The COM20020I contains an internal micr osequencer which performs all of the control operati ons necessar y to carry

out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program counter, two instruction

registers, an instruction decod er, a no-op generator, jump logic, and reconfiguration logic.

The COM20020I derives a 10 MHz and a 5 MHz clock from the output clock of the Clock Multiplier. These clocks

provide the rate at which the instructions ar e executed within the COM20020I. The 10 MHz clock is the rate at which

the program counter operates, while the 5 MHz clock is the rate at which the instructions are executed. The

microprogram is stored in the ROM and the instructions are fetched and then placed into the instruction registers.

One register holds the opcode, while the other holds the immediate data. Once the instruction is fetched, it is

decoded by the internal instruction decoder, at which point the COM20020I proceeds to execute the instruction.

When a no-op instruction is encountered, the microsequencer enters a timed loop and the program counter is

temporarily stopped until the loop is complete. When a jump instruction is encountered, the program counter is

loaded with the jump address from the ROM. The COM20020I contains an internal reconfiguration timer which

interrupts the microsequencer if it has timed out. At this point the program counter is c leared and the MYRECON bit

of the Diagnostic Status Register is set.

Table 2 - Read Register Summary

MSB READ

LSB

ADDR

STATUS RI/TRI X/RI X/TA POR TEST RECON TMA TA/

TTA 00

DIAG.

STATUS MY-RECON DUPID RCV-

ACT TOKEN EXC-

NAK TENTID NEW

X 01

ADDRESS

PTR HIGH RD-DATA AUTO-

INC X X X A10 A9 A8

ADDRESS

PTR LOW A7 A6 A5 A4 A3 A2 A1 A0

DATA D7 D6 D5 D4 D3 D2 D1 D0

SUB ADR (R/W)* 0 0 0 (R/W)*

SUB-

AD2 SUB-

AD1 SUB-

AD0 05

CONFIG-

URATION RESET CCHE

N TXEN ET1 ET2 BACK-

PLANE SUB-

AD1 SUB-

AD0 06

TENTID TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0

07-0

NODE ID NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0

07-1

SETUP1 P1 MODE FOUR

NAKS X RCV-

ALL CKP3 CKP2 CKP1

SLOW-

ARB 07-2

NEXT ID NXT ID7 NXT

ID6 NXT

ID5 NXT

ID4 NXT

ID3 NXT

ID2 NXT

ID1 NXT

ID0 07-3

SETUP2 RBUS-TMG X CKU

P1 CKUP0 EF NO-

SYNC RCN-

TM1 RCM-

TM2 07-4

Note*: (R/W) This bit can be Written or Read. For more information see Appendix B.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 25 Revision 12-06-06

DATASHEET

Table 3 - Write Register Summary

ADDR

MSB WRITE

LSB

00 RI/TR1 0 0 0 EXCNAK

RECO

N NEW

NEXTID TA/

TTA INTERRUPT

MASK

01 C7 C6 C5 C4 C3 C2 C1 C0

COMMAND

02 RD-

DATA AUTO-

INC 0 0 0 A10 A9 A8

ADDRESS

PTR HIGH

03 A7 A6 A5 A4 A3 A2 A1 A0

ADDRESS

PTR LOW

04 D7 D6 D5 D4 D3 D2 D1 D0 DATA

05 (R/W)* 0 0 0 (R/W)*

SUB-

AD2 SUB-

AD1 SUB-

AD0 SUBADR

06 RESE

T CCHEN TXEN ET1 ET2 BACK-

PLANE SUB-

AD1 SUB-

AD0 CONFIG-

URATION

07-0 TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 TENTID

07-1 NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0 NODEID

07-2 P1-

MODE FOUR

NAKS 0 RCV-

ALL CKP3 CKP2 CKP1

SLOW-

ARB SETUP1

07-3 0 0 0 0 0 0 0 0 TEST

07-4 RBUS-

TMG 0 CKUP

1 CKUP0 EF NO-

SYNC RCN-

TM1 RCN-

TM0 SETUP2

Note*: (R/W) This bit can be Written or Rea d. F or more information see Appendix B.

7.2 INTERNAL REGISTERS

The COM20020I contains 14 internal registers. TABLE 2 and TABLE 3 illustrate the COM20020I register map. All

undefined b its are rea d as undefined and must be written as logic "0".

Interrupt Mask Re gister (IMR)

The COM20020I is capable of generating an interrupt signal when certain status bits become true. A write to the IMR

specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position

as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic "1" in a particular

position enables the corresponding interrupt. The Status bits capable of generating an interrupt include the Receiver

Inhibited bit, New Next ID bit, Excessive NAK bit, Reconfiguration Timer bit, and Transmitter Available bit. No other

Status or Diagnostic Status bits can generate an inte rrupt.

The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to produce the

interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset to logic "0", but will reappear

when the corresponding mask bit is set to logic "1" again, unless the interrupt status condition has been cleared by this

time. A RECON interrupt is cleared when the "Clear Flags" command is issued. An EXCNAK interrupt is cleared when

the "POR Clear Flags" command is issued. A New Next ID interrupt is cleared by reading the Next ID Register. The

Interrupt Mask Register defaults to the value 0000 0000 upon h ardware rese t.

Data Register

This read/write 8-bit register is used as the channel through which the data to and from the RAM passes. The data is

placed in or retrieved from the address location presently specified by the address pointer. The contents of the Data

of COM20020I Internal Memory upon writing Address Pointer low only once.

Tentative ID Register

The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly

(please refer to the Configuration Register and SUB ADR Register). The Tentative ID Register can be used while the

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

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node is on-line to build a network map of those nodes existing on the network. It minimizes the need for operator

interaction with the network. The node determines the existence of other nodes by placing a Node ID value in the

Tentative ID Register and waiting to see if the T entative ID bit of the Diagnostic Status Register gets set. The network

map developed by this method is only valid for a short period of time, since nodes may join or depart from the network at

any time. When using the Tentative ID feature, a node cannot detect the existence of the next logical node to which it

passes the token. The Next ID Register will hold the ID value of that node. The Tentative ID Register defaults to the

value 0000 0000 upon hardware reset o nly.

Node ID Register

The Node ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (please

refer to the Configuration Register and SUB ADR Register). The Node ID Register contains the unique value which

identifies t his partic ular node. Eac h node on t he net work must have a uni que Node ID va lue at all ti mes. The Dupl icate

ID bit of the Diagnostic Status Register helps the user find a un ique Node ID. Refer to the Initiali za tion Sequence section

for further detail on the use of the DUPID bit. The core of the COM20020I does not wake up until a Node ID other than

zero is w ritt en into the Node ID Registe r. During this ti me, no microcode is executed, no tokens are passed by this node,

and no reconfigurations are caused by this node. Once a non-zero NodeID is placed into the Node ID Register, the core

wakes up but will not join the network until the TXEN bit of the Configuration Register is set. While the Transmitter is

disabled, the Receiver portion of the device is still functional and will provide the user with useful information about the

network. The Node ID Reg iste r defaul ts to the va lue 0000 0000 upon hardware reset only.

Next ID Register

The Next ID Register is an 8-bit, r ead-onl y registe r, accesse d when the sub-address bits are set up accordingly (please

refer to the Configuration Register and SUB ADR Register). The Next ID Register holds the value of the Node ID to

which the COM20020I will pass the token. When used in conjunction with the Tentative ID Register, the Next ID

network or when a network reconfiguration occurs. Each time the microsequencer updates the Next ID Register, a New

Next ID interrupt is generated. This bit is cleared by reading the Next ID Register. Default value is 0000 0000 upon

hardw a re or software reset.

Status Register

The COM20020I Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software

compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout status

was provided in bits 5 and 6 of the Status Register. In the COM20020I, the COM20020I, the COM90C66, and the

COM90C165, COM20020I-5, COM20051 and COM20051+ these bits exist in and are controlled by the Configuration

Chaining operation. Please refer to the Command Chaining section for the definition of the Status Register during

Command Chaining operation. The Status Register defaults to the value 1XX1 0001 upon either hardware or software

reset.

Diagnostic Status Register

The Diagnostic Status Register contains seven read-only bits which help the user troubleshoot the network or node

operation. Various combinations of these bits and the TXEN bit of the Configuration Register represent different

situations. All of these bits, except the Excessive NAcK bit and the New Next ID bit, are reset to logic "0" upon reading

the Diagnostic Status Register or upon software or hardware reset. The EXCNAK bit is reset by the "POR Clear Flags"

command or upon software or hardware reset. The Diagnostic Status Register defaults to the value 0000 000X upon

either hardw a re or softw are rese t.

Command Register

Execution of commands are initiated by performing microcontroller writes to this register. Any combinations of written

data other than those li sted in TABLE 5 are not permi tted and may result in in correct chip and /or network operation.

Address Pointer Registers

These read/write registers are each 8-bits wide and are used for addressing the internal RAM. New pointer addresses

should be written by first writing to the High Register and then writing to the Low Register because writing to the Low

reset. Writing to Address Pointer low loads the address.

Configuration Register

The Configuration Register is a read/write register which is used to configure the different modes of the COM20020I.

The Configuration Register defaults to the value 0001 1000 upon hardware reset only. SUBAD0 and SUBAD1 point to

the selection in Register 7.

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Sub-Address Register

The sub-address register is new to the COM20020I, previously a reserved register. Bits 2, 1 and 0 are used to select

one of the r egisters a ssigned to addres s 7h. SU BA D1 a nd SUBAD0 already exist in the Configurati on register on the

COM20020IB. They ar e exactly same as those in the Sub- Address register. If the SUBAD1 and SUBAD0 bits in the

Configuration register are changed, the SUBAD1and SUBAD0 in the Sub-Address register are also changed.

SUBAD2 is a ne w sub-address bit. It Is used to access the 1 new Set Up r egister, SETUP2. This register is selected

by setting SUBAD2=1. The SUBAD2 bit is cleare d automati c ally by writing the Configurati on register.

Setup 1 Register

The Setup 1 Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (see the

bit definitions of the Configuration Register). The Setup 1 Register allows the user to change the network speed (data

rate) or the arbitration speed independently, invoke the Receive All feature and change the nPULSE1 driver type. The

data rate may be slowed to 156.25Kbps and/or the arbitration speed may be slowed by a factor of two. The Setup 1

Setup 2 Register

The Setup 2 Regis ter is new t o the C OM200 20I. It is a n 8-bit read/write register accessed when the Sub Address Bits

SUBAD[2: 0] are set up accordingly (se e the bit defin itions of the Sub Ad dress Register). T his r egis ter c onta ins bits for

various functions. The CKUP1,0 bits select the clock to be generate d from the 20 MHz crystal. The RBUSTMG bit is

used to Disable/Enable Fast Read function for High Speed CPU bus support. The EF bit is used to enable the new

timing for certain functions in the COM20020I (if EF = 0, the timing is the same as in the COM20020I Rev. B). See

Appendix “A”. The NOSYNC bit is used to enable the NOSYNC function during initialization. If this bit is reset, the

line has to be idle for the RAM initialization sequence to be written. If set, the line does not have to be idle for the

initialization sequence to be written. See Appendix “A”.

The RCNTM[1,0] bits are used to set the time-out per iod of the recon timer. Programming this timer for shorter time

periods has the benefit of shortened network reconfiguration periods. The time periods shown in the table on the

following page are limited by a maximum number of nodes in the network. These time-out period values are for

5Mbps. For other data rates, s cale the time-o ut per iod time valu es acc ordi ngly; th e m axi mum n ode co unt rema ins the

same.

RCNTM1

RCNTM0 TIME-OUT

PERIOD MAX NODE

COUNT

0 0 420 mS Up to 255 nodes

0 1 105 mS Up to 64 nodes

1 0 52.5 mS Up to 32 nodes

1 1 26.25 mS* Up to 16 nodes*

Note*: The node ID value 255 must exist in the net work for the 26.25 mS time-out to be valid.

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Table 4 - Status Register

BIT BIT NAME SYMBOL DESCRIPTION

7 Receiver

Inhibited RI This bit, i f high, indica tes that the receive r i s not enabled because

either an "Enable Recei ve to Page fnn " command was n ever

issued, or a packet has been de po sited into the RAM buffe r page

fnn as specified by the last "Enab le Recei ve to Page fnn"

command. No message s will be re ceived unti l thi s co mmand is

issued, and once the message has been rece ived , the R I bit i s se t,

thereby inhibiting the receiver. The RI bit is cleared by issuing an

"Enable Recei ve to Page fnn " command . This bi t, w hen set, w ill

cause an interrupt if the corresponding bit of the Interrupt Mask

attempts to se nd a packe t to thi s sta tion , thi s sta tion w ill send a

NAK.

6,5 (Reserved) These bits are undefined.

4 Power On Reset POR This bit, if h igh, indicate s that the C OM20020I has been reset by

either a software reset, a hardware reset, or writing 00H to the

Node ID Register. The POR bit is cleared by the "Clear Flags"

command.

3 Test TEST This bit is intended fo r te st and diagnostic purpo ses. It is a logic

"0" under no rmal operating cond itions.

2 Reconfiguration RECON

This bit, if high, indi cate s th at the Line Idle Timer has ti med out

because the RX IN pin was idle for 41 μS. The RECON bit is

cleared during a "Cl ear Flags" command. Th is bi t, when se t, will

cause an interrupt if the corresponding bit in the IMR is also set.

The interrupt service routine should consist of examining the

MYRECON bit of the Diagno stic Status Reg ister to dete rmine

whether there are consecutive reconfigurations caused by this

node.

Transmitter

Message

Acknowledged

TMA This bit, if high, indicates that the packet transmitted as a result of

an "Enable Tran smit fro m Page fn n" co mmand has been

acknowledged . This bi t should only be con sidered valid after the

TA bit (bit 0) is set. Broadcast messages are never acknowledged.

The TMA bit is cleared by issuing the "Enable Transmit from Page

fnn" command.

0 Transmitter

Available TA This bit, if high, indica te s that the transmitter is available for

transmitting. This bi t is se t when the last byte o f sched uled pa cket

has been transmitted out, or upon execution of a "Disable

Transmitter" command. The TA bit is cleared by issuing the

"Enable Transmit from Page fnn" command after the node next

receives the token. This bit, when set, will cause an interrupt if the

corresponding bi t in the IMR i s a lso set.

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Ta ble 5 - Diagnostic Status Register

BIT BIT NAME SYMBOL DESCRIPTION

7 My

Reconfiguration MY-

RECON This bit, if high, indicates that a past reconfiguration was caused b y

this node. It is set when the Lost Token Timer times out, and

should be typically read following an interrupt caused by RECON.

Refer to the Imp roved Diagnosti cs se ction for fu rthe r detai l.

6 Duplicate ID DUPID This bit, if high, indicates that the value in the Node ID Register

matches both Destination ID characters of the token and a

response to this token has occurred. Trailing zero's are also

verified. A logic "1" on this bit indicates a duplicate Node ID, thus

the user should write a new value into the Node ID Register. This

bit is only useful for duplicate ID detection when the device is off

line, that is, when the transmitter is disabled. When the device is

on line this bit w ill be set every time t h e device gets the token. Th i s

bit is reset automatically upon reading the Diagnostic Status

detail.

5 Receive

Activity RCVACT T his bit, if high, indicates that data activity (logic "1") was detected

on the RXIN pin of the device. Refer to the Improved Diagnostics

section for further detail.

4 Token Seen TOKEN This bit, if high, indicates that a token has been seen on the

network, sent by a node o the r than this one. Refer to the Imp ro ved

Diagnostic section fo r furthe r detail .

3 Excessive NAK EXCNAK

This bit, if high, indicates that either 128 or 4 Negative

Acknowledgements have occurred in response to the Free Buffer

Enquiry. This bit is cleared upon the "POR Clear Flags" command.

Reading the Diagnostic Status Register does not clear this bit.

This bit, when set, will cause an interrupt if the corresponding bit in

the IMR is a lso set. Refer t o the Improve d Diagnostics sect ion for

further detail.

2 Tentative ID TENTID This bit, if high, indicates that a response to a token whose DID

matches the v alue in the Tent ative ID Register has occurred. The

second DID and the trailing zero's are not checked. Since each

node sees every token passed around the network, this feature

can be used with the device on-line in order to build and update a

network map . Re fer to the Improved Diagnostics section for further

detail.

1 New Next ID NEW

NXTID This bit, if high, indicates that the Next ID Register has been

updated and that a node has either joined or left the network.

Reading the Diagnostic Status Register does not clear this bit. This

bit, when set, will cause an interrupt if the corresponding bit in the

IMR is also set. The bit is cleared by reading the Next ID Register.

1,0 (Reserved) These bits are undefined.

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Table 6 - Command Register

DATA COMMAND DESCRIPTION

0000 0000 Clear

Transmit

Interrupt

This command is used only in the Command Chaining operation.

Please refer to the Command Chaining section for definition of

this command.

0000 0001 Disable

Transmitter This command will cancel any pending transmit command

(transmission that has not yet started) and will set the TA

(Transmitter Available) status bit to logic "1" when the

COM20020I nex t receives the to ken.

0000 0010 Disable

Receiver This command will cancel any pending receive command. If the

COM20020I is not yet receiving a packet, the RI (Receiver

Inhibited) bit will be set to logic "1" the next time the token is

received. If packet reception is already underway, reception will

run to its normal co nclusion.

b0fn n100 Enable

Receive to

Page fnn

This command allows the COM20020I to receive data packets

into RAM buffer page fnn and resets the RI status bit to logic "0".

The values placed in the "nn" bits indicate the page that the data

will be received into (page 0, 1, 2, or 3). If the value of "f" is a

logic "1", an offset of 256 bytes will be added to that page

specified in "nn", allowing a finer resolution of the buffer. Refer to

the Selecting RAM Page Size section for further detail. If the

value of "b" is logic "1", the device will also receive broadcasts

(transmissions to ID zero). The RI status bit is set to logic "1"

upon successful re cep tion o f a message .

00fn n011 Enable

Transmit from

Page fnn

This command prepares the COM20020I to begin a transmit

sequence from RAM buffer page fnn the next time it receives the

token. The valu es of the "nn" bit s indicat e whic h page to trans mit

from (0, 1, 2, or 3). If "f " is logic "1", an offset of 256 bytes is the

start of the page specified in "nn", allowing a finer resolution of the

buffer. Refer to the Selecting RAM Page Size section for further

detail. When this command is loaded, the TA and TMA bits are

reset to logic "0". The TA bit is set to logic "1" upon completion of

the transmit sequence. The TMA bit will have been set by this

time if the device has received an ACK from the destination node.

The ACK is strictly hardware level, sent by the receiving node

before its microcontroller is even aware of message reception.

Refer to Figure 1 for details of the transmit sequence and its

relation to the TA and TMA status bits.

0000 c101 Define

Configuration This command defines the maximum length of packets that may

be handled by the device. If "c" is a logic "1", the device handles

both long and short packets. If "c" is a logic "0", the device

handles only short packets.

000r p110 Clear Flags This command resets certain status bits of the COM20020I. A

logic "1" on "p" resets the POR status bit and the EXCNAK

Diagnostic stat us bit. A logic "1" on "r" res ets the RECON status

bit.

0000 1000 Clear

Receive

Interrupt

This command is used only in the Command Chaining operation.

Please refer to the Command Chaining section for definition of

this command.

0001 1000 Star t In te rna l

Operation This command restarts the stopped internal operation after

changing CKUP1 or CKUP0 bit.

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Table 7 - Address Pointer High Register

BIT BIT NAME SYMBOL DESCRIPTION

7 Read Data RDDATA This bit tells the COM20020I whether the following access

will be a read or write. A logic "1" prepares the device for a

read, a logic "0" prepares i t for a w rite.

6 Auto Increment AUTOINC This bit controls whether the address pointer will increment

automatically. A logic "1" on this bit allows automatic

increment of the po inter after each acces s, while a logic "0"

disables this function. Please refer to the Sequential

Access Memory section for further detail.

5-3 (Reserved) These bits are undefined.

2-0 Address 10-8 A10-A8 Thes e bits hold the upper three address bits which provide

addresses to RAM.

Table 8 - Address Pointer Low Register

BIT BIT NAME SYMBOL DESCRIPTION

7-0 Address 7-0 A7-A0

These bits hold the lower 8 address bits which provide the

addresses to RAM.

Table 9 - Sub Address Register

BIT BIT NAME SYMBOL DESCRIPTION

7-3 Reserved These bits are undefined.

2,1,0 Sub Address 2,1,0 SUBAD

2,1,0

These bits determine which register at address 07 may be

accessed. The combinations are as follows:

SUBAD2 SUBAD1 SUBAD0 Register

0 0 0 Tentative ID \ (Same

0 0 1 Node ID \ as in

0 1 0 Setup 1 / Config

0 1 1 Next ID / Register)

1 0 0 Setup 2

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

SUBAD1 and SUBAD0 are exactly the same as exist in the

Configuration Register. SUBAD2 is cleared automatically by

writing the Configuration Register.

Table 10 - Configuration Register

BIT BIT NAME SYMBOL DESCRIPTION

7 Reset RESET A software reset of the COM20020I is executed by writing a

logic "1" to this bit. A software reset does not reset the

microcontroller interface mode, nor does it affect the

Configuration Register. The only registers that the software

reset affect are th e Status R egister, the Next ID Register, and

the Diagnostic Status Register. This bit must be brought

back to logic "0" to release the reset.

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BIT BIT NAME SYMBOL DESCRIPTION

6 Command

Chaining Enable CCHEN

This bit, if high, enables the Command Chaining operation of

the device. Please refer to the Command Chaining section

for further details. A low level on this bit ensures software

compatibility with previous SMSC ARCNET devices.

5 Transmit Enable TXEN When low, this bit disables transmissions by keeping

nPULSE1, nPULSE2 if in non-Backplane Mode, and nTXEN

pin inactive. When high, it enables the above signals to be

activated during transmissions. This bit defaults low upon

reset. This bit is typically enabled once the Node ID is

determined, and never disabled during normal operation.

Please refer to the Improved Diagnostics section for details

on evaluating ne tw ork acti vity .

4,3 Extended

Timeout 1,2 ET1, ET2 These bits allow the network to operate over longer distances

than the default maximum 2 miles by controlling the

Response, Idle, and Recon figura tion Times. All nodes sho uld

be configured with the same timeout values for proper

network operation. For the COM20020I with a 20 MHz

crystal oscilla tor, the bit combination s fo llow :

ET2

ET1

Response

Time ( μS)

596.6

298.4

149.2

37.4

Idle Time

(μS)

656

328

164

Reconfig

Time

(mS)

840

420

Note: These values are for 5Mbps and RCNTMR[1,0]=00.

Reconfiguration time is changed by the RCNTMR1 and

RCNTMR0 bits.

2 Backplane BACK-

PLANE

A logic "1" on this bit puts the device into Backplane Mode

signaling which is used for Open Drain and Differential Driver

interfaces.

1,0 Sub Address 1,0 SUBAD

1,0

These bits determine which register at address 07 may be

accessed. The combinations are as follows:

SUBAD1 SUBAD0 Register

0 0 Tentative ID

0 1 Node ID

1 0 Setup 1

1 1 Next ID

See also the Sub Address Register.

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Table 11 - Setup 1 Reg is t er

BIT BIT NAME SYMBOL DESCRIPTION

7 Pulse1 Mode P1MODE This bit determines the type of PULSE1 output driver used

in Backplane Mode. When high, a push/pull output is used.

When low, an open drain output is used. The default is

open drain.

6 Four NACKS FOUR

NACKS This bit, when set, will cause the EXNACK bit in the

Diagnostic Status Register to set after four NACKs to Free

Buffer Enquiry are detected by the COM20020I. This bit,

when reset, will set the EXNACK bit after 128 NACKs to

Free Buffer Enqu iry. The defau lt is 128.

5 Reserved Do not set.

4 Receive All RCVALL This bit, when set, allows the COM20020I to receive all

valid data packets on the network, regardless of their

destination ID. This mode can be used to implement a

network monitor with the transmitter on- or off-line. Note

that ACKs are only sent for packets received with a

destination ID equal to the COM20020I's programmed node

ID. This feature can be used to put the COM20020I in a

'listen-only' mode, where the transmitter is disabled and the

COM20020I is not pa ssing to ken s. De faul ts low .

3,2,1 Cl ock Presca ler Bits

3,2,1 CKP3,2,1 These bits are used to determine the data rate of the

COM20020I. The following table is for a 20 MHz crystal:

(Clock Multiplier is bypassed)

CKP3

CKP2

CKP1

DIVISOR

128

SPEED

2.5Mbs

1.25Mbs

625Kbs

312.5Kbs

156.25Kbs

NOTE: The lowest data rate achievable by the COM20020I

is 156.25Kbs. Defaults to 000 or 2.5Mbs. For Clock

Multiplier output clock speed greater than 20 MHz, CKP3,

CKP2 and CKP1 must all be zero.

0 Slow Arbitration

Select SLOWARB This bit, when set, will divide the arbitration clock by 2.

Memory cycle times will increase when slow arbitration is

selected.

NOTE: For clock multiplier output clock speeds greater

than 40 MHz, SLOWARB must be set. Defaults to low.

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Table 12 - Setup 2 Reg is t er

BIT BIT NAME SYMBOL DESCRIPTION

7 Read Bus Timing

Select RBUSTMG This bit is used to Disable/Enable the High Speed CPU

Read function for High Speed CPU bus support.

RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable. It

does not influence write operation. High speed CPU Read

operation is only for non-multiplexed bus.

6 Reserved This bi t is undefined.

5,4 Clock Multiplier CKUP1, 0 Higher frequency clocks are generated from the 20 MHz

crystal through the selection of these two bits as shown.

This clock multiplier is powered-down on default. After

changing the CKUP1 and CKUP0 bits, the ARCNET core

operation is stopped and the internal PLL in the clock

multiplier is a wakened and it starts to gener ate the 40 MH z.

The lock out time of the internal PLL is 8μSec typically.

After 1 mS it is necessary to write command data '18H' to

command register for re-starting the ARCNET core

operation. EF bit must be ‘1’ if the data rate is over 5Mbps.

CAUTION: Changing the CKUP1 and CKUP0 bits must be

one time or less a fte r rele asing a ha rdware re set.

CKUP1 CKUP0 Clock Fr equency (Data Rate)

0 0 20 MHz (Up to 2.5Mbps) Default

0 1 40 MHz (Up to 5Mbps)

1 0 Reserved

1 1 Reserved

Note: After changing the CKUP1 or CKUP0 bits, it is

necessary to write a command data '18H' to the command

internal operation is stopped temporarily. The writing of the

command is to start the operation.

These initializing steps are shown below.

1) Hardware reset (Power ON)

2) Change CKUP[1, 0] bit

3) Wait 1mSec (wait until stable oscillation)

4) Write command '18H' (start internal operation)

5) Start initializing routine (Execute existing software)

3 Enhanced

Functions EF This bit is used to enable the new enhanced functions in the

COM20020I. EF = 0: Disable (Default), EF = 1: Enable. If

EF = 0, the timing and function is the same as in the

COM20020I, Revision B. See appendix “A”. EF bit must

be ‘1’ if the data rate is over 5Mbps.

EF bit should be ‘1’ for new design customers.

EF bit should be ‘0’ for replacement customers.

2 No Synchronous NOSYNC This bit is used to enable the SYNC command during

initialization. NOSYNC= 0, Enable (Default) The line must

be idle for the RAM initialization sequence to be written.

NOSYNC= 1, Disable:) The line d oes not have to be idle for

the RAM initialization sequence to be written. See appendix

“A”.

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BIT BIT NAME SYMBOL DESCRIPTION

1,0 Reconfiguration

Timer 1, 0 RCNTM1,0 These bit s are used to program the reconfiguration timer as a

function of maximum node count. These bits set the time out

period of the reconfiguration timer as shown below. The

time out periods shown are for 5 Mbps.

RCNTM1 RCNTM0 Time Out

Period Max Node Co unt

0 0 420 mS Up to 255 no des

0 1 105 mS Up to 64 node s

1 0 52.5 mS Up to 32 nodes

1 1 26.25 mS* Up to 16 node s

Note*: The node ID val ue 255 must exist in the network for

26.25 mS timeout to be valid.

Address P ointer Register

Low

2K x 8

RAM

D a ta R e gis ter

I/O A ddress 04H

I/O Address 03H

11-Bit Counter

Memory

Address Bus

Memory

D ata B us

D0-D7

High

I/O Address 02H

INTERNAL

FIGURE 8 – SEQUENTIAL ACCESS OPERATION

7.3 Internal Ram

The integration of the 2K x 8 RAM in the COM20020I represents significant real estate savings. The most obvious

benefit is the 48 pin package in which the device is now placed (a direct result of the integration of RAM). In addition,

the PC board is now free of the cumbersome external RAM, external latch, and multiplexed address/data bus and

control functions which were necessary to interface to the RAM. The integration of RAM represents significant cost

savings because it isolates the system designer from the changing costs of external RAM and it minimizes reliability

problems, assembly time and costs, and layout complexity.

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Sequential Acc ess Memory

The internal RAM is accessed via a pointer-based scheme. Rather than interfering with system memory, the internal

RAM is indi rectly accessed through the Address High an d Low Poin ter Registers. The data i s channe led to and fro m the

microcontroller via the 8-bi t data register. For exa mple: a packe t in the internal RAM buffer is read by the mi crocontroller

by writing the corresponding address into the Address Pointer High and Low Registers (offsets 02H and 03H). Note that

the High Register should be written first, followed by the Low Register, because writing to the Low Register loads the

address. At this point the device accesses that location and places the corresponding data into the data register. The

microcontroller then reads the data register (offset 04H) to obtain the data at the specified location. If the Auto

Increment bit i s set to logic "1", the device will aut omatically i ncrement the ad dress and place t he next byte of dat a into

the data register, again to be read by the microcontroller. This process is continued until the entire packet is read out of

RAM. Refer to Figure 8 for an illustration of the Sequential Access operation. When switching between reads and

writes, the pointer must first be written with the starting address. At least one cycle time should separate the pointer

being loaded and the fi rst read (see timi ng parame te rs).

Access Speed

The COM20020I is able to accommodate very fast access cycles to its registers and buffers. Arbitration to the buffer

does not slow down the cycle because the pointer based access method allows data to be prefetched from memory and

stored in a temporary register. Likewise, data to be written is stored in the temporary register and then written to

memory.

For systems which do not require quick access time, the arbitration clock may be slowed down by setting bit 0 of the

Setup1 Register equal to logic "1". Since the Slow Arbitration feature divides the input clock by two, the duty cycle of the

input clock may be relaxed.

SOFTWARE INTERFACE

The microcontroller interfaces to the COM20020I via software by accessing the various registers. These actions are

described in the Internal Registers section. The software flow for accessing the data buffer is based on the Sequential

Access scheme . The basi c seq uen ce is as follows:

 Disable Interrupts

 Write to Pointer Register High (spe cify ing Auto-In crement mode )

 Write to Pointer Register Low (this load s the add re ss)

 Enable Interrupts

 Read or Write the Data Reg ister (repeat as many time s as nece ssary to empty or fi ll the buffe r)

 The pointer may now be read to determine how many transfers w ere co mpleted .

The software flow for controlling the Configuration, Node ID, Tentative ID, and Next ID registers is generally limited to

the initializa tion sequen ce an d the ma inte nan ce of the netw ork map .

Additionally, it is necessary to understand the details of how the other Internal Registers are used in the transmit and

receive sequences and to know how the internal RAM buffer is properly set up. The sequence of events that tie these

actions togeth er is discusse d as follow s.

Selecting RAM Page Size

During normal operation, the 2K x 8 of RAM is divided into four pages of 512 bytes each. The page to be used is

specified in the "Enable Transmit (Receive) from (to) Page fnn" command, where "nn" specifies page 0, 1, 2, or 3.

This allows the user to have constant control over the allocation of RAM.

When the Offset bit "f" (bit 5 of the "Enable Transmit (Receive) from (to) Page fnn" command word) is set to logic "1", an

offset of 256 bytes is added to the page specified. For example: to transmit from the second half of page 0, the

command "Enable Transmit from Page fnn" (fnn=100 in this case) is issued by writing 0010 0011 to the Command

Register. This allows a finer resolution of the buffer pages without affecting software compatibility. This scheme is useful

for applications which frequently use packet sizes of 256 bytes or less, especially for microcontroller systems with limited

memory capacity. The remaining portions of the buffer pages which are not allocated for current transmit or receive

packets may b e used as temporary sto rage for previous ne twork data, packets to be sent later, or as extra memory for

the system, which may be indire ctly accessed.

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If the device is configured to handle both long and short packets (see "Define Configuration" command), then receive

pages should always be 512 bytes long because the user never knows what the length of the receive packet will be. In

this case, the transmit pages may be made 256 byt es long, leaving at least 512 b ytes free at any given time. Even if the

Command Chaining operation is being used, 512 bytes is still guaranteed to be free because Command Chaining only

requires two pages for transmit and two for receive (in this case, two 256 byte pages for transmit and two 512 byte

pages for receive, leaving 512 bytes free). Please note that it is the responsibility of software to reserve 512 bytes for

each receive page if the device is configured to handle long packets. The COM20020I does not check page boundaries

during reception. If the device is configured to handle only short packets, then both transmit and receive pages may be

allocate d as 256 bytes long, freeing at lea s t 1KByte at any given time .

Even if the Command Chaining operation is being used, 1KByte is still guaranteed to be free because Command

Chaining only requires two pages for transmit and two for receive (in this case, a total of four 256 byte pages, leaving 1K

free).

The general rule which may be applied to determine where in R A M a page begin s i s as follows:

Address = (nn x 512) + (f x 256).

Transmit Sequence

During a transmit sequence, the microcontroller selects a 256 or 512 byte segment of the RAM buffer and writes into it.

The appro pria te buffer size is specified in the " De fi ne Configuration" command. When long packets a re enabled, the

COM20020I interprets the packet as either a long or sho r t packe t, depending on whether the buffer add re ss 2 contains a

zero or non-zero value. The format of the buffer is shown in Figure 9. Address 0 contains the Source Identifier (SID);

Address 1 contains the Destination Identifier (DID); Address 2 (COUNT) contains, for short packets, the value 256-N,

where N represents the number of information byte s in the message , or for long packe ts, the val ue 0, indica ti ng tha t i t is

indeed a long packet. In the latter case, Address 3 (COUNT) would contain the value 512-N, where N represents the

number of information bytes in the message.

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FIGURE 9 – RAM BUFFER PACKET CONFIGURATION

The SID in Address 0 is used by the receivi ng node to reply to the transmitting no de. The COM20020I puts the local

ID in this location, therefore it is not necessar y to write into this locatio n. Please note that a short pack et may contain

between 1 and 253 data b ytes, while a long packet may co ntain between 257 and 508 data bytes. A minimum valu e

of 257 exists on a long packet so that the COUNT is expressible in eight bits. This leaves three exception packet

lengths which do not fit into either a short or long packet; packet lengths of 254, 255, or 256 bytes. If packets of

these lengths must be sent, the user must add dummy bytes to the packet in order to make the

packet fit into a long packet.

Once the packet is written into the buffer, the microcontroller awaits a logic "1" on the TA bit, indicating that a previous

transmit command has concluded and another may be issued. Each time the message is loaded and a transmit

command issued, it will take a variable amount of time before the message is transmitted, depending on the traffic on

the network a nd t he l oc at ion of the token at t h e t im e t he tr an sm it co mm an d was iss ue d. T he c o nc lusi on of t he Transmit

Command will generate an interrupt if the Inte r rupt Mask allows it. I f the device is configured for the Command Chai ning

operation, please see the Command Chaining section for further detail on the transmit sequence. Once the TA bit

becomes a logic "1", the microcontroller may issue the "Enable Transmit from Page fnn" command, which resets the TA

and TMA bits to logic "0". If the message is not a BROADCAST, the COM20020I automatically sends a FREE BUFFER

ENQUIRY to the destination node in order to send the message. At this point, one of four possibilities may occur.

SID

DID

COUNT = 256- N

NO T USED

DATA BYTE 1

DATA BYTE 2

DATA BYTE N-1

DATA BYTE N

NO T USED

SID

DID

COUNT = 512-N

NO T USED

DATA BYTE 1

DATA BYTE 2

DATA BYTE N-1

DATA BYTE N

SHORT PACKET

FORMAT LONG PAC KET

FORMAT

DDRESS ADDRESS

COUNT

255

511

N = D ATA PACK ET LENG TH

SID = SOURCE ID

DID = DESTINATION ID

(DI D = 0 FOR BROADC ASTS )

COUNT

511

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The first possibility is if a free buffer is available at the destination node, in which case it responds with an

ACKnowledgement. At this point, the COM20020I fetches the data from the Transmit Buffer and performs the transmit

sequence. If a successful transmit sequence is completed, the TMA bit and the TA bit are set to logic "1". If the packet

was not transmitted successfully, TMA will not be set. A successful transmission occurs when the receiving node

responds to the packet with an ACK. An unsuccessful transmission occurs when the receiving node does not respond

to the packet.

The second possibility is if the destination node responds to the Free Buffer Enquiry with a Negative AcKnowledgement.

A NAK occurs when the RI bit of the destination node is a logic "1". In this case, the token is passed on from the

transmitting node to the next node. The next time the transmitter receives the token, it will again transmit a FREE

BUFFER ENQUIRY. If a NAK is again received, the token is again passed onto the next node. The Excessive NAK bit

of the Diagnostic Status Register is used to prevent an endless sending of FBE's and NAK's. If no limit of FBE-NAK

sequences existed, the transmitting node would continue issuing a Free Buffer Enquiry, even though it would

continuously receive a NAK as a response. The EXCNAK bit generates an interrupt (if enabled) in order to tell the

microcontroller to disable the transmitter via the "Disable Transmitter" command. This causes the transmission to be

abandoned and the TA bit to be set to a logic "1" when the node next receives the token, while the TMA bit remains at a

logic "0". Please refe r to the Imp roved Diag no stics section fo r furthe r detai l on the EXCNAK bi t.

The third possibility which may occur after a FREE BUFFER ENQUIRY is issued is if the destination node does not

respond at all. In this case, the TA bit is set to a logic "1", while the TMA bit remains at a logic "0". The user should

determine whether th e node should try to reissue the tran smit command .

The fourth possi bility is if a non-traditional res ponse is received (some patt ern other than ACK or NAK, such as noise) .

In this case, the token is not passed onto the next node, which causes the Lost Token Timer of the next node to time

out, thus generating a network reconfiguration.

The "Disable Transmitter" command may be used to cancel any pending transmit command when the COM20020I next

receives the token. Normally, in an active network, this command will set the TA status bit to a logic "1" when the token

is received. If the "Disable Transmitter" command does not cause the TA bit to be set in the time it takes the token t o

make a round trip through the network, one of three situations exists. Either the node is disconnected from the network,

or there are no other nodes on the network, or the external receive circuitry has failed. These situations can be

determined by either using the improved diagnostic features of the COM20020I or using another software timeout which

is greater than the worst case time for a round trip token pass, which occurs when all nodes transmit a maximum length

message.

Receive Sequence

A receive sequence begins with the RI status bit becoming a logic "1", which indicates that a previous reception has

concluded. The microcontroller will be interrupted if the corresponding bit in the Interrupt Mask Register is set to logic

"1". Otherwise, the microcontroller must periodically check the Status Register. Once the microcontroller is aler ted to the

fact that the previous reception has concluded, it may issue the "Enable Receive to Page fnn" command, which resets

the RI bit to logic "0" and selects a new page in the RAM buffer. Again, the appropriate buffer size is specified in the

"Define Configuration" command. Typically, the page which just received the data packet will be read by the

microcontro ller at this point. Onc e the "Enable R eceive to Page f nn" command is issued, the mi crocontrol ler attends t o

other duties. There is no way of knowing how long the new reception will take, since another node may transmit a

packet at any time. When another node does transmit a packet to this node, and if the " D ef in e Co nf ig ur at i on" c omm a nd

has enabled the reception of long packets, the COM20020I interprets the packet as either a long or short packet,

depending on whether the content of the buffer location 2 is zero or non-zero. The format of the buffer is shown in

Figure 10. Address 0 contains the Source Identifier (SID), Address 1 contains the Destination Identifier (DID), and

Address 2 contains, for short packets, the value 256-N, where N represents the message length, or for long packets, the

value 0, indicating that it is indeed a long packet. In the latter case, Address 3 contains the value 512-N, where N

represents the message length. Note that on reception, the COM20020I deposits packets into the RAM buffer in the

same format that the transmitting node arranges them, which allows for a message to be received and then

retransmitted without rearranging any bytes in the RAM buffer other than the SID and DID. Once the packet is received

and stored correctly in the selected buffer, the COM20020I sets the RI bit to logic "1" to signal the microcontroller that

the reception is complete.

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FIGURE 10 - COMMAND CHAINING STA TUS REGISTER QUEU E

7.4 Command Chaining

The Command Chaining operation allows consecutive transmissions and receptions to occur without host

microcontroller in tervention.

Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status bits, are

pipelined.

In order for the COM20020I to be compatible with previous SMSC ARCNET device drivers, the device defaults to the

non-chaining mode. In order to take advantage of the Command Chaining operation, the Command Chaining Mode

must be enabled via a logic "1" on bit 6 o f the Configura tion Regi ster.

In Command Chaining, the Status Register appe ars as in Figure 10.

The following is a list of Command Chaining guidelines for the software programmer. Further detail can be found in the

Transmit Command Chaining and Receive Command Chaining sections.

 The device is designed such tha t the in te rrup t service routine la ten cy does not a ffect perfo rmance .

 Up to two outstanding transmissions and two outstanding receptions can be pending at any given time. The

commands may be g iven i n any order.

 Up to two outstanding transmit inte rrupts and two outstanding receive interrupts are stored by the device, along with

their respective status bits.

 The Interrupt Mask bits act on TTA (Rising Transition on Transmitter Available) for transmit operations and TRI

(Rising Transition of Receiver Inhibited) for receive operations. TTA is set upon completion of a packet

transmission only. TRI is set upon completion of a packet reception only. Typically there is no need to mask the

TTA and TRI bits after clearing the interrupt.

 The traditional TA and RI bits are still available to reflect the present status of the device.

Transmit Command Chaining

When the processor issues the first "Enable Transmit to Page fnn" command, the COM20020I responds in the usual

manner by resetting the TA and TMA bits to prepare for the transmission from the specified page. The TA bit can be

used to see if there is currently a transmission pending, but the TA bit is really meant to be used in the non-chaining

mode only. The TTA bits provide the relevant information for the device in the Command Chaining mode.

In the Command Chaining Mode, at any time after the first command is issued, the processor can issue a second

"Enable Transmit from Page fnn" command. The COM20020I stores the fact that the second transmit command was

issued, along with the page number.

After the first transmission is completed, the COM20020I updates the Status Register by setting the TTA bit, which

generates an interrupt. The interrupt service routine should read the Status Register. At this point, the TTA bit will be

found to be a logic "1" and the TMA (Transmit Message Acknowledge) bit will tell the processor whether the

transmission was succes sful. After reading the Status Register, the "Clear Transmit Interrupt" command is issued, thus

resetting the TTA bit and clearing the in te rrupt. Note that only the "Clear Transmit Inte rrup t" command will clear the TTA

bit and the int errupt. It is not necessary, however, to clear the bit or the interrupt right away because the status of the

transmit oper ation is dou ble buffered i n order to retai n the results of the first transmission for analysis by the processor.

TRI RI TA POR TEST RECON

TMA TTA

TRI

MSB LSB

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This information will remain in the Status Register until the "Clear Transmit Interrupt" command is issued. Note that the

interrupt will remain active until the command is issued, and the second interrupt will not occur until the first interrupt is

acknowledged. The COM20020I guarantees a minimum of 200nS (at EF=1) interrupt inactive time interval between

interrupts. The TMA bit is also double buffered to reflect whether the appropriate transmission was a success. The

TMA bit should only be considered valid after the corresponding TTA bit has been set to a logic "1". The TMA bit never

causes an interrupt.

When the token is received again, the second transmission will be automatically initiated after the first is completed by

using the stored "Enable Transmit from Page fnn" command. The operation is as if a new "Enable Transmit from Page

fnn" command has just been issued. After the first Transmit status bits are cleared, the Status Register will again be

updated with the results of the second transmission and a second interrupt resulting from the second transmission will

occur. The COM20020I guarantees a minimum of 200ns (at EF=1) interrupt inactive time interval before the following

edge.

The Transmitte r Available (T A) bit of the I nterrupt M ask Register no w masks only the TTA bit of the Status Register, not

the TA bit as in the non-chaining mode. Since the TTA bit is only set upon transmission of a packet (not by RESET),

and sinc e the T TA bit ma y easil y be r eset b y issu ing a "Cle ar Tr ansmit I nterru pt" comm and, th ere is no ne ed to use t he

TA bit of the Interrupt Mask Register to mask interrupts generated by the TTA bit of the Status Register.

In Command Chaining mode, the "Disable Transmitter" command will cancel the oldest transmission. This permits

canceling a packet destined for a node not ready to receive. If both packets should be canceled, two "Disable

Transmitte r" commands shou ld be issued.

Receive Comma nd C hai ning

Like the Transmit Command Chaining operation, the processor can issue two consecutive "Enable Receive from Page

fnn" commands.

After the first packet is received into the first specified page, the TRI bit of the Status Register will be set to logic "1",

causing an interrupt. Again, the interrupt need not be serviced immediately. Typically, the interrupt service routine will

read the Status Register. At this point, the RI bit will be found to be a logic "1". After reading the Status Register, the

"Clear Recei ve Interrupt" command should be issued, thus rese tting the TRI bit and clea ring the interrupt. Note that only

the "Clear Receive Interrupt" command will clear the TRI bit and the interrupt. It is not necessary, however, to clear the

bit or the interr upt right a way because the st atus of th e receiv e operatio n is double b uffered i n order to ret ain the res ults

of the first reception for analysis by the processor, therefore the information will remain in the Status Register until the

"Clear Re ceive Inte r rupt" comm and is issued. Note that the interrupt will remai n active until the "Clear Rece iv e Interrupt"

command is issued, and the second interrupt will be stored until the first interrupt is acknowledged. A minimum of

200nS (at EF=1) i n terrupt inacti ve time inte rval between in terrupts is guaranteed.

The second reception will occur as soon as a second packet is sent to the node, as long as the second "Enable Receive

to Page fnn" command was issued. The operation is as if a new "Enable Receive to Page fnn" command has just been

issued. After the first Receive stat us bits are cleared, the Status Register will again be updated with the results of the

second recep tion and a se co nd in te rrupt re sultin g fro m the second rece p tion will occu r.

In the COM20020I, the Receive Inhibit (RI) bit of the Interrupt Mask Register now masks only the TRI bit of the Status

RESET), and since the TRI bit may easily be reset by issuing a "Clear Receive Interrupt" command, there is no need to

use the RI bit of the Interrupt Mask Register to mask interrupts generated by the TRI bit of the Status Register. In

Command Chaining mode, the "Disable Receiver" command will cancel the oldest reception, unless the reception has

already begun . If both recep tions should be can ce led, two "Di sable Receiver" co mmands should b e issued.

RESET DETAILS

Internal Reset Logic

The COM20020I includes special reset circuitry to guarantee smooth operation during reset. Special care is taken to

assure pro per operation in a var iety of systems and mo des of operatio n. The COM20020I contains digit al filter circu itry

and a Schmitt Trigger on th e nRESET signa l to re ject gli tches in order to ensure fau lt-fre e opera tion.

The COM20020I supports two reset options; software and hardware reset. A software reset is generated when a logic

"1" is written t o bit 7 of the Configur ation Register. T he device remains in reset as long as this bit is set. The software

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reset does not affect the microcontroller interface modes determined after hardware reset, nor does it affect the contents

of the Address Pointer Registers, the Configuration Register, or the Setup1 Register. A hardware reset occurs when a

low signal is asserted on the nRESET input. The minimum reset pulse width is 5TXTL. This pulse width is used by the

internal digital filter, which filters short glitches to allow on ly valid re se ts to occu r.

Upon reset, the transmi t te r portion of the device is disabled and the inte rnal registers assume those states outlined in the

Internal Registers section. After the nRESET signal is removed the user may write to the internal registers. Since writing

a non-zero value to the Node ID Register wakes up the COM20020I core, the Setup1 Register should be written before

the Node ID Register. Once the Node ID Register is written to, the COM20020I reads the value and executes two write

cycles to the RAM buffer. Address 0 is written with the data D1H and address 1 is written with the Node ID. The data

pattern D1H w as chosen arbitra rily , and is meant to provide assurance of proper micro sequ encer operation.

7.5 Initialization Sequence

Bus Determination

Writing to and reading from an odd address location from the COM20020I's address space causes the COM20020I to

determine the appropriate bus interface. When the COM20020I is powered on the internal registers may be written to.

Since writing a non-zero value to the Node ID Register wakes up the core, the Setup1 Register should be written to

before the Node ID Register. Until a non-zero value is placed into the NID Register, no microcode is executed, no

tokens are passed by this no de , and no reconfi g u ra tio ns a re gene ra ted by this node. Once a no n-zero value is placed in

the register, the core wakes up, but the node will not attempt to join the network until the TX Enable bit of the

Configuration Register is set.

Before setting the TX Enable bit, the software may make some determinations. The software may first observe the

Receive Activity and the Token Seen bits of the Diagnostic Status Register to verify the health of the receiver and the

network.

Next, the uniqueness of the Node ID value placed in the Node ID Register is determined. The TX Enable bit should still

be a logic "0" until it is ensured that the Node ID is unique. If this node ID already exists, the Duplicate ID bit of the

Diagnostic Stat us Regist er is set aft er a maximum of 420mS (or 84 0mS if the ET 1 and ET2 bits are oth er than 1,1). T o

determine if another node on the network already has this ID, the COM20020I compares the value in the Node ID

Duplicate ID bit, and repeat the process until a unique Node ID is found. At this point, the TX Enable bit may be set to

allow the n ode to join t he net work. Once the node joins t he net work, a recon figurat ion occur s, as usual, th us setting t he

MYRECON bit of th e Di agnostic Status Register .

The Tentative ID Register may be used to build a network map of all the nodes on the network, even once the

COM20020I has joined the network. Once a value is placed in the Tentative ID Register, the COM20020I looks for a

response to a token whose DID matches the Tentative ID Register. The software can record this information and

continue placing Tentative ID values into the register to continue building the network map. A complete network map is

only valid until nodes are added to or deleted from the network. Note that a node cannot de tect the e xi sten ce of t he nex t

logical node on the network when using the Tentative ID. To determine the next logical node, the software should read

the Next ID Register.

7.6 Improved Diagnostics

The COM20020I allows the user to better manage the operation of the network through the use of the internal

Diagnostic Status Registe r.

A high lev el on the My Rec onfigurat ion (MYRECON) bit indicates th at the Token R eception T imer of this no de expired,

causing a reconfiguration by this node. After the Reconfiguration (RECON) bit of the Status Register interrupts the

microcontroller, the interrupt service routine will typically read the MYRECON bit of the Diagnostic Status Register.

Reading the Diagnostic Status Register resets the MYRECON bit. Successive occurrences of a logic "1" on the

MYRECON bit indicates that a problem exists with this node. At that point, the transmitter should be disabled so that the

entire netw ork is not held down w hile the node is being evaluate d .

The Duplicate ID (DUPID) bit is used before the node joins the network to ensure that another node with the same ID

does not exist on the network. Once it is determined that the ID in the Node ID Register is unique, the software should

write a logic "1" to bit 5 of the Configuration Register to enable the basic transmit function. This allows the node to join

the network.

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The Receive Activi ty (RCVACT) bi t of the Diagnostic Status Register w ill be set to a logic "1" whene ver activity (l ogic "1")

is detected on the RXIN pin.

The Token Seen (TOKEN) bit is set to a logic "1" whenever any token has been seen on the network (except those

tokens transmi tted by this node).

The RCVACT and TOKEN bits may help the user to troubleshoot the network or the node. If unusual events are

occurring on the network, the user may find it valuable to use the TXEN bit of the Configuration Register to qualify

events. Different combinations of the RCVACT, TOKEN, and TXEN bits, as shown indicate different situations:

Normal Results:

RCVACT=1, TOKEN=1, T XEN=0: The node is not part of the network. The network is operating properly without this

node.

RCVACT=1, TOKEN=1, TXEN=1: The node sees receive activity and sees the token. The basic transmit function is

enabled. Ne twork and node are operating properly .

MYRECON=0, DUPID=0, RCVACT=1, TXEN=0, TOK E N =1 : Single node network.

Abnormal Results:

RCVACT=1, TOKEN=0, TXEN=X: The node sees receive activity, but does not see the token. Either no other nodes

exist on the network, some type of data corruption exists, the media driver is malfunctioning, the topology is set up

incorrectly, there is noise on the network, or a reconfiguration is occurring.

RCVACT=0, TOKEN=0, TXEN=1: No receive activity is seen and the basic transmit function is enabled. The

transmitter and/or receiver are not functioning properly.

RCVACT=0, TOKEN= 0, TXEN=0: No receive activity and basic transmit function disabled. This node is not connected

to the netw ork.

The Excessive NAK (EXCNAK) bit is used to replace a timeout function traditionally implemented in software. This

function is necessary to limit the number of times a sender issues a FBE to a node with no available buffer. When the

destination node replies to 128 FBEs with 128 NAKs or 4 FBEs with 4 NAKs, the EXCNAK bit of the sender is set,

generating an interrupt. At this point the software may abandon the transmission via the "Disable Transmitter"

command. This sets the TA bit to logic "1" when the node next receives the token, to allow a different transmission to

occur. The timeout value for the EXNACK bit (128 or 4) is determined by the FOUR-NAKS bit on the Setup1 Register.

The user may choose to wait for more NAK's before disabling the transmitter by taking advantage of the wraparound

counter of the EXCNAK bit. When the EXCNAK bit goes high, indicating 128 or 4 NAKs, the "POR Clear Flags"

command maybe issued to reset the bit so that it will go high again after another count of 128 or 4. The software may

count the number of times the EXCNAK bit goes high, and once the final count is reached, the "Disable Transmitter"

command may be i ssued .

The New Next ID bi t permit s the so ftw are to dete ct the withd raw al or addi tion of node s to the ne twork.

The Tentative ID bit allows the user to build a network map of those nodes existing on the network. This feature is

useful because it minimizes the need for human intervention. When a value placed in the Tentative ID Register matches

the Node ID of another node on the network, the TENTID bit is set, telling the software that this NODE ID already exists

on the network. The software should periodically place values in the Tentative ID Register and monitor the New Next ID

bit to main tain an upda ted netw ork map.

OSCILLATOR

The COM20020I contains circuitry which, in conjunction with an external parallel resonant crystal or TTL clock, forms an

oscillator.

If an external crystal is used, two capacitors are needed (one from each leg of the crystal to ground). No external

resistor is required, since the COM20020I contains an internal resistor. The crystal must have an accuracy of 0.020% or

better. The oscilla tion freq uency range is fro m 10 MHz to 20 MHz.

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The crystal must have an accuracy of 0.010% or better when the internal clock multiplier is turned on. The oscillation

frequency must be 20 MHz when the internal clo ck multiplie r is turned on.

The XTAL2 side of the crystal may be loaded with a single 74HC-type buffer in order to generate a clock for other

devices.

The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a 390Ω pull-up

resistor is required on XTAL1, while XTAL2 shou ld be left unconnected.

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8.0 OPERATIONAL DESCRIPTION

8.1 Maximum Guaranteed Ratings*

Operating Temperature Range........................................................................................................................-40oC to +85oC

Storage Temperature Range.........................................................................................................................-55oC to +150oC

Lead Temperature (soldering, 10 seconds) ................................................................................................................+325 oC

Positive Voltage on any pin, with respect to ground ...............................................................................................VDD+0.3 V

Negative Voltage on any pin, with respect to ground......................................................................................................-0.3V

Maximum VDD ....................................................................................................................................................................+7V

*Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other condition above those indicated in the operational sections of this

specification is not implied.

Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum

Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their

outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on

the DC output. If this p ossibility exis ts it is suggested that a clamp circuit be used.

8.2 Dc Electrical Characteristics

VDD=3.3V±5%

TA=-40oC to +85oC

PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT

Low Inpu t Vol tage 1

(All inputs except A2,

XTAL1, nRESET, nRD,

nWR, and RXIN )

High Inpu t Voltage 1

(All inputs except A2,

XTAL1, nRESET, nRD,

nWR, and RXIN )

VIL1

VIH1

2.0

0.6 V

Low Inpu t Vol tage 2

(XTAL1)

High Inpu t Voltage 2

(XTAL 1)

VIL2

VIH2

2.4

1.0 V

TTL Clock Input

Low to High Threshol d

Input Voltage

(A2, nRESET, nRD, nWR,

and RXIN)

High to Low Threshol d

Input Voltage

(A2, nRESET, nRD, nWR,

and RXIN)

VILH

VIHL

1.8

1.2

Schmitt Trigger,

All Values at VDD =

3.3V

Low Output Voltage 1

(nPULSE1 in Push/Pull

Mode, nPULSE2,

NTXEN)

High Outpu t Vol tage 1

(nPULSE1 in Push/Pull

Mode, nPULSE2,

nTXEN)

VOL1

VOH1

2.4

0.4

ISINK=2mA

ISOURCE=-1mA

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT

Low Output Voltage 2

(D0-D7)

High Outpu t Vol tage 2

(D0-D7)

VOL2

VOH2

2.4

0.4 V

ISINK=8mA

ISOURCE=-6mA

Low Output Voltage 3

(nINTR)

High Outpu t Vol tage 3

(nINTR)

VOL3

VOH3

2.4

0.8 V

ISINK=12mA

ISOURCE=-5mA

Low Output Voltage 4

(nPULSE1 in Open-Drain

Mode)

VOL4 0.5 V ISINK=24mA

Open Drain Driver

Dynamic VDD Supply

Current IDD

35 mA

5 Mbps

All Outpu ts Open

Input Pull-up Current

(nPULSE1 in Open-Drain

Mode, A1, AD0-AD2,

D3-D7)

Input Leakage Current

(All inputs except A1,

AD0-AD2, D3-D7,

XTAL1, XTAL2

80 200

±10

µA

VIN=0 .0V

VSS < VIN < VDD

CAPACITANCE (TA = 2 5°C; fC = 1MHz; VDD = 0V)

Output and I/O pins capacitive load specified as follows:

PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT

Input Capaci tan ce CIN 5.0 pF

Output Ca pacitance 1

(All outputs except

XTAL2, nPULSE1 in

Push/Pull Mode )

Output Ca pacitance 2

(nPULSE1, in BackPlane

Mode Only - Open

Drain)

COUT1

COUT2

400

Maximum

Capaciti ve Load

which can be

supported by ea ch

output.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 47 Revision 12-06-06

DATASHEET

0.4V

AC Measurements are taken at the following points:

Inputs:

2.4V

1.4V 50%

50%

0.4V

2.4V

1.4V

0.8V

Outputs:

2.0V

0.8V

2.0V

Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin.

Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0".

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

9.0 TIMING DIAGRAMS

FIGURE 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE

D0-AD2, VALID

nCS t1

ALE

VALID DATA

t2,

D3-D7

DIR t9 t10

nDS

t11

t12

t13 t14

Note 2

Parameter min max units

t10

t11

t12

t13

t14

Address Setup to ALE Low

Address Hold from ALE Low

nCS Setup to ALE Low

nCS Hold from ALE Low

ALE Low to nDS Low

nDS Low to Valid Data

nDS High to Data High Impedance

Cycle Time (nDS Low to Next Time Low)

DIR Setup to nDS Active

DIR Hold from nDS Inactive

ALE High Width

ALE Low Width

nDS Low Width

nDS High Width

4TARB*

MUST BE: RBUSTMG bit = 0

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access

to Data Register requires a minimum of 5TARB from the trailing edge of nDS to

the leading edge of the next nDS.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 49 Revision 12-06-06

DATASHEET

FIGURE 12 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE

D0-AD2, VALID

nCS

ALE

VALID DA TA

t2,

D3-D7

nRD t9

t10

nWR t13 t11 t12

Note 3

Note 2

ALE High Width

ALE Low Width

nRD Low Width

nRD High Width

nWR to nRD Low

Parameter min max units

t10

t11

t12

t13

Address Setup to ALE Lo w

Address Hold from ALE Lo w

nCS Setup to ALE Low

nCS Hold from ALE Low

ALE Low to nRD Low

nRD L ow t o Valid Data

nRD High to Data High Impedance

Cycle Time (nRD Low to Next Time Low)

4TARB*

MUST BE: RBUSTMG bit = 0

The Microcontroller typically accesses the COM20020 on ev ery other cycle.

Therefore , the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLO W ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

Note 2: Read cycle for Address Pointer Lo w/High Registers occurring after a read from

Data Register requires a minimum of 5TARB from the trailing edge of nRD to the

leading edge of the next nRD.

Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to

Data Register requires a minimum of 5TARB from the trailing edge of nWR to the

leading edge of nRD.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

FIGURE 13 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE

D0-AD2, VALID

nCS t1

ALE

VALID DATA

t2,

D3-D7

DIR

t9 t10

Note 2

t8**

nDS

t11

t12

t13 t14

Parameter min max units

t10

t11

t12

t13

t14

4TARB*

Address Setup to ALE Low

Address Hold from ALE Low

nCS Setup to ALE Low

nCS Hold from ALE Low

ALE Low to nDS Low

Valid Data Setup to nDS High

Data Hold from nDS High

DIR Setup to nDS Active

DIR Hold from nDS Inactive

ALE High Width

ALE Low Width

nDS Low Width

nDS High Width

Cycle Time (nDS to Next )**

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

Any cycle occurring after a write to Address Pointer Low Register requires a

minimum of 4TARB from the trailing edge of nDS to the leading edge of the

next nDS.

Note 2:

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLO W ARB = 0

TARB is twice Topr if SLO W ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

Write cycle for Address P o in ter Lo w Register occurring after an access to

Data Register requires a minimum of 5TARB from the trail ing edge of nDS to

the leading edge of the next nDS.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 51 Revision 12-06-06

DATASHEET

FIGURE 14 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE

D0-AD2, VALID

nCS t1

ALE

VALID DATA

t2,

D3-D7

Note 2

t8**

nWR

t10

nRD t13 t11 t12 t8

Note 3

Parameter min max units

t10

t11

t12

t13

4TARB*

Address Set up to AL E Low

Address Hold from ALE Low

nCS Setup to ALE Low

nCS Hold from ALE Low

ALE Low to nDS Low

Valid Data Setup to nDS High

Data Hold from nDS High 30

ALE High Width

ALE Low Width

nWR Low Width

nWR High Width

nRD to nWR Low

Cycle Time (nWR to Next )**

TARB is the Arbitration Clock Period

TARB is identi cal to Topr if SL OW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, th e cycl e time speci f i ed in the mi cr o contro ller ' s datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

Any cycle occurring after a write to Address Pointer Low Register requires a

minimum of 4TARB from the trailing edge of nWR to the leading edge of the

next nWR.

Note 2:

Write cycle for Address Pointer Low Register occurring after a write to Data

leading edge of the ne xt nWR.

Note 3: Write cycle for Address P ointer Low Register occurring after a read from Data

leading edge of nWR.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

FIGURE 15 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE

0-A2

VALID DATA

VALID

D0-D7

nCS

t3 t5

nRD

nWR

t10 t8 t9

Note 3

Note 2

Parameter min max units

t10

5**

Address Setup to nRD Active

Address Hold from nRD Inactive

nCS Setup to nRD Active

nCS Hold from nRD Inactive

Cycle Time (nRD Low to Next Time Low)

nRD Low to Valid Data

nRD High to Data High Impedance

4TARB*

40**

CASE 1: RBUSTMG bit = 0

nRD Low Width

nRD High Width

nWR to nRD Low

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLO W ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

nCS may become active after control becomes act iv e, but th e access ti me (t6)

will now be 45nS measured from the leading edge of nCS.

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cyc le time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

Note 2: Read cycle for Address Pointer Low/ H i g h Registers occurring after a read f rom

Data Register requires a minimum of 5TARB from the tr ailing edge of nRD to the

leading edge of the next nRD.

Note 3: Read cycle for Address Pointer L ow/High Registers occurrin g afte r a w rit e to

Data Register requires a minimum of 5TARB from the tr ailing ed ge of nWR to the

leading edge of nRD .

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 53 Revision 12-06-06

DATASHEET

FIGURE 16 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE

0-A2

VALID DA TA

VALID

D0-D7

nCS

t3 t5

nRD

nWR

t10 t8 t9

Note 3

Note 2

Parameter min max units

t10

-5

Address Setup to nRD Active

Addre ss Ho ld from nRD Inactiv e

nCS Setup to nRD Active

nCS Hold from nRD Inactive

Cycle Time (n RD L ow to Next Time Low)

nRD Low to Valid Data

nRD High t o D a ta High Imped ance

4TARB*+30

100

60**

nRD Low Width

nRD High Width

nWR to nRD Low

CASE 2: RBUSTMG bit = 1

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

t6 is measured from the latest active (v a lid) timing among nCS, nRD, A0-A2.**

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

Note 2: Read cycl e for Addre s s Pointer Low/Hi gh Regist e r s occurring afte r a read from

Data Register requires a minimum of 5TARB from the trailing edge of nRD to the

leading edge of the next nRD.

Note 3: Read cycl e for Addr e s s Pointer Low/High Registers oc cu r ring af ter a write to

Data Register requires a minimum of 5TARB from the trailing edge of nWR to the

leading edge of nRD.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

FIGURE 17 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE

A0-A2

VALID DATA

VALID

D0-D7

nCS

nDS

DIR t5 t7

t10 t11

Note 2

Parameter min max units

5**

Address Setup to nDS Active

Address Hold from nDS Inactive

nCS Setup to nDS Active

nCS Hold from nDS Inactive

DIR Setup to nDS Active

Cycle Time (nDS Low to Next Time Lo w)

DIR Hold from nDS Inactive 4TARB*

t8 nS

nDS Low to Valid Data 40**

t10

t11

nDS High to Data High Impede nce

nDS Low Width

nDS High Width

CASE 1: RBUSTMG bit = 0

The Microcontroller typically accesses the COM20020 on ev ery other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

nCS may become active after control becomes active , but the access time (t8) will

now be 45n S measured from the le ad ing edge of nCS.

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operat ion clock. It depen ds on CKUP1 and CKUP0 bit s

Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access

to Data Register requires a minimum of 5TARB from the trailing edge o f nDS to

the leading edge of the next nDS.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 55 Revision 12-06-06

DATASHEET

FIGURE 18 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE

A0-A2

VALID DATA

VALID

D0-D7

nCS

nDS

DIR t5 t7

t10 t11

Note 2

Parameter min max units

-5

Address Setup to nDS Active

Addre ss Hold from nDS Inactive

nCS Setup to nDS Active

nCS Hold from nDS Inactive

DIR Setup to nDS A ctive

Cycle Time (nDS Low to Next Time Low)

DIR Hold from nDS Inactive 4TARB*+30

t8 nSnDS Low to Valid Data 60**

t10

t11

nDS High to Data High Impedence

nDS Low Width

nDS High Wid th

100

CASE 2: RBUSTMG bit = 1

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

** t8 is measured from the latest active (valid) timing among nCS, nDS, A0-A2.

TARB is the Arbitration Clock Period

TARB is identical to Topr i f SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of ope ration cloc k. It depends on CKUP1 and CKUP0 bits

Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access

to Data Register requires a minimum of 5TARB from the trailing edge of nDS to

the leading edge of the next nDS.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

FIGURE 19 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE

Data Hold from nWR High

nWR Low Wid t h

nWR High Width

nRD to nWR Low

A0-A2

VALID DATA

VALID

D0-D7

nCS

t3 t4

Note 2

nWR

nRD t10 t8 t9 t5

Note 3

t5**

t10

Parameter

Address Setup to nWR Active

nCS Setup to WR Active

Valid Data Setup to nWR High

min

max

4TARB*

30***

units

t4 nCS Hold from nWR Inactive 0nS

t2 Address Hold from nWR Inactive 10 nS

Cycle Time (nWR to Next )**

***: nCS may become active after control becomes active, but the data setup time will now

be 30 nS measured from the later of nCS falling or Valid Data available.

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cycle time specifie d in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

Note 2: Any cycle occurring after a write to the Address Pointer Low Register

requires a minimum of 4TARB from the trailing edge of nWR to the leading edge

of the next nWR.

TARB is the Arbitration Clock Period

TARB is iden tica l to Topr if SLO W ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

Write cycle for Address Pointer Low Register occur rin g after a write to Data

leading edge of the next nWR.

Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data

leading edge of nWR.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 57 Revision 12-06-06

DATASHEET

FIGURE 20 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE

A0-A2

VALID DATA

VALID

D0-D7

nCS

t10

Note 2

DIR

nDS t11

t6**

Parameter min max units

Address Setup to nDS Active

Address Hold from nDS Inactive

nCS Setup to nDS Active

nCS Hold from nDS Inact ive

DIR Setup to nDS Active

Cycle Time (nDS to Next Time )**

DIR Hold from nDS Inactive

Valid Data Setup to nDS High

Data Hold from nDS High

nDS Low Width

nDS High Width

t10

t11

4TARB*

30***

***: nCS may become active after control becomes active, bu t th e data setup time will now

be 30 nS measured from the later of nCS falling or Valid Data ava ilable.

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

**Note 2: Any cycle occu rring after a writ e to the Address Pointer Low Register

requires a minimum of 4TARB from the trailing edge of nDS to the le ad ing ed ge

of the ne xt nDS.

Write cycle for Address Pointer Low R egister s occurring after an access to

Data Register requires a minimum of 5TARB from the trailing edge of nDS to

the leading edge of the next nDS.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

FIGURE 21 – NORMAL MODE TRANSMIT OR RECEIVE TIMING

(These signals are to and from the hybrid)

FIGURE 22 – BACKPLANE MODE TRANSMIT OR RECEIVE TIMING

(These signals are to and from the differential driver or the cable)

Parameter

Input Clock High Time

Input Clock Period

min

max units

XTAL1

t4 Input Clock Frequ ency 100

t2 Input Clock Low Time nS

typ

40 MHz

t5 Frequ ency Accuracy* -200 200 ppm

Note*: Input clock frequency must be 20 MHz ( 100pp m or better) to use the internal Clock Multipli er.

t5is applied to crystal oscillaton.

4.0V 1.0V 50% of VDD

nPULSE2

Parameter

nPULSE1, nPULSE2 Pulse Width

nPULSE1, nPU LSE2 Over lap

RXIN Period

RXIN Inactive Pulse Width

min

100

-10

max units

nPULSE1

t6 RXIN Active Pulse Width

t2 nPULSE1, nPU LSE2 Period nS

400

0+10

typ

RXIN

10 400

nTXEN

t4 t5

LAST BIT

(400 nS BIT TIME)

t4 nTXEN Low to nPULSE1 Low 850 950 nS

t5 Beginn i ng of Last Bit Time to nTXEN High 250 350 nS

100

20 nS

Note: Use Only 2.5 Mbps

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 59 Revision 12-06-06

DATASHEET

FIGURE 23 – TTL INPUT TIMING ON XTAL1 PIN

Parameter

nRESET Pulse Width***

min max units

nRESET

t2 nINTR High to Next nINTR Low

typ

nINTR

5TXTL*

EF = 0

EF = 1 TDR**/2

4TXTL*

Note *: TXTL is period of external XTAL oscillation frequency.

Note **: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)

Note***: When the power is turned on, t1 is measured from stable XTAL

oscillation after VDD was over 4.5V.

FIGURE 24 – RESET AND INTERRUPT TIMING

Parameter

nRESET Pu lse Width***

min max units

nRESET

t2 nINTR High to Next nINTR Lo w

typ

nINTR

5TXTL*

EF = 0

EF = 1 TDR**/2

4TXTL*

Note*: TXTL is period of external XTAL oscillation frequency.

Note**: T DR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)

Note***: When the power is turned on, t1 is measured from stable XTAL

oscillation after VDD was over 4.5V.

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

10.0 PACKAGE OUTLINES

FIGURE 25 - 28 PIN PLCC PACKAGE DIMENSIONS

.160-.180

.090-.120

.013-.021

.026-.032

.020-.045

.485-.495

.450-.456

.390-.430

.300 RE F

.050 BSC

.042-.056

.042-.048

.025-.045

DIM 28L

J .000-.020

NOTES:

All dimensions are in inches.

Circle indicatin g pin 1 can appear on a top surface as shown on the drawin g or

right above it on a beveled ed ge.

PIN NO.

GEJ

JD1

Base

Plane

Seating

Plane

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V Page 61 Revision 12-06-06

DATASHEET

FIGURE 26 - 48 PIN TQFP PACKAGE OUTLINE

MIN NOMINAL MAX REMARK

A ~ ~ 1.6 Overall Package Height

A1 0.05 0.10 0.15 Standoff

A2 1.35 1.40 1.45 Body Thickness

D 8.80 9.00 9.20 X Span

D/2 4.40 4.50 4.60

1/2 X Span Measure from Centerline

D1 6.90 7.00 7.10 X body Size

E 8.80 9.00 9.10 Y Span

E/2 4.40 4.50 4.60

1/2 Y Span Measure from Centerline

E1 6.90 7.00 7.10 Y body Size

H 0.09 ~ 0.20 Lead Frame Thickness

L 0.45 0.60 0.75 Lead Foot Length from Cen terline

L1 ~ 1.00 ~ Lead Length

e 0.50 Basic Lead Pitch

θ 0o ~ 7o Lead Foot Angle

W 0.17 ~ 0.27 Lead Width

R1 0.08 ~ ~ Lead Shoulder Radius

R2 0.08 ~ 0.20 Lead Foot Radius

ccc ~ ~ 0.0762 Coplanarity (Assemblers)

ccc ~ ~ 0.08 Coplanarity (Test House)

Note 1: Controlling Unit: millimeter

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06 SMSC COM20020I 3.3V

DATASHEET

11.0 APPENDIX A

This appendix describes the function of the NOSYNC and EF bits.

NOSYNC Bit

The NOSYNC bit controls whether or not the RAM initialization sequence requires the line to be idle by enabling or

disabling the SYNC command during initialization. It is defined as foll ows:

NOSYNC: Enable/Disable S Y NC comm and dur i ng initializ ation. NOSYNC=0, Enable (Def ault): the lin e has to be i dle

for the RAM initialization seq uence to be written, NOSYNC= 1, Disable: the line does not have to be idle for the RAM

initialization sequence to be written.

The following discussion describes the function of this bit:

During initialization, after the CPU writes the Node ID, the COM20020I will write "D1"h data to Address 000h and

Node-ID to Address 001h of its internal RAM within 6uS. These values are read as part of the diagnostic test. If the

D1 and Node-ID initialization sequence cannot be read, the initialization routine will report it as a device diagnostic

failure. These writes are controlled by a micr o-program which sometimes waits if the lin e is active; SYNC is the micro-

program command that cause s the wait. When the micro-program waits, the i nitial RAM write d oes not occur, which

causes the diagnostic error. Thus in this case, if the line is not idle, the initialization sequence may not be written,

which will be reported as a device diagnostic failure.

However, the initialization sequence a nd diagn ostics of the COM20020I shou ld be ind epende nt of the net work status.

This is accomplished through some additional logic to decode the program counter, enabled by the NOSYNC bit.

When it finds that the micro-p rogram is in the initialization routine, it disabl es the SYNC command. In this case, the

initialization will not be held u p b y the line status.

Thus, by setting the NOSYNC bit, the line does not have to be idle for the RAM initialization sequence to be written.

EF Bit

The EF bit controls several modifications to internal operation timing and logic. It is defined as follows:

EF: Enable/Disable the n ew internal operatio n timing and lo gic refinements. EF= 0: (Default) Disable the ne w internal

operation timing (the timing is the same as in the COM20020I Rev. B); EF=1: Enable the new internal operation

timing.

The EF bit controls the following timing/logic refinements in the COM20020I:

A) Extend Interrupt Disable Time

While the interrupt is active (nINTR pin=0), the interrupt is disabled by writing the Clear T x/Rx interrupt and Clear Flag

command and by reading the Next-ID register. This minimum disable time is changed by the Data Rate. For

example, it is 200 nS at 2.5 Mbps an d 100 nS at 5 Mbps. T he 100 nS width will be too short to for the Interrupt to be

seen.

Setting the EF bit will change the minimum disable time to always be more than 200 nS even if the Data Rate is 5

Mbps . This is done by changing the clock which is suppl ied to the Interrupt Disable lo gic . T he frequenc y of this cloc k

is always less than 20MHz even if the data rate is 5 Mbps.

B) Synchronize the Pre-Scalar Output

The Pre-Scalar is used to change the data rate. The output clock is selected by CKP3-1 bits in the Set-Up register.

The CKP3-1 bits are c hanged by writing the Set-Up r egister from o utside the CPU. It' s not synchronized bet ween the

CPU and COM20020I. Thus, changing the CKP3-1 timing does not synchronize with the internal clocks of Pre-Scalar,

and changing CKP3-1 may cause spike noise to appear on the output clock lin e.

Setting the EF bit will include flip-flops inserted between the Configuration register and Pre-Scalar for synchronizing

the CKP3-1 with Pre-Scalar’s internal clocks.

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Never change the CKP3-1 when the data rate is over 5 Mbps. T he y must all be zero.

C) Shorten The Write Interval Time To The Command Register

The COM20020I limits the write interval time for continuous writing to the Command register. The minimum interval

time is changed by the Data Rate. It's 100 nS at the 2.5 Mbps and 1.6 μS at the 156.25 Kbps. This 1.6 μS is very long

for CPU.

Setting the EF bit will change the clock source from OSCK clock (8 times frequency of data rate) to XTAL clock

which is not changed by the data rate, such that the minimum interval time becomes 100 nS.

D) Eliminate The Write Prohibition Period For The Enable Tx/Rx Commands

The COM20020I has a write prohibition period for writing the Enable Transmit/Receive Commands. This period is

started by the TA or RI bit (Status Reg.) returning to High. This prohibition period is caused by setting the TA/RI bit

with a pulse signal. It is 3.2 μS at 156.25 Kbps. This period may b e a problem when using interrupt processing. The

interrupt occurrs when the RI bit returns to High. The CPU writes the next Enable Receive Command to the other

page immediately. In this case, the interval time between the interrupt and writing Command is shorter than 3.2 μS.

Setting the EF bit will cause the TA/RI bit to return to High upon release of the pulse signal for setting the TA/RI bit,

instead of at the start of the pulse. This is illustrated in Figure 27.

Tx/Rx comp leted

TA /R I bit

S e tt in g P u l s e

nINTR pin

prohibition period

EF=1 Tx/Rx com pleted

TA /R I bit

Setting Pulse

nINTR pi n

EF=0

FIGURE 27 - EFFECT OF THE EF BIT ON THE TA/RI BIT

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The EF bit also controls the resolution of the following issues from the COM20020I Rev. B:

A) Network MAP Generation

Tentative ID is used for generating the Net work MAP, but it sometimes detects a non-existent node. Every time the

Tentative-ID register is written, the effect of the old Tentative-ID remains active for a while, which results in an

incorrect network map. It can be avoided by a carefully coded software routine, but this requires the programmer to

have deep knowledge of how the COM20020I works. Duplicate-ID is mainly used for generating the Network MAP.

This has the same issue as Tentative-ID.

A minor logic change clears all the remaining effects of the old Tentative-ID and the old Duplicate-ID, when the

COM20020I detects a write operation to Tentative-ID or Node-ID register. With this change, programmers can use

the Tentative-ID or Duplicate-ID for generating the network MAP without any issues. This change is Enable d/Disabled

by the EF bit.

B) Mask Register Reset

The Mask register is reset by a soft reset in the COM20020I Rev. A, but is not reset in Rev. B. The Mask register is

related to the Status and Diagnostic register, so it should be reset by a soft reset. Otherwise, every time the soft

reset happens, the COM200 20I Rev. B generates an unnecessary interrup t since the status bits RI and T A are back

to one by the soft reset.

This is resolved by changing the logic to rese t the Mask register both by the hard reset an d by the soft reset. The soft

reset is activated by the Node-ID register going to 00h or by the RESET bit going to High in the Configuration

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12.0 APPENDIX B

12.1 Software Identification of the COM20020I Rev B, Rev C and Rev D

In order to properly write software to work with the COM2 0020I Rev B, C and D it is necessary to be able to identify

the different revisions of the part.

To identify the COM20020I Revision follow the following procedure:

1. Write 0x98 to Register-6 (Address = 6)

2. Write 0x02 to Register-5 (Address = 5)

3. Read Register-6

* If the value read from Register-6 is 0x98 then the part is a COM20020I Rev B or earlier

* If the value read from Register-6 is 0x9A then go to next step below

4. Write 0x80 to Register-5

5. Read Register-5

* If the value read from Register-5 is 0x00 then the part is a COM20020I Rev C

• If the value read from Register-5 is 0x80 then the part is a COM20020I Rev D