MCP414X/416X/424X/426X 7/8-Bit Single/Dual SPI Digital POT with Non-Volatile Memory Features Description * Single or Dual Resistor Network options * Potentiometer or Rheostat configuration options * Resistor Network Resolution - 7-bit: 128 Resistors (129 Steps) - 8-bit: 256 Resistors (257 Steps) * RAB Resistances options of: - 5 k - 10 k - 50 k - 100 k * Zero-Scale to Full-Scale Wiper operation * Low Wiper Resistance: 75 (typical) * Low Tempco: - Absolute (Rheostat): 50 ppm typical (0C to 70C) - Ratiometric (Potentiometer): 15 ppm typical * Non-volatile Memory - Automatic Recall of Saved Wiper Setting - WiperLockTM Technology * SPI serial interface (10 MHz, modes 0,0 & 1,1) - High-Speed Read/Writes to wiper registers - Read/Write to Data EEPROM registers - Serially enabled EEPROM write protect - SDI/SDO multiplexing (MCP41X1 only) * Resistor Network Terminal Disconnect Feature via: - Shutdown pin (SHDN) - Terminal Control (TCON) Register * Write Protect Feature: - Hardware Write Protect (WP) Control pin - Software Write Protect (WP) Configuration bit * Brown-out reset protection (1.5V typical) * Serial Interface Inactive current (2.5 uA typical) * High-Voltage Tolerant Digital Inputs: Up to 12.5V * Supports Split Rail Applications * Internal weak pull-up on all digital inputs * Wide Operating Voltage: - 2.7V to 5.5V - Device Characteristics Specified - 1.8V to 5.5V - Device Operation * Wide Bandwidth (-3dB) Operation: - 2 MHz (typical) for 5.0 k device * Extended temperature range (-40C to +125C) The MCP41XX and MCP42XX devices offer a wide range of product offerings using an SPI interface. WiperLock Technology allows application-specific calibration settings to be secured in the EEPROM. Package Types (top view) MCP41X1 Single Potentiometer 1 2 3 4 CS SCK SDI/SDO VSS 8 7 6 5 MCP41X2 Single Rheostat CS 1 8 VDD SCK 2 7 SDO SDI 3 6 P0B 5 P0W VSS 4 VDD P0B P0W P0A PDIP, SOIC, MSOP PDIP, SOIC, MSOP CS 1 8 VDD CS 1 7 P0B SCK 2 EP 9 VSS 4 6 P0W SDI 3 5 P0A VSS 4 5 P0W SDO 12 WP 2 11 NC EP 17 3 10 P0B 9 P0W 5 6 7 8 P0A 4 P1A PDIP, SOIC, TSSOP 16 15 14 13 1 P1B VDD SDO SCK SHDN SDI WP P0B VSS P0W V SS P0A P1W 14 13 12 11 10 9 8 VDD CS MCP42X1 Dual Potentiometers 1 2 3 4 5 6 7 6 P0B 3x3 DFN* 3x3 DFN* CS SCK SDI VSS P1B P1W P1A 7 SDO EP 9 SHDN SCK 2 SDI/SDO 3 8 VDD 4x4 QFN* MCP42X2 Dual Rheostat CS SCK SDI VSS P1B 1 2 3 4 5 10 9 8 7 6 MSOP, DFN CS 1 VDD SDO SCK 2 P0B P0W SDI 3 P1W VSS 4 10 VDD EP 11 9 SDO 8 P0B 7 P0W 6 P1W P1B 5 3x3 DFN* * Includes Exposed Thermal Pad (EP); see Table 3-1. (c) 2008 Microchip Technology Inc. DS22059B-page 1 MCP414X/416X/424X/426X Device Block Diagram VDD VSS CS SCK SDI SDO WP SHDN For Dual Potentiometer Devices Only Power-up/ Brown-out Control P0A Resistor Network 0 (Pot 0) P0W Wiper 0 & TCON Register SPI Serial Interface Module & Control Logic (WiperLockTM Technology) P0B P1A Resistor Network 1 (Pot 1) Memory (16x9) Wiper0 (V & NV) Wiper1 (V & NV) TCON STATUS Data EEPROM (10 x 9-bits) P1W Wiper 1 & TCON Register P1B For Dual Resistor Network Devices Only 1 MCP4141 1 Potentiometer (1) SPI Rheostat Mid-Scale 5.0, 10.0, 50.0, 100.0 RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V 75 VDD Operating Range (2) 129 1.8V to 5.5V MCP4142 1 EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V 1 Potentiometer (1) SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4152 (3) 1 RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4161 1 Potentiometer (1) SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4162 1 EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4231 (3) 2 Potentiometer (1) SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V 2 RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4232 Rheostat Rheostat Rheostat SPI No RAB Options (k) Wiper - RW () MCP4151 (3) (3) Rheostat SPI RAM Resistance (typical) # of Steps MCP4132 (3) POR Wiper Setting 1 Potentiometer (1) SPI Wiper Configuration WiperLock Technology MCP4131 (3) Device Memory Type Control Interface # of POTs Device Features SPI SPI SPI MCP4241 2 Potentiometer (1) SPI MCP4242 2 EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4251 (3) 2 Potentiometer (1) SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4252 (3) 2 RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4261 2 Potentiometer (1) SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V 2 EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4262 Note 1: 2: 3: Rheostat Rheostat Rheostat SPI SPI SPI Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor). Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted. Please check Microchip web site for device release and availability DS22059B-page 2 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Voltage on VDD with respect to VSS ............... -0.6V to +7.0V Voltage on CS, SCK, SDI, SDI/SDO, WP, and SHDN with respect to VSS ...................................... -0.6V to 12.5V Voltage on all other pins (PxA, PxW, PxB, and SDO) with respect to VSS ............................ -0.3V to VDD + 0.3V Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP ON HV pins) ......................20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ..................................................20 mA Maximum output current sunk by any Output pin ......................................................................................25 mA Maximum output current sourced by any Output pin ......................................................................................25 mA Maximum current out of VSS pin .................................100 mA Maximum current into VDD pin ....................................100 mA Maximum current into PXA, PXW & PXB pins ............2.5 mA Storage temperature ....................................-65C to +150C Ambient temperature with power applied .....................................................................-40C to +125C Total power dissipation (Note 1) ................................400 mW Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins .................................. 4 kV (HBM), .......................................................................... 300V (MM) Maximum Junction Temperature (TJ) ......................... +150C Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOI x IOL) (c) 2008 Microchip Technology Inc. DS22059B-page 3 MCP414X/416X/424X/426X AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Parameters Sym Min Typ Max Units Conditions Supply Voltage VDD 2.7 -- 5.5 V 1.8 -- 2.7 V Serial Interface only. VSS -- 12.5V V VDD 4.5V VSS -- VDD + 8.0V V VDD < 4.5V -- -- 1.65 V RAM retention voltage (VRAM) < VBOR CS, SDI, SDO, SCK, WP, SHDN pin Voltage Range VHV VDD Start Voltage to ensure Wiper Reset VBOR VDD Rise Rate to ensure Power-on Reset VDDRR Delay after device exits the reset state (VDD > VBOR) TBORD -- 10 20 s IDD -- -- 450 A Serial Interface Active, VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all 0's to volatile Wiper 0 (address 0h) -- -- 1 mA EE Write Current, VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all 0's to non-volatile Wiper 0 (address 2h) -- 2.5 5 A Serial Interface Inactive, CS = VIH, VDD = 5.5V -- 0.55 1 mA Serial Interface Active, VDD = 5.5V, CS = VIHH, SCK @ 5 MHz, decrement non-volatile Wiper 0 (address 2h) Supply Current (Note 10) (Note 9) The CS pin will be at one of three input levels (VIL, VIH or VIHH). (Note 6) V/ms Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network Note 1: 2: 3: 4: 5: 6: 7: DS22059B-page 4 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics Parameters Resistance ( 20%) Resolution Step Resistance Nominal Resistance Match Wiper Resistance (Note 3, Note 4) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym Min Typ Max Units Conditions RAB 4.0 5 6.0 k -502 devices (Note 1) 8.0 10 12.0 k -103 devices (Note 1) 40.0 50 60.0 k -503 devices (Note 1) 80.0 100 120.0 k -104 devices (Note 1) N 257 Taps 8-bit No Missing Codes 129 Taps 7-bit No Missing Codes -- RAB / (256) -- 8-bit Note 6 -- RAB / (128) -- 7-bit Note 6 |RAB0 - RAB1| / RAB -- 0.2 1.25 % MCP42X1 devices only |RBW0 - RBW1| / RBW -- 0.25 1.5 % MCP42X2 devices only, Code = Full-Scale RW -- 75 160 VDD = 5.5 V, IW = 2.0 mA, code = 00h -- 75 300 VDD = 2.7 V, IW = 2.0 mA, code = 00h -- 50 -- ppm/C TA = -20C to +70C -- 100 -- ppm/C TA = -40C to +85C -- 150 -- ppm/C TA = -40C to +125C ppm/C Code = Midscale (80h or 40h) RS Nominal Resistance Tempco RAB/T Ratiometeric Tempco VWB/T -- 15 -- Resistor Terminal Input Voltage Range (Terminals A, B and W) VA,VW,VB Vss -- VDD V Maximum current through A, W or B IW -- -- 2.5 mA Note 6, Worst case current through wiper when wiper is either Full-Scale or Zero Scale. Leakage current into A, W or B IWL -- 100 -- nA MCP4XX1 PxA = PxW = PxB = VSS -- 100 -- nA MCP4XX2 PxB = PxW = VSS Note 5, Note 6 Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network Note 1: 2: 3: 4: 5: 6: 7: (c) 2008 Microchip Technology Inc. DS22059B-page 5 MCP414X/416X/424X/426X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics Parameters Full-Scale Error (MCP4XX1 only) (8-bit code = 100h, 7-bit code = 80h) Zero-Scale Error (MCP4XX1 only) (8-bit code = 00h, 7-bit code = 00h) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym Min Typ Max Units VWFSE -6.0 -0.1 -- LSb -4.0 -0.1 -- LSb -3.5 -0.1 -- LSb -2.0 -0.1 -- LSb -0.8 -0.1 -- LSb -0.5 -0.1 -- LSb -0.5 -0.1 -- -0.5 -0.1 -- -- +0.1 +6.0 LSb VWZSE Potentiometer Integral Non-linearity INL Potentiometer Differential Non-linearity DNL Bandwidth -3 dB (See Figure 2-58, load = 30 pF) BW Conditions 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V LSb 100 k 8-bit 3.0V VDD 5.5V LSb 7-bit 3.0V VDD 5.5V 5 k 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V 10 k 8-bit 3.0V VDD 5.5V -- +0.1 +3.0 LSb -- +0.1 +3.5 LSb -- +0.1 +2.0 LSb -- +0.1 +0.8 LSb 5 k 10 k 50 k 50 k 7-bit 3.0V VDD 5.5V 8-bit 3.0V VDD 5.5V -- +0.1 +0.5 LSb 7-bit 3.0V VDD 5.5V -- +0.1 +0.5 LSb 100 k 8-bit 3.0V VDD 5.5V -- +0.1 +0.5 LSb 7-bit 3.0V VDD 5.5V -1 0.5 +1 LSb 8-bit -0.5 0.25 +0.5 LSb 7-bit 3.0V VDD 5.5V MCP4XX1 devices only (Note 2) 3.0V VDD 5.5V MCP4XX1 devices only (Note 2) -0.5 0.25 +0.5 LSb 8-bit -0.25 0.125 +0.25 LSb 7-bit -- 2 -- MHz 5 k -- 2 -- MHz -- 1 -- MHz -- 1 -- MHz -- 200 -- kHz 8-bit Code = 80h -- 200 -- kHz 7-bit Code = 40h -- 100 -- kHz 100 k 8-bit Code = 80h -- 100 -- kHz 7-bit Code = 40h 10 k 50 k 8-bit Code = 80h 7-bit Code = 40h 8-bit Code = 80h 7-bit Code = 40h Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network Note 1: 2: 3: 4: 5: 6: 7: DS22059B-page 6 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics Parameters Rheostat Integral Non-linearity MCP41X1 (Note 4, Note 8) MCP4XX2 devices only (Note 4) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym R-INL Min Typ Max Units -1.5 0.5 +1.5 LSb -8.25 +4.5 +8.25 LSb -1.125 0.5 +1.125 LSb -6.0 +4.5 +6.0 LSb -1.5 0.5 +1.5 LSb -5.5 +2.5 +5.5 LSb -1.125 0.5 +1.125 LSb -4.0 +2.5 +4.0 LSb -1.5 0.5 +1.5 LSb -2.0 +1 +2.0 LSb -1.125 0.5 +1.125 LSb -1.5 +1 +1.5 LSb -1.0 0.5 +1.0 LSb -1.5 +0.25 +1.5 LSb -0.8 0.5 +0.8 LSb -1.125 +0.25 +1.125 LSb Conditions 5 k 8-bit 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 7-bit 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 10 k 8-bit 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 7-bit 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 50 k 8-bit 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 7-bit 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 100 k 8-bit 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7) 7-bit 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7) Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network Note 1: 2: 3: 4: 5: 6: 7: (c) 2008 Microchip Technology Inc. DS22059B-page 7 MCP414X/416X/424X/426X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics Parameters Rheostat Differential Non-linearity MCP41X1 (Note 4, Note 8) MCP4XX2 devices only (Note 4) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym Min Typ Max Units R-DNL -0.5 0.25 +0.5 LSb -1.0 +0.5 +1.0 LSb -0.375 0.25 +0.375 LSb -0.75 +0.5 +0.75 LSb -0.5 0.25 +0.5 LSb -1.0 +0.25 +1.0 LSb -0.375 0.25 +0.375 LSb -0.75 +0.5 +0.75 LSb -0.5 0.25 +0.5 LSb -0.5 0.25 +0.5 LSb -0.375 0.25 +0.375 LSb -0.375 0.25 +0.375 LSb -0.5 0.25 +0.5 LSb -0.5 0.25 +0.5 LSb -0.375 0.25 +0.375 LSb -0.375 0.25 +0.375 LSb Conditions 5 k 8-bit 5.5V, IW = 900 A 3.0V (Note 7) 7-bit 5.5V, IW = 900 A 3.0V (Note 7) 10 k 8-bit 5.5V, IW = 450 A 3.0V (Note 7) 7-bit 5.5V, IW = 450 A 3.0V (Note 7) 8-bit 5.5V, IW = 90 A 7-bit 5.5V, IW = 90 A 100 k 8-bit 5.5V, IW = 45 A 7-bit 5.5V, IW = 45 A 50 k 3.0V (Note 7) 3.0V (Note 7) 3.0V (Note 7) 3.0V (Note 7) Capacitance (PA) CAW -- 75 -- pF f =1 MHz, Code = Full-Scale Capacitance (Pw) CW -- 120 -- pF f =1 MHz, Code = Full-Scale Capacitance (PB) CBW -- 75 -- pF f =1 MHz, Code = Full-Scale Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network Note 1: 2: 3: 4: 5: 6: 7: DS22059B-page 8 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics Parameters All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym Min Typ Max Units Conditions Digital Inputs/Outputs (CS, SDI, SDO, SCK, WP, SHDN) Schmitt Trigger High Input Threshold VIH 0.45 VDD -- -- V 2.7V VDD 5.5V (Allows 2.7V Digital VDD with 5V Analog VDD) 0.5 VDD -- -- V 1.8V VDD 2.7V Schmitt Trigger Low Input Threshold VIL -- -- 0.2VDD V Hysteresis of Schmitt Trigger Inputs VHYS -- 0.1VDD -- V High Voltage Input Entry Voltage VIHH 8.5 -- 12.5 (6) V High Voltage Input Exit Voltage VIHH -- -- VDD + 0.8V (6) V High Voltage Limit VMAX -- -- 12.5 (6) V Pin can tolerate VMAX or less. Output Low Voltage (SDO) VOL Output High Voltage (SDO) VOH Weak Pull-up / Pull-down Current IPU CS Pull-up / Pull-down Resistance Input Leakage Current Pin Capacitance Threshold for WiperLockTM Technology VSS -- 0.3VDD V IOL = 5 mA, VDD = 5.5V VSS -- 0.3VDD V IOL = 1 mA, VDD = 1.8V 0.7VDD -- VDD V IOH = -2.5 mA, VDD = 5.5V 0.7VDD -- VDD V IOL = -1 mA, VDD = 1.8V -- -- 1.75 mA Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VCS = 12.5V -- 170 -- A CS pin, VDD = 5.5V, VCS = 3V RCS -- 16 -- k VDD = 5.5V, VCS = 3V IIL -1 -- 1 A VIN = VDD and VIN = VSS CIN, COUT -- 10 -- pF fC = 20 MHz Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network Note 1: 2: 3: 4: 5: 6: 7: (c) 2008 Microchip Technology Inc. DS22059B-page 9 MCP414X/416X/424X/426X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics Parameters All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym Min Typ Max Units Conditions N 0h -- 1FFh hex 8-bit device 0h -- 1FFh hex 7-bit device RAM (Wiper) Value Value Range EEPROM Endurance -- 1M -- Cycles EEPROM Range N 0h -- 1FFh hex Initial Factory Setting N Endurance EEPROM Programming Write Cycle Time 80h hex 8-bit WiperLock Technology = Off 40h hex 7-bit WiperLock Technology = Off tWC -- 5 10 ms PSS -- 0.0015 0.0035 %/% 8-bit VDD = 2.7V to 5.5V, VA = 2.7V, Code = 80h -- 0.0015 0.0035 %/% 7-bit VDD = 2.7V to 5.5V, VA = 2.7V, Code = 40h Power Requirements Power Supply Sensitivity (MCP41X2 and MCP42X2 only) Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network Note 1: 2: 3: 4: 5: 6: 7: DS22059B-page 10 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 1.1 SPI Mode Timing Waveforms and Requirements VIHH VIH CS VIH VIL 84 70 72 SCK 83 71 78 79 80 MSb SDO LSb BIT6 - - - - - -1 77 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 FIGURE 1-1: TABLE 1-1: # SPI Timing Waveform (Mode = 11). SPI REQUIREMENTS (MODE = 11) Characteristic SCK Input Frequency Symbol Min Max Units FSCK -- -- 60 45 500 45 500 10 20 -- -- 10 1 -- -- -- -- -- -- -- 50 70 170 -- 70 71 CS Active (VIL or VIHH) to SCK input SCK input high time 72 SCK input low time 73 74 77 80 Setup time of SDI input to SCK edge Hold time of SDI input from SCK edge CS Inactive (VIH) to SDO output hi-impedance SDO data output valid after SCK edge TDIV2scH TscH2DIL TcsH2DOZ TscL2DOV 83 CS Inactive (VIH) after SCK edge TscH2csI Hold time of CS Inactive (VIH) to CS Active (VIL or VIHH) Note 1: This specification by design. 84 (c) 2008 Microchip Technology Inc. TcsA2scH TscH TscL TcsA2csI 100 1 50 -- MHz MHz ns ns ns ns ns ns ns ns ns ns ns ms ns Conditions VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V Note 1 VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V DS22059B-page 11 MCP414X/416X/424X/426X VIH VIHH VIH 82 CS VIL SCK 84 70 83 71 MSb SDO BIT6 - - - - - -1 LSb 75, 76 73 SDI 80 72 MSb IN 77 BIT6 - - - -1 LSb IN 74 FIGURE 1-2: TABLE 1-2: # SPI Timing Waveform (Mode = 00). SPI REQUIREMENTS (MODE = 00) Characteristic Symbol Min Max Units FSCK 10 1 -- -- -- -- -- -- -- 50 70 170 70 MHz MHz ns ns ns ns ns ns ns ns ns ns ns -- ns ms ns 70 71 CS Active (VIL or VIHH) to SCK input SCK input high time 72 SCK input low time 73 74 77 80 Setup time of SDI input to SCK edge Hold time of SDI input from SCK edge CS Inactive (VIH) to SDO output hi-impedance SDO data output valid after SCK edge TDIV2scH TscH2DIL TcsH2DOZ TscL2DOV -- -- 60 45 500 45 500 10 20 -- -- 82 SDO data output valid after CS Active (VIL or VIHH) CS Inactive (VIH) after SCK edge TssL2doV -- TscH2csI 100 1 50 SCK Input Frequency 83 Hold time of CS Inactive (VIH) to CS Active (VIL or VIHH) Note 1: This specification by design. 84 DS22059B-page 12 TcsA2scH TscH TscL TcsA2csI -- Conditions VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V Note 1 VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X TABLE 1-3: SPI REQUIREMENTS FOR SDI/SDO MULTIPLEXED (READ OPERATION ONLY) (2) Characteristic Symbol Min Max Units Conditions -- 250 kHz VDD= 2.7V to 5.5V SCK Input Frequency FSCK TcsA2scH 60 -- ns CS Active (VIL or VIHH) to SCK input SCK input high time TscH 1.8 -- us SCK input low time TscL 1.8 -- ns 40 -- ns Setup time of SDI input to SCK edge TDIV2scH 40 -- ns Hold time of SDI input from SCK edge TscH2DIL CS Inactive (VIH) to SDO output hi-impedance TcsH2DOZ -- 50 ns Note 1 -- 1.6 us SDO data output valid after SCK edge TscL2DOV TssL2doV -- 50 ns SDO data output valid after CS Active (VIL or VIHH) TscH2csI 100 -- ns CS Inactive (VIH) after SCK edge TcsA2csI 50 -- ns Hold time of CS Inactive (VIH) to CS Active (VII or VIHH) Note 1: This specification by design 2: This table is for the devices where the SPI's SDI and SDO pins are multiplexed (SDI/SDO) and a Read command is issued. This is NOT required for SDI/SDO operation with the Increment, Decrement, or Write commands. This data rate can be increased by having external pull-up resistors to increase the rising edges of each bit. (c) 2008 Microchip Technology Inc. DS22059B-page 13 MCP414X/416X/424X/426X TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 -- +125 C Operating Temperature Range TA -40 -- +125 C Storage Temperature Range TA -65 -- +150 C Thermal Resistance, 8L-MSOP JA -- 211 -- C/W Thermal Resistance, 8L-PDIP JA -- 89.3 -- C/W Thermal Resistance, 8L-SOIC JA -- 149.5 -- C/W Thermal Resistance, 8L-DFN (3x3) JA -- 60 -- C/W Thermal Resistance, 10L-DFN (3x3) JA -- 57 -- C/W Thermal Resistance, 10L-MSOP JA -- 202 -- C/W Thermal Resistance, 14L-PDIP JA -- 70 -- C/W Thermal Resistance, 14L-SOIC JA -- 95.3 -- C/W Thermal Resistance, 14L-TSSOP JA -- 100 -- C/W Thermal Resistance, 16L-QFN JA -- 43 -- C/W Conditions Temperature Ranges Thermal Package Resistances DS22059B-page 14 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 2.0 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: 200 ICS 150 100 50 RCS 0 2.00 4.00 6.00 8.00 fSCK (MHz) 10.00 12.00 FIGURE 2-1: Device Current (IDD) vs. SPI Frequency (fSCK) and Ambient Temperature (VDD = 2.7V and 5.5V). 2 3 4 5 6 7 VCS (V) 8 9 10 FIGURE 2-4: CS Pull-up/Pull-down Resistance (RCS) and Current (ICS) vs. CS Input Voltage (VCS) (VDD = 5.5V). 12 3.0 2.5 CS V PP Threshold (V) Standby Current (Istby) (A) 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 250 2.7V -40C 2.7V 25C 2.7V 85C 2.7V 125C 5.5V -40C 5.5V 25C 5.5V 85C 5.5V 125C ICS (A) 650 600 550 500 450 400 350 300 250 200 150 100 50 0 0.00 RCS (kOhms) Operating Current (I DD) (A) Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 5.5V 2.0 1.5 1.0 2.7V 0.5 0.0 10 5.5V Entry 8 2.7V Entry 5.5V Exit 6 4 2.7V Exit 2 0 -40 25 85 125 Ambient Temperature (C) FIGURE 2-2: Device Current (ISHDN) and VDD. (CS = VDD) vs. Ambient Temperature. -40 -20 0 20 40 60 80 Ambient Temperature (C) 100 120 FIGURE 2-5: CS High Input Entry/Exit Threshold vs. Ambient Temperature and VDD. EE Write Current (Iwrite) (A) 900.0 800.0 700.0 600.0 5.5V 500.0 400.0 300.0 -40 25 85 125 Ambient Temperature (C) FIGURE 2-3: Write Current (IWRITE) vs. Ambient Temperature and VDD. (c) 2008 Microchip Technology Inc. DS22059B-page 15 MCP414X/416X/424X/426X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 0.2 0.1 80 0 60 -0.1 125C 20 0 -40C 25C 85C -0.2 RW -40C Rw -40C INL -40C DNL 260 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 0.1 180 0 140 RW 60 -40C 20 0 32 25C -0.1 -0.2 85C 85C 25C 32 -40C -1.25 64 96 128 160 192 224 256 Wiper Setting (decimal) -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL INL 2 0 -40C 60 125C 20 0 32 85C 25C DNL -2 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-10: 5 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). AB) 5000 RWB (Ohms) 5100 4 100 5250 5150 4000 3000 2000 -40C 25C 85C 125C 1000 5.5V 5050 6 RW 6000 2.7V 125C Rw 125C INL 125C DNL 140 5300 5200 -0.75 RW 180 -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-7: 5 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). Nominal Resistance (R (Ohms) 40 260 125C 0.75 -0.25 DNL 220 DNL 100 60 300 INL 220 1.25 FIGURE 2-9: 5 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 0.3 0.2 125C Rw 125C INL 125C DNL 0.25 0 Error (LSb) Wiper Resistance (RW) (ohms) 300 85C Rw 85C INL 85C DNL 80 20 FIGURE 2-6: 5 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 25C Rw 25C INL 25C DNL INL 125C -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) 32 -40C Rw -40C INL -40C DNL 100 INL DNL 40 120 0.3 Error (LSb) 125C Rw 125C INL 125C DNL Error (LSb) 85C Rw 85C INL 85C DNL Wiper Resistance (RW) (ohms) 100 25C Rw 25C INL 25C DNL Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (RW) (ohms) 120 0 -40 0 40 80 Ambient Temperature (C) 120 FIGURE 2-8: 5 k - Nominal Resistance () vs. Ambient Temperature and VDD. DS22059B-page 16 0 32 64 96 128 160 192 Wiper Setting (decimal) 224 256 FIGURE 2-11: 5 k - RWB () vs. Wiper Setting and Ambient Temperature. (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. FIGURE 2-12: 5 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-15: 5 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-13: 5 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div). FIGURE 2-16: 5 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div). FIGURE 2-14: 5 k - Power-Up Wiper Response Time (20 ms/Div). (c) 2008 Microchip Technology Inc. DS22059B-page 17 MCP414X/416X/424X/426X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 125C Rw 125C INL 125C DNL INL DNL 0.2 0.1 80 0 60 -0.1 25C -40C 125C 85C -0.2 RW 20 -0.3 0 260 220 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL INL DNL 0.1 180 0 140 100 25C 125C 85C 20 0 32 -0.2 -40C 125C 85C 25C 2 1 0 100 -40C 60 DNL RW -1 -2 0 25 50 75 100 125 150 175 200 225 250 Wiper Setting (decimal) FIGURE 2-21: 10 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). RWB (Ohms) 8000 6000 4000 -40C 25C 85C 125C 2000 10000 3 INL 20 AB) 5.5V 4 125C Rw 125C INL 125C DNL 140 10000 10050 85C Rw 85C INL 85C DNL 180 10200 10100 25C Rw 25C INL 25C DNL 220 12000 2.7V -0.5 DNL -1 64 96 128 160 192 224 256 Wiper Setting (decimal) -40C Rw -40C INL -40C DNL 260 10250 10150 32 RW -40C 125C 85C 25C -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-18: 10 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). Nominal Resistance (R (Ohms) 40 300 -0.1 RW 60 0 60 FIGURE 2-20: 10 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 0.3 0.2 1 125C Rw 125C INL 125C DNL 80 0 Error (LSb) Wiper Resistance (R W) (ohms) -40C Rw -40C INL -40C DNL 85C Rw 85C INL 85C DNL 0.5 20 FIGURE 2-17: 10 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 25C Rw 25C INL 25C DNL INL 25 50 75 100 125 150 175 200 225 250 Wiper Setting (decimal) 300 -40C Rw -40C INL -40C DNL 100 Wiper Resistance (R W) (ohms) 40 120 0.3 Error (LSb) 85C Rw 85C INL 85C DNL Error (LSb) 100 25C Rw 25C INL 25C DNL Wiper Resistance (R W) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (R W) (ohms) 120 0 -40 0 40 80 Ambient Temperature (C) 120 FIGURE 2-19: 10 k - Nominal Resistance () vs. Ambient Temperature and VDD. DS22059B-page 18 0 32 64 96 128 160 192 Wiper Setting (decimal) 224 256 FIGURE 2-22: 10 k - RWB () vs. Wiper Setting and Ambient Temperature. (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. FIGURE 2-23: 10 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-25: 10 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-24: 10 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div). FIGURE 2-26: 10 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div). (c) 2008 Microchip Technology Inc. DS22059B-page 19 MCP414X/416X/424X/426X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. INL DNL 0.2 0.1 80 0 60 -0.1 40 125C 25C 85C 20 0 -40C 120 0.3 100 -0.2 RW -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) 32 260 220 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL INL DNL 180 0 140 RW 100 -40C 60 0 32 -40C Rw -40C INL -40C DNL 125C Rw 125C INL 125C DNL 49400 0.75 0.25 -0.25 -0.5 -40C 60 85C 25C 0 32 64 -0.75 -1 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-31: 50 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). 40000 30000 20000 -40C 25C 85C 125C 10000 49600 1 0.5 RW 20 RWB (Ohms) 5.5V 85C Rw 85C INL 85C DNL DNL 100 50000 49800 25C Rw 25C INL 25C DNL 0 50600 50000 -0.2 -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) 32 140 60000 2.7V RW INL 50800 50200 85C 25C 125C 125C 50400 -40C 180 -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-28: 50 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). AB) -0.1 40 125C 85C 25C 20 Nominal Resistance (R (Ohms) 0 260 -0.2 0.1 60 300 -0.1 0.2 DNL 220 0.1 0.3 125C Rw 125C INL 125C DNL FIGURE 2-30: 50 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 0.3 0.2 85C Rw 85C INL 85C DNL 80 0 Error (LSb) Wiper Resistance (R W) (ohms) -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL INL 20 FIGURE 2-27: 50 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 300 -40C Rw -40C INL -40C DNL Error (LSb) 125C Rw 125C INL 125C DNL Error (LSb) 85C Rw 85C INL 85C DNL Wiper Resistance (R W) (ohms) 100 25C Rw 25C INL 25C DNL Wiper Resistance (R W) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (R W) (ohms) 120 0 -40 0 40 80 Ambient Temperature (C) 120 FIGURE 2-29: 50 k - Nominal Resistance () vs. Ambient Temperature and VDD. DS22059B-page 20 0 32 64 96 128 160 192 Wiper Setting (decimal) 224 256 FIGURE 2-32: 50 k - RWB () vs. Wiper Setting and Ambient Temperature. (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. FIGURE 2-33: 50 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-35: 50 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-34: 50 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div). FIGURE 2-36: 50 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div). (c) 2008 Microchip Technology Inc. DS22059B-page 21 MCP414X/416X/424X/426X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 125C Rw 125C INL 125C DNL 0.2 120 100 0.1 INL DNL 80 0 60 -0.1 40 25C -40C -40C Rw -40C INL -40C DNL RW -0.2 64 96 128 160 192 224 256 Wiper Setting (decimal) 32 -40C Rw -40C INL -40C DNL 260 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL INL -0.1 40 -40C 220 DNL 260 0 140 -0.05 100 RW 60 -40C -0.15 125C 85C 25C 20 0 32 -0.1 -0.2 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-38: 100 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). 125C Rw 125C INL 125C DNL 0 RW 100 60 -40C -0.2 -0.4 125C 85C 25C 0 32 -0.6 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-41: 100 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). Rwb (Ohms) 80000 60000 40000 -40C 25C 85C 125C 5.5V 20000 99000 0.4 140 100000 99500 0.6 0.2 DNL 20 AB) Nominal Resistance (R (Ohms) 85C Rw 85C INL 85C DNL 180 101000 100000 25C Rw 25C INL 25C DNL INL 220 120000 2.7V -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) 32 -40C Rw -40C INL -40C DNL 101500 100500 -0.2 FIGURE 2-40: 100 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 0.15 0.05 180 RW 125C 85C 25C 300 0.1 0.1 0 0.2 Error (LSb) Wiper Resistance (R W) (ohms) 300 0.2 60 0 FIGURE 2-37: 100 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 0.3 125C Rw 125C INL 125C DNL DNL 80 20 Wiper Resistance (Rw) (ohms) 0 85C Rw 85C INL 85C DNL INL 125C 85C 20 25C Rw 25C INL 25C DNL Error (LSb) 85C Rw 85C INL 85C DNL Error (LSb) 100 25C Rw 25C INL 25C DNL Wiper Resistance (R W) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (R W) (ohms) 120 0 -40 0 40 80 Ambient Temperature (C) 120 FIGURE 2-39: 100 k - Nominal Resistance () vs. Ambient Temperature and VDD . DS22059B-page 22 0 32 64 96 128 160 192 Wiper Setting (decimal) 224 256 FIGURE 2-42: 100 k - RWB () vs. Wiper Setting and Ambient Temperature. (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. FIGURE 2-43: 100 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-45: 100 k - Power-Up Wiper Response Time (1 s/Div). FIGURE 2-44: 100 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div). FIGURE 2-46: 100 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div). (c) 2008 Microchip Technology Inc. DS22059B-page 23 MCP414X/416X/424X/426X 0.12 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0.1 0.08 5.5V % % Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 0.06 0.04 3.0V 0.02 3.0V 0 -40 0 40 80 Temperature (C) 120 FIGURE 2-47: Resistor Network 0 to Resistor Network 1 RAB (5 k) Mismatch vs. VDD and Temperature. -40 0.04 0.05 0.03 0.04 40 80 Temperature (C) 0.03 5.5V 0.01 0 120 FIGURE 2-49: Resistor Network 0 to Resistor Network 1 RAB (50 k) Mismatch vs. VDD and Temperature. 0.02 5.5V 0.02 0 % % 5.5V -0.01 3.0V 0 3.0V -0.02 0.01 -0.01 -0.03 -0.02 -0.04 -0.03 -40 0 40 80 Temperature (C) 120 FIGURE 2-48: Resistor Network 0 to Resistor Network 1 RAB (10 k) Mismatch vs. VDD and Temperature. DS22059B-page 24 -40 10 60 Temperature (C) 110 FIGURE 2-50: Resistor Network 0 to Resistor Network 1 RAB (100 k) Mismatch vs. VDD and Temperature. (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 2.4 0 2.2 -5 IOH (mA) VIH (V) -10 5.5V 2 1.8 1.6 1.4 2.7V 2.7V -15 -20 5.5V -25 -30 -35 1.2 -40 1 -45 -40 0 40 80 120 -40 0 Temperature (C) FIGURE 2-51: VIH (SDI, SCK, CS, WP, and SHDN) vs. VDD and Temperature. 1.3 5.5V IOL (mA) VIL (V) 1.1 1 0.9 0.8 2.7V 0.7 0.6 -40 0 40 80 120 50 45 40 35 30 25 20 15 10 5 0 120 5.5V 2.7V -40 Temperature (C) FIGURE 2-52: VIL (SDI, SCK, CS, WP, and SHDN) vs. VDD and Temperature. (c) 2008 Microchip Technology Inc. 80 IOH (SDO) vs. VDD and FIGURE 2-53: Temperature. 1.4 1.2 40 Temperature (C) 0 40 80 120 Temperature (C) FIGURE 2-54: Temperature. IOL (SDO) vs. VDD and DS22059B-page 25 MCP414X/416X/424X/426X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 2.1 Test Circuits 4.2 +5V tWC (ms) 4.0 VIN 3.8 3.6 Offset GND 3.4 3.2 A W B + VOUT - 2.5V DC 3.0 -40 0 40 80 120 Temperature (C) FIGURE 2-55: Nominal EEPROM Write Cycle Time vs. VDD and Temperature. FIGURE 2-58: Test. -3 db Gain vs. Frequency 1.2 1 5.5V VDD (V) 0.8 0.6 2.7V 0.4 0.2 0 -40 0 40 80 120 Temperature (C) FIGURE 2-56: and Temperature. POR/BOR Trip point vs. VDD 15.0 14.5 fsck (MHz) 5.5V 14.0 2.7V 13.5 13.0 12.5 12.0 -40 0 40 80 120 Temperature (C) FIGURE 2-57: SCK Input Frequency vs. Voltage and Temperature. DS22059B-page 26 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follows. TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP414X/416X/424X/426X Pin Single Symbol I/O Buffer Type Weak Pull-up/ down (Note 2) Dual Rheo Pot (1) Rheo Pot Standard Function 8L 8L 10L 14L 16L 1 1 1 1 16 CS I HV w/ST "smart" SPI Chip Select Input 2 2 2 2 1 SCK I HV w/ST "smart" SPI Clock Input 3 -- 3 3 2 SDI I HV w/ST "smart" SPI Serial Data Input -- 3 -- -- -- SDI/SDO I/O HV w/ST "smart" SPI Serial Data Input/Output (Note 1, Note 3) 4 4 4 4 3, 4 VSS -- P -- Ground -- -- 5 5 5 P1B A Analog No Potentiometer 1 Terminal B -- -- 6 6 6 P1W A Analog No Potentiometer 1 Wiper Terminal -- -- -- 7 7 P1A A Analog No Potentiometer 1 Terminal A -- 5 -- 8 8 P0A A Analog No Potentiometer 0 Terminal A 5 6 7 9 9 P0W A Analog No Potentiometer 0 Wiper Terminal 6 7 8 10 10 P0B A Analog No Potentiometer 0 Terminal B -- -- -- 11 12 WP I I "smart" Hardware Protect -- -- -- 12 13 SHDN I HV w/ST "smart" Hardware Shutdown 7 -- 9 13 14 SDO O O No SPI Serial Data Out 8 8 10 14 15 VDD -- P -- Positive Power Supply Input -- -- -- -- 11 NC -- -- -- No Connection 9 9 11 -- 17 EP -- -- -- Exposed Pad. (Note 4) Legend: Note 1: 2: 3: 4: EEPROM Write HV w/ST = High Voltage tolerant input (with Schmidtt trigger input) A = Analog pins (Potentiometer terminals) I = digital input (high Z) O = digital output I/O = Input / Output P = Power The 8-lead Single Potentiometer devices are pin limited so the SDO pin is multiplexed with the SDI pin (SDI/SDO pin). After the Address/Command (first 6-bits) are received, If a valid Read command has been requested, the SDO pin starts driving the requested read data onto the SDI/SDO pin. The pin's "smart" pull-up shuts off while the pin is forced low. This is done to reduce the standby and shutdown current. The SDO is an open drain output, which uses the internal "smart" pull-up. The SDI input data rate can be at the maximum SPI frequency. the SDO output data rate will be limited by the "speed" of the pull-up, customers can increase the rate with external pull-up resistors. The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device's VSS pin. (c) 2008 Microchip Technology Inc. DS22059B-page 27 MCP414X/416X/424X/426X 3.1 Chip Select (CS) The CS pin is the serial interface's chip select input. Forcing the CS pin to VIL enables the serial commands. Forcing the CS pin to VIHH enables the high-voltage serial commands. 3.2 Serial Data In (SDI) The SDI pin is the serial interfaces Serial Data In pin. This pin is connected to the Host Controllers SDO pin. 3.3 Serial Data In / Serial Data Out (SDI/SDO) On the MCP41X1 devices, pin-out limitations do not allow for individual SDI and SDO pins. On these devices, the SDI and SDO pins are multiplexed. The MCP41X1 serial interface knows when the pin needs to change from being an input (SDI) to being an output (SDO). The Host Controller's SDO pin must be properly protected from a drive conflict. 3.4 Ground (VSS) The VSS pin is the device ground reference. 3.5 Potentiometer Terminal B The terminal B pin is connected to the internal potentiometer's terminal B. The potentiometer's terminal B is the fixed connection to the Zero Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. The terminal B pin does not have a polarity relative to the terminal W or A pins. The terminal B pin can support both positive and negative current. The voltage on terminal B must be between VSS and VDD. MCP42XX devices have two terminal B pins, one for each resistor network. 3.6 Potentiometer Wiper (W) Terminal The terminal W pin is connected to the internal potentiometer's terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal W pin can support both positive and negative current. The voltage on terminal W must be between VSS and VDD. MCP42XX devices have two terminal W pins, one for each resistor network. DS22059B-page 28 3.7 Potentiometer Terminal A The terminal A pin is available on the MCP4XX1 devices, and is connected to the internal potentiometer's terminal A. The potentiometer's terminal A is the fixed connection to the Full Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x100 for 8-bit devices or 0x80 for 7-bit devices. The terminal A pin does not have a polarity relative to the terminal W or B pins. The terminal A pin can support both positive and negative current. The voltage on terminal A must be between VSS and VDD. The terminal A pin is not available on the MCP4XX2 devices, and the internally terminal A signal is floating. MCP42X1 devices have two terminal A pins, one for each resistor network. 3.8 Write Protect (WP) The WP pin is used to force the non-volatile memory to be write protected. 3.9 Shutdown (SHDN) The SHDN pin is used to force the resistor network terminals into the hardware shutdown state. 3.10 Serial Data Out (SDO) The SDO pin is the serial interfaces Serial Data Out pin. This pin is connected to the Host Controllers SDI pin. This pin allows the Host Controller to read the digital potentiometers registers, or monitor the state of the command error bit. 3.11 Positive Power Supply Input (VDD) The VDD pin is the device's positive power supply input. The input power supply is relative to VSS. While the device VDD < Vmin (2.7V), the electrical performance of the device may not meet the data sheet specifications. 3.12 No Connection (NC) Those pins should be either connected to VDD or VSS. 3.13 Exposed Pad (EP) This pad is conductively connected to the device's substrate. This pad should be tied to the same potential as the VSS pin (or left unconnected). This pad could be used to assist as a heat sink for the device when connected to a PCB heat sink. (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 4.0 FUNCTIONAL OVERVIEW This Data Sheet covers a family of thirty-two Digital Potentiometer and Rheostat devices that will be referred to as MCP4XXX. The MCP4XX1 devices are the Potentiometer configuration, while the MCP4XX2 devices are the Rheostat configuration. As the Device Block Diagram shows, there are four main functional blocks. These are: * * * * POR/BOR Operation Memory Map Resistor Network Serial Interface (SPI) The POR/BOR operation and the Memory Map are discussed in this section and the Resistor Network and SPI operation are described in their own sections. The Device Commands commands are discussed in Section 7.0. 4.1 POR/BOR Operation The Power-on Reset is the case where the device is having power applied to it from VSS. The Brown-out Reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. The devices RAM retention voltage (VRAM) is lower than the POR/BOR voltage trip point (VPOR/VBOR). The maximum VPOR/VBOR voltage is less then 1.8V. When VPOR/VBOR < VDD < 2.7V, the electrical performance may not meet the data sheet specifications. In this region, the device is capable of reading and writing to its EEPROM and incrementing, decrementing, reading and writing to its volatile memory if the proper serial command is executed. 4.1.1 POWER-ON RESET When the device powers up, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage crosses the VPOR/VBOR voltage the following happens: * Volatile wiper register is loaded with value in the corresponding non-volatile wiper register * The TCON register is loaded it's default value * The device is capable of digital operation (c) 2008 Microchip Technology Inc. 4.1.2 BROWN-OUT RESET When the device powers down, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage decreases below the VPOR/VBOR voltage the following happens: * Serial Interface is disabled * EEPROM Writes are disabled If the VDD voltage decreases below the VRAM voltage the following happens: * Volatile wiper registers may become corrupted * TCON register may become corrupted As the voltage recovers above the VPOR/VBOR voltage see Section 4.1.1 "Power-on Reset". Serial commands not completed due to a brown-out condition may cause the memory location (volatile and non-volatile) to become corrupted. 4.2 Memory Map The device memory is 16 locations that are 9-bits wide (16x9 bits). This memory space contains both volatile and non-volatile locations (see Table 4-1). TABLE 4-1: Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh MEMORY MAP Function Volatile Wiper 0 Volatile Wiper 1 Non-Volatile Wiper 0 Non-Volatile Wiper 1 Volatile TCON Register Status Register Data EEPROM Data EEPROM Data EEPROM Data EEPROM Data EEPROM Data EEPROM Data EEPROM Data EEPROM Data EEPROM Data EEPROM Memory Type RAM RAM EEPROM EEPROM RAM RAM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM DS22059B-page 29 MCP414X/416X/424X/426X 4.2.1 NON-VOLATILE MEMORY (EEPROM) 4.2.1.4 This memory can be grouped into two uses of non-volatile memory. These are: * General Purpose Registers * Non-Volatile Wiper Registers The non-volatile wipers starts functioning below the devices VPOR/VBOR trip point. 4.2.1.1 General Purpose Registers These locations allow the user to store up to 10 (9-bit) locations worth of information. 4.2.1.2 Non-Volatile Wiper Registers Special Features There are 3 non-volatile bits that are not directly mapped into the address space. These bits control the following functions: * EEPROM Write Protect * WiperLock Technology for Non-Volatile Wiper 0 * WiperLock Technology for Non-Volatile Wiper 1 The operation of WiperLock Technology is discussed in Section 5.3. The state of the WL0, WL1, and WP bits is reflected in the STATUS register (see Register 4-1). EEPROM Write Protect All internal EEPROM memory can be Write Protected. When EEPROM memory is Write Protected, Write commands to the internal EEPROM are prevented. These locations contain the wiper values that are loaded into the corresponding volatile wiper register whenever the device has a POR/BOR event. There are up to two registers, one for each resistor network. Write Protect (WP) can be enabled/disabled by two methods. These are: The non-volatile wiper register enables stand-alone operation of the device (without Microcontroller control) after being programmed to the desired value. * External WP Hardware pin (MCP42X1 devices only) * Non-Volatile configuration bit 4.2.1.3 High Voltage commands are required to enable and disable the nonvolatile WP bit. These commands are shown in Section 7.9 "Modify Write Protect or WiperLock Technology (High Voltage)". Factory Initialization of Non-Volatile Memory (EEPROM) The Non-Volatile Wiper values will be initialized to mid-scale value. This is shown in Table 4-2. The General purpose EEPROM memory will be programmed to a default value of 0xFF. It is good practice in the manufacturing flow to configure the device to your desired settings. -502 5.0 k Mid-scale 80h 40h Disabled -103 10.0 k Mid-scale 80h 40h Disabled -503 50.0 k Mid-scale 80h 40h Disabled -104 100.0 k Mid-scale 80h 40h Disabled Resistance Code Default POR Wiper Setting Wiper Code WiperLockTM Technology and Write Protect Setting DEFAULT FACTORY SETTINGS SELECTION Typical RAB Value TABLE 4-2: DS22059B-page 30 8-bit 7-bit To write to EEPROM, both the external WP pin and the internal WP EEPROM bit must be disabled. Write Protect does not block commands to the volatile registers. 4.2.2 VOLATILE MEMORY (RAM) There are four Volatile Memory locations. These are: * Volatile Wiper 0 * Volatile Wiper 1 (Dual Resistor Network devices only) * Status Register * Terminal Control (TCON) Register The volatile memory starts functioning at the RAM retention voltage (VRAM). (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 4.2.2.1 Status (STATUS) Register STATUS register can be accessed via the READ commands. Register 4-1 describes each STATUS register bit. This register contains 5 status bits. These bits show the state of the WiperLock bits, the Shutdown bit the Write Protect bit, and if an EEPROM write cycle is active. The REGISTER 4-1: R-1 The STATUS register is placed at Address 05h. STATUS REGISTER R-1 R-1 R-1 D8:D5 R-0 EEWA R-x WL1 (1) R-x WL0 (1) R-x R-x SHDN WP (1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 8-5 D8:D5: Reserved. Forced to "1" bit 4 EEWA: EEPROM Write Active Status bit This bit indicates if the EEPROM Write Cycle is occurring. 1 = An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory locations are allowed (addresses 00h, 01h, 04h, and 05h) 0 = An EEPROM Write cycle is NOT currently occurring bit 3 WL1: WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 "WiperLockTM Technology" for further information) WiperLock (WL) prevents the Volatile and Non-Volatile Wiper 1 addresses and the TCON register bits R1HW, R1A, R1W, and R1B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wiper and TCON register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are "Locked" (Write Protected) 0 = Wiper and TCON of Resistor Network 1 (Pot 1) can be modified Note: bit 2 WL0: WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 "WiperLockTM Technology" for further information) The WiperLock Technology bits (WLx) prevents the Volatile and Non-Volatile Wiper 0 addresses and the TCON register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wiper and TCON register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are "Locked" (Write Protected) 0 = Wiper and TCON of Resistor Network 0 (Pot 0) can be modified Note: bit 1 Note 1: The WL1 bit always reflects the result of the last programming cycle to the non-volatile WL1 bit. After a POR or BOR event, the WL1 bit is loaded with the non-volatile WL1 bit value. The WL0 bit always reflects the result of the last programming cycle to the non-volatile WL0 bit. After a POR or BOR event, the WL0 bit is loaded with the non-volatile WL0 bit value. SHDN: Hardware Shutdown pin Status bit (Refer to Section 5.4 "Shutdown" for further information) This bit indicates if the Hardware shutdown pin (SHDN) is low. A hardware shutdown disconnects the Terminal A and forces the wiper (Terminal W) to Terminal B (see Figure 5-2). While the device is in Hardware Shutdown (the SHDN pin is low) the serial interface is operational so the STATUS register may be read. 1 = MCP4XXX is in the Hardware Shutdown state 0 = MCP4XXX is NOT in the Hardware Shutdown state Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit is Not directly written, but reflects the system state (for this feature). (c) 2008 Microchip Technology Inc. DS22059B-page 31 MCP414X/416X/424X/426X REGISTER 4-1: bit 0 Note 1: STATUS REGISTER (CONTINUED) WP: EEPROM Write Protect Status bit (Refer to Section "EEPROM Write Protect" for further information) This bit indicates the status of the write protection on the EEPROM memory. When Write Protect is enabled, writes to all non-volatile memory are prevented. This includes the General Purpose EEPROM memory, and the non-volatile Wiper registers. Write Protect does not block modification of the volatile wiper register values or the volatile TCON register value (via Increment, Decrement, or Write commands). This status bit is an OR of the devices Write Protect pin (WP) and the internal non-volatile WP bit. High Voltage commands are required to enable and disable the internal WP EEPROM bit. 1 = EEPROM memory is Write Protected 0 = EEPROM memory can be written Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit is Not directly written, but reflects the system state (for this feature). DS22059B-page 32 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 4.2.2.2 Terminal Control (TCON) Register This register contains 8 control bits. Four bits are for Wiper 0, and four bits are for Wiper 1. Register 4-2 describes each bit of the TCON register. The state of each resistor network terminal connection is individually controlled. That is, each terminal connection (A, B and W) can be individually connected/ disconnected from the resistor network. This allows the system to minimize the currents through the digital potentiometer. (c) 2008 Microchip Technology Inc. The value that is written to this register will appear on the resistor network terminals when the serial command has completed. When the WL1 bit is enabled, writes to the TCON register bits R1HW, R1A, R1W, and R1B are inhibited. When the WL0 bit is enabled, writes to the TCON register bits R0HW, R0A, R0W, and R0B are inhibited. On a POR/BOR this register is loaded with 1FFh (9-bits), for all terminals connected. The HostController needs to detect the POR/BOR event and then update the Volatile TCON register value. DS22059B-page 33 MCP414X/416X/424X/426X REGISTER 4-2: TCON BITS (1, 2) R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 D8 R1HW R1A R1W R1B R0HW R0A R0W R0B bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 8 D8: Reserved. Forced to "1" bit 7 R1HW: Resistor 1 Hardware Configuration Control bit This bit forces Resistor 1 into the "shutdown" configuration of the Hardware pin 1 = Resistor 1 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 1 is forced to the hardware pin "shutdown" configuration bit 6 R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network 1 = P1A pin is connected to the Resistor 1 Network 0 = P1A pin is disconnected from the Resistor 1 Network bit 5 R1W: Resistor 1 Wiper (P1W pin) Connect Control bit This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network 1 = P1W pin is connected to the Resistor 1 Network 0 = P1W pin is disconnected from the Resistor 1 Network bit 4 R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network 1 = P1B pin is connected to the Resistor 1 Network 0 = P1B pin is disconnected from the Resistor 1 Network bit 3 R0HW: Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the "shutdown" configuration of the Hardware pin 1 = Resistor 0 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 0 is forced to the hardware pin "shutdown" configuration bit 2 R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network 1 = P0A pin is connected to the Resistor 0 Network 0 = P0A pin is disconnected from the Resistor 0 Network bit 1 R0W: Resistor 0 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network 1 = P0W pin is connected to the Resistor 0 Network 0 = P0W pin is disconnected from the Resistor 0 Network bit 0 R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network 1 = P0B pin is connected to the Resistor 0 Network 0 = P0B pin is disconnected from the Resistor 0 Network Note 1: 2: The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to the inactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify the state of the TCON bits. These bits do not affect the wiper register values. DS22059B-page 34 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 5.0 RESISTOR NETWORK 5.1 The Resistor Network has either 7-bit or 8-bit resolution. Each Resistor Network allows zero scale to full scale connections. Figure 5-1 shows a block diagram for the resistive network of a device. The Resistor Network is made up of several parts. These include: * Resistor Ladder * Wiper * Shutdown (Terminal Connections) Devices have either one or two resistor networks, These are referred to as Pot 0 and Pot 1. A RW RS RW R RAB S The resistor ladder is a series of equal value resistors (RS) with a connection point (tap) between the two resistors. The total number of resistors in the series (ladder) determines the RAB resistance (see Figure 5-1). The end points of the resistor ladder are connected to analog switches which are connected to the device Terminal A and Terminal B pins. The RAB (and RS) resistance has small variations over voltage and temperature. For an 8-bit device, there are 256 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 256 resistors thus providing 257 possible settings (including terminal A and terminal B). 8-Bit N= 257 (1) (100h) 7-Bit N= 128 (80h) For a 7-bit device, there are 128 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 128 resistors thus providing 129 possible settings (including terminal A and terminal B). 256 (FFh) 127 (7Fh) Equation 5-1 shows the calculation for the step resistance. 255 (FEh) 126 (7Eh) EQUATION 5-1: RW (1) RS Resistor Ladder Module (1) RS CALCULATION R AB R S = ------------( 256 ) 8-bit Device R AB R S = ------------( 128 ) 7-bit Device W RW RS RW 1 (1) (01h) 1 (01h) 0 (00h) 0 (00h) (1) Analog Mux B Note 1: The wiper resistance is dependent on several factors including, wiper code, device VDD, Terminal voltages (on A, B, and W), and temperature. Also for the same conditions, each tap selection resistance has a small variation. This RW variation has greater effects on some specifications (such as INL) for the smaller resistance devices (5.0 k) compared to larger resistance devices (100.0 k). FIGURE 5-1: Resistor Block Diagram. (c) 2008 Microchip Technology Inc. DS22059B-page 35 MCP414X/416X/424X/426X 5.2 Wiper 5.3 Each tap point (between the RS resistors) is a connection point for an analog switch. The opposite side of the analog switch is connected to a common signal which is connected to the Terminal W (Wiper) pin. A value in the volatile wiper register selects which analog switch to close, connecting the W terminal to the selected node of the resistor ladder. The wiper can connect directly to Terminal B or to Terminal A. A zero-scale connections, connects the Terminal W (wiper) to Terminal B (wiper setting of 000h). A full-scale connections, connects the Terminal W (wiper) to Terminal A (wiper setting of 100h or 80h). In these configurations the only resistance between the Terminal W and the other Terminal (A or B) is that of the analog switches. A wiper setting value greater than full scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a Full Scale setting (Terminal W (wiper) connected to Terminal A). Table 5-1 illustrates the full wiper setting map. Equation 5-2 illustrates the calculation used to determine the resistance between the wiper and terminal B. The MCP4XXX device's WiperLock technology allows application-specific calibration settings to be secured in the EEPROM without requiring the use of an additional write-protect pin. There are two WiperLock Technology configuration bits (WL0 and WL1). These bits prevent the Non-Volatile and Volatile addresses and bits for the specified resistor network from being written. The WiperLock technology prevents commands from doing the following: RWB CALCULATION R AB N R WB = ------------- + RW ( 256 ) 8-bit Device N = 0 to 256 (decimal) R AB N - + RW R WB = ------------( 128 ) 7-bit Device the serial * Changing a volatile wiper value * Writing to a non-volatile wiper memory location * Changing the volatile TCON register value For either Resistor Network 0 or Resistor Network 1 (Potx), the WLx bit controls the following: * Non-Volatile Wiper Register * Volatile Wiper Register * Volatile TCON register bits RxHW, RxA, RxW, and RxB High Voltage commands are required to enable and disable WiperLock. Please refer to the Modify Write Protect or WiperLock Technology (High Voltage) command for operation. 5.3.1 EQUATION 5-2: WiperLockTM Technology POR/BOR OPERATION WHEN WIPERLOCK TECHNOLOGY ENABLED The WiperLock Technology state is not affected by a POR/BOR event. A POR/BOR event will load the Volatile Wiper register value with the Non-Volatile Wiper register value, refer to Section 4.1. N = 0 to 128 (decimal) TABLE 5-1: VOLATILE WIPER VALUE VS. WIPER POSITION MAP Wiper Setting Properties 7-bit Pot 8-bit Pot 3FFh 081h 3FFh 101h 080h 100h 07Fh 041h 040h 03Fh 001h 000h 0FFh 081 080h 07Fh 001 000h DS22059B-page 36 Reserved (Full Scale (W = A)), Increment and Decrement commands ignored Full Scale (W = A), Increment commands ignored W=N W = N (Mid-Scale) W=N Zero Scale (W = B) Decrement command ignored (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 5.4 5.4.2 Shutdown Shutdown is used to minimize the device's current consumption. The MCP4XXX has two methods to achieve this. These are: * Hardware Shutdown Pin (SHDN) * Terminal Control Register (TCON) The Hardware Shutdown pin is backwards compatible with the MCP42XXX devices. 5.4.1 HARDWARE SHUTDOWN PIN (SHDN) The SHDN pin is available on the dual potentiometer devices. When the SHDN pin is forced active (VIL): The Terminal Control (TCON) register is a volatile register used to configure the connection of each resistor network terminal pin (A, B, and W) to the Resistor Network. This register is shown in Register 4-2. The RxHW bits forces the selected resistor network into the same state as the SHDN pin. Alternate low power configurations may be achieved with the RxA, RxW, and RxB bits. Note: * The P0A and P1A terminals are disconnected * The P0W and P1W terminals are simultaneously connect to the P0B and P1B terminals, respectively (see Figure 5-2) * The Serial Interface is NOT disabled, and all Serial Interface activity is executed * Any EEPROM write cycles are completed The Hardware Shutdown pin mode does NOT corrupt the values in the Volatile Wiper Registers nor the TCON register. When the Shutdown mode is exited (SHDN pin is inactive (VIH)): * The device returns to the Wiper setting specified by the Volatile Wiper value * The TCON register bits return to controlling the terminal connection state Resistor Network A TERMINAL CONTROL REGISTER (TCON) 5.4.3 When the RxHW bit forces the resistor network into the hardware SHDN state, the state of the TCON register RxA, RxW, and RxB bits is overridden (ignored). When the state of the RxHW bit no longer forces the resistor network into the hardware SHDN state, the TCON register RxA, RxW, and RxB bits return to controlling the terminal connection state. In other words, the RxHW bit does not corrupt the state of the RxA, RxW, and RxB bits. INTERACTION OF SHDN PIN AND TCON REGISTER Figure 5-3 shows how the SHDN pin signal and the RxHW bit signal interact to control the hardware shutdown of each resistor network (independently). Using the TCON bits allows each resistor network (Pot 0 and Pot 1) to be individually "shutdown" while the hardware pin forces both resistor networks to be "shutdown" at the same time. W SHDN (from pin) RxHW (from TCON register) To Pot x Hardware Shutdown Control B FIGURE 5-2: Hardware Shutdown Resistor Network Configuration. (c) 2008 Microchip Technology Inc. FIGURE 5-3: Interaction. RxHW bit and SHDN pin DS22059B-page 37 MCP414X/416X/424X/426X NOTES: DS22059B-page 38 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 6.0 SERIAL INTERFACE (SPI) The MCP4XXX devices support the SPI serial protocol. This SPI operates in the slave mode (does not generate the serial clock). The SPI interface uses up to four pins. These are: * * * * CS - Chip Select SCK - Serial Clock SDI - Serial Data In SDO - Serial Data Out Typical SPI Interfaces are shown in Figure 6-1. In the SPI interface, The Master's Output pin is connected to the Slave's Input pin and the Master's Input pin is connected to the Slave's Output pin. The MCP4XXX SPI's module supports two (of the four) standard SPI modes. These are Mode 0,0 and 1,1. The SPI mode is determined by the state of the SCK pin (VIH or VIL) on the when the CS pin transitions from inactive (VIH) to active (VIL or VIHH). All SPI interface signals are high-voltage tolerant. Typical SPI Interface Connections Host Controller MCP4XXX SDO ( Master Out - Slave In (MOSI) ) SDI SDI ( Master In - Slave Out (MISO) ) SDO SCK SCK I/O (1) CS Typical MCP41X1 SPI Interface Connections (Host Controller Hardware SPI) Host Controller MCP41X1 SDI/SDO SDO SDI SDI R1(2) SDO SCK I/O (1) SCK CS Alternate MCP41X1 SPI Interface Connections (Host Controller Firmware SPI) Host Controller I/O (SDO/SDI) MCP41X1 SDI/SDO SDI SDO I/O (SCK) I/O (1) SCK CS Note 1: If High voltage commands are desired, some type of external circuitry needs to be implemented. 2: FIGURE 6-1: R1 must be sized to ensure VIL and VIH of the devices are met. Typical SPI Interface Block Diagram. (c) 2008 Microchip Technology Inc. DS22059B-page 39 MCP414X/416X/424X/426X 6.1 SDI, SDO, SCK, and CS Operation The operation of the four SPI interface pins are discussed in this section. These pins are: * * * * SDI (Serial Data In) SDO (Serial Data Out) SCK (Serial Clock) CS (Chip Select) 6.1.3 Note: SDI/SDO MCP41X1 Devices Only . For device packages that do not have enough pins for both an SDI and SDO pin, the SDI and SDO functionality is multiplexed onto a single I/O pin called SDI/SDO. The serial interface works on either 8-bit or 16-bit boundaries depending on the selected command. The Chip Select (CS) pin frames the SPI commands. The SDO will only be driven for the command error bit (CMDERR) and during the data bits of a read command (after the memory address and command has been received). 6.1.1 6.1.3.1 SERIAL DATA IN (SDI) The Serial Data In (SDI) signal is the data signal into the device. The value on this pin is latched on the rising edge of the SCK signal. 6.1.2 SERIAL DATA OUT (SDO) The Serial Data Out (SDO) signal is the data signal out of the device. The value on this pin is driven on the falling edge of the SCK signal. Once the CS pin is forced to the active level (VIL or VIHH), the SDO pin will be driven. The state of the SDO pin is determined by the serial bit's position in the command, the command selected, and if there is a command error state (CMDERR). SDI/SDO Operation Figure 6-2 shows a block diagram of the SDI/SDO pin. The SDI signal has an internal "smart" pull-up. The value of this pull-up determines the frequency that data can be read from the device. An external pull-up can be added to the SDI/SDO pin to improve the rise time and therefore improve the frequency that data can be read. Note: To support the High voltage requirement of the SDI function, the SDO function is an open-drain output. Data written on the SDI/SDO pin can be at the maximum SPI frequency. Note: Care must be take to ensure that a Drive conflict does not exist between the Host Controllers SDO pin (or software SDI/SDO pin) and the MCP41x1 SDI/SDO pin (see Figure 6-1). On the falling edge of the SCK pin during the C0 bit (see Figure 7-1), the SDI/SDO pin will start outputting the SDO value. The SDO signal overrides the control of the smart pull-up, such that whenever the SDI/SDO pin is outputting data, the smart pull-up is enabled. The SDI/SDO pin will change from an input (SDI) to an output (SDO) after the state machine has received the Address and Command bits of the Command Byte. If the command is a Read command, then the SDI/SDO pin will remain an output for the remainder of the command. For any other command, the SDI/SDO pin returns to an input. "smart" pull-up SDI/SDO SDI Open Drain Control Logic FIGURE 6-2: Diagram. DS22059B-page 40 SDO Serial I/O Mux Block (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 6.1.4 SERIAL CLOCK (SCK) (SPI FREQUENCY OF OPERATION) 6.1.5 THE CS SIGNAL The SPI interface is specified to operate up to 10 MHz. The actual clock rate depends on the configuration of the system and the serial command used. Table 6-1 shows the SCK frequency for different configurations. The Chip Select (CS) signal is used to select the device and frame a command sequence. To start a command, or sequence of commands, the CS signal must transition from the inactive state (VIH) to an active state (VIL or VIHH). TABLE 6-1: After the CS signal has gone active, the SDO pin is driven and the clock bit counter is reset. SCK FREQUENCY Command Memory Type Access Read Non-Volatile Memory Write, Increment, Decrement SDI, SDO 10 MHz 10 MHz (2, 3) (4) SDI/SDO 250 kHz 10 MHz (2, 3) (1) Volatile Memory SDI, SDO 10 MHz SDI/SDO 250 kHz (4) 10 MHz 10 MHz (1) Note 1: MCP41X1 devices only 2: Non-Volatile memory does not support the Increment or Decrement command. 3: After a Write command, the internal write cycle must complete before the next SPI command is received. 4: This is the maximum clock frequency without an external pull-up resistor. Note: There is a required delay after the CS pin goes active to the 1st edge of the SCK pin. If an error condition occurs for an SPI command, then the Command byte's Command Error (CMDERR) bit (on the SDO pin) will be driven low (VIL). To exit the error condition, the user must take the CS pin to the VIH level. When the CS pin returns to the inactive state (VIH) the SPI module resets (including the address pointer). While the CS pin is in the inactive state (VIH), the serial interface is ignored. This allows the Host Controller to interface to other SPI devices using the same SDI, SDO, and SCK signals. The CS pin has an internal pull-up resistor. The resistor is disabled when the voltage on the CS pin is at the VIL level. This means that when the CS pin is not driven, the internal pull-up resistor will pull this signal to the VIH level. When the CS pin is driven low (VIL), the resistance becomes very large to reduce the device current consumption. The high voltage capability of the CS pin allows High Voltage commands. High Voltage commands allow the device's WiperLock Technology and write protect features to be enabled and disabled. (c) 2008 Microchip Technology Inc. DS22059B-page 41 MCP414X/416X/424X/426X 6.2 The SPI Modes 6.3 The SPI module supports two (of the four) standard SPI modes. These are Mode 0,0 and 1,1. The mode is determined by the state of the SDI pin on the rising edge of the 1st clock bit (of the 8-bit byte). 6.2.1 Figure 6-3 through Figure 6-8 show the different SPI command waveforms. Figure 6-3 and Figure 6-4 are read and write commands. Figure 6-5 and Figure 6-6 are read commands when the SDI and SDO pins are multiplexed on the same pin (SDI/SDO). Figure 6-7 and Figure 6-8 are increment and decrement commands. The high voltage increment and decrement commands are used to enable and disable WiperLock Technology and Write Protect. MODE 0,0 In Mode 0,0: SCK idle state = low (VIL), data is clocked in on the SDI pin on the rising edge of SCK and clocked out on the SDO pin on the falling edge of SCK. 6.2.2 SPI Waveforms MODE 1,1 In Mode 1,1: SCK idle state = high (VIH), data is clocked in on the SDI pin on the rising edge of SCK and clocked out on the SDO pin on the falling edge of SCK. VIH CS VIHH VIL SCK Write to SSPBUF CMDERR bit SDO bit15 bit14 bit13 bit12 bit11 SDI AD3 AD2 AD1 AD0 bit15 bit14 bit13 bit12 C1 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 X bit9 D8 bit8 D7 bit7 D6 bit6 D5 bit5 D4 bit4 D3 bit3 D2 D1 bit2 bit1 C0 bit1 bit0 D0 bit0 Input Sample FIGURE 6-3: VIH CS 16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1). VIHH VIL SCK Write to SSPBUF SDO SDI CMDERR bit bit15 bit14 bit13 bit12 bit11 AD3 AD2 AD1 AD0 bit15 bit14 bit13 bit12 C1 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 X bit9 D8 bit8 D7 bit7 D6 bit6 D5 bit5 D4 bit4 D3 bit3 D2 D1 bit2 bit1 C0 bit1 bit0 D0 bit0 Input Sample FIGURE 6-4: DS22059B-page 42 16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0). (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X VIH CS VIHH VIL SCK Write to SSPBUF CMDERR bit D9 D8 D7 bit9 bit8 bit7 SDO AD3 AD2 AD1 AD0 bit15 bit14 bit13 bit12 SDI C1 1 C0 1 (1) (1) (1) D6 bit6 D5 bit5 D4 bit4 D3 bit3 D2 bit2 D1 bit1 D0 bit0 (1) (1) (1) (1) (1) (1) (1) Input Sample Note 1: The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven FIGURE 6-5: 16-Bit Read Command for Devices with SDI/SDO multiplexed SPI Waveform (Mode 1,1). VIH CS VIHH VIL SCK Write to SSPBUF CMDERR bit D8 D7 X bit9 bit8 bit7 SDO SDI AD3 AD2 AD1 AD0 bit15 bit14 bit13 bit12 C1 C0 1 1 (1) (1) (1) D4 D3 bit6 D6 bit5 D5 bit4 bit3 bit2 D2 bit1 D1 bit0 D0 (1) (1) (1) (1) (1) (1) (1) Input Sample Note 1: The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven FIGURE 6-6: 16-Bit Read Command for Devices with SDI/SDO multiplexed SPI Waveform (Mode 0,0). (c) 2008 Microchip Technology Inc. DS22059B-page 43 MCP414X/416X/424X/426X CS VIH VIHH VIL SCK Write to SSPBUF CMDERR bit "1" = "Valid" Command/Address "0" = "Invalid" Command/Address SDO bit7 SDI AD3 bit6 AD2 bit5 AD1 bit4 AD0 bit3 C1 bit2 C0 bit1 X bit0 X bit0 bit7 Input Sample FIGURE 6-7: 8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock Technology) - SPI Waveform with PIC MCU (Mode 1,1). VIH CS VIHH VIL SCK Write to SSPBUF SDO SDI CMDERR bit "1" = "Valid" Command/Address "0" = "Invalid" Command/Address bit7 AD3 bit7 bit6 AD2 bit5 AD1 bit4 AD0 bit3 C1 bit2 C0 bit1 X bit0 X bit0 Input Sample FIGURE 6-8: 8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock Technology) - SPI Waveform with PIC MCU (Mode 0,0). DS22059B-page 44 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 7.0 DEVICE COMMANDS 7.1 Command Byte The Command Byte has three fields, the Address, the Command, and 2 Data bits, see Figure 7-1. Currently only one of the data bits is defined (D8). This is for the Write command. The MCP4XXX's SPI command format supports 16 memory address locations and four commands. Each command has two modes. These are: * Normal Serial Commands * High-Voltage Serial Commands The device memory is accessed when the master sends a proper Command Byte to select the desired operation. The memory location getting accessed is contained in the Command Byte's AD3:AD0 bits. The action desired is contained in the Command Byte's C1:C0 bits, see Table 7-1. C1:C0 determines if the desired memory location will be read, written, Incremented (wiper setting +1) or Decremented (wiper setting -1). The Increment and Decrement commands are only valid on the volatile wiper registers, and in High Voltage commands to enable/disable WiperLock Technology and Software Write Protect. Normal serial commands are those where the CS pin is driven to VIL. With High-Voltage Serial Commands, the CS pin is driven to VIHH. In each mode, there are four possible commands. These commands are shown in Table 7-1. The 8-bit commands (Increment Wiper and Decrement Wiper commands) contain a Command Byte, see Figure 7-1, while 16-bit commands (Read Data and Write Data commands) contain a Command Byte and a Data Byte. The Command Byte contains two data bits, see Figure 7-1. As the Command Byte is being loaded into the device (on the SDI pin), the device's SDO pin is driving. The SDO pin will output high bits for the first six bits of that command. On the 7th bit, the SDO pin will output the CMDERR bit state (see Section 7.3 "Error Condition"). The 8th bit state depends on the the command selected. Table 7-2 shows the supported commands for each memory location and the corresponding values on the SDI and SDO pins. Table 7-3 shows an overview of all the SPI commands and their interaction with other device features. TABLE 7-1: COMMAND BIT OVERVIEW C1:C0 Bit Command States 11 00 01 10 Operates on Volatile/ Non-Volatile memory # of Bits Read Data 16-Bits Both Write Data 16-Bits Both Increment (1) 8-Bits Volatile Only Decrement (1) 8-Bits Volatile Only Note 1: High Voltage Increment and Decrement commands on select non-volatile memory locations enable/disable WiperLock Technology and the software Write Protect feature. 16-bit Command 8-bit Command Command Byte A A A A C C D D D D D D 1 0 9 8 3 2 1 0 Memory Address Data Bits Command Bits FIGURE 7-1: Command Byte Data Byte A A A A C C D D D D D D D D D D D D D D 1 0 9 8 7 6 5 4 3 2 1 0 3 2 1 0 Data Bits Memory Address Command Bits Command Bits CC 1 0 0 0 = Write Data 0 1 = INCR 1 0 = DECR 1 1 = Read Data General SPI Command Formats. (c) 2008 Microchip Technology Inc. DS22059B-page 45 MCP414X/416X/424X/426X TABLE 7-2: MEMORY MAP AND THE SUPPORTED COMMANDS Address Command Value 00h 01h 02h 03h Function Volatile Wiper 0 Volatile Wiper 1 NV Wiper 0 NV Wiper 1 Data (10-bits) (1) SPI String (Binary) MISO (SDO pin) (2) MOSI (SDI pin) Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn Increment Wiper -- 0000 0100 1111 1111 Decrement Wiper -- 0000 1000 1111 1111 Write Data nn nnnn nnnn 0001 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 0001 11nn nnnn nnnn 1111 111n nnnn nnnn Increment Wiper -- 0001 0100 1111 1111 Decrement Wiper -- 0001 1000 1111 1111 Write Data nn nnnn nnnn 0010 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 0010 11nn nnnn nnnn 1111 111n nnnn nnnn HV Inc. (WL0 DIS) (3) -- 0010 0100 1111 1111 HV Dec. (WL0 EN) (4) -- 0010 1000 1111 1111 Write Data nn nnnn nnnn 0011 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 0011 11nn nnnn nnnn 1111 111n nnnn nnnn HV Inc. (WL1 DIS) (3) -- 0011 0100 1111 1111 HV Dec. (WL1 EN) (4) -- 0011 1000 1111 1111 04h (5) Volatile TCON Register Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn 05h (5) Status Register Read Data nn nnnn nnnn 0101 11nn nnnn nnnn 1111 111n nnnn nnnn 06h (5) Data EEPROM Write Data nn nnnn nnnn 0110 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 0110 11nn nnnn nnnn 1111 111n nnnn nnnn 07h (5) Data EEPROM Write Data nn nnnn nnnn 0111 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 0111 11nn nnnn nnnn 1111 111n nnnn nnnn 08h (5) Data EEPROM Write Data nn nnnn nnnn 1000 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 1000 11nn nnnn nnnn 1111 111n nnnn nnnn 09h (5) Data EEPROM Write Data nn nnnn nnnn 1001 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 1001 11nn nnnn nnnn 1111 111n nnnn nnnn 0Ah (5) Data EEPROM Write Data nn nnnn nnnn 1010 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 1010 11nn nnnn nnnn 1111 111n nnnn nnnn 0Bh (5) Data EEPROM Write Data nn nnnn nnnn 1011 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 1011 11nn nnnn nnnn 1111 111n nnnn nnnn Write Data nn nnnn nnnn 1100 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 1100 11nn nnnn nnnn 1111 111n nnnn nnnn 0Dh (5) Data EEPROM Write Data nn nnnn nnnn 1101 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 1101 11nn nnnn nnnn 1111 111n nnnn nnnn 0Eh (5) Data EEPROM Write Data nn nnnn nnnn 1110 00nn nnnn nnnn 1111 1111 1111 1111 0Ch (5) Data EEPROM 0Fh Data EEPROM Note 1: 2: 3: 4: 5: Read Data nn nnnn nnnn 1110 11nn nnnn nnnn 1111 111n nnnn nnnn Write Data nn nnnn nnnn 1111 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 1111 11nn nnnn nnnn 1111 111n nnnn nnnn HV Inc. (WP DIS) (3) -- 1111 0100 1111 1111 HV Dec. (WP EN) (4) -- 1111 1000 1111 1111 The Data Memory is only 9-bits wide, so the MSb is ignored by the device. All these Address/Command combinations are valid, so the CMDERR bit is set. Any other Address/Command combination is a command error state and the CMDERR bit will be clear. Disables WiperLock Technology for wiper 0 or wiper 1, or disables Write Protect. Enables WiperLock Technology for wiper 0 or wiper 1, or enables Write Protect. Reserved addresses: Increment or Decrement commands are invalid for these addresses. DS22059B-page 46 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 7.2 Data Byte Only the Read Command and the Write Command use the Data Byte, see Figure 7-1. These commands concatenate the 8-bits of the Data Byte with the one data bit (D8) contained in the Command Byte to form 9-bits of data (D8:D0). The Command Byte format supports up to 9-bits of data so that the 8-bit resistor network can be set to Full Scale (100h or greater). This allows wiper connections to Terminal A and to Terminal B. The D9 bit is currently unused, and corresponds to the position on the SDO data of the CMDERR bit. 7.3 Error Condition The CMDERR bit indicates if the four address bits received (AD3:AD0) and the two command bits received (C1:C0) are a valid combination (see Table 4-1). The CMDERR bit is high if the combination is valid and low if the combination is invalid. The command error bit will also be low if a write to a Non-Volatile Address has been specified and another SPI command occurs before the CS pin is driven inactive (VIH). SPI commands that do not have a multiple of 8 clocks are ignored. Once an error condition has occurred, any following commands are ignored. All following SDO bits will be low until the CMDERR condition is cleared by forcing the CS pin to the inactive state (VIH). (c) 2008 Microchip Technology Inc. 7.3.1 ABORTING A TRANSMISSION All SPI transmissions must have the correct number of SCK pulses to be executed. The command is not executed until the complete number of clocks have been received. Some commands also require the CS pin to be forced inactive (VIH). If the CS pin is forced to the inactive state (VIH) the serial interface is reset. Partial commands are not executed. SPI is more susceptible to noise than other bus protocols. The most likely case is that this noise corrupts the value of the data being clocked into the MCP4XXX or the SCK pin is injected with extra clock pulses. This may cause data to be corrupted in the device, or a command error to occur, since the address and command bits were not a valid combination. The extra SCK pulse will also cause the SPI data (SDI) and clock (SCK) to be out of sync. Forcing the CS pin to the inactive state (VIH) resets the serial interface. The SPI interface will ignore activity on the SDI and SCK pins until the CS pin transition to the active state is detected (VIH to VIL or VIH to VIHH). Note 1: When data is not being received by the MCP4XXX, It is recommended that the CS pin be forced to the inactive level (VIL) 2: It is also recommended that long continuous command strings should be broken down into single commands or shorter continuous command strings. This reduces the probability of noise on the SCK pin corrupting the desired SPI commands. DS22059B-page 47 MCP414X/416X/424X/426X 7.4 Continuous Commands The device supports the ability to execute commands continuously. While the CS pin is in the active state (VIL or VIHH). Any sequence of valid commands may be received. The following example is a valid sequence of events: 1. 2. 3. 4. 5. 6. 7. 8. Note 1: It is recommended that while the CS pin is active, only one type of command should be issued. When changing commands, it is recommended to take the CS pin inactive then force it back to the active state. 2: It is also recommended that long command strings should be broken down into shorter command strings. This reduces the probability of noise on the SCK pin corrupting the desired SPI command string. CS pin driven active (VIL or VIHH). Read Command. Increment Command (Wiper 0). Increment Command (Wiper 0). Decrement Command (Wiper 1). Write Command (Volatile memory). Write Command (Non-Volatile memory). CS pin driven inactive (VIH). TABLE 7-3: COMMANDS Command Name # of Bits Operates on High Writes Volatile/ Voltage Value in Non-Volatile (VIHH) on EEPROM CS pin? memory Impact on WiperLock or Write Protect Works when Wiper is "locked"? Write Data 16-Bits Yes (1) Both -- unlocked (1) No Read Data 16-Bits -- Both -- unlocked (1) No (1) No No Increment Wiper 8-Bits -- Volatile Only -- unlocked Decrement Wiper 8-Bits -- Volatile Only -- unlocked (1) High Voltage Write Data 16-Bits Yes Both Yes unchanged No High Voltage Read Data 16-Bits -- Both Yes unchanged Yes High Voltage Increment Wiper 8-Bits -- Volatile Only Yes unchanged No High Voltage Decrement Wiper 8-Bits -- Volatile Only Yes unchanged No (2) Non-Volatile Only (2) Yes locked/ protected (2) Yes Non-Volatile Only (3) Yes unlocked/ unprotected (3) Yes Modify Write Protect or WiperLock Technology (High Voltage) Enable 8-Bits -- Modify Write Protect or WiperLock Technology (High Voltage) Disable 8-Bits -- (3) Note 1: This command will only complete if wiper is "unlocked" (WiperLock Technology is Disabled). 2: If the command is executed using address 02h or 03h, then that corresponding wiper is locked or if with address 0Fh, then Write Protect is enabled. 3: If the command is executed using with address 02h or 03h, then that corresponding wiper is unlocked or if with address 0Fh, then Write Protect is disabled. DS22059B-page 48 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 7.5 7.5.2 Write Data Normal and High Voltage The sequence to write to to a single non-volatile memory location is the same as a single write to volatile memory with the exception that after the CS pin is driven inactive (VIH), the EEPROM write cycle (tWC) is started. A write cycle will not start if the write command isn't exactly 16 clocks pulses. This protects against system issues from corrupting the Non-Volatile memory locations. The Write command is a 16-bit command. The Write Command can be issued to both the Volatile and Non-Volatile memory locations. The format of the command is shown in Figure 7-2. A Write command to a Volatile memory location changes that location after a properly formatted Write Command (16-clock) have been received. A Write command to a Non-Volatile memory location will only start a write cycle after a properly formatted Write Command (16-clock) have been received and the CS pin transitions to the inactive state (VIH). Note: 7.5.1 SINGLE WRITE TO NON-VOLATILE MEMORY After the CS pin is driven inactive (VIH), the serial interface may immediately be re-enabled by driving the CS pin to the active state (VILor VIHH). During an EEPROM write cycle, only serial commands to Volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. All other serial commands are ignored until the EEPROM write cycle (twc) completes. This allows the Host Controller to operate on the Volatile Wiper registers and the TCON register, and to Read the Status Register. The EEWA bit in the Status register indicates the status of an EEPROM Write Cycle. Writes to certain memory locations will be dependant on the state of the WiperLock Technology bits and the Write Protect bit. SINGLE WRITE TO VOLATILE MEMORY The write operation requires that the CS pin be in the active state (VILor VIHH). Typically, the CS pin will be in the inactive state (VIH) and is driven to the active state (VIL). The 16-bit Write Command (Command Byte and Data Byte) is then clocked in on the SCK and SDI pins. Once all 16 bits have been received, the specified volatile address is updated. A write will not occur if the write command isn't exactly 16 clocks pulses. This protects against system issues from corrupting the Non-Volatile memory locations. Once a write command to a Non-Volatile memory location has been received, NO other SPI commands should be received before the CS pin transitions to the inactive state (VIH) or the current SPI command will have a Command Error (CMDERR) occur. Figure 6-3 and Figure 6-4 show possible waveforms for a single write. COMMAND BYTE A D 3 1 SDO 1 SDI A D 2 1 1 A D 1 1 1 A D 0 1 1 DATA BYTE 0 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Valid Address/Command combination 0 Invalid Address/Command combination (1) Note 1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state). FIGURE 7-2: Write Command - SDI and SDO States. (c) 2008 Microchip Technology Inc. DS22059B-page 49 MCP414X/416X/424X/426X 7.5.3 CONTINUOUS WRITES TO VOLATILE MEMORY 7.5.4 Continuous writes are possible only when writing to the volatile memory registers (address 00h, 01h, and 04h). Continuous writes to non-volatile memory are not allowed, and attempts to do so will result in a command error (CMDERR) condition. Figure 7-3 shows the sequence for three continuous writes. The writes do not need to be to the same volatile memory address. COMMAND BYTE SDI SDO A D 3 1 A D 2 1 A D 1 1 A D 0 1 A D 3 1 A D 2 1 A D 1 1 A D 0 1 A D 3 1 A D 2 1 A D 1 1 A D 0 1 CONTINUOUS WRITES TO NON-VOLATILE MEMORY DATA BYTE 0 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 1 1 1* 1 1 1 1 1 1 1 1 1 0 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 1 1 1* 1 1 1 1 1 1 1 1 1 0 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 1 1 1* 1 1 1 1 1 1 1 1 1 Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH). FIGURE 7-3: DS22059B-page 50 Continuous Write Sequence (Volatile Memory only). (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 7.6 7.6.1 Read Data Normal and High Voltage The read operation requires that the CS pin be in the active state (VILor VIHH). Typically, the CS pin will be in the inactive state (VIH) and is driven to the active state (VILor VIHH). The 16-bit Read Command (Command Byte and Data Byte) is then clocked in on the SCK and SDI pins. The SDO pin starts driving data on the 7th bit (CMDERR bit) and the addressed data comes out on the 8th through 16th clocks. Figure 6-3 through Figure 6-6 show possible waveforms for a single read. The Read command is a 16-bit command. The Read Command can be issued to both the Volatile and Non-Volatile memory locations. The format of the command is shown in Figure 7-4. The first 6-bits of the Read command determine the address and the command. The 7th clock will output the CMDERR bit on the SDO pin. The remaining 9-clocks the device will transmit the 9 data bits (D8:D0) of the specified address (AD3:AD0). Figure 6-5 and Figure 6-6 show the single read waveforms when the SDI and SDO signals are multiplexed on the same pin. For additional information on the multiplexing of these signals, refer to Section 6.1.3 "SDI/SDO". Figure 7-4 shows the SDI and SDO information for a Read command. During a write cycle (Write or High Voltage Write to a Non-Volatile memory location) the Read command can only read the Volatile memory locations. By reading the Status Register (04h), the Host Controller can determine when the write cycle has completed (via the state of the EEWA bit). COMMAND BYTE SDI SDO SINGLE READ DATA BYTE A D 3 1 A D 2 1 A D 1 1 A D 0 1 1 1 X X X X X X X X X X 1 1 1 1 1 1 1 1 1 0 D 8 0 D 7 0 D 6 0 D 5 0 D 4 0 D 3 0 D 2 0 D 1 0 D Valid Address/Command combination 0 0 Attempted Non-Volatile Memory Read during Non-Volatile Memory Write Cycle READ DATA FIGURE 7-4: Read Command - SDI and SDO States. (c) 2008 Microchip Technology Inc. DS22059B-page 51 MCP414X/416X/424X/426X 7.6.2 CONTINUOUS READS Figure 7-5 shows the sequence for three continuous reads. The reads do not need to be to the same memory address. Continuous reads allows the devices memory to be read quickly. Continuous reads are possible to all memory locations. If a non-volatile memory write cycle is occurring, then Read commands may only access the volatile memory locations. COMMAND BYTE SDI SDO A D 3 1 A D 2 1 A D 1 1 A D 0 1 A D 3 1 A D 2 1 A D 1 1 A D 0 1 A D 3 1 A D 2 1 A D 1 1 A D 0 1 DATA BYTE 1 1 X X X X X X X X X X 1 1 1* D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 1 1 X X X X X X X X X X 1 1 1* D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 1 1 X X X X X X X X X X 1 1 1* D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH). FIGURE 7-5: DS22059B-page 52 Continuous Read Sequence. (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 7.7 Increment Wiper Normal and High Voltage The Increment Command is an 8-bit command. The Increment Command can only be issued to volatile memory locations. The format of the command is shown in Figure 7-6. An Increment Command to the volatile memory location changes that location after a properly formatted command (8-clocks) have been received. Increment commands provide a quick and easy method to modify the value of the volatile wiper location by +1 with minimal overhead. COMMAND BYTE (INCR COMMAND (n+1) ) A D 3 1 SDO 1 SDI A D 2 1 1 A D 1 1 1 A D 0 1 1 0 1 X X 1 1 1 1 1* 0 1 Note 1, 2 0 Note 1, 3 Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination all following SDO bits will be low until the CMDERR condition is cleared. (the CS pin is forced to the inactive state). 4: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH). FIGURE 7-6: Increment Command SDI and SDO States. Note: Table 7-2 shows the valid addresses for the Increment Wiper command. Other addresses are invalid. (c) 2008 Microchip Technology Inc. 7.7.1 SINGLE INCREMENT Typically, the CS pin starts at the inactive state (VIH), but may be already be in the active state due to the completion of another command. Figure 6-7 through Figure 6-8 show possible waveforms for a single increment. The increment operation requires that the CS pin be in the active state (VILor VIHH). Typically, the CS pin will be in the inactive state (VIH) and is driven to the active state (VILor VIHH). The 8-bit Increment Command (Command Byte) is then clocked in on the SDI pin by the SCK pins. The SDO pin drives the CMDERR bit on the 7th clock. The wiper value will increment up to 100h on 8-bit devices and 80h on 7-bit devices. After the wiper value has reached Full Scale (8-bit =100h, 7-bit =80h), the wiper value will not be incremented further. If the Wiper register has a value between 101h and 1FFh, the Increment command is disabled. See Table 7-4 for additional information on the Increment Command versus the current volatile wiper value. The Increment operations only require the Increment command byte while the CS pin is active (VILor VIHH) for a single increment. After the wiper is incremented to the desired position, the CS pin should be forced to VIH to ensure that unexpected transitions on the SCK pin do not cause the wiper setting to change. Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired increment occurs. TABLE 7-4: Current Wiper Setting 7-bit Pot 8-bit Pot 3FFh 081h 080h 07Fh 041h 040h 03Fh 001h 000h 3FFh 101h 100h 0FFh 081 080h 07Fh 001 000h INCREMENT OPERATION VS. VOLATILE WIPER VALUE Increment Command Operates? Wiper (W) Properties Reserved (Full-Scale (W = A)) Full-Scale (W = A) W=N No W = N (Mid-Scale) W=N Yes Zero Scale (W = B) Yes No DS22059B-page 53 MCP414X/416X/424X/426X 7.7.2 CONTINUOUS INCREMENTS Increment commands can be sent repeatedly without raising CS until a desired condition is met. The value in the Volatile Wiper register can be read using a Read Command and written to the corresponding Non-Volatile Wiper EEPROM using a Write Command. Continuous Increments are possible only when writing to the volatile memory registers (address 00h, and 01h). Figure 7-7 shows a Continuous Increment sequence for three continuous writes. The writes do not need to be to the same volatile memory address. When executing a continuous command string, The Increment command can be followed by any other valid command. When executing an continuous Increment commands, the selected wiper will be altered from n to n+1 for each Increment command received. The wiper value will increment up to 100h on 8-bit devices and 80h on 7-bit devices. After the wiper value has reached Full-Scale (8-bit =100h, 7-bit =80h), the wiper value will not be incremented further. If the Wiper register has a value between 101h and 1FFh, the Increment command is disabled. (INCR COMMAND (n+1) ) A D 3 1 1 SDO 1 1 A D 2 1 1 1 1 A D 1 1 1 1 1 A D 0 1 1 1 1 After the wiper is incremented to the desired position, the CS pin should be forced to VIH to ensure that unexpected transitions (on the SCK pin do not cause the wiper setting to change). Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired increment occurs. COMMAND BYTE COMMAND BYTE COMMAND BYTE SDI The wiper terminal will move after the command has been received (8th clock). (INCR COMMAND (n+2) ) 0 1 X X 1 1 1 1 1 1 1 1 1* 0 1 1 1 0 1 1 A D 3 1 0 1 1 A D 2 1 0 1 1 A D 1 1 0 1 1 A D 0 1 0 1 1 (INCR COMMAND (n+3) ) 0 1 X X 1 0 1 1 1 0 1 1 1* 0 0 1 1 0 0 1 A D 3 1 0 0 1 A D 2 1 0 0 1 A D 1 1 0 0 1 A D 0 1 0 0 1 0 1 X X 1 0 0 1 1 0 0 1 1* 0 0 0 1 0 0 0 Note 1, 2 Note 3, 4 Note 3, 4 Note 3, 4 Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination. 4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state). FIGURE 7-7: DS22059B-page 54 Continuous Increment Command - SDI and SDO States. (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 7.8 Decrement Wiper Normal and High Voltage The Decrement Command is an 8-bit command. The Decrement Command can only be issued to volatile memory locations. The format of the command is shown in Figure 7-6. An Decrement Command to the volatile memory location changes that location after a properly formatted command (8-clocks) have been received. Decrement commands provide a quick and easy method to modify the value of the volatile wiper location by -1 with minimal overhead. COMMAND BYTE (DECR COMMAND (n+1)) A D 3 1 SDO 1 SDI A D 2 1 1 A D 1 1 1 A D 0 1 1 1 0 X X 1 1 1 1 1* 0 1 Note 1, 2 0 Note 1, 3 Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination all following SDO bits will be low until the CMDERR condition is cleared. (the CS pin is forced to the inactive state). 4: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH). FIGURE 7-8: Decrement Command SDI and SDO States. Note: Table 7-2 shows the valid addresses for the Decrement Wiper command. Other addresses are invalid. (c) 2008 Microchip Technology Inc. 7.8.1 SINGLE DECREMENT Typically the CS pin starts at the inactive state (VIH), but may be already be in the active state due to the completion of another command. Figure 6-7 through Figure 6-8 show possible waveforms for a single Decrement. The decrement operation requires that the CS pin be in the active state (VILor VIHH). Typically the CS pin will be in the inactive state (VIH) and is driven to the active state (VILor VIHH). Then the 8-bit Decrement Command (Command Byte) is clocked in on the SDI pin by the SCK pins. The SDO pin drives the CMDERR bit on the 7th clock. The wiper value will decrement from the wipers Full Scale value (100h on 8-bit devices and 80h on 7-bit devices). Above the wipers Full Scale value (8-bit =101h to 1FFh, 7-bit = 81h to FFh), the decrement command is disabled. If the Wiper register has a Zero Scale value (000h), then the wiper value will not decrement. See Table 7-4 for additional information on the Decrement Command vs. the current volatile wiper value. The Decrement commands only require the Decrement command byte, while the CS pin is active (VILor VIHH) for a single decrement. After the wiper is decremented to the desired position, the CS pin should be forced to VIH to ensure that unexpected transitions on the SCK pin do not cause the wiper setting to change. Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired decrement occurs. TABLE 7-5: Current Wiper Setting 7-bit Pot 8-bit Pot 3FFh 081h 080h 07Fh 041h 040h 03Fh 001h 000h 3FFh 101h 100h 0FFh 081 080h 07Fh 001 000h DECREMENT OPERATION VS. VOLATILE WIPER VALUE Decrement Command Operates? Wiper (W) Properties Reserved (Full-Scale (W = A)) Full-Scale (W = A) W=N No Yes W = N (Mid-Scale) W=N Yes Zero Scale (W = B) No DS22059B-page 55 MCP414X/416X/424X/426X 7.8.2 CONTINUOUS DECREMENTS Decrement commands can be sent repeatedly without raising CS until a desired condition is met. The value in the Volatile Wiper register can be read using a Read Command and written to the corresponding Non-Volatile Wiper EEPROM using a Write Command. Continuous Decrements are possible only when writing to the volatile memory registers (address 00h, 01h, and 04h). Figure 7-9 shows a continuous Decrement sequence for three continuous writes. The writes do not need to be to the same volatile memory address. When executing a continuous command string, The Decrement command can be followed by any other valid command. When executing an continuous Decrement commands, the selected wiper will be altered from n to n-1 for each Decrement command received. The wiper value will decrement from the wipers Full Scale value (100h on 8-bit devices and 80h on 7-bit devices). Above the wipers Full-Scale value (8-bit =101h to 1FFh, 7-bit = 81h to FFh), the decrement command is disabled. If the Wiper register has a Zero Scale value (000h), then the wiper value will not decrement. See Table 7-4 for additional information on the Decrement Command vs. the current volatile wiper value. (DECR COMMAND (n-1) ) A D 3 1 1 SDO 1 1 A D 2 1 1 1 1 A D 1 1 1 1 1 A D 0 1 1 1 1 After the wiper is decremented to the desired position, the CS pin should be forced to VIH to ensure that "unexpected" transitions (on the SCK pin do not cause the wiper setting to change). Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired decrement occurs. COMMAND BYTE COMMAND BYTE COMMAND BYTE SDI The wiper terminal will move after the command has been received (8th clock). 1 0 X X 1 1 1 1 1 1 1 1 1* 0 1 1 1 0 1 1 (DECR COMMAND (n-1) ) A D 3 1 0 1 1 A D 2 1 0 1 1 A D 1 1 0 1 1 A D 0 1 0 1 1 1 0 X X 1 0 1 1 1 0 1 1 1* 0 0 1 1 0 0 1 (DECR COMMAND (n-1) ) A D 3 1 0 0 1 A D 2 1 0 0 1 A D 1 1 0 0 1 A D 0 1 0 0 1 1 0 X X 1 0 0 1 1 0 0 1 1* 0 0 0 1 0 0 0 Note 1, 2 Note 3, 4 Note 3, 4 Note 3, 4 Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination. 4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state). FIGURE 7-9: DS22059B-page 56 Continuous Decrement Command - SDI and SDO States. (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 7.9 Modify Write Protect or WiperLock Technology (High Voltage) Enable and Disable This command is a special case of the High Voltage Decrement Wiper and High Voltage Increment Wiper commands to the non-volatile memory locations 02h, 03h, and 0Fh. This command is used to enable or disable either the software Write Protect, wiper 0 WiperLock Technology, or wiper 1 WiperLock Technology. Table 7-6 shows the memory addresses, the High Voltage command and the result of those commands on the non-volatile WP, WL0, 0r WL1 bits. The format of the command is shown in Figure 7-8 (Enable) or Figure 7-6 (Disable). 7.9.1 SINGLE ENABLE WRITE PROTECT OR WIPERLOCK TECHNOLOGY (HIGH VOLTAGE) Figure 6-7 through Figure 6-8 show possible waveforms for a single Modify Write Protect or WiperLock Technology command. A Modify Write Protect or WiperLock Technology Command will only start an EEPROM write cycle (twc) after a properly formatted Command (8-clocks) has been received and the CS pin transitions to the inactive state (VIH). After the CS pin is driven inactive (VIH), the serial interface may immediately be re-enabled by driving the CS pin to the active state (VILor VIHH). During an EEPROM write cycle, only serial commands to Volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. All other serial commands are ignored until the EEPROM write cycle (twc) completes. This allows the Host Controller to operate on the Volatile Wiper registers and the TCON register, and to Read the Status Register. The EEWA bit in the Status register indicates the status of an EEPROM Write Cycle. TABLE 7-6: Memory Address ADDRESS MAP TO MODIFY WRITE PROTECT AND WIPERLOCK TECHNOLOGY Command's and Result High Voltage Decrement Wiper High Voltage Increment Wiper 00h Wiper 0 register is decremented Wiper 0 register is incremented 01h Wiper 1 register is decremented Wiper 1 register is incremented 02h WL0 is enabled WL0 is disabled 03h WL1 is enabled WL1 is disabled 04h (1) TCON register not changed, CMDERR bit is set TCON register not changed, CMDERR bit is set 05h - 0Eh (1) Reserved Reserved 0Fh WP is enabled WP is disabled Note 1: Reserved addresses: Increment or Decrement commands are invalid for these addresses. (c) 2008 Microchip Technology Inc. DS22059B-page 57 MCP414X/416X/424X/426X NOTES: DS22059B-page 58 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 8.0 APPLICATIONS EXAMPLES Non-volatile digital potentiometers have a multitude of practical uses in modern electronic circuits. The most popular uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. The MCP414X/416X/424X/426X devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within CMOS process limitations (VDD = 2.7V to 5.5V). 8.1 Split Rail Applications All inputs that would be used to interface to a Host Controller support High Voltage on their input pin. This allows the MCP4XXX device to be used in split power rail applications. 5V SDI CS SCK WP SHDN SDO FIGURE 8-1: System 1. Figure 8-1 through Figure 8-2 show three example split rail systems. In this system, the MCP4XXX interface input signals need to be able to support the PIC MCU output high voltage (VOH). In Example #1 (Figure 8-1), the MCP4XXX interface input signals need to be able to support the PIC MCU output high voltage (VOH). If the split rail voltage delta becomes too large, then the customer may be required to do some level shifting due to MCP4XXX VOH levels related to Host Controller VIH levels. In Example #2 (Figure 8-2), the MCP4XXX interface input signals need to be able to support the lower voltage of the PIC MCU output high voltage level (VOH). Table 8-1 shows an example PIC microcontroller I/O voltage specifications and the MCP4XXX specifications. So this PIC MCU operating at 3.3V will drive a VOH at 2.64V, and for the MCP4XXX operating at 5.5V, the VIH is 2.47V. Therefore, the interface signals meet specifications. (c) 2008 Microchip Technology Inc. SDI CS SCK WP SHDN SDO Example Split Rail 5V Voltage Regulator 3V MCP4XXX PIC MCU SDI CS SCK WP SHDN SDI CS SCK WP SHDN For SPI applications, these inputs are: CS SCK SDI (or SDI/SDO) WP SHDN MCP4XXX PIC MCU An example of this is a battery application where the PIC(R) MCU is directly powered by the battery supply (4.8V) and the MCP4XXX device is powered by the 3.3V regulated voltage. * * * * * 3V Voltage Regulator SDO SDO FIGURE 8-2: System 2. Example Split Rail TABLE 8-1: VOH - VIH COMPARISONS PIC (1) MCP4XXX (2) Comment VDD 5.5 5.0 4.5 3.3 3.0 2.7 Note VIH VOH VDD VIH VOH 4.4 4.4 2.7 1.215 -- (3) 4.0 4.0 3.0 1.35 -- (3) 3.6 3.6 3.3 1.485 -- (3) 2.64 2.64 4.5 2.025 -- (3) 2.4 2.4 5.0 2.25 -- (3) 2.16 2.16 5.5 2.475 -- (3) 1: VOH minimum = 0.8 * VDD; VOL maximum = 0.6V VIH minimum = 0.8 * VDD; VIL maximum = 0.2 * VDD; 2: VOH minimum (SDA only) =; VOL maximum = 0.2 * VDD VIH minimum = 0.45 * VDD; VIL maximum = 0.2 * VDD 3: The only MCP4XXX output pin is SDO, which is Open-Drain (or Open-Drain with Internal Pull-up) with High Voltage Support DS22059B-page 59 MCP414X/416X/424X/426X 8.2 Techniques to force the CS pin to VIHH PIC10F206 The circuit in Figure 8-3 shows a method using the TC1240A doubling charge pump. When the SHDN pin is high, the TC1240A is off, and the level on the CS pin is controlled by the PIC(R) microcontrollers (MCUs) IO2 pin. When the SHDN pin is low, the TC1240A is on and the VOUT voltage is 2 * VDD. The resistor R1 allows the CS pin to go higher than the voltage such that the PIC MCU's IO2 pin "clamps" at approximately VDD. PIC MCU TC1240A C+ VIN CSHDN VOUT IO1 IO2 C1 MCP402X R1 CS C2 FIGURE 8-3: Using the TC1240A to generate the VIHH voltage. The circuit in Figure 8-4 shows the method used on the MCP402X Non-volatile Digital Potentiometer Evaluation Board (Part Number: MCP402XEV). This method requires that the system voltage be approximately 5V. This ensures that when the PIC10F206 enters a brown-out condition, there is an insufficient voltage level on the CS pin to change the stored value of the wiper. The MCP402X Non-volatile Digital Potentiometer Evaluation Board User's Guide (DS51546) contains a complete schematic. R1 GP0 MCP4XXX GP2 CS C1 C2 FIGURE 8-4: MCP4XXX Non-volatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the VIHH voltage. 8.3 Using Shutdown Modes Figure 8-5 shows a possible application circuit where the independent terminals could be used. Disconnecting the wiper allows the transistor input to be taken to the Bias voltage level (disconnecting A and or B may be desired to reduce system current). Disconnecting Terminal A modifies the transistor input by the RBW rheostat value to the Common B. Disconnecting Terminal B modifies the transistor input by the RAW rheostat value to the Common A. The Common A and Common B connections could be connected to VDD and VSS. Common A Input A GP0 is a general purpose I/O pin, while GP2 can either be a general purpose I/O pin or it can output the internal clock. For high-voltage serial commands, force the GP0 output pin to output a high level (VOH) and configure the GP2 pin to output the internal clock. This will form a charge pump and increase the voltage on the CS pin (when the system voltage is approximately 5V). To base of Transistor (or Amplifier) W For the serial commands, configure the GP2 pin as an input (high impedance). The output state of the GP0 pin will determine the voltage on the CS pin (VIL or VIH). B Input Common B Balance Bias FIGURE 8-5: Example Application Circuit using Terminal Disconnects. DS22059B-page 60 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 8.4 8.4.2 Design Considerations In the design of a system with the MCP4XXX devices, the following considerations should be taken into account: * Power Supply Considerations * Layout Considerations 8.4.1 POWER SUPPLY CONSIDERATIONS The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-6 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 F. This capacitor should be placed as close (within 4 mm) to the device power pin (VDD) as possible. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane. VDD Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP4XXX's performance. Careful board layout minimizes these effects and increases the Signal-to-Noise Ratio (SNR). Multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. If low noise is desired, breadboards and wire-wrapped boards are not recommended. 8.4.3 VDD Characterization curves of the resistor temperature coefficient (Tempco) are shown in Figure 2-8, Figure 2-19, Figure 2-29, and Figure 2-39. These curves show that the resistor network is designed to correct for the change in resistance as temperature increases. This technique reduces the end to end change is RAB resistance. 8.4.4 VSS FIGURE 8-6: Connections. PIC(R) Microcontroller MCP414X/416X/ 424X/426X B U/D HIGH VOLTAGE TOLERANT PINS High Voltage support (VIHH) on the Serial Interface pins supports two features. These are: Note: 0.1 F W RESISTOR TEMPCO * In-Circuit Accommodation of split rail applications and power supply sync issues * User configuration of the Non-Volatile EEPROM, Write Protect, and WiperLock feature 0.1 F A LAYOUT CONSIDERATIONS In many applications, the High Voltage will only be present at the manufacturing stage so as to "lock" the Non-Volatile wiper value (after calibration) and the contents of the EEPROM. This ensures that the since High Voltage is not present under normal operating conditions, that these values can not be modified. CS VSS Typical Microcontroller (c) 2008 Microchip Technology Inc. DS22059B-page 61 MCP414X/416X/424X/426X NOTES: DS22059B-page 62 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 9.0 DEVELOPMENT SUPPORT 9.1 Development Tools 9.2 Technical Documentation Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table 9-2 shows some of these documents. Several development tools are available to assist in your design and evaluation of the MCP4XXX devices. The currently available tools are shown in Table 9-1. These boards may be purchased directly from the Microchip web site at www.microchip.com. TABLE 9-1: DEVELOPMENT TOOLS Board Name Part # Supported Devices MCP42XX Digital Potentiometer PICtail Plus Demo MCP42XXDM-PTPLS Board MCP42XX MCP4XXX Digital Potentiometer Daughter Board (1) MCP4XXXDM-DB MCP42XXX, MCP42XX, MCP4021, and MCP4011 8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board SOIC8EV Any 8-pin device in DIP, SOIC, MSOP, or TSSOP package 14-pin SOIC/MSOP/DIP Evaluation Board SOIC14EV Any 14-pin device in DIP, SOIC, or MSOP package Note 1: Requires the use of a PICDEM Demo board (see User's Guide for details) TABLE 9-2: TECHNICAL DOCUMENTATION Application Note Number Title Literature # AN1080 Understanding Digital Potentiometers Resistor Variations DS01080 AN737 Using Digital Potentiometers to Design Low Pass Adjustable Filters DS00737 AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692 AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691 AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219 -- Digital Potentiometer Design Guide DS22017 -- Signal Chain Design Guide DS21825 (c) 2008 Microchip Technology Inc. DS22059B-page 63 MCP414X/416X/424X/426X NOTES: DS22059B-page 64 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X 10.0 PACKAGING INFORMATION 10.1 Package Marking Information Example: 8-Lead DFN (3x3) XXXX XYWW NNN Part Number Code Part Number Code MCP4141-502E/MF DAAJ MCP4142-502E/MF DABC MCP4141-103E/MF DAAK MCP4142-103E/MF DABD MCP4141-104E/MF DAAM MCP4142-104E/MF DABF MCP4141-503E/MF DAAL MCP4142-503E/MF DABE MCP4161-502E/MF DAAT MCP4162-502E/MF DABG MCP4161-103E/MF DAAU MCP4162-103E/MF DABH MCP4161-104E/MF DAAW MCP4162-104E/MF DABK MCP4161-503E/MF DAAV MCP4162-503E/MF DABJ Part Number Code Part Number Code MCP4141-502E/MS 414152 MCP4142-502E/MS 414252 MCP4141-103E/MS 414113 MCP4142-103E/MS 414213 MCP4141-104E/MS 414114 MCP4142-104E/MS 414214 MCP4141-503E/MS 414153 MCP4142-503E/MS 414253 MCP4161-502E/MS 416152 MCP4162-502E/MS 416252 MCP4161-103E/MS 416113 MCP4162-103E/MS 416213 MCP4161-104E/MS 416114 MCP4162-104E/MS 416214 MCP4161-503E/MS 416153 MCP4162-503E/MS 416253 8-Lead MSOP XXXXXX YWWNNN Legend: XX...X Y YY WW NNN e3 * Note: DAAJ E816 256 Example 414152 816256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2008 Microchip Technology Inc. DS22059B-page 65 MCP414X/416X/424X/426X 8-Lead PDIP XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC 4141-502 E/P e3 256 0816 Example XXXXXXXX XXXXYYWW 4141502E SN^^^0816 e3 NNN 256 Legend: XX...X Y YY WW NNN e3 * Note: DS22059B-page 66 Example Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X Package Marking Information (Continued) Example: 10-Lead DFN (3x3) XXXX YYWW NNN Part Number Code Part Number Code MCP4242-502E/MF BAEM MCP4262-502E/MF BAEW MCP4242-103E/MF BAEP MCP4262-103E/MF BAEX MCP4242-104E/MF BAER MCP4262-104E/MF BAEZ MCP4242-503E/MF BAEQ MCP4262-503E/MF BAEY 10-Lead MSOP BAEH 0816 256 Example XXXXXX Part Number Code Part Number Code YWWNNN MCP4242-502E/MS 424252 MCP4262-502E/MS 426252 MCP4242-103E/MS 424213 MCP4262-103E/MS 426213 MCP4242-104E/MS 424214 MCP4262-104E/MS 426214 MCP4242-503E/MS 424253 MCP4262-503E/MS 426253 14-Lead PDIP XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (.150") XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP XXXXXXXX YYWW NNN 16-Lead QFN (4x4) XXXXX XXXXXX XXXXXX YYWWNNN (c) 2008 Microchip Technology Inc. 423252 816256 Example MCP4261 e3 502E/P^^ 0816256 Example MCP4261 502E/SL^^ e3 0816256 Example 4261502E 0816 256 Example 4261 502 e3 E/ML^^ 0816256 DS22059B-page 67 MCP414X/416X/424X/426X % 2% & %! % * %% 133)))& &3 " ) * ' !"#$ % * D e b N $ % % " % N L EXPOSED PAD E2 E K NOTE 1 1 2 D2 2 NOTE 1 1 BOTTOM VIEW TOP VIEW A NOTE 2 A3 A1 4% & 5&% 6!&( $ 55,, 6 6 67 8 9 % :./0 7 ; % 9 % "$$ . 0% %* + 7 5 % ,# , " "<"% ,2 +/0 = : 7 <"% , ,# = ( . + +. 5 + .. > = = " "5 % 0% %<"% 0% %5 % 0% % % ,# " " +/0 % ! " #$ %! & '(!%&! %( % ")%% % " * & & # "% ( % " + * ) ! % " & "% ,-. /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! ) 0 :/ DS22059B-page 68 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X % 2% & %! % * %% 133)))& &3 (c) 2008 Microchip Technology Inc. " ) * ' !"#$ % * $ % % " % DS22059B-page 69 MCP414X/416X/424X/426X % &' ( ) '#'( $ 2% & %! % * %% 133)))& &3 " ) * ' % * $ % % " % D N E E1 NOTE 1 1 2 e b A2 A c L L1 A1 4% & 5&% 6!&( $ 55,, 6 6 :./0 7 ; % * % "$$ 7 <"% " " * 7 5 % 8 9 % " " * 67 = = . 9. . = . , <"% /0 , +/0 +/0 2%5 % 5 2% % 5 2% I ? = 9? 5 9 = + "* : 9 .,2 5 "<"% ( = % ! " #$ %! & '(!%&! %( % ")%% % " & ","%!" &"$ %! "$ %! % # ".&& + & "% ,-. /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! " ) 0 / DS22059B-page 70 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X % *) ) 2% & %! % * %% 133)))& &3 " ) * !"# * $ ' % * $ % % " % N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 4% & 5&% 6!&( $ 60;, 6 6 67 8 9 % /0 % % = = . + . . = = !" %!" <"% , + +. " " * " " * / % * % , . 9 7 5 % +9 +:. % 5 . + . 9 . 5 4 <"% % "* 5 "<"% ( : 5) 5 "<"% ( 9 / = = 7 ) @ + % ! " #$ %! & '(!%&! %( % ")%% % " @ $ %0 % % + & ","%!" &"$ %! "$ %! % # "A & "% ,-. /01/ & % # % ! ))%!%% " ) 0 9/ (c) 2008 Microchip Technology Inc. DS22059B-page 71 MCP414X/416X/424X/426X % ' ( )'&&+ 2% & %! % * %% 133)))& &3 " ) * ' !"#'(*,$ % * $ % % " % D e N E E1 NOTE 1 1 2 3 h b h A2 A c L A1 L1 4% & 5&% 6!&( $ 55,, 6 6 8 /0 7 ; % * % "$$@ 7 <"% " " * 67 9 % " " * = = . = = = . , <"% 7 5 % . :/0 , +/0 /0 0 &$ B % C . = . 2%5 % 5 = 2% % 5 2% I ? = 9? 5 "* = . 5 "<"% ,2 ( + = . " $% D .? = .? " $% /%%& E .? = .? % ! " #$ %! & '(!%&! %( % ")%% % " @ $ %0 % % + & ","%!" &"$ %! "$ %! % # ".&& & "% ,-. /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! " ) 0 ./ DS22059B-page 72 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X % ' ( )'&&+ 2% & %! % * %% 133)))& &3 (c) 2008 Microchip Technology Inc. " ) * ' !"#'(*,$ % * $ % % " % DS22059B-page 73 MCP414X/416X/424X/426X - % 2% & %! % * %% 133)))& &3 " ) * ' !"#$ % * D $ % % " % e b N N L K E E2 EXPOSED PAD NOTE 1 1 2 2 1 NOTE 1 D2 BOTTOM VIEW TOP VIEW A A1 A3 NOTE 2 4% & 5&% 6!&( $ 55,, 6 6 67 8 % ./0 7 ; % 9 % "$$ . 0% %* + 7 5 % ,# " "5 % ,2 +/0 +. 9 7 <"% , ,# , .9 . ( 9 . + 5 + . > = = " "<"% 0% %<"% 0% %5 % 0% % % ,# " " +/0 % ! " #$ %! & '(!%&! %( % ")%% % " * & & # "% ( % " + * ) ! % " & "% ,-. /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! ) 0 :+/ DS22059B-page 74 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X - % 2% & %! % * %% 133)))& &3 (c) 2008 Microchip Technology Inc. " ) * ' !"#$ % * $ % % " % DS22059B-page 75 MCP414X/416X/424X/426X - % &' ( ) .#'( $ 2% & %! % * %% 133)))& &3 " ) * ' % * $ % % " % D N E E1 NOTE 1 1 2 b e A A2 c L A1 L1 4% & 5&% 6!&( $ 55,, 6 6 ./0 7 ; % * % "$$ 7 <"% " " * 7 5 % 8 % " " * 67 = = . 9. . = . , <"% /0 , +/0 +/0 2%5 % 5 2% % 5 2% I ? = 9? 5 9 = + "* : 9 .,2 5 "<"% ( . = ++ % ! " #$ %! & '(!%&! %( % ")%% % " & ","%!" &"$ %! "$ %! % # ".&& + & "% ,-. /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! " ) 0 / DS22059B-page 76 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X -/ % *) ) 2% & %! % * %% 133)))& &3 " ) * !"# * $ ' % * $ % % " % N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 4% & 5&% 6!&( $ 60;, 6 6 67 8 % /0 % % = = . + . . = = !" %!" <"% , + +. " " * " " * / % * % , . 9 7 5 % +. . . % 5 . + . 9 . 5 4 <"% % "* 5 "<"% ( . : 5) 5 "<"% ( 9 / = = 7 ) @ + % ! " #$ %! & '(!%&! %( % ")%% % " @ $ %0 % % + & ","%!" &"$ %! "$ %! % # "A & "% ,-. /01/ & % # % ! ))%!%% " ) 0 ./ (c) 2008 Microchip Technology Inc. DS22059B-page 77 MCP414X/416X/424X/426X -/ % ' ( )'&&+ 2% & %! % * %% 133)))& &3 " ) * ' !"#'(*,$ % * $ % % " % D N E E1 NOTE 1 1 2 3 e h b A2 A c L A1 L1 4% & 5&% 6!&( $ 55,, 6 6 8 /0 7 ; % * % "$$@ 7 <"% " " * 67 % " " * h = = . = = = . , <"% 7 5 % . :/0 , +/0 9:./0 0 &$ B % C . = . 2%5 % 5 = 2% % 5 2% I ? = 9? 5 "* = . 5 "<"% ,2 ( + = . " $% D .? = .? " $% /%%& E .? = .? % ! " #$ %! & '(!%&! %( % ")%% % " @ $ %0 % % + & ","%!" &"$ %! "$ %! % # ".&& & "% ,-. /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! " ) 0 :./ DS22059B-page 78 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X % 2% & %! % * %% 133)))& &3 (c) 2008 Microchip Technology Inc. " ) * ' % * $ % % " % DS22059B-page 79 MCP414X/416X/424X/426X -/ % 01 )'1& )' ( )'0// 2% & %! % * %% 133)))& &3 " ) * ' !"#0''( $ % * $ % % " % D N E E1 NOTE 1 1 2 e b A2 A c A1 L L1 4% & 5&% 6!&( $ 55,, 6 6 8 % :./0 7 ; % " " * 67 * % "$$ 7 <"% = = 9 . . = . , :/0 " " * <"% , + " " * 5 % . . 2%5 % 5 . : . 2% % 5 2% I ? = 9? 5 = "* . ,2 5 "<"% ( = + % ! " #$ %! & '(!%&! %( % ")%% % " & ","%!" &"$ %! "$ %! % # ".&& + & "% ,-. /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! " ) 0 9/ DS22059B-page 80 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X -2 % 3 // 2% & %! % * %% 133)))& &3 " ) * ' !"#3$ % * $ % % " % D2 D EXPOSED PAD e E E2 2 2 1 b 1 TOP VIEW K N N NOTE 1 L BOTTOM VIEW A3 A A1 4% & 5&% 6!&( $ 55,, 6 6 67 8 : % :./0 7 ; % 9 % "$$ . 0% %* + 7 <"% , ,# , " "<"% 7 5 % ,# " "5 % ,2 /0 . :. 9 /0 . :. 0% %<"% ( . + +. 0% %5 % 5 + . = = 0% % % ,# " " > % ! " #$ %! & '(!%&! %( % ")%% % " * ) ! % " + & "% ,-. /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! 9 ) 0 / (c) 2008 Microchip Technology Inc. DS22059B-page 81 MCP414X/416X/424X/426X % 2% & %! % * %% 133)))& &3 DS22059B-page 82 " ) * ' % * $ % % " % (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X APPENDIX A: REVISION HISTORY APPENDIX B: Revision B (December 2008) The following is the list of modifications: 1. 2. 3. 4. 5. Updated IPU specifications to specify test conditions and new limit. Updated DFN and QFN package in "Package Types (top view)", to include Exposed Thermal Pad samples (EP). Added new descriptions in Section 3.0 "Pin Descriptions". Added new Development Tool support item. Updated Package Outline section. Revision A (August 2007) * Original Release of this Document. MIGRATING FROM THE MCP41XXX AND MCP42XXX DEVICES This is intended to give an overview of some of the differences to be aware of when migrating from the MCP41XXX and MCP42XXX devices. B.1 MCP41XXX to MCP41XX Differences Here are some of the differences to be aware of: 1. SI pin is now SDI/SDO pin, and the contents of the device memory can be read 2. Need to address the Terminal Connect Feature (TCON register) of MCP41XX 3. MCP41XX supports software Shutdown mode 4. New 5 k version 5. MCP41XX have 7-bit resolution options 6. MCP41XX are Non-Volatile 7. Alternate pinout versions (for Rheostat configuration) 8. Verify device's electrical specifications 9. Interface signals are now high voltage tolerant 10. Interface signals now have internal pull-up resistors B.2 MCP42XXX to MCP42XX Differences Here are some of the differences to be aware of: Hardware Reset (RS) pin replace by Hardware Write Protect (WP) pin 2. Daisy chaining of devices is no longer supported 3. SDO pin allows contents of device memory to be read 4. Need to address the Terminal Connect Feature (TCON register) of MCP42XX 5. MCP42XX supports software Shutdown mode 6. New 5 k version 7. MCP42XX have 7-bit resolution options 8. MCP42XX are Non-Volatile 9. Alternate package/pinout versions (for Rheostat configuration) 10. Verify device's electrical specifications 11. Interface signals are now high voltage tolerant 12. Interface signals now have internal pull-up resistors 1. (c) 2008 Microchip Technology Inc. DS22059B-page 83 MCP414X/416X/424X/426X NOTES: DS22059B-page 84 (c) 2008 Microchip Technology Inc. MCP414X/416X/424X/426X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XXX X /XX Device Resistance Version Temperature Range Package Device MCP4141: MCP4141T: MCP4142: MCP4142T: MCP4161: MCP4161T: MCP4162: MCP4162T: MCP4241: MCP4241T: MCP4242: MCP4242T: MCP4261: MCP4261T: MCP4262: MCP4262T: Resistance Version: Single Non-Volatile 7-bit Potentiometer Single Non-Volatile 7-bit Potentiometer (Tape and Reel) Single Non-Volatile 7-bit Rheostat Single Non-Volatile 7-bit Rheostat (Tape and Reel) Single Non-Volatile 8-bit Potentiometer Single Non-Volatile 8-bit Potentiometer (Tape and Reel) Single Non-Volatile 8-bit Rheostat Single Non-Volatile 8-bit Rheostat (Tape and Reel) Dual Non-Volatile 7-bit Potentiometer Dual Non-Volatile 7-bit Potentiometer (Tape and Reel) Dual Non-Volatile 7-bit Rheostat Dual Non-Volatile 7-bit Rheostat (Tape and Reel) Dual Non-Volatile 8-bit Potentiometer Dual Non-Volatile 8-bit Potentiometer (Tape and Reel) Dual Non-Volatile 8-bit Rheostat Dual Non-Volatile 8-bit Rheostat (Tape and Reel) 502 103 503 104 = = = = Temperature Range I E = -40C to +85C (Industrial) = -40C to +125C (Extended) Package MF ML MS P SN SL ST UN = = = = = = = = 5 k 10 k 50 k 100 k Plastic Dual Flat No-lead (3x3 DFN), 8/10-lead Plastic Quad Flat No-lead (4x4 QFN), 16-lead Plastic Micro Small Outline (MSOP), 8-lead Plastic Dual In-line (PDIP) (300 mil), 8/14-lead Plastic Small Outline (SOIC), (150 mil), 8-lead Plastic Small Outline (SOIC), (150 mil), 14-lead Plastic Thin Shrink Small Outline (TSSOP), 14-lead Plastic Micro Small Outline (MSOP), 10-lead (c) 2008 Microchip Technology Inc. Examples: a) b) c) d) e) f) g) h) MCP4141-502E/XX: MCP4141T-502E/XX: MCP4141-103E/XX: MCP4141T-103E/XX: MCP4141-503E/XX: MCP4141T-503E/XX: MCP4141-104E/XX: MCP4141T-104E/XX: 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device a) b) c) d) e) f) g) h) MCP4142-502E/XX: MCP4142T-502E/XX: MCP4142-103E/XX: MCP4142T-103E/XX: MCP4142-503E/XX: MCP4142T-503E/XX: MCP4142-104E/XX: MCP4142T-104E/XX: 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device a) b) c) d) e) f) g) h) MCP4161-502E/XX: MCP4161T-502E/XX: MCP4161-103E/XX: MCP4161T-103E/XX: MCP4161-503E/XX: MCP4161T-503E/XX: MCP4161-104E/XX: MCP4161T-104E/XX: 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device a) b) c) d) e) f) g) h) MCP4162-502E/XX: MCP4162T-502E/XX: MCP4162-103E/XX: MCP4162T-103E/XX: MCP4162-503E/XX: MCP4162T-503E/XX: MCP4162-104E/XX: MCP4162T-104E/XX: 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device a) b) c) d) e) f) g) h) MCP4241-502E/XX: MCP4241T-502E/XX: MCP4241-103E/XX: MCP4241T-103E/XX: MCP4241-503E/XX: MCP4241T-503E/XX: MCP4241-104E/XX: MCP4241T-104E/XX: 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device a) b) c) d) e) f) g) h) MCP4242-502E/XX: MCP4242T-502E/XX: MCP4242-103E/XX: MCP4242T-103E/XX: MCP4242-503E/XX: MCP4242T-503E/XX: MCP4242-104E/XX: MCP4242T-104E/XX: 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device a) b) c) d) e) f) g) h) MCP4261-502E/XX: MCP4261T-502E/XX: MCP4261-103E/XX: MCP4261T-103E/XX: MCP4261-503E/XX: MCP4261T-503E/XX: MCP4261-104E/XX: MCP4261T-104E/XX: 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device a) b) c) d) e) f) g) h) MCP4262-502E/XX: MCP4262T-502E/XX: MCP4262-103E/XX: MCP4262T-103E/XX: MCP4262-503E/XX: MCP4262T-503E/XX: MCP4262-104E/XX: MCP4262T-104E/XX: 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device XX = = = = = = = = MF for 8/10-lead 3x3 DFN ML for 16-lead QFN MS for 8-lead MSOP P for 8/14-lead PDIP SN for 8-lead SOIC SL for 14-lead SOIC ST for 14-lead TSSOP UN for 10-lead MSOP DS22059B-page 85 MCP414X/416X/424X/426X NOTES: DS22059B-page 86 (c) 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2008 Microchip Technology Inc. DS22059B-page 87 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 01/02/08 DS22059B-page 88 (c) 2008 Microchip Technology Inc.