OMC942723157 H8/3614 Series H8/3614 HD6473614, HD6433614 H8/3613 HD6433613 H8/3612 HD6433612 Hardware Manual Preface The H8/3614 Series of single-chip microcomputers has an H8/300L CPU core and a variety of peripheral functions needed in system configurations. This manual describes the CPU architecture, peripheral functions, electrical characteristics, and package dimensions of the H8/3614 Series. Refer to the H8/300L Series Programming Manual (ADE-602-040) for a detailed description of the instruction set. Contents Section 1 1.1 1.2 1.3 Overview......................................................................................................................... Internal Block Diagram .................................................................................................. Pin Arrangement and Functions ..................................................................................... 1.3.1 Pin Arrangement................................................................................................. 1.3.2 Pin Functions ...................................................................................................... Section 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Overview.......................................................................................................... CPU ................................................................................................................... Overview......................................................................................................................... 2.1.1 Features............................................................................................................... 2.1.2 Address Space..................................................................................................... 2.1.3 Register Configuration........................................................................................ Register Descriptions...................................................................................................... 2.2.1 General Registers................................................................................................ 2.2.2 Control Registers ................................................................................................ 2.2.3 Initial Register Values ........................................................................................ Data Formats................................................................................................................... 2.3.1 Data Formats in General Registers ..................................................................... 2.3.2 Memory Data Formats........................................................................................ Addressing Modes .......................................................................................................... 2.4.1 Addressing Modes .............................................................................................. 2.4.2 Effective Address Calculation ............................................................................ Instruction Set................................................................................................................. 2.5.1 Data Transfer Instructions .................................................................................. 2.5.2 Arithmetic Operations ........................................................................................ 2.5.3 Logic Operations ................................................................................................ 2.5.4 Shift Operations .................................................................................................. 2.5.5 Bit Manipulations ............................................................................................... 2.5.6 Branching Instructions........................................................................................ 2.5.7 System Control Instructions ............................................................................... 2.5.8 Block Data Transfer Instruction ......................................................................... CPU States ...................................................................................................................... 2.6.1 Overview............................................................................................................. 2.6.2 Program Execution State .................................................................................... 2.6.3 Program Halt State.............................................................................................. 2.6.4 Exception-Handling States ................................................................................. Basic Operation Timing.................................................................................................. 2.7.1 Access to On-Chip Memory (RAM, ROM) ....................................................... 2.7.2 Access to On-Chip Peripheral Modules ............................................................. Application Notes ........................................................................................................... 2.8.1 Notes on Data Access ......................................................................................... 1 1 5 7 7 11 15 15 15 16 17 18 18 18 20 20 21 22 23 23 25 29 31 33 34 34 36 40 42 43 45 45 46 46 46 47 47 48 49 49 2.8.2 Section 3 3.1 3.2 3.3 3.4 Notes on Bit Manipulation.................................................................................. 51 System Control .............................................................................................. 55 Overview......................................................................................................................... Exception Handling ........................................................................................................ 3.2.1 Reset ................................................................................................................... 3.2.2 Interrupts............................................................................................................. 3.2.3 Interrupt Control Registers ................................................................................. 3.2.4 External Interrupts .............................................................................................. 3.2.5 Internal Interrupts ............................................................................................... 3.2.6 Interrupt Operations............................................................................................ 3.2.7 Return from an Interrupt..................................................................................... 3.2.8 Interrupt Response Time..................................................................................... 3.2.9 Valid Interrupts in Each Mode ........................................................................... 3.2.10 Notes on Stack Area Use .................................................................................... 3.2.11 Note on Clearing Interrupt Request Registers .................................................... System Modes................................................................................................................. 3.3.1 Overview............................................................................................................. 3.3.2 Active Mode ....................................................................................................... 3.3.3 Sleep Mode ......................................................................................................... 3.3.4 Standby Mode..................................................................................................... 3.3.5 Watch Mode........................................................................................................ 3.3.6 Subactive Mode .................................................................................................. 3.3.7 Application Notes ............................................................................................... System Control Registers ............................................................................................... 3.4.1 System Control Register 1 (SYSCR1)................................................................ 3.4.2 System Control Register 2 (SYSCR2)................................................................ Section 4 4.1 4.2 4.3 Clock Pulse Generators ............................................................................... Overview......................................................................................................................... 4.1.1 Block Diagram.................................................................................................... System Clock Generator ................................................................................................. Subclock Generator ........................................................................................................ Section 5 5.1 5.2 55 55 55 56 58 66 67 67 72 72 73 74 74 75 75 77 77 77 78 79 81 82 82 84 85 85 85 86 89 I/O Ports ........................................................................................................... 91 Overview......................................................................................................................... 5.1.1 Port Types and Mask Options............................................................................. 5.1.2 Pull-Up MOS ...................................................................................................... Port 0 ............................................................................................................................ 5.2.1 Overview............................................................................................................. 5.2.2 Register Configuration and Description ............................................................. 5.2.3 Pin Functions ...................................................................................................... 5.2.4 Pin States ............................................................................................................ 91 93 94 95 95 95 96 96 5.3 5.4 5.5 5.6 5.7 5.8 Port 1 5.3.1 5.3.2 5.3.3 5.3.4 Port 2 5.4.1 5.4.2 5.4.3 5.4.4 Port 4 5.5.1 5.5.2 5.5.3 5.5.4 Port 8 5.6.1 5.6.2 5.6.3 5.6.4 Port 9 5.7.1 5.7.2 5.7.3 5.7.4 Port A 5.8.1 5.8.2 5.8.3 5.8.4 Section 6 6.1 6.2 6.3 ............................................................................................................................ 97 Overview............................................................................................................. 97 Register Configuration and Description ............................................................. 97 Pin Functions ...................................................................................................... 102 Pin States ............................................................................................................ 103 ............................................................................................................................ 104 Overview............................................................................................................. 104 Register Configuration and Description ............................................................. 104 Pin Functions ...................................................................................................... 105 Pin States ............................................................................................................ 105 ............................................................................................................................ 106 Overview............................................................................................................. 106 Register Configuration and Description ............................................................. 106 Pin Functions ...................................................................................................... 107 Pin States ............................................................................................................ 107 ............................................................................................................................ 108 Overview............................................................................................................. 108 Register Configuration and Description ............................................................. 108 Pin Functions ...................................................................................................... 109 Pin States ............................................................................................................ 109 ............................................................................................................................ 110 Overview............................................................................................................. 110 Register Configuration and Description ............................................................. 110 Pin Functions ...................................................................................................... 114 Pin States ............................................................................................................ 116 ............................................................................................................................ 117 Overview............................................................................................................. 117 Register Configuration and Description ............................................................. 117 Pin Functions ...................................................................................................... 118 Pin States ............................................................................................................ 118 Timers ............................................................................................................... 119 Overview......................................................................................................................... 119 6.1.1 Prescaler Operation............................................................................................. 120 Timer A........................................................................................................................... 122 6.2.1 Overview............................................................................................................. 122 6.2.2 Register Descriptions.......................................................................................... 123 6.2.3 Timer Operation.................................................................................................. 125 Timer B........................................................................................................................... 127 6.3.1 Overview............................................................................................................. 127 6.3.2 Register Descriptions.......................................................................................... 128 6.3.3 Timer Operation.................................................................................................. 130 6.4 6.5 6.6 6.7 6.8 Timer C........................................................................................................................... 132 6.4.1 Overview............................................................................................................. 132 6.4.2 Register Descriptions.......................................................................................... 134 6.4.3 Timer Operation.................................................................................................. 136 Timer D........................................................................................................................... 138 6.5.1 Overview............................................................................................................. 138 6.5.2 Register Descriptions.......................................................................................... 139 6.5.3 Timer Operation.................................................................................................. 141 Timer E ........................................................................................................................... 142 6.6.1 Overview............................................................................................................. 142 6.6.2 Register Descriptions.......................................................................................... 144 6.6.3 Timer Operation.................................................................................................. 148 Interrupts......................................................................................................................... 151 Application Notes ........................................................................................................... 151 Section 7 7.1 7.2 7.3 14-Bit PWM ................................................................................................... 153 Overview......................................................................................................................... 153 7.1.1 Features............................................................................................................... 153 7.1.2 Block Diagram.................................................................................................... 153 7.1.3 Pin Configuration................................................................................................ 154 7.1.4 Register Configuration........................................................................................ 154 Register Descriptions...................................................................................................... 155 7.2.1 PWM Control Register (PWCR) ........................................................................ 155 7.2.2 PWM Data Registers U and L (PWDRU, PWDRL) .......................................... 156 Operation ........................................................................................................................ 157 Section 8 8.1 8.2 8.3 SCI1 .................................................................................................................. 159 Overview......................................................................................................................... 159 8.1.1 Features............................................................................................................... 159 8.1.2 Block Diagram.................................................................................................... 159 8.1.3 Pin Configuration................................................................................................ 160 8.1.4 Register Configuration........................................................................................ 160 Register Descriptions...................................................................................................... 161 8.2.1 Serial Mode Register 1 (SMR1) ......................................................................... 161 8.2.2 Serial Data Register U1 (SDRU1)...................................................................... 162 8.2.3 Serial Data Register L1 (SDRL1)....................................................................... 163 8.2.4 Serial Port Register 1 (SPR1) ............................................................................. 163 8.2.5 Port Mode Register 2 (PMR2)............................................................................ 164 8.2.6 Port Mode Register 3 (PMR3)............................................................................ 165 Operation ........................................................................................................................ 166 8.3.1 Overview............................................................................................................. 166 8.3.2 Data Transfer Format.......................................................................................... 167 8.3.3 Clock................................................................................................................... 167 8.3.4 8.3.5 8.3.6 8.3.7 Data Transmit/Receive ....................................................................................... 167 SCI1 State Transitions ........................................................................................ 170 Transfer Clock Error Detection .......................................................................... 171 Interrupts............................................................................................................. 172 Section 9 9.1 9.2 9.3 9.4 9.5 SCI2 .................................................................................................................. 173 Overview......................................................................................................................... 173 9.1.1 Features............................................................................................................... 173 9.1.2 Block Diagram.................................................................................................... 173 9.1.3 Pin Configuration................................................................................................ 174 9.1.4 Register Configuration........................................................................................ 174 Register Descriptions...................................................................................................... 175 9.2.1 Start Address Register (STAR) .......................................................................... 175 9.2.2 End Address Register (EDAR)........................................................................... 175 9.2.3 Serial Control Register 2 (SCR2) ....................................................................... 176 9.2.4 Status Register (STSR) ....................................................................................... 177 9.2.5 Port Mode Register 3 (PMR3)............................................................................ 179 Operation ........................................................................................................................ 181 9.3.1 Overview............................................................................................................. 181 9.3.2 Clock................................................................................................................... 182 9.3.3 Data Transfer Format.......................................................................................... 182 9.3.4 Data Transmit/Receive ....................................................................................... 184 Interrupts......................................................................................................................... 186 Application Notes ........................................................................................................... 186 Section 10 A/D Converter ................................................................................................ 187 10.1 10.2 10.3 10.4 10.5 10.6 Overview......................................................................................................................... 187 10.1.1 Features............................................................................................................... 187 10.1.2 Block Diagram.................................................................................................... 188 10.1.3 Pin Configuration................................................................................................ 189 10.1.4 Register Configuration........................................................................................ 189 Register Descriptions...................................................................................................... 190 10.2.1 A/D Result Register (ADRR) ............................................................................. 190 10.2.2 A/D Mode Register (AMR) ................................................................................ 190 10.2.3 A/D Start Register (ADSR) ................................................................................ 193 10.2.4 Port Mode Register 0 (PMR0)............................................................................ 194 Operation ........................................................................................................................ 194 Interrupts......................................................................................................................... 194 Typical Use..................................................................................................................... 195 Application Notes ........................................................................................................... 199 Section 11 RAM ................................................................................................................. 201 11.1 Overview......................................................................................................................... 201 11.1.1 Block Diagram.................................................................................................... 201 Section 12 ROM.................................................................................................................. 203 12.1 12.2 12.3 Overview......................................................................................................................... 203 12.1.1 Block Diagram.................................................................................................... 203 PROM Mode................................................................................................................... 204 12.2.1 Setting to PROM Mode ...................................................................................... 204 12.2.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 204 Programming .................................................................................................................. 207 12.3.1 Writing and Verifying......................................................................................... 207 12.3.2 Precautions When Writing.................................................................................. 210 12.3.3 Reliability of Written Data ................................................................................. 211 Section 13 Electrical Specifications.............................................................................. 213 13.1 13.2 13.3 13.4 13.5 13.6 Absolute Maximum Ratings ........................................................................................... 213 HD6473614 Electrical Characteristics .......................................................................... 214 13.2.1 HD6473614 DC Characteristics ......................................................................... 214 13.2.2 HD6473614 AC Characteristics ......................................................................... 220 13.2.3 HD6473614 A/D Converter Characteristics....................................................... 223 HD6433613 and HD6433614 Electrical Characteristics................................................ 224 13.3.1 HD6433613 and HD6433614 DC Characteristics.............................................. 224 13.3.2 HD6433613 and HD6433614 AC Characteristics.............................................. 230 13.3.3 HD6433613 and HD6433614 A/D Converter Characteristics ........................... 233 HD6433612 Electrical Characteristics ........................................................................... 234 13.4.1 HD6433612 DC Characteristics ......................................................................... 234 13.4.2 HD6433612 AC Characteristics ......................................................................... 240 13.4.3 HD6433612 A/D Converter Characteristics....................................................... 243 Operational Timing......................................................................................................... 244 Differences in Electrical Characteristics between Mask ROM and ZTATTM Versions ........................................................................................................... 247 Appendix A CPU Instruction Set.................................................................................. 249 A.1 A.2 A.3 Instruction Set List.......................................................................................................... 249 Operation Code Map....................................................................................................... 250 Number of States Required for Execution...................................................................... 252 Appendix B On-Chip Registers..................................................................................... 259 B.1 B.2 On-Chip Registers (1)..................................................................................................... 259 On-Chip Registers (2)..................................................................................................... 262 Appendix C I/O Port Block Diagrams ......................................................................... 287 C.1 C.2 C.3 C.4 C.5 C.6 C.7 Port 0 Block Diagram ..................................................................................................... Port 1 Block Diagram ..................................................................................................... Port 2 Block Diagram ..................................................................................................... Port 4 Block Diagram ..................................................................................................... Port 8 Block Diagram ..................................................................................................... Port 9 Block Diagram ..................................................................................................... Port A Block Diagram .................................................................................................... 287 288 291 292 293 294 300 Appendix D Port States in Each Processing State .................................................... 301 Appendix E List of Mask Options ................................................................................. 302 Appendix F Package Dimensions .................................................................................. 303 Section 1 Overview 1.1 Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3614 Series of microcomputers are equipped with five timers, a 14-bit pulse width modulator (PWM), two serial communication interface channels, an A/D converter, and other on-chip peripheral functions. The H8/3614 series includes three chips: the H8/3612, which has a 16-kbyte ROM and 512-byte RAM; the H8/3613, which has a 24-kbyte ROM and 1024-byte RAM; and the H8/3614, which has a 32-kbyte ROM and 1024-byte RAM. The H8/3612 does not have the 14-bit PWM. The ZTATTM* versions of the H8/3614 come with user-programmable PROM on-chip. Table 1-1 summarizes the main features of the H8/3614 Series. Note: * ZTAT (zero turn around time) is a trademark of Hitachi, Ltd. 1 Table 1-1 Features Item Specification CPU High-speed H8/300L CPU * General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) * Operating speed -- Max. operating speed: 4.19 MHz -- Add/subtract: 0.5 s (operating at o = 4 MHz) -- Multiply/divide: 3.5 s (operating at o = 4 MHz) -- Can run on 32 kHz subclock * Instruction set compatible with H8/300 CPU -- Instruction length of 2 bytes or 4 bytes -- Basic arithmetic operations between registers -- MOV instruction for data transfer between memory and registers * Typical instructions -- Multiply (8 bits x 8 bits) -- Divide (16 bits / 8 bits) -- Bit accumulator -- Register-indirect designation of bit position Interrupts 15 interrupt sources * Six external interrupt pins: IRQ5 to IRQ0 * Nine internal interrupt sources Low-power operation modes 4 power-down modes * Sleep mode * Standby mode * Watch mode * Subactive mode Clock oscillators Two on-chip clock oscillators * System clock oscillator: 1 to 8.4 MHz * Subclock oscillator: 32.768 kHz I/O ports 54 I/O pins * PMOS open-drain I/O pins: 6 * Standard-voltage I/O pins: 38 * Standard-voltage input pins: 10 2 Table 1-1 Features (cont) Item Specification Timers Five on-chip timers * Timer A: 8-bit interval timer Count-up timer with selection of eight internal clock signals divided from the system clock (o)* and four clock signals divided from the subclock (oSUB) Operating on the subclock, timer A can provide a time base for timekeeping. * Timer B: 8-bit reload timer Count-up timer with selection of seven internal clock signals or event input from pin P10/IRQ0 * Timer C: 8-bit reload timer Count-up/count-down timer with selection of seven internal clock signals or event input from pin P11/IRQ1 * Timer D: 8-bit event counter Up-counter for counting input from pin P16/EVENT * Timer E: 8-bit reload timer Count-up timer with selection of eight internal clock signals. A fixedfrequency waveform can be output from pin P15/IRQ5/TMOE, or an arbitrary square wave (50% duty) can be output by timer E overflow. Note: * o indicates a clock frequency that is divided in half from the original oscillator frequency 14-bit PWM* * Pulse-division PWM designed for less ripple * Can be used as a 14-bit D/A converter by connecting to an external lowpass filter Note: * The H8/3612 does not have this function. Serial communication interface Two channels on chip * Choice of 8-bit or 16-bit transfer data (SCI1) * Automatic transfer of 32-byte data (SCI2) A/D converter * Successive approximations using a resistance ladder * Resolution: 8 bits * 8-channel analog input port * Conversion time: 31/o or 62/o per channel 3 Table 1-1 Features (cont) Item Specification Memory Large on-chip memory H8/3612: 16-kbyte ROM, 512-byte RAM H8/3613: 24-kbyte ROM, 1024-byte RAM H8/3614: 32-kbyte ROM, 1024-byte RAM H8/3614ZTAT: 32-kbyte PROM, 1024-byte RAM Product lineup Product Code Mask ROM Version ZTAT Version Package ROM/RAM Size HD6433612H -- 64-pin QFP (FP-64A) ROM: 16 kbytes RAM: 512 bytes HD6433612P -- 64-pin SDIP (DP-64S) HD6433613H -- 64-pin QFP (FP-64A) HD6433613P -- 64-pin SDIP (DP-64S) HD6433614H HD6473614H 64-pin QFP (FP-64A) HD6433614P HD6473614P 64-pin SDIP (DP-64S) 4 ROM: 24 kbytes RAM: 1024 bytes ROM: 32 kbytes RAM: 1024 bytes 1.2 Internal Block Diagram RES TEST VSS VCC OSC2 Port 1 Port 2 Data bus (upper) Mask ROM P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/IRQ3 P14/IRQ4 P15/IRQ5/TMOE P16/EVENT P17 P20 P21 P22 P23 P24 P25 P26 P27 Port A Address bus Port 9 RAM Address bus P80 P81 P82 P83 P84 P85 P86 P87 H8/300L CPU Data bus (lower) Port 8 P90 P91/SCK1 P92/SI1 P93/SO1 P94/SCK2 P95/SI2/CS P96/SO2 P97/UD System clock pulse generator Data bus (upper) Subclock pulse generator OSC1 X2 X1 Figure 1-1 shows an internal block diagram of the H8/3612. Figure 1-2 shows an internal block diagram of the H8/3613 and H8/3614. PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Timer A Timer B Serial communication 1 Timer C Timer D Serial communication 2 Timer E A/D converter Data bus (upper) Address bus AVSS AVCC Port 0 P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 Port 4 P40 P41 P42 P43 P44 P45 Figure 1-1 Block Diagram (H8/3612) 5 RES TEST VSS VCC OSC2 Port 1 P20 P21 P22 P23 P24 P25 P26 P27 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Address bus Data bus (upper) Port 2 Port 9 P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/IRQ3 P14/IRQ4 P15/IRQ5/TMOE P16/EVENT P17 Port A Data bus (upper) H8/300L CPU RAM Address bus P80 P81 P82 P83 P84 P85 P86 P87 System clock pulse generator Data bus (lower) Port 8 P90/PWM P91/SCK1 P92/SI1 P93/SO1 P94/SCK2 P95/SI2/CS P96/SO2 P97/UD OSC1 X2 X1 Subclock pulse generator Mask ROM (PROM) Timer A Timer B Serial communication 1 Timer C Timer D Serial communication 2 Timer E 14-bit PWM A/D converter Data bus (upper) Address bus AVSS AVCC Port 0 P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 Port 4 P40 P41 P42 P43 P44 P45 Figure 1-2 Block Diagram (H8/3613 and H8/3614) 6 1.3 Pin Arrangement and Functions 1.3.1 Pin Arrangement 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVCC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 P97/UD The pin arrangements for the H8/3612 are shown in figures 1-3 (FP-64A) and 1-4 (DP-64S). The pin arrangements for the H8/3613 and H8/3614 are shown in figures 1-5 (FP-64A) and 1-6 (DP-64S). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P16/EVENT P17 P27 P26 P25 P24 P23 P22 P21 P20 P45 P44 P43 P42 P41 P40 P06/AN6 P07/AN7 AVSS TEST X2 X1 VSS OSC1 OSC2 RES P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/IRQ3 P14/IRQ4 P15/IRQ5/TMOE Figure 1-3 H8/3612 Pin Arrangement (FP-64A: Top View) 7 P96/SO2 P95/SI2/CS P94/SCK2 P93/SO1 P92/SI1 P91/SCK1 P90 P87 P86 P85 P84 P83 P82 P81 P80 VCC PA7 AVCC P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 AVSS TEST X2 X1 VSS OSC1 OSC2 RES P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/IRQ3 P14/IRQ4 P15/IRQ5/TMOE P16/EVENT P17 P27 P26 P25 P24 P23 P22 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA6 PA5 PA4 PA3 PA2 PA1 PA0 P97/UD P96/SO2 P95/SI2/CS P94/SCK2 P93/SO1 P92/SI1 P91/SCK1 P90 P87 P86 P85 P84 P83 P82 P81 P80 VCC P40 P41 P42 P43 P44 P45 P20 P21 Figure 1-4 H8/3612 Pin Arrangement (DP-64S: Top View) 8 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVCC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 P97/UD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P96/SO2 P95/SI2/CS P94/SCK2 P93/SO1 P92/SI1 P91/SCK1 P90/PWM P87 P86 P85 P84 P83 P82 P81 P80 VCC P16/EVENT P17 P27 P26 P25 P24 P23 P22 P21 P20 P45 P44 P43 P42 P41 P40 P06/AN6 P07/AN7 AVSS TEST X2 X1 VSS OSC1 OSC2 RES P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/IRQ3 P14/IRQ4 P15/IRQ5/TMOE Figure 1-5 H8/3613 and H8/3614 Pin Arrangement (FP-64A: Top View) 9 PA7 AVCC P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 AVSS TEST X2 X1 VSS OSC1 OSC2 RES P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/IRQ3 P14/IRQ4 P15/IRQ5/TMOE P16/EVENT P17 P27 P26 P25 P24 P23 P22 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA6 PA5 PA4 PA3 PA2 PA1 PA0 P97/UD P96/SO2 P95/SI2/CS P94/SCK2 P93/SO1 P92/SI1 P91/SCK1 P90/PWM P87 P86 P85 P84 P83 P82 P81 P80 VCC P40 P41 P42 P43 P44 P45 P20 P21 Figure 1-6 H8/3613 and H8/3614 Pin Arrangement (DP-64S: Top View) 10 1.3.2 Pin Functions Table 1-3 explains the functions of each pin. Table 1-3 Pin Functions Pin No. Type Symbol FP-64A DP-64S I/O Power supply pins VCC 33 41 Input Power supply: All VCC pins should be connected to the system power supply (+5 V). VSS 7 15 Input Ground: All VSS pins should be connected to the system power supply (0 V). AVCC 58 2 Input Analog power supply: This is the power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5 V). AVSS 3 11 Input Analog ground: This is the A/D converter ground pin. It should be connected to the system power supply (0 V). OSC1 8 16 Input This pin connects to a crystal or ceramic oscillator, or can be used to input an external clock. Clock pins Name and Functions See section 4, Clock Pulse Generators, for a typical connection diagram. OSC2 9 17 Output This pin connects to a crystal or ceramic oscillator. X1 6 14 Input This pin connects to a 32.768 kHz crystal oscillator. For a typical connection diagram, see section 4, Clock Pulse Generators. System control X2 5 13 Output This pin connects to a 32.768 kHz crystal oscillator. RES 10 18 Input Reset: When this pin goes to low level, the chip is reset. TEST 4 12 Input Test: This pin is not for use in application systems. It should be grounded to a VSS potential. 11 Table 1-3 Pin Functions (cont) Pin No. Type Symbol FP-64A DP-64S I/O Interrupt pins IRQ0 11 19 Input Name and Functions External interrupt request 0: This is an input pin for external interrupts for which there is a choice between rising and falling edge sensing. It can be used to exit low-power mode. This pin can be used as the event input pin for timer B. A noise cancel function is also provided. IRQ1 12 20 Input External interrupt request 1: This is an input pin for external interrupts for which there is a choice between rising and falling edge sensing. It can be used to exit low-power mode. This pin can be used as the event input pin for timer C. Timer pins IRQ2 13 21 Input External interrupt request 2: This is an input pin for external interrupts that are detected at the falling edge. IRQ3 14 22 Input External interrupt request 3: This is an input pin for external interrupts that are detected at the falling edge. IRQ4 15 23 Input External interrupt request 4: This is an input pin for external interrupts for which there is a choice between rising and falling edge sensing. IRQ5 16 24 Input External interrupt request 5: This is an input pin for external interrupts that are detected at the falling edge. IRQ0 11 19 Input Timer B event counter input: This is an event input pin for input to the timer B counter. IRQ1 12 20 Input Timer C event counter input: This is an event input pin for input to the timer C counter. UD 49 57 Input Timer C up/down select: This pin selects whether the timer C counter is used for up- or down-counting. At high level it selects down-counting, and at low level up-counting. Input to this pin is valid only when bit TMC6 in timer mode register C (TMC) is set to 1. 12 Table 1-3 Pin Functions (cont) Pin No. Type Symbol FP-64A DP-64S I/O Name and Functions Timer pins EVENT 17 25 Input Timer D event counter input: This is an event input pin for input to the timer D counter. TMOE 16 24 Output Timer E output: This is an output pin for waveforms generated by the timer E output circuit. 14-bit PWM pin* PWM 42 50 Output 14-bit PWM output: This is an output pin for waveforms generated by the 14-bit PWM. Serial communication interface (SCI) pins SO1 SO2 45 48 53 56 Output Serial transmit data output (channels 1 and 2): These are SCI data output pins. SI1 SI2 44 47 52 55 Input Serial receive data input (channels 1 and 2): These are SCI data input pins. SCK1 SCK2 43 46 51 54 I/O Serial clock I/O (channels 1 and 2): These are SCI clock I/O pins. CS 47 55 Output Chip select output: When SCI2 is in transmit mode and the serial clock is an internal clock, this pin goes low. This function is valid when bit SI2 in port mode register 2 (PMR2) is 1 and the CS bit in PMR3 is 1. I/O ports P07 to P00 2, 1, 10 to 3 64 to 59 Input Port 0: This is an 8-bit input port. P17 18 26 Input Port 1 (bit 7): This is a 1-bit input pin. P16 17 25 Input Port 1 (bit 6): This is a 1-bit input pin. P15 to P10 16 to 11 24 to 19 I/O Port 1: This is a 6-bit group of I/O pins. Input or output can be designated for each bit by means of port control register 1 (PCR1). P27 to P20 19 to 26 27 to 34 I/O Port 2: This is an 8-bit I/O port. P45 to P40 27 to 32 35 to 40 I/O Port 4: This is a 6-bit I/O port. P87 to P80 41 to 34 49 to 42 I/O Port 8: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 8 (PCR8). Note: * The H8/3612 does not have this function. 13 Table 1-3 Pin Functions (cont) Pin No. Type Symbol FP-64A DP-64S I/O Name and Functions I/O ports P97 to P90 49 to 42 57 to 50 I/O Port 9: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 9 (PCR9). PA7 to PA0 57 to 50 1, I/O 64 to 58 Port A: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register A (PCRA). AN7 to AN0 2, 1, 10 to 3 64 to 59 Analog input channels 7 to 0: These are analog data input channels to the A/D converter. A/D converter Input 14 Section 2 CPU 2.1 Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise, optimized instruction set is designed for high-speed operation. 2.1.1 Features The main features of the H8/300L CPU are listed below. * General-register architecture -- Sixteen 8-bit general registers, also usable as eight 16-bit general registers * Instruction set with 55 basic instructions, including: -- Multiply and divide instructions -- Powerful bit-manipulation instructions * Eight addressing modes -- Register direct -- Register indirect -- Register indirect with displacement -- Register indirect with post-increment or pre-decrement -- Absolute address -- Immediate -- Program-counter relative -- Memory indirect Rn @Rn @(d:16, Rn) @Rn+ or @-Rn @aa:8 or @aa:16 #xx:8 or #xx:16 @(d:8, PC) @@aa:8 * * 64-kbyte address space High-speed operation -- All frequently used instructions are executed in two to four states -- High-speed arithmetic and logic operations -- 8- or 16-bit register-register add or subtract: 0.5 s* -- 8 x 8-bit multiply: 3.5 s* -- 16 / 8-bit divide: 3.5 s* * Low-power operation modes -- SLEEP instruction for transfer to low-power operation Note: * These values are at o = 4 MHz. 15 2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. The H8/3614 Series memory map varies with the ROM size, as shown in figure 2-1. H8/3612 H'0000 H'002B H8/3613 H8/3614 Interrupt vector (44 bytes) 16,384 bytes On-chip ROM 24,576 bytes 32,256 bytes H'3FFF H'5FFF H'7DFF H'FB80 1,024 bytes H'FD80 512 bytes On-chip RAM H'FF7F H'FF80 H'FF9F H'FFA0 H'FFA3 H'FFA4 H'FFAF H'FFB0 H'FFFF 32-byte data buffer Internal I/O register (4 bytes) Reserved Internal I/O register (80 bytes) Figure 2-1 Memory Map 16 1,024 bytes 2.1.3 Register Configuration Figure 2-2 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) 7 0 7 0 R0H R0L R1H R1L R2H R2L R3H R3L R4H R4L R5H R5L R6H R6L R7H (SP) SP: Stack pointer R7L Control registers 15 0 PC CCR PC: Program counter 7 6 5 4 3 2 1 0 I UHUNZ VC CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit Figure 2-2 CPU Registers 17 2.2 Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing and subroutine calls. When it functions as the stack pointer, as indicated in figure 2-3, SP (R7) points to the top of the stack. Lower address side [H'0000] Unused area SP (R7) Stack area Upper address side [H'FFFF] Figure 2-3 Stack Pointer 2.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). 1. Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored (always regarded as 0). 2. Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. 18 Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see 3.2.2, Interrupts. Bit 6--User Bit (U): Can be written and read by software for its own purposes (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. The H flag is used implicitly by the DAA and DAS instructions. When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. Bit 4--User Bit (U): Can be written and read by software for its own purposes (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 3--Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the CCR, and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits. 19 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to a value loaded from vector address H'0000, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be initialized by software, by the first instruction executed after a reset. 2.3 Data Formats The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. * Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). * All arithmetic instructions except ADDS and SUBS can operate on byte data. * The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data. * The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit. 20 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-4. Data Type Register No. Data Format 7 1-bit data RnH 1-bit data RnL 7 0 6 5 4 3 2 1 0 Don't care 7 Byte data RnH Byte data RnL Word data Rn Don't care 7 0 MSB LSB Don't care RnH 4-bit BCD data RnL 0 6 5 4 3 2 1 0 Don't care 7 0 MSB LSB 15 0 MSB LSB 7 4-bit BCD data 7 4 3 Upper digit 0 Lower digit Don't care 7 4 Upper digit Don't care Notation: RnH: Upper digit of general register RnL: Lower digit of general register MSB: Most significant bit LSB: Least significant bit Figure 2-4 Register Data Formats 21 0 3 Lower digit 2.3.2 Memory Data Formats Figure 2-5 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, the access is performed at the preceding even address. This rule affects the MOV.W instruction, and also applies to instruction fetching. Word access is possible only to ROM and RAM areas. For details, see 2.8.1, Notes on Data Access. Data Type Address Data Format 7 1-bit data Address n 7 Byte data Address n MSB Even address MSB Word data Odd address Byte data (CCR) on stack Word data on stack 0 6 5 4 3 2 1 0 LSB Upper 8 bits Lower 8 bits LSB Even address MSB CCR LSB Odd address MSB CCR* LSB Even address MSB Odd address LSB Note: * Ignored on return Notation: CCR: Condition code register Figure 2-5 Memory Data Formats When the stack is accessed using R7 as an address register, word access should always be performed. For details, see 3.2.10, Notes on Stack Area Use. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored. 22 2.4 Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes No. Address Modes Symbol 1 Register direct Rn 2 Register indirect @Rn 3 Register indirect with displacement @(d:16, Rn) 4 Register indirect with post-increment Register indirect with pre-decrement @Rn+ @-Rn 5 Absolute address @aa:8 or @aa:16 6 Immediate #xx:8 or #xx:16 7 Program-counter relative @(d:8, PC) 8 Memory indirect @@aa:8 1. Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands. 2. Register Indirect--@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand. 3. Register Indirect with Displacement--@(d:16, Rn): The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address. This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even. 23 4. Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn: * Register indirect with post-increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. * Register indirect with pre-decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. The register retains the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the register must be even. 5. Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535). 6. Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. Program-Counter Relative--@(d:8, PC): This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. The displacement should be an even number. 24 8. Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that in the H8/300L Series, low addresses are assigned to the vector table. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See 2.3.2, Memory Data Formats, for further information. 2.4.2 Effective Address Calculation Table 2-2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or absolute addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to specify the bit position. 25 Table 2-2 Effective Address Calculation No. Addressing Mode and Instruction Format 1 Register direct, Rn Effective Address Calculation Method Effective Address (EA) 3 0 rm 15 8 7 op 2 4 3 rm 7 6 op 3 rn Operand is contents indicated by rm/rn. 15 26 15 0 15 0 15 0 15 0 0 rm Register indirect with displacement, @(d:16, Rn) 15 0 Contents (16 bits) of register indicated by rm 4 3 0 rn 0 Register indirect, @Rn 15 3 7 6 op 4 3 15 0 Contents (16 bits) of register indicated by rm 0 rm disp disp 4 15 Register indirect with post-increment, @Rn+ 15 7 6 op 0 Contents (16 bits) of register indicated by rm 4 3 0 rm 1 or 2 Register indirect with pre-decrement, @-Rn 15 7 6 op 4 3 rm 15 0 Contents (16 bits) of register indicated by rm 0 Incremented or decremented by 1 if operand is byte size, 1 or 2 and by 2 if word size. Table 2-2 Effective Address Calculation (cont) No. 5 Addressing Mode and Instruction Format Effective Address Calculation Method 15 Absolute address @aa:8 15 8 7 0 H'FF 8 7 op Effective Address (EA) 0 abs @aa:16 15 15 0 0 op abs 6 Immediate #xx:8 27 15 8 7 op 0 IMM Operand is 1- or 2-byte immediate data. #xx:16 15 0 op IMM 7 15 Program-counter relative @(d:8, PC) 15 8 7 op PC contents 0 disp 0 Sign extension 15 disp 0 Table 2-2 Effective Address Calculation (cont) No. Addressing Mode and Instruction Format 8 Memory indirect, @@aa:8 15 Effective Address Calculation Method 8 7 op Effective Address (EA) 0 abs 15 8 7 H'00 0 abs 15 Memory contents (16 bits) 28 Notation: rm, rn: Register field Operation field op: disp: Displacement IMM: Immediate data abs: Absolute address 0 2.5 Instruction Set The H8/300L CPU can use a total of 55 instructions, which are grouped by function in table 2-3. Table 2-3 Instruction Set Function Instructions Types PUSH*1, POP*1 Data transfer MOV, 1 Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG 14 Logic operations AND, OR, XOR, NOT 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8 Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST 14 Branch Bcc*2, JMP, BSR, JSR, RTS 5 System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8 Block data transfer EEPMOV 1 Total: 55 Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. 2. Bcc is a conditional branch instruction in which cc represents a condition code. Tables 2-4 to 2-11 give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. 29 Notation Rd General register (destination) Rs General register (source) Rn General register (EAd) <EAd> Destination operand (EAs) <EAs> Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag of CCR C C (carry) flag of CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition - Subtraction x Multiplication / Division AND logical OR logical Exclusive OR logical Move Inverse logic (logical complement) :3 3-bit length :8 8-bit length :16 16-bit length ()< > Contents of operand effective address 30 2.5.1 Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-6 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction Size* Function MOV B/W (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @-Rn, and @Rn+ addressing modes are available for word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. PUSH W Rn @-SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @-SP. POP W @SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. Notes: * Size: Operand size B: Byte W: Word Certain precautions are required in data access. See 2.8.1, Notes on Data Access, for details. 31 15 8 7 0 op rm 15 8 rn 0 rm 8 RmRn 7 op 15 MOV rn @RmRn 7 0 op rm rn @(d:16, Rm)Rn disp 15 8 7 0 op rm 15 8 op 7 0 rn 15 @Rm+Rn, or Rn @-Rm rn abs 8 @aa:8Rn 7 0 op rn @aa:16Rn abs 15 8 op 7 0 rn 15 IMM 8 #xx:8Rn 7 0 op rn #xx:16Rn IMM 15 8 op 7 0 1 1 1 rn Notation: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2-6 Data Transfer Instruction Codes 32 PUSH, POP @SP+ Rn, or Rn @-SP 2.5.2 Arithmetic Operations Table 2-5 describes the arithmetic instructions. Table 2-5 Arithmetic Instructions Instruction Size* Function ADD SUB B/W Rd Rs Rd, Rd + #IMM Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. ADDX SUBX B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. INC DEC B Rd 1 Rd Increments or decrements a general register. ADDS SUBS W Rd 1 Rd, Rd 2 Rd Adds or subtracts immediate data to or from data in a general register. The immediate data must be 1 or 2. DAA DAS B Rd decimal adjust Rd MULXU B Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. DIVXU B Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. CMP B/W Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR according to the result. Word data can be compared only between two general registers. NEG B 0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register. Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in a general register by referring to the CCR. Notes: * Size: Operand size B: Byte W: Word 33 2.5.3 Logic Operations Table 2-6 describes the four instructions that perform logic operations. Table 2-6 Logic Operation Instructions Instruction Size* Function AND B Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B ~ Rd Rd Obtains the one's complement (logical complement) of general register contents. Notes: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2-7 describes the eight shift instructions. Table 2-7 Shift Instructions Instruction Size* Function SHAL SHAR B Rd shift Rd SHLL B Performs an arithmetic shift operation on general register contents. SHLR ROTL Performs a logical shift operation on general register contents. B ROTR ROTXL ROTXR Rd shift Rd Rd rotate Rd Rotates general register contents. B Rd rotate through carry Rd Rotates general register contents through the C (carry) bit. Notes: * Size: Operand size B: Byte 34 Figure 2-7 shows the instruction code format of arithmetic, logic, and shift instructions. 15 8 7 op 0 rm 15 8 7 0 op 15 7 op 0 rm 8 op rn 7 MULXU, DIVXU 0 rn ADD, ADDX, SUBX, CMP (#XX:8) IMM 15 8 7 op 0 rm 15 8 op ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT rn 8 15 ADD, SUB, CMP, ADDX, SUBX (Rm) rn 7 rn 15 rn AND, OR, XOR (Rm) 0 IMM 8 AND, OR, XOR (#xx:8) 7 0 op rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Notation: op: Operation field rm, rn: Register field IMM: Immediate data Figure 2-7 Arithmetic, Logic, and Shift Instruction Codes 35 2.5.5 Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-8 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ~ (<bit-No.> of <EAd>) (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ~ (<bit-No.> of <EAd>) Z Tests a specified bit in a general register or memory and sets or clears the zero flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C (<bit-No.> of <EAd>) C ANDs the carry flag with a specified bit in a general register or memory and stores the result in the carry flag. BIAND B C [~ (<bit-No.> of <EAd>)] C ANDs the carry flag with the inverse of a specified bit in a general register or memory and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C (<bit-No.> of <EAd>) C ORs the carry flag with a specified bit in a general register or memory and stores the result in the carry flag. BIOR B C [~ (<bit-No.> of <EAd>)] C ORs the carry flag with the inverse of a specified bit in a general register or memory and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Notes: * Size: Operand size B: Byte 36 Table 2-8 Bit-Manipulation Instructions (cont) Instruction Size* Function BXOR B C (<bit-No.> of <EAd>) C XORs the carry flag with a specified bit in a general register or memory and stores the result in the carry flag. BIXOR B C ~ [(<bit-No.> of <EAd>)] C XORs the carry flag with the inverse of a specified bit in a general register or memory and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (<bit-No.> of <EAd>) C Copies a specified bit in a general register or memory to the carry flag. BILD B ~ (<bit-No.> of <EAd>) C Copies the inverse of a specified bit in a general register or memory to the carry flag. The bit number is specified by 3-bit immediate data. BST B C (<bit-No.> of <EAd>) Copies the carry flag to a specified bit in a general register or memory. BIST B ~ C (<bit-No.> of <EAd>) Copies the inverse of the carry flag to a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. Notes: * Size: Operand size B: Byte Certain precautions are required in bit manipulation. See 2.8.2, Notes on Bit Manipulation, for details. 37 BSET, BCLR, BNOT, BTST 15 8 7 op 0 IMM 15 8 7 op 0 rm 15 8 Operand: register direct (Rn) Bit No.: immediate (#xx:3) rn Operand: register direct (Rn) Bit No.: register direct (Rm) rn 7 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit No.: op rn 0 0 0 0 Operand: register indirect (@Rn) op rm 0 0 0 0 Bit No.: op op 15 8 15 8 7 0 7 abs IMM 15 8 0 Operand: absolute (@aa:8) 0 0 7 0 Bit No.: immediate (#xx:3) 0 op abs op register direct (Rm) 0 op op immediate (#xx:3) rm 0 Operand: absolute (@aa:8) 0 0 0 Bit No.: register direct (Rm) BAND, BOR, BXOR, BLD, BST 15 8 7 op 0 IMM 15 8 7 op op 15 8 Operand: register direct (Rn) Bit No.: immediate (#xx:3) rn 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit No.: 7 0 op abs op immediate (#xx:3) IMM 0 Operand: absolute (@aa:8) 0 0 0 Bit No.: immediate (#xx:3) Notation: Operation field op: rm, rn: Register field Absolute address abs: IMM: Immediate data Figure 2-8 Bit Manipulation Instruction Codes 38 BIAND, BIOR, BIXOR, BILD, BIST 15 8 7 op 0 IMM 15 8 7 op op 15 8 Operand: register direct (Rn) Bit No.: immediate (#xx:3) rn 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit No.: 7 0 op abs op immediate (#xx:3) IMM 0 Operand: absolute (@aa:8) 0 0 0 Bit No.: immediate (#xx:3) Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-8 Bit Manipulation Instruction Codes (cont) 39 2.5.6 Branching Instructions Table 2-9 describes the branching instructions. Table 2-9 Branching Instructions Instruction Size Function Bcc -- Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never BHI High CZ=0 BLS Low or same CZ=1 BCC (BHS) Carry clear (high or same) C=0 BCS (BLO) Carry set (low) C=1 BNE Not equal Z=0 BEQ Equal Z=1 BVC Overflow clear V=0 BVS Overflow set V=1 BPL Plus N=0 BMI Minus N=1 BGE Greater or equal NV=0 BLT Less than NV=1 BGT Greater than Z (N V) = 0 BLE Less or equal Z (N V) = 1 JMP -- Branches unconditionally to a specified address. JSR -- Branches to a subroutine at a specified address. BSR -- Branches to a subroutine at a specified displacement from the current address. RTS -- Returns from a subroutine. 40 Figure 2-9 shows the instruction code format of branching instructions. 15 8 op 7 0 cc 15 disp 8 7 op 0 rm 15 Bcc 8 0 0 0 7 0 JMP (@Rm) 0 op JMP (@aa:16) abs 15 8 7 0 op abs 15 8 JMP (@@aa:8) 7 0 op disp 15 8 7 op 0 rm 15 BSR 8 0 0 0 7 0 JSR (@Rm) 0 op JSR (@aa:16) abs 15 8 7 0 op abs 15 8 7 JSR (@@aa:8) 0 op RTS Notation: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2-9 Branching Instruction Codes 41 2.5.7 System Control Instructions Table 2-10 describes the system control instructions. Figure 2-10 shows their object code formats. Table 2-10 System Control Instructions Instruction Size* Function RTE -- Returns from an exception-handling routine. SLEEP -- Causes a transition from active mode to a power-down mode (sleep mode, standby mode, or watch mode), or from subactive mode to watch mode, or from subactive mode via watch mode to active mode. For details, see 3.3, System Modes. LDC B Rs CCR, #IMM CCR Moves immediate data or general register contents to the condition code register. STC B CCR Rd Copies the condition code register to a specified general register. ANDC B CCR #IMM CCR Logically ANDs the condition code register with immediate data. ORC B CCR #IMM CCR Logically ORs the condition code register with immediate data. XORC B CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data. NOP -- PC + 2 PC Only increments the program counter. Notes: * Size: Operand size B: Byte 42 15 8 7 0 op 15 8 RTE, SLEEP, NOP 7 0 op 15 rn 8 7 LDC, STC (Rn) 0 op IMM ANDC, ORC, XORC, LDC (#xx:8) Notation: op: Operation field rn: Register field IMM: Immediate data Figure 2-10 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-11 describes the block data transfer instruction. Figure 2-11 shows its object code format. Table 2-11 Block Data Transfer Instruction Instruction Size Function EEPMOV -- If R4L 0 then repeat until @R5+ @R6+ R4L - 1 R4L R4L = 0 else next; Moves a data block according to parameters set in general registers R4L, R5, and R6. R4L: Size of block (bytes) R5: Starting source address R6: Starting destination address Execution of the next instruction starts as soon as the block transfer is completed. 43 15 8 7 0 op op Notation: op: Operation field Figure 2-11 Block Data Transfer Instruction Code Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 R6 R5 + R4L 2. R6 + R4L When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction. R5 R5 + R4L R6 H'FFFF Not allowed 44 R6 + R4L 2.6 CPU States 2.6.1 Overview There are three CPU states: program execution state, program halt state, and exception-handling state. Program execution state includes active mode and subactive mode. In program halt state there are sleep mode, standby mode, and watch mode. These states are shown in figure 2-12. Figure 2-13 shows the state transitions. State Program execution state Active mode The CPU executes successive program instructions, synchronized by the system clock. Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock. Program halt state Sleep mode A state in which CPU operations are stopped to conserve power. Standby mode Watch mode Exceptionhandling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt. Figure 2-12 CPU Operation States 45 Low-power operation modes Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt Exception- Exceptionhandling handling request ends Program halt state Program execution state SLEEP instruction executed Note: On the transitions between modes, see 3.3, System Modes. Figure 2-13 State Transitions 2.6.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are two modes in this state, active mode and subactive mode. Operation is synchronized with the system clock in active mode, and with a subclock in subactive mode. For details on these modes, see 3.3, System Modes. 2.6.3 Program Halt State In the program halt state there are three modes: sleep mode, standby mode, and watch mode. For details on these modes, see 3.3, System Modes. 2.6.4 Exception-Handling State The exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt, and the CPU changes its normal processing flow. In exception handling caused by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack. For details on interrupt handling, see 3.2.2, Interrupts. 46 2.7 Basic Operation Timing CPU operation is synchronized by a clock (oi). oi is either the system clock (o) generated by the system clock oscillator circuit, or the subclock (oSUB) generated by the subclock oscillator circuit. oi denotes o in active mode and oSUB in subactive mode. For details, see section 4, Clock Pulse Generators. The period from the rising edge of oi to the next rising edge is called one state. A memory cycle or bus cycle consists of two states; access to on-chip memory and to on-chip peripheral modules always takes place in two states. 2.7.1 Access to On-Chip Memory (RAM, ROM) Two-state access is employed for on-chip memory. The data bus width is 16 bits, allowing access in byte or word size. Figure 2-14 shows the on-chip memory access cycle. Bus cycle T1 state T2 state oi Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2-14 On-Chip Memory Access Cycle 47 2.7.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states. The data bus width is 8 bits, so access is made in byte size only. This means that two instructions must be used for a word size data access. Figure 2-15 shows the on-chip peripheral module access cycle. Bus cycle T1 state T2 state oi Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2-15 On-Chip Peripheral Module Access Cycle 48 2.8 Application Notes The following points are to be observed in using the H8/300L CPU. 2.8.1 Notes on Data Access 1. The address space of the H8/300L CPU includes some empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. Transfer from CPU to empty area: The transferred data will be lost. This action may also cause the CPU to misoperate. Transfer from empty area to CPU: Unpredictiable data is transferred. 2. Internal data transfer to or from on-chip modules other than ROM and RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the following results will occur. Word access from CPU to I/O register area: Upper byte: Will be written to I/O register. Lower byte: Transferred data will be lost. Word access from I/O register to CPU: Upper byte: Will be written to upper part of CPU register. Lower byte: Data written to lower part of CPU register cannot be guaranteed. Byte size instructions should therefore be used when transferring data to or from I/O registers outside the on-chip ROM and RAM areas. Figure 2-16 shows the data size in which access can be made with on-chip peripheral modules. 49 Access Word Byte H'0000 H'002B Interrupt vector (44 bytes) 32,256*1 bytes On-chip ROM (32,212 bytes) *1 H'7DFF *2 H'FB80 1,024*2 bytes On-chip RAM H'FF7F H'FF80 H'FF9F H'FFA0 H'FFA3 H'FFA4 H'FFAF H'FFB0 32-byte data buffer x Internal I/O register (4 bytes) Reserved x Internal I/O ergister (80 bytes) x x H'FFFF Notes: The H8/3614 is shown as an example. 1. The H8/3612 has 16,384 bytes up to address H'3FFF. The H8/3613 has 24,576 bytes up to address H'5FFF. 2. The H8/3612 has 512 bytes from address H'FD80. The H8/3613 is the same as the H8/3614. Figure 2-16 Data Size for Access to and from On-Chip Peripheral Modules 50 2.8.2 Notes on Bit Manipulation The H8/300L CPU executes bit manipulation instructions by a read-modify-write operation on 8-bit data. When bit manipulation instructions are executed in the cases illustrated below, care must be taken since the operation may affect other bits besides those being manipulated. 1. Bit manipulation in two registers assigned to the same address (when the source and destination are different) Example 1: Timer load register and timer counter In this example, a bit manipulation instruction is executed in the timer load register and timer counter of a reloadable timer. Since the timer load register and timer counter share the same address, the operations take place as follows. a. Read: The timer counter value at the time is read. b. Modify: The CPU modifies (sets or resets) the bit designated with the instruction. (Other bits remain the same.) c. Write: The modified data is written to the timer load register. The timer counter is counting based on the system clock (o), so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. Figure 2-17 shows the reloadable timer configuration. R Timer counter Reload W Timer load register Internal bus o R: Read W: Write Figure 2-17 Reloadable Timer Configuration Example 2: Port data register (pin input and data register) When a bit manipulation instruction is executed designating a port data register, it may cause changes in pin I/O states or data register contents other than the intended bit. 51 As noted above, the H8/300L CPU executes bit manipulation instructions by a read-modify-write operation on 8-bit data. Since the same address is used for the I/O port data register and reading of pin input, a bit manipulation instruction designating a port functions as follows. PMOS open-drain pins: pins other than the modified bit * When set as an input pin (data register = 0) First the CPU reads the pin input level (read), then it sets or resets the designated bit (modify; other bits remain the same), and writes that value to the data register (write). If the input level is high (read data = 1), a value of 1 is written to the data register, changing the input pin to an output pin (high-level output). If the input level is low, no change occurs. * When set as an output pin (data register = 1, high-level output) If the output level is higher than the input high level (VIH), there is no change. If the output level is lower than the input low level (VIL), a value of 0 is written to the data register, so that the PMOS buffer transistor is turned off resulting in pull-down (low level) or high-impedance state. If the output level is pulled down by the load to an intermediate level, the resulting state is indeterminate. Standard I/O pins: pins other than the modified bit * When set as an input pin The CPU reads the pin input level and writes that value to the data register, which may or may not result in a change to the data register contents. * When set as an output pin The data register is read, so no change occurs. 2. Bit manipulation in a register containing a write-only bit Example: PWM data register, etc. (Note that read and write characteristics can differ from bit to bit.) Write-only bits cannot be read. Write-only bits other than the intended bit are set to 1. 52 Table 2-12 lists the registers that share the same address, while table 2-13 lists the registers that contain write-only bits. Table 2-12 Registers Assigned to the Same Address Register Name Abbreviation Address Timer load register B/Timer counter B TLB/TCB H'FFC3 Timer load register C/Timer counter C TLC/TCC H'FFC5 Timer load register E/Timer counter E TLE/TCE H'FFC9 Port data register 1* PDR1 H'FFD1 Port data register 2* PDR2 H'FFD2 Port data register 4* PDR4 H'FFD4 Port data register 8* PDR8 H'FFD8 Port data register 9* PDR9 H'FFD9 Port data register A* PDRA H'FFDA Note: * These port data registers are used also for pin input. Table 2-13 Registers with Write-Only Bits Register Name Abbreviation Address Serial mode register 1 SMR1 H'FFB0 PWM control register*1 PWCR H'FFCC PWM data register U*1 PWDRU H'FFCD PWN data register L*1 PWDRL H'FFCE Port control register 1 PCR1 H'FFE1 Port control register 2 PCR2 H'FFE2 Port control register 8 PCR8 H'FFE8 Port control register 9 PCR9 H'FFE9 Port control register A PCRA H'FFEA Port mode register 0 PMR0 H'FFEF Timer mode register D*2 TMD H'FFC6 System control register 2*3 SYSCR2 H'FFF1 Notes: 1. Not present in the H8/3612. 2. Only bit CRL (bit 7) is write-only. 3. Bit DTON (bit 3) is a write-only bit only in subactive mode. In active mode it cannot be read or written. 53 Section 3 System Control 3.1 Overview This section explains the reset state, exception handling, and system modes. 3.2 Exception Handling Exception handling includes processing of reset exceptions and of interrupts. Table 3-1 summarizes the exception sources and their priorities. Reset exception handling has the highest priority. Table 3-1 Types of Exception Handling and Priorities Priority Exception Source Timing for Start of Exception Handling High Reset Reset exception handling starts as soon as RES pin changes from low to high. Interrupt When interrupt request is made, interrupt exception handling starts after execution of present instruction is completed. Low 3.2.1 Reset When the RES pin goes low, all processing stops and the chip enters the reset state. The internal state of the CPU and the registers of on-chip peripheral modules are initialized. The I bit of the condition code register (CCR) is set, masking all interrupts. As soon as the RES pin goes from low to high, reset exception handling starts. The contents of the reset vector address (H'0000 to H'0001) are read and loaded into the program counter (PC). Then program execution starts from the address indicated in PC. Figure 3-1 shows the reset sequence. Notes: 1. To make sure a reset is carried out properly, when power is turned on the RES pin should be held low for at least 20 ms (ceramic oscillator) or 40 ms (crystal oscillator) after the power supply starts up. 2. When resetting during operation, keep the RES pin at low level for at least 10 system clock cycles. 3. After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. Programs should be coded to initialize the stack pointer before clearing the interrupt mask. An even-numbered address must be set in SP. It is recommended that programs start with an instruction initializing SP (e.g., MOV.W #xx:16, SP). 55 Reset state Reset exception handling and program execution Vector fetch Internal processing Prefetch of first instruction of program RES o Internal address bus (1) (2) Internal read signal Internal write signal Internal data bus (16 bits) (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program starting address (3) First instruction of program Figure 3-1 Reset Sequence 3.2.2 Interrupts The interrupt sources include external interrupts (IRQ5 to IRQ0), and internal interrupts requested from on-chip peripheral modules. Table 3-2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed. The interrupts have the following features. 1. Both internal and external interrupts (IRQ5 to IRQ0) can be masked by the I bit of CCR. When this bit is set to 1, the interrupt request flag is set but interrupts cannot be accepted. 2. The external interrupt pins IRQ4, IRQ1, and IRQ0 can each be set independently to either rising-edge sensing or falling-edge sensing. The remaining external interrupt pins, IRQ5, IRQ3, and IRQ2, are fixed at falling-edge sensing. 56 Table 3-2 Interrupt Sources Priority Interrupt Origin of Interrupt Vector Starting Address High Reset External pin H'0000 (Reserved)*1 -- H'0002 H'0004 H'0006 IRQ0 External pin H'0008 IRQ1 H'000A IRQ2 H'000C IRQ3 H'000E IRQ4 H'0010 IRQ5 H'0012 (Reserved)*1 -- H'0014 Timer A overflow Timer A H'0016 Timer B overflow Timer B H'0018 Timer C overflow Timer C H'001A Timer D overflow Timer D H'001C Timer E overflow Timer E Direct transfer Standby timer (Reserved)*1 -- H'001E activator*2 H'0020 H'0022 H'0024 Low SCI1 transfer complete, error Serial communication interface 1 H'0026 SCI2 transfer complete, error Serial communication interface 2 H'0028 A/D conversion complete A/D converter H'002A Notes: 1. Vector addresses indicated as "Reserved" cannot be used. 2. This circuit is triggered by a SLEEP instruction and generates an interrupt after a certain time. 57 3.2.3 Interrupt Control Registers Table 3-3 lists the registers that are used to control interrupts. Table 3-3 Interrupt Control Registers Register Name Abbreviation R/W Initial Value Address Port mode register 1 PMR1 R/W H'00 H'FFEB IRQ edge select register IEGR R/W H'EC H'FFF2 Interrupt enable register 1 IENR1 R/W H'C0 H'FFF3 Interrupt enable register 2 IENR2 R/W H'00 H'FFF4 Interrupt enable register 3 IENR3 R/W H'3C H'FFF5 Interrupt request register 1 IRR1 R/W* H'C0 H'FFF6 Interrupt request register 2 IRR2 R/W* H'00 H'FFF7 Interrupt request register 3 IRR3 R/W* H'3C H'FFF8 Note: * Only a write of 0 for flag clearing is possible. 1. Port mode register 1 (PMR1) Bit 7 6 5 4 3 2 1 0 NOISE CANCEL EVENT IRQC5 IRQC4 IRQC3 IRQC2 IRQC1 IRQC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PMR1 is an 8-bit read/write register that designates whether pins in port 1 are used for generalpurpose I/O or for external interrupt input. It is also used to turn the noise canceller function of pin IRQ0 on or off. Note: Before switching a pin function by modifying bits IRQ5 to IRQ0 in PMR1, first clear the interrupt enable flag to disable the interrupt. After the pin function has been switched, issue any instruction, then clear the interrupt request flag to 0. Program example: MOV. B R0L, @IENR1 MOV. B R0L, @PMR1 NOP MOV. B R0L, @IRR1 MOV. B R1L, @IENR1 ...................... Disable interrupt ...................... Change pin function ...................... Issue any instruction ...................... Clear interrupt request flag ...................... Enable interrupt 58 Bit 7: Noise cancel (NOISE CANCEL) This bit enables or disables the noise canceller function of pin IRQ0. Bit 7 NOISE CANCEL Description 0 Disables the noise canceller function of pin IRQ0. 1 Enables the noise canceller function of pin IRQ0. Input is sampled at intervals of 256 states. If two consecutive values do not match, the input is regarded as noise. (initial value) Bit 6: P16/EVENT pin function switch (EVENT) Bit 6 EVENT Description 0 P16/EVENT pin functions as P16 pin. 1 P16/EVENT pin functions as EVENT pin. (initial value) Bit 5: P15/IRQ5/TMOE pin function switch (IRQC5) Bit 5 IRQC5 Description 0 P15/IRQ5/TMOE pin functions as P15/TMOE pin.* 1 P15/IRQ5/TMOE pin functions as IRQ5 pin. (initial value) Note: * On use of this pin as TMOE pin, see 5.3.2, Port Mode Register 4 (PMR4). Bit 4: P14/IRQ4 pin function switch (IRQC4) Bit 4 IRQC4 Description 0 P14/IRQ4 pin functions as P14 pin. 1 P14/IRQ4 pin functions as IRQ4 pin. (initial value) Bit 3: P13/IRQ3 pin function switch (IRQC3) Bit 3 IRQC3 Description 0 P13/IRQ3 pin functions as P13 pin. 1 P13/IRQ3 pin functions as IRQ3 pin. (initial value) 59 Bit 2: P12/IRQ2 pin function switch (IRQC2) Bit 2 IRQC2 Description 0 P12/IRQ2 pin functions as P12 pin. 1 P12/IRQ2 pin functions as IRQ2 pin. (initial value) Bit 1: P11/IRQ1 pin function switch (IRQC1) Bit 1 IRQC1 Description 0 P11/IRQ1 pin functions as P11 pin. 1 P11/IRQ1 pin functions as IRQ1 pin. (initial value) Bit 0: P10/IRQ0 pin function switch (IRQC0) Bit 0 IRQC0 Description 0 P10/IRQ0 pin functions as P10 pin. 1 P10/IRQ0 pin functions as IRQ0 pin. 2. (initial value) IRQ edge select register (IEGR) Bit 7 6 5 4 3 2 1 0 -- -- -- IEG4 -- -- IEG1 IEG0 Initial value 1 1 1 0 1 1 0 0 Read/Write -- -- -- R/W -- -- R/W R/W IEGR is an 8-bit read/write register, used to designate whether pins IRQ0, IRQ1, and IRQ4 are set to rising edge sensing or falling edge sensing. Bits 7 to 5: Reserved bits Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bit 4: IRQ4 pin input edge select (IEG4) Bit 4 IEG4 Description 0 Falling edge of IRQ4 pin input is detected. 1 Rising edge of IRQ4 pin input is detected. 60 (initial value) Bits 3 and 2: Reserved bits Bits 3 and 2 are reserved; they are always read as 1, and cannot be modified. Bit 1: IRQ1 pin input edge select (IEG1) Bit 1 IEG1 Description 0 Falling edge of IRQ1 pin input is detected. 1 Rising edge of IRQ1 pin input is detected. (initial value) Bit 0: IRQ0 pin input edge select (IEG0) Bit 0 IEG0 Description 0 Falling edge of IRQ0 pin input is detected. 1 Rising edge of IRQ0 pin input is detected. 3. (initial value) Interrupt enable register 1 (IENR1) Bit 7 6 5 4 3 2 1 0 -- -- IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 Initial value 1 1 0 0 0 0 0 0 Read/Write -- -- R/W R/W R/W R/W R/W R/W IENR1 is an 8-bit read/write register that enables or disables external interrupts. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved; they are always read as 1, and cannot be modified. Bits 5 to 0: IRQ5 to IRQ0 interrupt enable (IEN5 to IEN0) Bits 5 to 0 IEN5 to IEN0 Description 0 Disables interrupt requests by IRRI5 to IRRI0. 1 Enables interrupt requests by IRRI5 to IRRI0. 61 (initial value) 4. Interrupt enable register 2 (IENR2) Bit 7 6 5 4 3 2 1 0 -- -- IENDT IENTE IENTD IENTC IENTB IENTA Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W IENR2 is an 8-bit read/write register that enables or disables direct transfer interrupts and timer A to E overflow interrupts. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved, but they can be written and read. Bit 5: Direct transfer interrupt enable (IENDT) Bit 5 IENDT Description 0 Disables direct transfer interrupt requests by IRRDT. 1 Enables interrupt requests by IRRDT. (initial value) Bits 4 to 0: Timer E to A interrupt enable (IENTE to IENTA) Bits 4 to 0 IENTE to IENTA Description 0 Disables interrupt requests by IRRTE to IRRTA. 1 Enables interrupt requests by IRRTE to IRRTA. 5. (initial value) Interrupt enable register 3 (IENR3) Bit 7 6 5 4 3 2 1 0 IENAD -- -- -- -- -- IENS2 IENS1 Initial value 0 0 1 1 1 1 0 0 Read/Write R/W R/W -- -- -- -- R/W R/W IENR3 is an 8-bit read/write register that enables or disables interrupts from the A/D converter and serial communication interfaces 1 and 2. 62 Bit 7: A/D conversion complete interrupt enable (IENAD) Bit 7 IENAD Description 0 Disables interrupt requests by IRRAD. 1 Enables interrupt requests by IRRAD. (initial value) Bit 6: Reserved bit Bit 6 is reserved, but it can be written and read. Bits 5 to 2: Reserved bits Bits 5 to 2 are reserved; they are always read as 1, and cannot be modified. Bits 1 and 0: Serial communication interface 2 and 1 interrupt enable (IENS2 and IENS1) Bits 1, 0 IENS2, IENS1 Description 0 Disables interrupt requests by IRRS2 and IRRS1. 1 Enables interrupt requests by IRRS2 and IRRS1. 6. (initial value) Interrupt request register 1 (IRR1) Bit Initial value Read/Write 7 6 5 4 3 2 1 0 -- -- IRRI5 IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 1 1 0 0 0 0 0 0 -- R/W * R/W * R/W * R/W * -- R/W * R/W * Note: * Only a write of 0 for flag clearing is possible. IRR1 is an 8-bit read/write register with flags that are set to 1 when an external interrupt is requested. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved; they are always read as 1, and cannot be modified. 63 Bits 5 to 0: IRQ5 to IRQ0 interrupt request (IRRI5 to IRRI0) Bits 5 to 0 IRRI5 to IRRI0 Description 0 No interrupt request from the corresponding pin (IRQ5 to IRQ0). (initial value) 1 Setting conditions: Set when the corresponding pin (IRQ5 to IRQ0) designated for interrupt input in PMR1 and the designated edge is input. Clearing method: Cleared when software writes 0 in the flag. (The flag is not automatically cleared when an interrupt is accepted.) 7. Interrupt request register 2 (IRR2) Bit 7 6 5 4 3 2 1 0 -- -- IRRDT IRRTE IRRTD IRRTC IRRTB IRRTA Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- R/W * R/W * R/W * R/W* R/W * R/W * Note: * Only a write of 0 for flag clearing is possible. IRR2 is an 8-bit read/write register with flags that are set to 1 when a direct transfer interrupt or timer A to E overflow interrupt is requested. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved; they are always read as 0, and only 0 may be written. Bit 5: Direct transfer interrupt request (IRRDT) Bit 5 IRRDT Description 0 No direct transfer interrupt request. 1 Setting conditions: In subactive mode, when the system control register 2 (SYSCR2) DTON bit = 1, the system control register 1 (SYSCR1) LSON bit = 0,and the interrupt enable register 2 (IENR2) IENDT bit = 1, execution of a SLEEP instruction results in direct transfer to active mode via watch mode. During this process a direct transfer interrupt is requested and the IRRDT flag is set to 1. (initial value) Clearing method: Cleared when software writes 0 in the flag. (The flag is not automatically cleared when an interrupt is accepted.) 64 Bits 4 to 0: Timers E to A interrupt request (IRRTE to IRRTA) Bits 4 to 0 IRRTE to IRRTA Description 0 No overflow interrupt request from the corresponding timer (E to A). (initial value) 1 Setting conditions: When a timer E to A overflow interrupt is requested, the corresponding flag (IRRTE to IRRTA ) is set to 1. Clearing method: Cleared when software writes 0 in the flag. (The flag is not automatically cleared when an interrupt is accepted.) 8. Interrupt request register 3 (IRR3) Bit 7 6 5 4 3 2 1 0 IRRAD -- -- -- -- -- IRRS2 IRRS1 Initial value 0 0 1 1 1 1 0 0 Read/Write R/W * -- -- -- -- -- R/W * R/W * Note: * Only a write of 0 for flag clearing is possible. Bit 7: A/D conversion complete interrupt request (IRRAD) Bit 7 IRRAD Description 0 No A/D conversion complete interrupt request. 1 Setting conditions: When the A/D converter completes A/D conversion, an interrupt is requested and the IRRAD flag is set to 1. (initial value) Clearing method: Cleared when software writes 0 in the flag. (The flag is not automatically cleared when an interrupt is accepted.) Bit 6: Reserved bit Bit 6 is reserved; it is always read as 0, and only 0 may be written. Bits 5 to 2: Reserved bits Bits 5 to 2 are reserved; they are always read as 1, and cannot be modified. 65 Bits 1 and 0: Serial communication interface 2 and 1 interrupt request (IRRS2, IRRS1) Bits 1, 0 IRRS2, IRRS1 Description 0 No transfer complete or error interrupt request by the corresponding serial communication interface. (initial value) 1 Setting conditions: When an interrupt is requested due to transfer complete or error on serial communication interface 2 or 1, the corresponding flag (IRRS2 or IRRS1) is set to 1. Clearing method: Cleared when software writes 0 in the flag. (The flag is not automatically cleared when an interrupt is accepted.) 3.2.4 External Interrupts There are six external interrupts, IRQ5 to IRQ0. These interrupts are requested by means of input signals at pins IRQ5 to IRQ0. Interrupts IRQ4, IRQ1, and IRQ0 are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG4, IEG1, and IEG0 in the IRQ edge select register (IEGR). The other external interrupts, IRQ5, IRQ3, and IRQ2, are detected by falling edge sensing only. In order to enable external interrupt input, it is first necessary to set the corresponding bit in port mode register 1 (PMR1) to 1. When the designated edge is input at pins IRQ5 to IRQ0, the corresponding flag in interrupt request register 1 (IRR1) is set to 1. After the interrupt is accepted, the flag that was set is not automatically cleared, so the interrupt handling routine must be programmed to clear the flag to 0. A given interrupt request can be disabled by clearing its interrupt enable flag to 0. Interrupts IRQ5 to IRQ0 are enabled by setting bits IEN5 to IEN0 to 1 in interrupt enable register 1. All interrupts can be masked by setting the I bit in CCR to 1. When IRQ5 to IRQ0 interrupt requests are accepted, the I bit is set to 1. The order of priority is from IRQ0 (high) to IRQ5 (low). For details see table 3-2. A noise canceller function can be selected for IRQ0 interrupts, in which case a noise cancellation circuit samples the IRQ0 input every 256 states. If two consecutive sampling results do not match, noise is assumed and the request is not accepted. 66 3.2.5 Internal Interrupts There are nine internal interrupts that can be requested by the on-chip peripheral modules. These interrupts can be masked (held pending) by setting the I bit in CCR to 1. When an internal interrupt request is accepted and an interrupt handler is executed, the I bit is set to 1. For the order of priority of interrupts from on-chip peripheral modules, see table 3-2. 3.2.6 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3-2 shows a block diagram of the interrupt controller, while figure 3-3 shows the flow up to interrupt acceptance. Priority decision Interrupt controller IRQ 5 to IRQ 0 interrupt request flag or internal interrupt request flag Interrupt request IRQ 5 to IRQ 0 interrupt enable bits and internal interrupt enable bits I CCR (CPU) Figure 3-2 Block Diagram of Interrupt Controller 67 Program execution state IRRI0=1 No Yes IEN0=1 No Yes IRRI1=1 No Yes IEN1=1 No Yes IRRI2=1 No Yes IEN2=1 No Yes IRRAD = 1 No Yes IENAD = 1 No Yes I=0 No Yes PC contents saved CCR contents saved I1 Notation: PC: Program counter CCR: Condition code register I bit of CCR I: Branch to interrupt handling routine Figure 3-3 Flow up to Interrupt Acceptance 68 The following operations take place when an interrupt occurs. 1. When an interrupt is requested by external interrupt pin input or by a peripheral module, an interrupt request signal is sent to the interrupt controller. 2. When the interrupt controller receives an interrupt request signal, it sets the interrupt request flag. 3. From among the interrupts for which the corresponding interrupt enable bit is also set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (See table 3-2.) 4. The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is accepted; if the I bit is 1, the interrupt request is held pending. 5. If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 6. The I bit of CCR is set to 1, masking all further interrupts. 7. A vector address is generated for the accepted interrupt, and the contents of that address are read and loaded into PC. Program execution then resumes from the address indicated in PC. Note: No interrupt detection takes place immediately after completion of ORC, ANDC, XORC, or LDC instructions. 69 SP - 4 SP (R7) CCR SP - 3 SP + 1 CCR* SP - 2 SP + 2 PCH SP - 1 SP + 3 PCL SP (R7) SP + 4 Even address Stack area Prior to start of interrupt exception handling Contents saved to stack After completion of interrupt exception handling Notation: PCH: Upper 8 bits of program counter (PC) PCL: Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt. 2. Saving and restoring of register contents must always be done in word size, and must start from an even-numbered address. * Ignored on return from interrupt. Figure 3-4 Stack State after Completion of Interrupt Exception Handling Figure 3-5 shows a typical interrupt sequence. 70 Figure 3-5 Interrupt Sequence 71 Internal data bus (16 bits) Internal write signal Internal read signal Internal address bus o Interrupt request signal (4) Instruction prefetch (3) Internal processing (5) (1) Stack access (6) (7) (9) Vector fetch (8) Internal processing (10) (9) Prefetch instruction of interrupt-handling routine (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine (2) (1) Interrupt level decision and wait for end of instruction Interrupt is accepted 3.2.7 Return from an Interrupt After completion of interrupt handling, the handler routine ends by executing an RTE instruction, to resume the original program from the point of the interrupt. When RTE is executed, the values saved on the stack are restored to CCR and PC as shown in figure 3-6. Instruction execution resumes from the address indicated in PC. (Processing of RTE instruction) (Stack state) Memory contents of address indicated in SP are sent to CCR. SP value +2 Memory contents of address indicated in SP are sent to PC. SP (R7) CCR SP - 4 CCR SP + 1 CCR* SP - 3 CCR* SP + 2 PC H SP + 3 PC L Stack SP - 2 area SP - 1 SP + 4 PC H PC L SP (R7) SP value +2 Stack area CCR and PC values restored Before RTE instruction is executed After RTE instruction is executed Note: Ignored on return from interrupt. Figure 3-6 Stack State When RTE Instruction is Executed 3.2.8 Interrupt Response Time Table 3-4 shows the number of wait states after an interrupt request flag is set and until the first instruction of the interrupt handler is executed. Table 3-4 Interrupt Wait States No. Item States 1 Waiting time for completion of executing instruction* 1 to 13 2 Saving of PC and CCR to stack 4 3 Vector fetch 2 4 Instruction fetch 4 5 Internal processing 4 Total 15 to 27 Note: * Not including EEPMOV instruction. 72 3.2.9 Valid Interrupts in Each Mode Table 3-5 shows the valid interrupts in each mode. For details of the modes, see 3.3, System Modes. Table 3-5 Valid Interrupts in Each Mode Mode Interrupt Active Sleep Standby Watch Subactive IRQ0 IRQ1 x x IRQ2 x x x x IRQ3 x x x x IRQ4 x x x x IRQ5 x x x x Timer A overflow x Timer B overflow x x x x Timer C overflow x x x x Timer D overflow x x x x Timer E overflow x x x x Direct transfer x x x x SCI1 transfer complete or error x x x x SCI2 transfer complete or error x x x x A/D conversion end x x x x Note: The above table does not include interrupts occurring during a mode transition. Notation: : When an interrupt request flag is set, interrupt exception handling is started if the I bit = 0 in CCR and the interrupt enable bit = 1 for that interrupt. In sleep mode, standby mode, and watch mode, a mode transition takes place before interrupt exception handling starts. : When a SLEEP instruction is executed while the DTON bit = 1 and the LSON bit = 0, first a transition is made to watch mode and the interrupt request flag is set in synchronization with the subclock. When the interrupt request flag is set, if the interrupt enable bit = 1 for that interrupt and the I bit = 0 in CCR, a transition is made to active mode and interrupt exception handling starts. x: The interrupt request flag is not set, and no mode transition occurs. 73 3.2.10 Notes on Stack Area Use When word data is accessed in the H8/300L Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. Setting an odd address in SP may cause a program to crash. An example is shown in figure 3-7. PCH SP PCL SP R1L H'FEFC PCL H'FEFD H'FEFF SP BSR instruction SP set to H'FEFF MOV.B R1L, @-R7 Stack accessed beyond SP Contents of PCH are lost Notation: PCH: Upper byte of program counter PCL: Lower byte of program counter R1L: General register R1L SP: Stack pointer Figure 3-7 CPU Operation When Odd Address is Set in SP Word access is also performed when the condition code register (CCR) is saved and restored by the interrupt exception-handling sequence and RTE instruction. When CCR is saved, the CCR value is saved in both the upper and lower bytes of the word data. When CCR is restored, it is loaded with the value at the even address. The value at the odd address is ignored. 3.2.11 Note on Clearing Interrupt Request Registers When bits in IRR1, IRR2, and IRR3 are cleared, if an interrupt is requested during execution of the clearing instruction, setting of the interrupt request flag takes priority. 74 3.3 System Modes 3.3.1 Overview The H8/3614 Series has five modes, including power-down modes with reduced power dissipation. Table 3-6 summarizes the modes. Table 3-6 Modes Mode Description Active mode The CPU executes programs on the system clock Power-down modes Sleep mode The CPU halts, but the time-base function of timer A operates on the system clock Standby mode The CPU and all on-chip peripheral modules halt Watch mode The CPU halts, but the time-base function of timer A operates on the subclock Subactive mode The CPU and the time-base function of timer A operate on the subclock Figure 3-8 shows the transitions among these modes. SSBY = 1 and TMA3 = 1 and SLEEP instruction SSBY = 0 and SLEEP instruction Active mode LSON = 0 and IRQ0 , or LSON = 0 and time base * IRQ 0 or IRQ 1 or timer A Sleep mode Watch mode IRQ 0 or IRQ 1 DTON = 0 LSON = 0 and and SLEEP DTON = 1 and instruction LSON = 1 and SLEEP instruction IRQ0, or LSON = 1 and time base* SSBY = 1 and TMA3 = 0 and SLEEP instruction Subactive mode Standby mode RES RES RES RES Reset RES Note: * Time base: Timer A interrupt during time-based operation running on subclock. Figure 3-8 System Mode Transition Diagram 75 Table 3-7 shows the internal states in each mode. Table 3-7 Internal States in Operation Modes Function Active System clock Subclock CPU operation Watch Subactive Functions Functions Halted Halted Halted Functions Functions Functions Functions Functions Instruction Functions Halted Halted Halted Functions RAM Functions Retained Retained Retained Functions Register Functions Retained Retained Retained Functions Functions Retained Retained*1 Retained*1 Functions*2 Functions Functions Functions Functions Functions Functions Functions Functions Retained Retained Retained Retained Functions*3 I/O Peripheral module IRQ0 interrupts IRQ1 Sleep IRQ2 to IRQ5 Functions Retained Standby Retained Timer A Functions Functions Retained Functions*3 Timer B Functions Retained Retained Retained Retained Timer C Functions Retained Retained Retained Retained Timer D Functions Retained Retained Retained Retained Timer E Functions Retained Retained Retained Retained SCI1, SCI2 Functions Retained Retained Retained Retained PWM Functions Retained Retained Retained Retained A/D Functions Retained Retained Retained Retained Notes: 1. Register contents retained; output high-impedance. 2. Register contents retained; output high-impedance; ports can be read. 3. Functions when the time base function is selected. 76 3.3.2 Active Mode In active mode, the CPU executes programs in synchronization with the system clock. 3.3.3 Sleep Mode * Transition to sleep mode The system goes from active mode to sleep mode when a SLEEP instruction is executed while the SSBY bit in system control register 1 (SYSCR1) is cleared to 0. In this mode CPU operation is halted but the register, RAM, and port contents are retained. The clock pulse generator operates, as do external interrupts (IRQ1 and IRQ0) and timer A. * Clearing sleep mode Sleep mode is cleared by an interrupt (IRQ1, IRQ0, or timer A) or by input at the RES pin. -- Clearing by interrupt (IRQ1, IRQ0, or timer A) When an IRQ1, IRQ0, or timer A interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable register. Before transition to sleep mode, other interrupts should be disabled. -- Clearing by RES input When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. 3.3.4 Standby Mode * Transition to standby mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in system control register 1 (SYSCR1) is set to 1 and bit TMA3 in timer mode register A (TMA) is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning. As long as a minimum required voltage is applied, the CPU register contents and data in the on-chip RAM will be retained. The I/O ports go to the high-impedance state. 77 * Clearing standby mode Standby mode is cleared by an external interrupt (IRQ1, IRQ0) or by input at the RES pin. -- Clearing by interrupt (IRQ1, IRQ0) When an IRQ1 or IRQ0 interrupt signal is input, the clock pulse generator starts. After the time set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed, a stable clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. Before the transition to standby mode, other interrupts should be disabled. Standby mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable register. -- Clearing by RES input When the RES pin goes low, the clock pulse generator starts and standby mode is cleared. After the pulse generator output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling. Since clock signals are supplied to the entire chip as soon as the clock pulse generator starts functioning, the RES pin should be kept at the low level until the pulse generator output stabilizes. 3.3.5 Watch Mode * Transition to watch mode The system goes from active mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. The system also goes from subactive mode to watch mode when a SLEEP instruction is executed while the DTON bit in system control register 2 (SYSCR2) is cleared to 0. In watch mode, operation of the system clock pulse generator and of on-chip peripheral modules is halted, except for the time-base function of timer A. Output from the on-chip peripheral modules is reset; but as long as a minimum required voltage is applied, the contents of the internal registers of the CPU and on-chip peripheral modules, and the on-chip RAM contents, are retained. 78 * Clearing watch mode Watch mode is cleared by a time-base interrupt from timer A, by an IRQ0 interrupt, or by input at the RES pin. -- Clearing by timer A time-base interrupt or IRQ0 interrupt When timer A overflows or an IRQ0 interrupt signal is input, if the LSON bit in system control register 1 (SYSCR1) is cleared to 0, the clock pulse generator starts. After the time set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. If LSON = 1, the system goes to subactive mode. In watch mode, the subclock (oSUB) is prescaled to generate a clock signal which is supplied to timer A. Timer A operates as a time base. Before the transition to watch mode, other external interrupts should be disabled. Watch mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable register. -- Clearing by RES input Clearing by the RES pin is as described in 3.3.4, Standby Mode. 3.3.6 Subactive Mode * Transition to subactive mode The system goes from watch mode to subactive mode if the LSON bit in system control register 1 (SYSCR1) is set to 1 at the time of a timer A time-base interrupt or IRQ0 interrupt request. In subactive mode, the CPU operates in synchronization with the subclock (oSUB). The on-chip peripheral modules halt operation, except for the time base function of timer A. Output from the on-chip peripheral modules is reset; but as long as a minimum required voltage is applied, the contents of the internal registers of the on-chip peripheral modules are retained. The I/O ports go to the high-impedance state. 79 * Clearing subactive mode Subactive mode is cleared by a SLEEP instruction or by input at the RES pin. -- Clearing by SLEEP instruction When a SLEEP instruction is executed in subactive mode, subactive mode is cleared. If the DTON bit of system control register 2 (SYSCR2) is cleared to 0 when the SLEEP instruction is executed, the system goes to watch mode. If DTON = 1 and LSON = 0, a direct transfer interrupt is requested and the clock pulse generator starts. After the time set in bits STS2 to STS0 in system control register 1 (SYSCR1) has elapsed, a stable clock signal is supplied to the entire chip, and the system goes to active mode. Before the transition to active mode, other interrupts should be disabled. The direct transfer from subactive mode to active mode does not take place if the I bit in the condition code register (CCR) is set to 1 or the direct transfer interrupt is disabled in the interrupt enable register. -- Clearing by RES input Clearing by the RES pin is as described in 3.3.4, Standby Mode. 80 3.3.7 Application Notes 1. In order to ensure sufficient time for the clock pulse generator to reach stable operation after clearing of standby mode or watch mode, or after direct transfer from subactive to active mode, bits STS2-STS0 in system control register 1 (SYSCR1) should be set as follows. * When a ceramic oscillator is used Set bits STS2-STS0 for a waiting time of at least 10 ms (see figure 3-9). For details, see 3.4.1, System Control Register 1 (SYSCR1). * When an external clock is used Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set. Oscillator wave V t Waiting time 10 ms Oscillator stabilization time tr Power-on or standby cleared Figure 3-9 Waiting Time 2. To make a transition from subactive mode to active mode, the LSON bit in SYSCR1 should be cleared to 0 and the DTON bit in system control register 2 (SYSCR2) should be set to 1. Direct transfer is not possible when the LSON bit = 1. 81 3.4 System Control Registers Table 3-7 shows how the system control registers (SYSCR1 and SYSCR2) are configured. These two registers are used to control the power-down modes. Table 3-7 Register Configuration Name Abbreviation R/W Initial Value Address System control register 1 SYSCR1 R/W H'00 H'FFF0 System control register 2 SYSCR2 R/W H'F4 H'FFF1 3.4.1 System Control Register 1 (SYSCR1) Bit Initial value Read/Write 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 LSON -- -- -- 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W -- -- R/W * Note: * Write is enabled only in active mode. SYSCR1 is an 8-bit read/write register for control of power-down modes. Bit 7: Standby (SSBY) This bit designates transition to standby mode or watch mode. When standby mode is cleared by an external interrupt and the system goes to active mode, this bit remains set to 1. It must be cleared by writing a 0. Writing is possible only in active mode. Bit 7 SSBY Explanation 0 When a SLEEP instruction is executed, a transition is made to sleep mode. 1 When a SLEEP instruction is executed, a transition is made to standby mode or watch mode. 82 (initial value) Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0) When a mode in which the system clock is stopped (standby, watch, or subactive mode) is cleared, the system waits for stable clock operation for a time set in these bits. The designation should be made according to the clock frequency so that the waiting time is at least 10 ms. Bit 6 STS2 Bit 5 STS1 Bit 4 STS0 Explanation 0 0 0 Wait time = 8,192 states. 0 0 1 Wait time = 16,384 states. 0 1 0 Wait time = 32,768 states. 0 1 1 Wait time = 65,536 states. 1 * * Wait time = 131,072 states. (initial value) Note: * Don't care. Bit 3: Low speed on flag (LSON) This bit chooses the system clock (o) or subclock (oSUB) as the CPU operating clock when watch mode is cleared. Since this relates to the transitions between operation modes, this bit functions in combination with other control bits and interrupt input. Bit 3 LSON Explanation 0 The CPU operates on the system clock (o). 1 The CPU operates on the subclock (oSUB). (initial value) Bit 2: Reserved bit This bit is reserved, but it can be written and read. Bits 1 and 0: Reserved bits These bits are reserved; they are always read as 0, and cannot be modified. 83 3.4.2 System Control Register 2 (SYSCR2) Bit 7 6 5 4 3 2 1 0 -- -- -- -- DTON -- -- -- Initial value 1 1 1 1 0 1 0 0 Read/Write -- -- -- -- W* -- -- -- Note: * Write is enabled only in subactive mode. SYSCR2 is an 8-bit read/write register for control of direct transfer from subactive mode to active mode. Bits 7 to 4: Reserved bits These bits are reserved; they are always read as 1, and cannot be modified. Bit 3: Direct transfer on flag (DTON) This bit designates whether a transition is made to active mode or to watch mode when a SLEEP instruction is executed in subactive mode. When transfer to active mode is designated, the transition takes place via watch mode to allow time for the clock pulse generator to stabilize. Bit 3 DTON Explanation 0 When a SLEEP instruction is executed in subactive mode, a transition is (initial value) made to watch mode. 1 When a SLEEP instruction is executed in subactive mode while the LSON bit in system control register 1 (SYSCR1) is cleared to 0, a direct transfer interrupt is requested, and the system goes to active mode via watch mode. Bit 2: Reserved bit This bit is reserved; it is always read as 1, and cannot be modified. Bits 1 and 0: Reserved bits These bits are reserved; they are always read as 0, and cannot be modified. 84 Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: Clock Pulse Generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, system clock divider, and a clock divider (prescaler S) for the on-chip peripheral modules. The subclock pulse generator consists of a subclock oscillator, subclock divider, and a further subclock divider (prescaler W) for time-base use. 4.1.1 Block Diagram Figure 4-1 shows a block diagram of the clock pulse generators. System clock pulse generator Prescaler S OSC1 OSC2 System clock oscillator f OSC System clock divider (1/2) o Prescaler W X1 X2 Subclock oscillator fX Subclock divider (1/8) Subclock pulse generator Figure 4-1 Block Diagram of Clock Pulse Generators 85 o/2 to o/8192 oSUB/32 oSUB 4.2 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. Connecting a crystal oscillator * Circuit configuration Figure 4-2 shows a typical method of connecting a crystal oscillator. C1 OSC 1 OSC 2 Rf C2 Rf = 1 M 20% C1 = C 2 = 12 pF 20% Figure 4-2 Typical Connection to Crystal Oscillator * Crystal oscillator Figure 4-3 shows the equivalent circuit of the crystal oscillator. An oscillator having the characteristics given in table 4-1 should be used. CL L RS OSC 1 OSC 2 C0 Figure 4-3 Equivalent Circuit of Crystal Oscillator Table 4-1 Crystal Oscillator Parameters Frequency (MHz) 2 4 8 Rs max () 500 100 50 Co max (pF) 7 7 7 86 2. Connecting a ceramic oscillator * Circuit configuration Figure 4-4 shows a typical method of connecting a ceramic oscillator. OSC 1 C1 Ceramic oscillator Rf OSC 2 C2 R f : 1 M 20% C 1 : 30 pF 20% C 2 : 30 pF 20% Figure 4-4 Typical Connection to a Ceramic Oscillator 3. Notes on board design When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 4-5.) The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2. 87 To be avoided Signal A Signal B H8/3614 Series C2 OSC 1 OSC 2 C1 Figure 4-5 Note on Board Design of Oscillator Circuit 4. External clock input * Circuit configuration When an external clock is used, it is input at pin OSC1. Pin OSC2 should be left open. Figure 4-6 shows a typical connection. OSC 1 OSC 2 External clock input Open Figure 4-6 External Clock Input (example) * External clock Frequency Twice clock frequency (o) Duty 45% to 55% 88 4.3 Subclock Generator 1. Connecting to 32.768 kHz crystal oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz crystal oscillator, as shown in figure 4-7. Follow the same precautions as noted for the system clock. C1 X1 X2 C2 C1 = C2 = 15 pF typ Figure 4-7 Typical Connection to Crystal Oscillator (subclock) Figure 4-8 shows the equivalent circuit of the crystal oscillator. CS L RS C0 C0 = 1.5 pF typ RS = 14 k typ f = 32.768 kHz Figure 4-8 Equivalent Circuit of Crystal Oscillator 2. Pin connection when not using subclock When the subclock is not used, connect VCC to pin X1 and leave pin X2 open, as shown in figure 4-9. 89 VCC X1 X2 Open Figure 4-9 Pin Connection When Not Using Subclock 90 Section 5 I/O Ports 5.1 Overview The H8/3614 Series has five 8-bit CMOS I/O ports,* one 6-bit PMOS open-drain I/O port, and one 8-bit input port. Table 5-1 indicates the functions of each port. The CMOS I/O ports (ports 1, 2, 8, 9, and A) each have a port control register (PCR) that controls the input/output direction, and a port data register (PDR) that stores output data. Input or output can be assigned to individual bits. The PMOS open-drain I/O port (port 4) has a port data register (PDR) that stores output data. Output can be controlled on a bit-by-bit basis. Block diagrams of each port are given in Appendix C. Note: * Pins P17 and P16 of port 1 are input-only pins. When read, the ports operate as follows. * CMOS I/O ports -- Pins set for general-purpose port usage with PCR = 0 return the pin level. -- Pins set for general-purpose port usage with PCR = 1 return the PDR bit data. -- Pins set for on-chip peripheral function usage return the pin level. * PMOS open-drain I/O port -- All pins return the pin level. 91 Table 5-1 Port Functions Function Switching Register Port Description Pins Other Functions Port 0 8-bit input port P07 to P00/ AN7 to AN0 Analog data input channels 7 to 0 PMR0 Port 1 Pins P17 and P16: 2-bit input ports P17 None None P16/EVENT Timer D event input PMR1 P15/IRQ5/ TMOE External interrupt 5; Timer E output PMR1 PMR4 Pins P15 to P10: 6-bit CMOS I/O port External interrupts 4 to 0 P14 to P10/ IRQ4 to IRQ0 PMR1 Port 2 8-bit CMOS I/O port P27 to P20 None None Port 4 6-bit PMOS open-drain I/O port P45 to P40 None None Port 8 8-bit CMOS I/O port P87 to P80 None None Port 9 8-bit CMOS I/O port P97/UD Timer C count-up/down setting PMR2 PMR3 Serial communication interface 2 data output P96/SO2 Port A 8-bit CMOS I/O port P95/SI2 Serial communication interface 2 data input P94/SCK2 Serial communication interface 2 clock I/O P93/SO1 Serial communication interface 1 data output P92/SI1 Serial communication interface 1 data input P91/SCK1 Serial communication interface 1 clock I/O P90/PWM* 14-bit PWM waveform output pin* PA1 to PA0 None Note: * The H8/3612 does not have this function. 92 None 5.1.1 Port Types and Mask Options The choice of I/O pin options and the resulting states are shown in table 5-2. Upon reset, registers PDR, PCR, and PMR are initialized, cancelling the choices of peripheral functions. Table 5-2 Choice of I/O Port Options Class Pins With MOS Pull-Up No MOS Pull-Up I/O pins P15 to P10, P27 to P20, P87 to P80, P97 to P90, PA7 to PA0 With MOS pull-up No MOS pull-up Input-only pins P16 With MOS pull-up No MOS pull-up P17 No option No MOS pull-up On-chip peripheral function I/O pins SCK2, SCK1 (output mode) With MOS pull-up No MOS pull-up On-chip peripheral function output pins SO2, SO1, PWM, TMOE With MOS pull-up No MOS pull-up On-chip peripheral function input pins SI2, SI1, IRQ5 to IRQ0, UD, EVENT With MOS pull-up No MOS pull-up Note: Ports 0 and 4 have no MOS pull-up. There is no option for these ports. If external clock input mode is selected when the serial communication interface is used, pins SCK2 and SCK1 will be input-only pins. Table 5-3 shows the mask options with mask ROM versions. The mask ROM versions are compatible with the ZTATTM versions only when the no MOS pull-up option is selected for all pins. Table 5-3 Correspondence between Mask ROM and ZTATTM Versions Type With MOS Pull-Up No MOS Pull-Up Mask ROM Option Option ZTAT -- Fixed 93 5.1.2 Pull-Up MOS Ports 1, 2, 8, 9, and A can be designated by mask options as having or not having MOS pull-up transistors for their (CMOS) outputs. (This does not apply to ZTATTM versions.) The MOS pull-up option cannot be selected for pin P17. Figure 5-1 shows the MOS pull-up circuit configuration. When "with MOS pull-up" is selected by mask option, the MOS pull-up will normally be on, regardless of the port data register (PDR) and port control register (PCR) settings. (See table 5-4.) STBY *2 VCC *1 VCC MOS pull-up PDR CMOS buffer PCR VSS Input data Notes: 1. Dotted lines indicate mask option. 2. In low-power modes (except sleep mode), the MOS pull-up is switched off by a STBY signal. Figure 5-1 Pull-Up MOS Circuit Configuration Table 5-4 MOS Pull-Up Control Mask Option PCR PDR CMOS buffer MOS pull-up With MOS Pull-Up No MOS Pull-Up 0 0 1 1 0 1 0 1 0 1 0 1 PMOS Off Off Off On Off Off Off On NMOS Off Off On Off Off Off On Off On On On On -- -- -- -- 94 5.2 Port 0 5.2.1 Overview Port 0 is an 8-bit input-only port. Figure 5-2 shows the pin configuration. P0 7 /AN 7 (input) P0 6 /AN 6 (input) P0 5 /AN 5 (input) P0 4 /AN 4 (input) Port 0 P0 3 /AN 3 (input) P0 2 /AN 2 (input) P0 1 /AN 1 (input) P0 0 /AN 0 (input) Figure 5-2 Port 0 Pin Configuration 5.2.2 Register Configuration and Description Table 5-5 shows the port 0 register configuration. Table 5-5 Port 0 Registers Name Abbrev. R/W Initial Value Address Port mode register 0 PMR0 W H'00 H'FFEF Port data register 0 PDR0 R -- H'FFD0 1. Port mode register 0 (PMR0) Bit 7 6 5 4 3 2 1 0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Each PMR0 bit designates whether the corresponding port 0 pin is to be used for general input or as an analog input channel to the A/D converter. Upon reset, PMR0 is initialized to H'00. 95 Bit n ANn Explanation 0 P0n/ANn pin function for P0n input. 1 P0n/ANn pin function for ANn input. (initial value) (n = 0 to 7) 2. Port data register 0 (PDR0) Bit 7 6 5 4 3 2 1 0 PDR0 7 PDR0 6 PDR0 5 PDR0 4 PDR03 PDR0 2 PDR0 1 PDR0 0 Initial value -- -- -- -- -- -- -- -- Read/Write R R R R R R R R When port 0 is read while the corresponding PMR bit is 0, the pin state can be read. If the corresponding PMR0 bit is 1, PDR0 is read as 1. 5.2.3 Pin Functions Table 5-6 gives the port 0 pin functions. Table 5-6 Port 0 Pin Functions Pin Pin Functions and Selection Method P07/AN7 to P00/AN0 Functions are switched as follows by means of bits AN7 to AN0 in PMR0. ANn 0 1 Pin function P0n input pin ANn input pin (n = 7 to 0) 5.2.4 Pin States Table 5-7 shows the port 0 pin states in each operating mode. Table 5-7 Port 0 Pin States Pins Reset Sleep Standby Watch Subactive Active P07/AN7 to P00/AN0 High impedance Previous state retained High impedance High impedance High impedance Normal operation 96 5.3 Port 1 5.3.1 Overview Port 1 consists of six I/O pins and two input-only pins. Figure 5-3 shows the pin configuration. P17 (input) P16 /EVENT (input/input) P15 /IRQ5 /TMOE (IO/input/output) Port 1 P14 /IRQ4 (IO/input) P13 /IRQ3 (IO/input) P12 /IRQ2 (IO/input) P11 /IRQ1 (IO/input) P10 /IRQ0 (IO/input) Note: IO indicates input/output. Figure 5-3 Port 1 Pin Configuration 5.3.2 Register Configuration and Description Table 5-8 shows the port 1 register configuration. Table 5-8 Port 1 Registers Name Abbrev. R/W Initial Value Address Port mode register 1 PMR1 R/W H'00 H'FFEB Port control register 1 PCR1 W H'C0 H'FFE1 Port data register 1 PDR1 R/W Not fixed H'FFD1 Port mode register 4 PMR4 R/W H'0F H'FFEE 97 1. Port mode register 1 (PMR1) Bit 7 6 5 4 3 2 1 0 NOISE CANCEL EVENT IRQC5 IRQC4 IRQC3 IRQC2 IRQC1 IRQC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PMR1 is an 8-bit read/write register that controls the selection of pin functions for pin P16/EVENT and pins P15/IRQ5 to P10/IRQ0, and turns the pin IRQ0 noise canceller function on and off. Upon reset, PMR1 is initialized to H'00. Bit 7: Noise cancel (NOISE CANCEL) This bit turns the IRQ0 noise canceller function on and off. In standby, watch, and subactive modes the noise canceller function is off regardless of the setting of this bit. Bit 7 NOISE CANCEL Explanation 0 Noise canceller function is off. 1 Noise canceller function is on. Input is sampled at intervals of 256 states. If two consecutive input values do not match, noise is assumed. (initial value) Bit 6: P16/EVENT pin function switch (EVENT) This bit selects whether pin P16/EVENT is used as P16 or as EVENT. Bit 6 EVENT Explanation 0 P16/EVENT pin functions as P16.* 1 P16/EVENT pin functions as EVENT (timer D event input). (initial value) Note: * Even when pin P16/EVENT is used as P16, the timer D counter may increment when pin P16 is read. If timer D is used the counter must be cleared by means of the CLR bit in timer mode register D (TMD). Bit 5: P15/IRQ5/TMOE pin function switch (IRQC5) This bit selects whether pin P15/IRQ5/TMOE is used as P15/TMOE or as IRQ5. Bit 5 IRQC5 Explanation 0 P15/IRQ5/TMOE pin functions as P15/TMOE. 1 P15/IRQ5/TMOE pin functions for IRQ5 input. 98 (initial value) Bit 4: P14/IRQ4 pin function switch (IRQC4) This bit selects whether pin P14/IRQ4 is used as P14 or as IRQ4. Bit 4 IRQC4 Explanation 0 P14/IRQ4 pin functions as P14. 1 P14/IRQ4 pin functions for IRQ4* input. (initial value) Note: * Rising or falling edge sensing can be designated for pin IRQ4. For details see 3.2.3 (2), IRQ edge select register (IEGR). Bit 3: P13/IRQ3 pin function switch (IRQC3) This bit selects whether pin P13/IRQ3 is used as P13 or as IRQ3. Bit 3 IRQC3 Explanation 0 P13/IRQ3 pin functions as P13. 1 P13/IRQ3 pin functions for IRQ3 input. (initial value) Bit 2: P12/IRQ2 pin function switch (IRQC2) This bit selects whether pin P12/IRQ2 is used as P12 or as IRQ2. Bit 2 IRQC2 Explanation 0 P12/IRQ2 pin functions as P12. 1 P12/IRQ2 pin functions for IRQ2 input. (initial value) Bit 1: P11/IRQ1 pin function switch (IRQC1) This bit selects whether pin P11/IRQ1 is used as P11 or as IRQ1. Bit 1 IRQC1 Explanation 0 P11/IRQ1 pin functions as P11. 1 P11/IRQ1 pin functions for IRQ1* input. (initial value) Note: * Rising or falling edge sensing can be designated for pin IRQ1. For details see 3.2.3 2, IRQ edge select register (IEGR). 99 Bit 0: P10/IRQ0 pin function switch (IRQC0) This bit selects whether pin P10/IRQ0 is used as P10 or as IRQ0. Bit 0 IRQC0 Explanation 0 P10/IRQ0 pin functions as P10. 1 P10/IRQ0 pin functions for IRQ0* input. (initial value) Note: * Rising or falling edge sensing can be designated for pin IRQ0. For details see 3.2.3 (2), IRQ edge select register (IEGR). 2. Port control register 1 (PCR1) Bit 7 6 5 4 3 2 1 0 -- -- PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 Initial value 1 1 0 0 0 0 0 0 Read/Write -- -- W W W W W W PCR1 is an 8-bit register for controlling whether each of port 1 pins P15 to P10 functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin from P15 to P10 an output pin, while clearing the bit to 0 makes it an input pin. PCR1 is a write-only register. All bits are read as 1. Bits 7 and 6 are reserved; they are always read as 1, and cannot be modified. The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I/O pin. Upon reset, PCR1 is initialized to H'C0. 3. Port data register 1 (PDR1) Bit 7 6 5 4 3 2 1 0 -- -- PDR1 5 PDR14 PDR13 PDR1 2 PDR11 PDR10 Initial value --* --* 0 0 0 0 0 0 Read/Write -- -- R/W R/W R/W R/W R/W R/W Note: * Pins P17 and P16 are for input only; reading PDR1 always gives the level of these pins. PDR1 is an 8-bit register for storing data of pins P15 through P10. When port 1 is read while a PCR1 bit is set to 1, the PDR1 value will be read directly, regardless of the actual pin states. When port 1 is read while a PCR1 bit is cleared to 0, the pin state will be read. 100 4. Port mode register 4 (PMR4) Bit 7 6 5 4 3 2 1 0 TEO TEO ON FREQ VRFR -- -- -- -- Initial value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/W -- -- -- -- PMR4 is an 8-bit read/write register that switches the P15/IRQ5/TMOE pin function and controls TMOE pin waveform output. Bits 3 to 0 are reserved; they are always read as 1, and cannot be modified. Upon reset, PMR4 is initialized to H'0F. Bit 7: Timer E output select (TEO) Bit 6: Timer E output on/off (TEO ON) Bit 5: Fixed frequency select (FREQ) Bit 4: Variable frequency select (VRFR) The P15/IRQ5/TMOE pin functions are switched as follows, by means of bits 7 to 4 of PMR4 and bit IRQC5 of PMR1. PMR1 PMR4 Description Bit 5 Bit 7 Bit 6 Bit 5 IRQC5 TEO TEO ON FREQ Bit 4 VRFR Pin Function Pin State 0 0 0 0 0 P15 pin I/O port 0 0 * * * P15 pin I/O port 0 1 0 * * TMOE output pin (off) Low level output 0 1 1 0 0 TMOE output pin (on) Fixed frequency output: (o/2048) 1.95 kHz (o = 4 MHz) 0.98 kHz (o = 2 MHz) 0 1 1 1 0 TMOE output pin (on) Fixed frequency output: (o/1024) 3.9 kHz (o = 4 MHz) 1.95 kHz (o = 2 MHz) 0 1 1 * 1 TMOE output pin (on) Variable frequency output: toggled by timer E overflow 1 * * * * IRQ5 input pin Note: * Don't care 101 (initial value) External interrupt input 5.3.3 Pin Functions Table 5-9 shows the port 1 pin functions. Table 5-9 Port 1 Pin Functions Pin Pin Functions and Selection Method P17 Functions as P17 input pin. P16/EVENT Function is switched as follows by EVENT bit in PMR1 EVENT 0 1 Pin function P16 input pin EVENT input pin* Note: Timer D event input P15/IRQ5/TMOE, P14/IRQ4 to P10/IRQ0 Function switched as follows by bits IRQC5 to IRQC0* in PMR1 and bit PCR1n in PCR1 (n = 5 to 0) PMR1 PCR1n Pin function 0 0 1 1 P1n input pin P1n output pin -- IRQn input pin Notes: 1. Before switching pin functions using bits IRQ5 to IRQ0 in PMR1, first disable the corresponding interrupts by clearing their interrupt enable bits. After the pin functions have been switched, issue any instruction, then clear the interrupt request flags to 0. For details see section 3.2.3 (1), Port mode register (PMR1). 2. Before entering power-down mode, pins set to external interrupt input by bits IRQC5 to IRQC0 in PMR1 should be kept from floating by external connection or should be set to general I/O in PMR1 prior to the state transition. 3. For details on the TMOE function, refer to section 5.3.2 4, Port mode register 4 (PMR4). IRQ4, IRQ1, and IRQ0 input can be set for either rising edge or falling edge detection by register IEGR. For details, refer to section 3.2.3 2, IRQ edge select register (IEGR). IRQ0 and IRQ1 can be used as event input pins for timer B and timer C, respectively. For details, refer to section 6, Timers. 102 5.3.4 Pin States Table 5-10 shows the port 1 pin states in each operating mode. Table 5-10 Port 1 Pin States Pins Reset Sleep Standby Watch Subactive Active P17 High impedance Previous state retained High impedance High impedance High impedance Normal operation P16/EVENT, P15/IRQ5/ TMOE, P14/IRQ4 to P10/IRQ0 High impedance or pulled up 103 5.4 Port 2 5.4.1 Overview Port 2 is an 8-bit I/O port. Figure 5-4 shows the pin configuration. P27 (I/O) P26 (I/O) P25 (I/O) P24 (I/O) Port 2 P23 (I/O) P22 (I/O) P21 (I/O) P20 (I/O) Figure 5-4 Port 2 Pin Configuration 5.4.2 Register Configuration and Description Table 5-11 shows the port 2 register configuration. Table 5-11 Port 2 Registers Name Abbrev. R/W Initial Value Address Port control register 2 PCR2 W H'00 H'FFE2 Port data register 2 PDR2 R/W H'00 H'FFD2 1. Port control register 2 (PCR2) Bit 7 6 5 4 3 2 1 0 PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PCR2 is an 8-bit register for controlling whether each of port 2 pins P27 to P20 functions as an input pin or output pin. Setting a PCR2 bit to 1 makes the corresponding pin from P27 to P20 an output pin, while clearing the bit to 0 makes it an input pin. PCR2 is a write-only register. All bits are read as 1. Upon reset, PCR2 is initialized to H'00. 104 2. Port data register 2 (PDR2) Bit 7 6 5 4 3 2 1 0 PDR27 PDR26 PDR25 PDR24 PDR23 PDR22 PDR21 PDR20 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR2 is an 8-bit register that stores data for port 2 pins P27 to P20. If port 2 is read while a PCR2 bit is set to 1, the PDR2 value will be read directly, regardless of the actual pin state. If port 2 is read while a PCR2 bit is cleared to 0, the pin state will be read. Upon reset, PDR2 is initialized to H'00. 5.4.3 Pin Functions Table 5-12 shows the port 2 pin functions. Table 5-12 Port 2 Pin Functions Pin Selection Method and Pin Function P27 to P20 Switched as follows by PCR2n bits in PCR2. PCR2n 0 1 Pin function P2n input pin P2n output pin (n = 7 to 0) 5.4.4 Pin States Table 5-13 shows the port 2 pin states in each operating mode. Table 5-13 Port 2 Pin States Pins Reset Sleep Standby Watch Subactive Active P27 to P20 High impedance or pulled up Previous state retained High impedance High impedance High impedance Normal operation 105 5.5 Port 4 5.5.1 Overview Port 4 is a 6-bit PMOS open-drain I/O port. Figure 5-5 shows the pin configuration. P45 (I/O) P44 (I/O) P43 (I/O) Port 4 P42 (I/O) P41 (I/O) P40 (I/O) Figure 5-5 Port 4 Pin Configuration 5.5.2 Register Configuration and Description Table 5-14 shows the port 4 register configuration. Table 5-14 Port 4 Registers Name Abbrev. R/W Initial Value Address Port data register 4 PDR4 R/W H'C0 H'FFD4 1. Port data register 4 (PDR4) Bit 7 6 5 4 3 2 1 0 -- -- PDR4 5 PDR44 PDR4 3 PDR4 2 PDR4 1 PDR4 0 Initial value 1 1 0 0 0 0 0 0 Read/Write -- -- R/W R/W R/W R/W R/W R/W PDR4 is a 6-bit register that stores data for port 4 pins P45 to P40. Bits 7 and 6 are reserved. They are always read as 1 and cannot be modified. Upon reset, PDR4 is initialized to H'C0. 106 5.5.3 Pin Functions Table 5-15 shows the port 4 pin functions. Table 5-15 Port 4 Pin Functions Pin Selection Method and Pin Function P45 to P40 PMOS open-drain I/O pins, switched as follows by the PDR4n bits in PDR4. PDR4n 0 1 Pin function I/O pin Output pin Pin state High impedance High level (n = 5 to 0) 5.5.4 Pin States Table 5-16 shows the port 4 pin states in each operating mode. Table 5-16 Port 4 Pin States Pins Reset Sleep Standby Watch Subactive Active P40 to P45 High impedance Previous state retained High impedance High impedance High impedance Normal operation 107 5.6 Port 8 5.6.1 Overview Port 8 is an 8-bit I/O port. Figure 5-6 shows the pin configuration. P87 (I/O) P86 (I/O) P85 (I/O) P84 (I/O) Port 8 P83 (I/O) P82 (I/O) P81 (I/O) P80 (I/O) Figure 5-6 Port 8 Pin Configuration 5.6.2 Register Configuration and Description Table 5-17 shows the port 8 register configuration. Table 5-17 Port 8 Registers Name Abbrev. R/W Initial Value Address Port control register 8 PCR8 W H'00 H'FFE8 Port data register 8 PDR8 R/W H'00 H'FFD8 1. Port control register 8 (PCR8) Bit 7 6 5 4 3 2 1 0 PCR8 7 PCR8 6 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PCR8 is an 8-bit register for controlling whether each of port 8 pins P87 to P80 functions as an input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes it an input pin. PCR8 is a write-only register. All bits are read as 1. Upon reset, PCR8 is initialized to H'00. 108 2. Port data register 8 (PDR8) Bit 7 6 5 4 3 2 1 0 PDR8 7 PDR8 6 PDR8 5 PDR84 PDR8 3 PDR8 2 PDR8 1 PDR8 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR8 is an 8-bit register for storing the data of port 8 pins P87 to P80. If port 8 is read while a PCR8 bit is set to 1, the PDR8 value will be read directly, regardless of the actual pin state. If port 8 is read while a PCR8 bit is cleared to 0, the pin state will be read. Upon reset, PDR8 is initialized to H'00. 5.6.3 Pin Functions Table 5-18 gives the port 8 pin functions. Table 5-18 Port 8 Pin Functions Pin Selection Method and Pin Function P87 to P80 Functions are switched as follows by means of the PCR8n bits in PCR8. PCR8n 0 1 Pin function P8n input pin P8n output pin (n = 7 to 0) 5.6.4 Pin States Table 5-19 shows the port 8 pin states in each operating mode. Table 5-19 Port 8 Pin States Pins Reset Sleep Standby Watch Subactive Active P87 to P80 High impedance or pulled up Contents retained High impedance High impedance High impedance Normal operation 109 5.7 Port 9 5.7.1 Overview Port 9 is an 8-bit I/O port. Figure 5-7 shows the pin configuration. P97 /UD (IO/input) P96 /SO 2 (IO/output) P95 /SI 2 /CS (IO/input/output) P94 /SCK 2 (IO/IO) Port 9 P93 /SO1 (IO/output) P92 /SI1 (IO/input) P91 /SCK1 (IO/IO) P90 /PWM* (IO/output) Note: IO indicates input/output. * The H8/3612 does not have the PWM function. Figure 5-7 Port 9 Pin Configuration 5.7.2 Register Configuration and Description Table 5-20 shows the port 9 register configuration. Table 5-20 Port 9 Registers Name Abbrev. R/W Initial Value Address Port mode register 2 PMR2 R/W H'00 H'FFEC Port control register 9 PCR9 W H'00 H'FFE9 Port data register 9 PDR9 R/W H'00 H'FFD9 110 1. Port mode register 2 (PMR2) Bit 7 6 5 4 3 2 1 0 UP/ DOWN SO2 SI2 SCK2 SO1 SI1 SCK1 PWM * Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: * The H8/3612 does not have the PWM function. PMR2 is an 8-bit read/write register, controlling the selection of port 9 pin functions. Upon reset, PMR2 is initialized to H'00. Bit 7: P97/UD pin function switch (UP/DOWN) This bit selects whether pin P97/UD function as the P97 I/O pin or the UD input pin. Up/down control input (UD) is valid only when bit TMC6 = 1 in timer mode register C (TMC). Bit 7 UP/DOWN Description 0 P97/UD pin functions for P97 input/output. 1 P97/UD pin functions for UD input. If bit TMC6 in TMC is set to 1, then when the UD input is high, timer C counts down, and when UD is low, timer C counts up. (initial value) Bit 6: P96/SO2 pin function switch (SO2) This bit selects whether pin P96/SO2 functions as the P96 I/O pin or the SO2 output pin. Bit 6 SO2 Description 0 P96/SO2 pin functions for P96 input/output. 1 P96/SO2 pin functions for SO2 output. (initial value) Bit 5: P95/SI2/CS pin function switch (SI2) This bit selects whether pin P95/SI2/CS functions as the P95 I/O pin or the SI2 input/CS output pin. For the switching between SI2 input and CS output see 9.2.5, Port Mode Register 3 (PMR3). Bit 5 SI2 Description 0 P95/SI2/CS pin functions for P95 input/output. 1 P95/SI2/CS pin functions for SI2 input or CS output. 111 (initial value) Bit 4: P94/SCK2 pin function switch (SCK2) This bit selects whether pin P94/SCK2 functions as the P94 I/O pin or the SCK2 I/O pin. Bit 4 SCK2 Description 0 P94/SCK2 pin functions for P94 input/output. 1 P94/SCK2 pin functions for SCK2 input/output. The clock input/output direction and the divider ratio are set in serial mode register 2 (SMR2). (initial value) Bit 3: P93/SO1 pin function switch (SO1) This bit selects whether pin P93/SO1 functions as the P93 I/O pin or the SO1 output pin. Bit 3 SO1 Description 0 P93/SO1 pin functions for P93 input/output. 1 P93/SO1 pin functions for SO1 output. (initial value) Bit 2: P92/SI1 pin function switch (SI1) This bit selects whether pin P92/SI1 functions as the P92 I/O pin or the SI1 input pin. Bit 2 SI1 Description 0 P92/SI1 pin functions for P92 input/output. 1 P92/SI1 pin functions for SI1 input. (initial value) Bit 1: P91/SCK1 pin function switch (SCK1) This bit selects whether pin P91/SCK1 functions as the P91 I/O pin or the SCK1 I/O pin. Bit 1 SCK1 Description 0 P91/SCK1 pin functions for P91 input/output. 1 P91/SCK1 pin functions for SCK1 input/output. The clock input/output direction and the divider ratio are set in serial mode register 1 (SMR1). 112 (initial value) Bit 0: P90/PWM pin function switch (PWM)* This bit selects whether pin P90/PWM pin functions as the P90 I/O pin or the PWM output pin. Bit 0 PWM Description 0 P90/PWM pin functions for P90 input/output. 1 P90/PWM pin functions for PWM output. (initial value) Note: * The H8/3612 does not have the PWM function. 2. Port control register 9 (PCR9) Bit 7 6 5 4 3 2 1 0 PCR9 7 PCR9 6 PCR95 PCR94 PCR93 PCR92 PCR91 PCR90 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PCR9 is an 8-bit register for controlling whether each of port 9 pins P97 to P90 functions as an input or output pin. Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR9 and PDR9 are valid when the affected pin is designated in PMR2 as a general-purpose I/O pin. PCR9 is a write-only register. All bits are read as 1. Upon reset, PCR9 is initialized to H'00. 3. Port data register 9 (PDR9) Bit 7 6 5 4 3 2 1 0 PDR9 7 PDR9 6 PDR9 5 PDR94 PDR9 3 PDR9 2 PDR9 1 PDR9 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR9 is an 8-bit register that stores data for port 9 pins P97 to P90. If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read. Upon reset, PDR9 is initialized to H'00. 113 5.7.3 Pin Functions Table 5-21 shows the port 9 pin functions. Table 5-21 Port 9 Pin Functions Pin Pin Functions and Selection Method P97/UD Functions are switched as follows by means of the UP/DOWN bit* in PMR2 and bit PCR97 in PCR9. UP/DOWN PCR97 Pin function 0 0 1 1 -- P97 input pin P97 output pin UD input pin Note: * Before entering power-down mode, if this pin is set to UD input by the UP/DOWN bit in PMR2, it should be kept from floating by external connection or should be set to general I/O use by clearing the UP/DOWN bit to 0 prior to the state transition. P96/SO2* Functions are switched as follows by means of bit SO2 in PMR2 and bit PCR96 in PCR9. SO2 PCR96 Pin function 0 0 1 1 P96 input pin P96 output pin -- SO2 output pin Note: * The PMOS buffer transistor of pin P96/SO2 can be enabled or disabled by the SO2PMOS bit in PMR3. For details see 9.2.5, Port Mode Register 3 (PMR3). P95/SI2/ CS Functions are switched as follows by means of bit SI2 in PMR2,* bit CS in PMR3, and bit PCR95 in PCR9. SI2 0 CS -- PCR95 Pin function 0 1 1 0 1 -- -- P95 input pin P95 output pin SI2 input pin CS output pin Note: * Before entering power-down mode, if this pin is set to SI2 input by bit SI2 in PMR2, it should be kept from floating by external connection or should be set to general I/O use by clearing bit SI2 to 0 prior to the state transition. 114 Table 5-21 Port 9 Pin Functions (cont) Pin Pin Functions and Selection Method P94/SCK2 Functions are switched as follows by means of bit SCK2* in PMR2, bits PS1 and PS0* in serial control register 2 (SCR2), and bit PCR94 in PCR9. SCK2 0 PS1, 0 -- PCR94 Pin function 0 1 1 Not 11 11 -- -- P94 input pin P94 output pin SCK2 output pin SCK2 input pin Note: * Before entering power-down mode, if this pin is set to SCK2 input by bit SCK2 in PMR2 and bits PS1 and PS0 in SCR2, it should be kept from floating by external connection, or else should be set to some other use by changing bits SCK2 and bits PS1 and PS0 prior to the state transition. For the settings of bits PS1 and PS0 in SCR2, see 9.2.3, Serial Control Register 2 (SCR2). P93/SO1* Functions are switched as follows by means of bit SO1 in PMR2 and bit PCR93 in PCR9. SO1 PCR93 Pin function 0 0 1 1 P93 input pin P93 output pin -- SO1 output pin Note: * The PMOS buffer transistor of pin P93/SO1 can be enabled or disabled by the SO1PMOS bit in PMR3. For details see 8.2.6, Port Mode Register 3 (PMR3). P92/SI1 Functions are switched as follows by means of bit SI1* in PMR2 and bit PCR92 in PCR9. SI1 PCR92 Pin function 0 0 1 1 P92 input pin P92 output pin -- SI1 input pin Note: * Before entering power-down mode, if this pin is set to SI1 input by bit SI1 in PMR2, it should be kept from floating by external connection or should be set to general I/O use by clearing bit SI1 to 0 prior to the state transition. 115 Table 5-21 Port 9 Pin Functions (cont) Pin Selection Method and Pin Function P91/SCK1 Functions are switched as follows by means of bit SCK1 in PMR2,* bits SMR13 to SMR10 in serial mode register 1 (SMR1)*, and bit PCR91 in PCR9. SCK1 0 SMR13 to 10 -- 0 PCR91 Pin function 1 1 Not 1111 1111 -- -- P91 input pin P91 output pin SCK1 output pin SCK1 input pin Note: * Before entering power-down mode, if this pin is set to SCK1 input by bit SCK1 in PMR2 and bits SMR13 to SMR10 in SMR1, it should be kept from floating by external connection, or else should be set to some other use by changing the SCK1 bit or bits SMR13 to SMR10 prior to the state transition. For the settings of bits SMR13 to SMR10 in SMR1, see 8.2.1, Serial Mode Register 1 (SMR1). P90/PWM* Functions are switched as follows by means of bit PWM in PMR2 and bit PCR90 in PCR9. PWM 0 PCR90 Pin function 0 1 1 P90 input pin P90 output pin -- PWM output pin Note: * The H8/3612 does not have the PWM function. 5.7.4 Pin States Table 5-22 shows the port 9 pin states in each operating mode. Table 5-22 Port 9 Pin States Pins Reset Sleep P97/UD, P96/SO2, P95/SI2/CS, P94/SCK2, P93/SO1, P92/SI1, P91/SCK1, P90/PWM High Previous impedance or state pulled up retained Standby Watch Subactive Active High impedance High impedance High impedance Normal operation 116 5.8 Port A 5.8.1 Overview Port A is an 8-bit I/O port. Figure 5-8 shows the pin configuration. PA7 (I/O) PA6 (I/O) PA5 (I/O) PA4 (I/O) Port A PA3 (I/O) PA2 (I/O) PA1 (I/O) PA0 (I/O) Figure 5-8 Port A Pin Configuration 5.8.2 Register Configuration and Description Table 5-23 shows the port A register configuration. Table 5-23 Port A Registers Name Abbrev. R/W Initial Value Address Port control register A PCRA W H'00 H'FFEA Port data register A PDRA R/W H'00 H'FFDA 1. Port control register A (PCRA) Bit 7 6 5 4 3 2 1 0 PCRA7 PCRA6 PCRA5 PCRA4 PCRA3 PCRA2 PCRA1 PCRA0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PCRA is an 8-bit register for controlling whether each of port A pins PA1 and PA0 functions as an input or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. 117 PCRA is a write-only register, which is always read as 1. Upon reset, PCRA is initialized to H'00. 2. Port data register A (PDRA) Bit 7 6 5 4 3 2 1 0 PDRA7 PDRA6 PDRA5 PDRA4 PDRA3 PDRA2 PDRA 1 PDRA 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDRA is an 8-bit register for storing the data of port A pins PA7 to PA0. If port A is read while a PCRA bit is set to 1, the PDRA value will be read directly, regardless of the actual pin state. If port A is read while a PCRA bit is cleared to 0, the pin state will be read. Upon reset, PDRA is initialized to H'00. 5.8.3 Pin Functions Table 5-24 shows the port A pin functions. Table 5-24 Port A Pin Functions Pin Selection Method and Pin Function PA7 to PA0 Functions are switched as follows by means of the PCRAn bit in PCRA. PCRAn 0 1 Pin function PAn input pin PAn output pin (n = 7 to 0) 5.8.4 Pin States Table 5-25 shows the port A pin states in each operating mode. Table 5-25 Port A Pin States Pins Reset Sleep Standby Watch Subactive Active PA7 to PA0 High impedance or pulled up Previous state retained High impedance High impedance High impedance Normal operation 118 Section 6 Timers 6.1 Overview The H8/3614 Series provides on-chip two prescalers (prescaler S and prescaler W) with different input clocks, and five timers (timers A to E). Prescaler S (PSS) is a 13-bit counter clocked by the system clock (o = fOSC/2). Its prescaled outputs are used by timers A to C and timer E. Prescaler W (PSW) is a 5-bit counter clocked by the subclock (oSUB = fX/8). Its prescaled output is used for time-base operation by timer A. Table 6-1 outlines the functions of timers A to E. Table 6-1 Timer A to E Functions Name Functions Timer A * 8-bit interval timer * Time base Timer B * 8-bit reloadable timer * 8-bit interval timer Operating Clock (Internal) Event Input Pin Waveform Output Pin Remarks o/8 to o/8192 -- (choice of 8 sources) -- -- oSUB/32 (choice of 4 overflow periods) -- -- o/8 to o/8192 P10/IRQ0 (choice of 7 sources) -- -- o/8 to o/8192 P11/IRQ1 (choice of 7 sources) -- Counting direction can be controlled by software or hardware. * Event counter Timer C * 8-bit reloadable timer * 8-bit interval timer * Event counter * Choice of up- or down-counting Timer D * 8-bit event counter -- Timer E * 8-bit reloadable timer o/8 to o/8192 -- (choice of 8 sources) * 8-bit interval timer P16/EVENT -- 119 P15/IRQ5/ TMOE -- Can output square wave with 50% duty cycle 6.1.1 Prescaler Operation 1. Prescaler S (PSS) PSS is a 13-bit counter using the system clock (o = fOSC/2) as its input clock. Each input clock cycle causes prescaler S to increment once. PSS is initialized to H'0000 by a reset, and starts counting upon return to active mode. In standby mode, watch mode, and subactive mode, the system clock (o) pulse generator stops, so PSS also stops functioning. Its value is reset to H'0000. The CPU cannot read or write PSS data. The output from PSS is shared by timers A to C and E as well as serial communication interfaces 1 and 2. The frequency division ratio can be set separately for each on-chip peripheral function. 2. Prescaler W (PSW) PSW is a 5-bit counter using the subclock (oSUB = fX/8) as its input clock. PSW is initialized to H'00 by a reset, and starts counting upon return to active mode. Even in standby mode, watch mode, or subactive mode, PSW continues functioning so long as clock signals are supplied to pins X1 and X2. PSW can be reset by setting bits TMA3 and TMA2 to 1 in timer mode register A (TMA). The output from PSW can be used as the clock source for timer A, in which case timer A functions as a time base. Figure 6-1 shows the clock signals supplied by PSS and PSW to peripheral modules. 120 o/2 to o/8192 OSC1 OSC2 System f OSC clock pulse generator System clock divider 1/2 Prescaler S o Timers A to C and E; serial communication interfaces 1 and 2 oSUB/32 X1 X2 Subclock pulse generator fX Subclock oSUB divider 1/8 Prescaler W System clock selection (LSON bit in system control register 1) Figure 6-1 Clock Supply 121 Timer A CPU, ROM, RAM, registers, flags, I/O 6.2 Timer A 6.2.1 Overview Timer A is an 8-bit interval timer. It can be connected to a 32.768 kHz crystal oscillator for use as a real-time clock time base. 1. Features Features of timer A are given below. Choice of eight internal clock sources (o/8192, o/4096, o/2048, o/512, o/256, o/128, o/32, o/8). * Choice of four overflow periods (2 s, 1 s, 0.5 s, 125 ms) when timer A is used as a time base (using a 32.768 kHz crystal oscillator). * An interrupt is requested when the counter overflows. Block diagram Figure 6-2 shows a block diagram of timer A. Prescaler W (PSW) 1/8 TMA oSUB oSUB/32 System clock Prescaler S (PSS) 1/2 /256 /128 o/8192, o/4096, o/2048, o/512, o/256, o/128, o/32, o/8 /64 TCA Interval timer overflow Internal data bus 32 kHz crystal oscillator /16 2. * IRRTA o Note: * Can be selected only when the input clock to TCA is the output from prescaler W (oSUB/32). Notation: TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag (interrupt request register 2) Figure 6-2 Block Diagram of Timer A 122 3. Register configuration Table 6-2 shows the register configuration of timer A. Table 6-2 Timer A Registers Name Abbrev. R/W Initial Value Address Timer mode register A TMA R/W H'F0 H'FFC0 Timer counter A TCA R H'00 H'FFC1 6.2.2 Register Descriptions 1. Timer mode register A (TMA) Bit 7 6 5 4 3 2 1 0 -- -- -- -- TMA3 TMA2 TMA1 TMA0 Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W TMA is an 8-bit read/write register for selecting the prescaler and input clock. Upon reset, TMA is initialized to H'F0. Bits 7 to 4: Reserved bits Bits 7 to 4 are reserved; they are always read as 1, and cannot be modified. Bit 3: Prescaler select (TMA3) Bit 3 selects either prescaler S or prescaler W as the clock input source for timer A. Bit 3 TMA3 Description 0 Prescaler S (PSS) is clock input source for timer A. 1 Prescaler W (PSW) is clock input source for timer A. 123 (initial value) Bits 2 to 0: Clock select (TMA2 to TMA0) Bits 2 to 0 select the clock input to TCA. The selection is made as follows by the combination of these bits and bit TMA3. Bit 3 TMA3 0 Bit 2 TMA2 0 Bit 1 TMA1 0 1 1 0 1 1 0 0 1 1 0 Bit 0 TMA0 Description Prescaler divider ratio (interval timer) or overflow period (time base) Operation mode 0 PSS, o/8192 (initial value) Interval timer mode 1 PSS, o/4096 0 PSS, o/2048 1 PSS, o/512 0 PSS, o/256 1 PSS, o/128 0 PSS, o/32 1 PSS, o8 0 PSW, 2 s 1 PSW, 1 s 0 PSW, 0.5 s 1 PSW, 125 ms 0 PSW and TCA are cleared to H'00 Time-base mode 1 1 0 1 Note: o = fOSC/2 124 2. Timer counter A (TCA) Bit 7 6 5 4 3 2 1 0 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). The TCA value can be read by the CPU at any time. TCA is cleared to H'00 by setting bits TMA3 and TMA2 of TMA to 1. When TCA overflows, the IRRTA bit in interrupt request register 2 (IRR2) is set to 1. Upon reset, TCA is initialized to H'00. 6.2.3 Timer Operation Timer A is an 8-bit timer which can be used either as an interval timer or, if a 32.768 kHz crystal oscillator is connected, as a real-time clock time base. 1. Interval timer operation When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately after the reset. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow, setting bit IRRTA to 1 in interrupt request register 2 (IRR2). If IENTA = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.* At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. During interval timer operation (when bit TMA3 = 0), TCA cannot be cleared. Note: * For details on interrupts, see 3.2.2, Interrupts. 125 2. Real-time clock time base operation When bit TMA3 in TMA is set to 1, timer A functions as a time base for a real-time clock by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. During clock time-base operation (when bit TMA3 = 1), if bit TMA2 is set to 1, TCA and prescaler W are both cleared to H'00. 126 6.3 Timer B 6.3.1 Overview Timer B is an 8-bit up-counter that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. It can also function as an event counter. 1. Features Features of timer B are given below. Choice of seven internal clock sources (o/8192, o/2048, o/512, o/256, o/128, o/32, o/8) or an external clock (can be used to count external events). * An interrupt is requested when the counter overflows. Block diagram Figure 6-3 shows a block diagram of timer B. TMB System clock Prescaler S (13 bits) TCB IRQ 0 Internal data bus 2. * TLB Notation: TMB: Timer mode register B TCB: Timer counter B TLB: Timer load register B IRRTB: Timer B overflow interrupt request flag (interrupt request register 2) Figure 6-3 Block Diagram of Timer B 127 IRRTB 3. Pin configuration Table 6-3 shows the timer B pin configuration. Table 6-3 Pin Configuration Name Abbrev. I/O Function Event input pin P10/IRQ0 Input Timer B event input 4. Register configuration Table 6-4 shows the register configuration of timer B. Table 6-4 Timer B Registers Name Abbrev. R/W Initial Value Address Timer mode register B TMB R/W H'78 H'FFC2 Timer counter B TCB R H'00 H'FFC3 Timer load register B TLB W H'00 H'FFC3 6.3.2 Register Descriptions 1. Timer mode register B (TMB) Bit 7 6 5 4 3 2 1 0 TMB7 -- -- -- -- TMB2 TMB1 TMB0 Initial value 0 1 1 1 1 0 0 0 Read/Write R/W -- -- -- -- R/W R/W R/W TMB is an 8-bit read/write register for selecting the auto-reload function and input clock. Upon reset, TMB is initialized to H'78. Bit 7: Auto-reload function select (TMB7) Bit 7 selects the auto-reload function of timer B. Bit 7 TMB7 Description 0 Interval timer function selected. 1 Auto-reload function selected. (initial value) 128 Bits 6 to 3: Reserved bits Bits 6 to 3 are reserved; they are always read as 1, and cannot be modified. Bits 2 to 0: Clock select (TMB2 to TMB0) Bits 2 to 0 select the clock input to TCB. For external clock counting, either the rising or falling edge can be selected. Bit 2 TMB2 Bit 1 TMB1 Bit 0 TMB0 Description 0 0 0 Internal clock: o/8192. 0 0 1 Internal clock: o/2048. 0 1 0 Internal clock: o/512. 0 1 1 Internal clock: o/256. 1 0 0 Internal clock: o/128. 1 0 1 Internal clock: o/32. 1 1 0 Internal clock: o/8. 1 1 1 External clock (P10/IRQ0): rising or falling edge.* (initial value) Note: * The edge of the external event signal is selected by bit IEG0 in the IRQ edge select register (IEGR). For details see 3.2.3 (2), IRQ edge select register (IEGR). To count external events, set bit IRQC0 to 1 in port mode register 1 (PMR1). 2. Timer counter B (TCB) Bit 7 6 5 4 3 2 1 0 TCB7 TCB6 TCB5 TCB4 TCB3 TCB2 TCB1 TCB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R TCB is an 8-bit read-only up-counter, which is incremented by internal or external clock input. The clock source for input to this counter is selected by bits TMB2 to TMB0 in timer mode register B (TMB). The TCB value can be read by the CPU at any time. When TCB overflows from H'FF to H'00 or to the value set in TLB, the IRRTB bit in interrupt request register 2 (IRR2) is set to 1. TCB is allocated to the same address as timer load register B (TLB). Upon reset, TCB is initialized to H'00. 129 3. Timer load register B (TLB) Bit 7 6 5 4 3 2 1 0 TLB7 TLB6 TLB5 TLB4 TLB3 TLB2 TLB1 TLB0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W TLB is an 8-bit write-only register for setting the reload value of timer counter B (TCB). When a reload value is set in TLB, the same value is loaded into timer counter B (TCB) as well, and TCB starts counting up from that value. When TCB overflows during operation in auto-reload mode, the TLB value is loaded in TCB. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLB as to TCB. Upon reset, TLB is initialized to H'00. 6.3.3 Timer Operation Timer B is an 8-bit multifunction timer. It can be used as an interval timer, an auto-reload timer, or an event counter. 1. Interval timer operation When bit TMB7 in timer mode register B (TMB) is cleared to 0, timer B functions as an 8-bit interval timer. Upon reset, TCB is cleared to H'00 and bit TMB7 is cleared to 0, so up-counting and interval timing resume immediately after the reset. The clock input to timer B is selected from seven internal clock signals output by prescaler S, or an external clock input at pin P10/IRQ0. The selection is made by bits TMB2 to TMB0 of TMB. After the count value in TCB reaches H'FF, the next clock signal input causes timer B to overflow, setting bit IRRTB to 1 in interrupt request register 2 (IRR2). If IENTB = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.* At overflow, TCB returns to H'00 and starts counting up again. During interval timer operation (TMB7 = 0), when a value is set in timer load register B (TLB), the same value is set in TCB. Note: * For details on interrupts, see 3.2.2, Interrupts. 130 2. Auto-reload timer operation Setting bit TMB7 in TMB to 1 causes timer B to function as an 8-bit auto-reload timer. When a reload value is set in TLB, the same value is loaded into TCB, becoming the value from which TCB starts its count. After the count value in TCB reaches H'FF, the next clock signal input causes timer B to overflow. The TLB value is then loaded into TCB, and the count continues from that value. The overflow period can be set within a range from 1 to 256 input clocks, depending on the TLB value. The clock sources and interrupts in auto-reload mode are the same as for interval mode. In auto-reload mode (bit TMB7 = 1), setting a new TLB value also initializes TCB. 3. Operation as event counter Timer B can operate as an event counter, using P10/IRQ0 as the event input pin. External event counting is selected by setting bits TMB2 to 0 in timer register B (TMB) to all 1's (111). TCB can count either rising or falling edges of the input at pin P10/IRQ0. When timer B is used to count external event input, bit IRQC0 in port mode register 1 (PMR1) should be set to 1, and bit IEN0 in interrupt enable register 1 (IENR1) should be cleared to 0 to disable interrupt requests at IRQ0. 131 6.4 Timer C 6.4.1 Overview Timer C is an 8-bit up/down counter that increments or decrements each time a clock pulse is input. This timer has two operation modes, interval and auto reload. It can also function as an event counter. 1. Features Features of timer C are given below. Choice of seven internal clock sources (o/8192, o/2048, o/512, o/256, o/128, o/32, o/8) or an external clock (can be used to count external events). * An interrupt is requested when the counter overflows. * Can be switched between up- and down-counting by software or hardware control. Block diagram Figure 6-4 shows a block diagram of Timer C. System clock Prescaler S TMC UD TCC IRQ 1 Internal data bus 2. * TLC Notation: TMC: Timer mode register C TCC: Timer counter C TLC: Timer load register C IRRTC: Timer C overflow interrupt request flag (interrupt request register 2) Figure 6-4 Block Diagram 132 IRRTC 3. Pin configuration Table 6-5 shows the timer C pin configuration. Table 6-5 Pin Configuration Name Abbrev. I/O Function Event input pin P11/IRQ1 Input Timer C event input Input Timer C up/down control Up-/down-count selection pin P97/UD 4. Register configuration Table 6-6 shows the register configuration of timer C. Table 6-6 Timer C Registers Name Abbrev. R/W Initial Value Address Timer mode register C TMC R/W H'18 H'FFC4 Timer counter C TCC R H'00 H'FFC5 Timer load register C TLC W H'00 H'FFC5 133 6.4.2 Register Descriptions 1. Timer mode register C (TMC) Bit 7 6 5 4 3 2 1 0 TMC7 TMC6 TMC5 -- -- TMC2 TMC1 TMC0 Initial value 0 0 0 1 1 0 0 0 Read/Write R/W R/W R/W -- -- R/W R/W R/W TMC is an 8-bit read/write register for selecting the auto-reload function, counting direction, and input clock. Upon reset, TMC is initialized to H'18. Bit 7: Auto-reload function select (TMC7) Bit 7 selects the auto-reload function of timer C. Bit 7 TMC7 Description 0 Interval timer function selected. 1 Auto-reload function selected. (initial value) Bits 6 and 5: Counter up/down control (TMC6 and TMC5) These bits select whether TCC operates as an up-counter, as a down-counter, or as either an upcounter or down-counter depending on the input at pin P97/UD. Bit 6 TMC6 Bit 5 TMC5 Description 0 0 TCC is an up-counter. 0 1 TCC is a down-counter. 1 * TCC up/down control is by input at pin P97/UD. TCC is a down-counter if UD input is high, and an up-counter if UD input is low. (initial value) Note: * Don't care. Bits 4 and 3: Reserved bits Bits 4 and 3 are reserved; they are always read as 1, and cannot be modified. Bits 2 to 0: Clock select (TMC2 to TMC0) 134 Bits 2 to 0 select the clock input to TCC. For external clock counting, either the rising or falling edge can be selected. Bit 2 TMC2 Bit 1 TMC1 Bit 0 TMC0 Description 0 0 0 Internal clock: o/8192. 0 0 1 Internal clock: o/2048. 0 1 0 Internal clock: o/512. 0 1 1 Internal clock: o/256. 1 0 0 Internal clock: o/128. 1 0 1 Internal clock: o/32. 1 1 0 Internal clock: o/8. 1 1 1 External clock (P11/IRQ1): rising or falling edge.* (initial value) Note: * External clock edge selection is made by setting bit IEG1 in the IRQ edge select register (IEGR). For details see 3.2.3 2, IRQ edge select register (IEGR). Before setting bits TMC2 to TMC0 to all 1's (111), first set bit IRQC1 to 1 in port mode register 1 (PMR1). 2. Timer counter C (TCC) Bit 7 6 5 4 3 2 1 0 TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R TCC is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or external clock input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC). The TCC value can be read by the CPU at any time. When TCC overflows (from H'FF to H'00 or to the value set in TLC) or underflows (from H'00 to H'FF or to the value set in TLC), the IRRTC bit in interrupt request register 2 (IRR2) is set to 1. TCC is allocated to the same address as timer load register C (TLC). Upon reset, TCC is initialized to H'00. 135 3. Timer load register C (TLC) Bit 7 6 5 4 3 2 1 0 TLC7 TLC6 TLC5 TLC4 TLC3 TLC2 TLC1 TLC0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W TLC is an 8-bit write-only register for setting the reload value of TCC. When a reload value is set in TLC, the same value is loaded into timer counter C (TCC) as well, and TCC starts counting up or down from that value. When TCC overflows or underflows during operation in auto-reload mode, the TLC value is loaded in TCC. Accordingly, overflow and underflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLC as to TCC. Upon reset, TLC is initialized to H'00. 6.4.3 Timer Operation Timer C is an 8-bit multifunction timer. It can be used as an interval or auto-reload timer, or, depending on the input pin combination, as an event counter. 1. Operation as interval timer When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit interval timer. Upon reset, timer counter C (TCC) is initialized to H'00 and TMC to H'18, so up-counting and interval timing resume immediately after the reset. The clock input to timer C is selected from seven internal clock signals output by prescaler S, or an external clock input at pin P11/IRQ1. The selection is made by bits TMC2 to TMC0 in TMC. Either software or hardware can control whether TCC counts up or down. The selection is made by TMC bits TMC6 and TMC5. 136 After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow (underflow), setting bit IRRTC to 1 in interrupt request register 2 (IRR2). If bit IENTC = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.* At overflow or underflow, TCC returns to H'00 or H'FF and starts counting up or down again. During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC), the same value is set in TCC. Note: * For details on interrupts, see 3.2.2, Interrupts. 2. Operation as auto-reload timer Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count. After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow (or underflow). The TLC value is then loaded into TCC, and the count continues from that value. The overflow (underflow) period can be set within a range from 1 to 256 input clocks, depending on the TLC value. The clock sources, up/down control, and interrupts in auto-reload mode are the same as for interval mode. In auto-reload mode (bit TMC7 = 1), setting a new TLC value also initializes TCC. 3. Operation as event counter Timer C can operate as an event counter, using P11/IRQ1 as the event input pin. External event counting is selected by setting bits TMC2 to TMC0 in timer register C (TMC) to all 1's (111). TCC can count either rising or falling edges of the input at pin P11/IRQ1. When timer C is used to count external event input, bit IRQC1 in port mode register 1 (PMR1) should be set to 1, and bit IEN1 in interrupt enable register 1 (IENR1) should be cleared to 0 to disable IRQ1 interrupt requests. 4. TCC up/down control by hardware The counting direction of timer C can be controlled by input at pin P97/UD. When bit TMC6 in TMC is set to 1, high-level input at the UD pin selects down-counting, while low-level input selects up-counting. When using input at pin UD for this control function, set the UP/DOWN bit in port mode register 2 (PMR2) to 1. 137 6.5 Timer D 6.5.1 Overview Timer D is an 8-bit event counter, which is incremented by input of an external event signal. Either rising or falling edges of the external event signal can be counted. 1. Features Features of timer D are given below. * Choice of rising or falling edge for external event counting. * An interrupt is requested when the counter overflows. 2. Block diagram Figure 6-5 shows a block diagram of timer D EVENT TCD Internal data bus TMD Notation: TMD: Timer mode register D IRRTD TCD: Timer counter D IRRTD: Timer D overflow interrupt request flag (interrupt request register 2) Figure 6-5 Block Diagram 138 3. Pin configuration Table 6-7 shows the timer D pin configuration. Table 6-7 Pin Configuration Name Abbrev. I/O Function Event input pin P16/EVENT Input Timer D event input 4. Register configuration Table 6-8 shows the register configuration of timer D. Table 6-8 Timer D Registers Name Abbrev. R/W Initial Value Address Timer mode register D TMD R/W* H'7E H'FFC6 Timer counter D TCD R H'00 H'FFC7 Note: * Writing to bit 7 of TMD is possible only when writing 1 to clear the counter. 6.5.2 Register Descriptions 1. Timer mode register D (TMD) Bit 7 6 5 4 3 2 1 0 CLR -- -- -- -- -- -- EDG Initial value 0 1 1 1 1 1 1 0 Read/Write W -- -- -- -- -- -- R/W TMD is an 8-bit read/write register for clearing timer counter D (TCD), and for selecting whether input at the external event pin is sensed at the rising or falling edge. Bit 7: Counter clear (CLR) Bit 7 initializes TCD to H'00. Bit 7 CLR Description 0 TCD continues operating. 1 TCD is initialized to H'00 (after which this bit is automatically cleared to 0). (initial value) Note: It is only possible to write 1 to clear the counter. Writing 0 has no effect on counter operation. 139 Bits 6 to 1: Reserved bits Bits 6 to 1 are reserved; they are always read as 1, and cannot be modified. Bit 0: Edge select (EDG) Bit 0 selects the rising or falling edge of input at external event pin P16/EVENT. Bit 0 EDG Description 0 TCD counts falling edges of input at pin P16/EVENT. 1 TCD counts rising edges of input at pin P16/EVENT. 2. (initial value) Timer counter D (TCD) Bit 7 6 5 4 3 2 1 0 TCD7 TCD6 TCD5 TCD4 TCD3 TCD2 TCD1 TCD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R TCD is an 8-bit read-only up-counter, which is incremented by external clock input at pin P16/EVENT. The input clock edge is selected by the EDG bit in timer mode register D (TMD). The TCD value can be read by the CPU at any time. When TCD overflows from H'FF to H'00, the IRRTD bit in interrupt request register 2 (IRR2) is set to 1. Upon reset, TCD is initialized to H'00. 140 6.5.3 Timer Operation Timer D operates on an external clock input at pin P16/EVENT, used as an event input pin. The rising or falling edge of this input is selected by the EDG bit in timer mode register D (TMD). After the count value in TCD reaches H'FF, the next clock signal input causes timer D to overflow, setting bit IRRTD in interrupt request register 2 (IRR2) to 1 . If bit IENTD = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.* At overflow, TCD returns to H'00 and starts counting up again. TCD can be cleared by setting the CLR bit to 1 in TMD. To use external event input, the EVENT bit in port mode register 1 (PMR1) must be set to 1. Note: * For details on interrupts, see 3.2.2, Interrupts. 141 6.6 Timer E 6.6.1 Overview Timer E is an 8-bit up-counter that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. In addition, it can output a square wave with a 50% duty cycle, using overflow signals or signals from prescaler S. 1. Features Features of timer E are given below. * Choice of eight internal clock sources (o/8192, o/4096, o2048, o/512, o/256, o/128, o/32, o/8). * An interrupt is requested when the counter overflows. * Prescaler signals can provide a fixed-frequency output with a 50% duty cycle. When o = 4 MHz, output is 1.95 kHz or 3.9 kHz. When o = 2 MHz, output is 0.98 kHz or 1.95 kHz. * Overflow signals can produce square wave output of any frequency with a 50% duty cycle. 142 2. Block diagram Figure 6-6 shows a block diagram of timer E. TME System clock Prescaler S Internal data bus TLE TCE Notation: TME: Timer mode register E TCE: Timer counter E TLE: Timer load register E IRRTE: Timer E overflow interrupt request flag (interrupt request register 2) Figure 6-6 Block Diagram 3. Pin configuration Table 6-9 shows the timer E pin configuration. Table 6-9 Pin Configuration Name Abbrev. I/O Function Timer E waveform output pin P15/IRQ5/TMOE Output Timer E output 143 IRRTE Latched to TMOE output 4. Register configuration Table 6-10 shows the register configuration of timer E. Table 6-10 Timer E Registers Name Abbrev. R/W Initial Value Address Timer mode register E TME R/W H'78 H'FFC8 Timer counter E TCE R H'00 H'FFC9 Timer load register E TLE W H'00 H'FFC9 Port mode register 4 PMR4 R/W H'0F H'FFEE 6.6.2 Register Descriptions 1. Timer mode register E (TME) Bit 7 6 5 4 3 2 1 0 TME7 -- -- -- -- TME2 TME1 TME0 Initial value 0 1 1 1 1 0 0 0 Read/Write R/W -- -- -- -- R/W R/W R/W TME is an 8-bit read/write register for selecting the auto-reload function and input clock. Upon reset, TME is initialized to H'78. Bit 7: Auto-reload function select (TME7) Bit 7 selects the auto-reload function of timer E. Bit 7 TME7 Description 0 Interval timer function selected. 1 Auto-reload function selected. (initial value) Bits 6 to 3: Reserved bits Bits 6 to 3 are reserved; they are always read as 1, and cannot be modified. 144 Bits 2 to 0: Clock select (TME2 to TME0) Bits 2 to 0 select the clock input to TCE. Bit 2 TME2 Bit 1 TME1 Bit 0 TME0 Description 0 0 0 Internal clock: o/8192. 0 0 1 Internal clock: o/4096. 0 1 0 Internal clock: o/2048. 0 1 1 Internal clock: o/512. 1 0 0 Internal clock: o/256. 1 0 1 Internal clock: o/128. 1 1 0 Internal clock: o/32. 1 1 1 Internal clock: o/8. 2. (initial value) Timer counter E (TCE) Bit 7 6 5 4 3 2 1 0 TCE7 TCE6 TCE5 TCE4 TCE3 TCE2 TCE1 TCE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R TCE is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TME2 to TME0 in timer mode register E (TME). The TCE value can be read by the CPU at any time. When TCE overflows from H'FF to H'00 or to the value set in TLE, the IRRTE bit in interrupt request register 2 (IRR2) is set to 1. TCE is allocated to the same address as timer load register E (TLE). Upon reset, TCE is initialized to H'00. 145 3. Timer load register E (TLE) Bit 7 6 5 4 3 2 1 0 TLE7 TLE6 TLE5 TLE4 TLE3 TLE2 TLE1 TLE0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W TLE is an 8-bit write-only register for setting the reload value of TCE. When a reload value is set in TLE, the same value is loaded into timer counter E (TCE) as well, and TCE starts counting up from that value. When TCE overflows during operation in auto-reload mode, the TLE value is loaded in TCE. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLE as to TCE. Upon reset, TLE is initialized to H'00. 4. Port mode register 4 (PMR4) Bit 7 6 5 4 3 2 1 0 TEO TEO ON FREQ VRFR -- -- -- -- Initial value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/W -- -- -- -- PMR4 is an 8-bit read/write register, for switching functions of pin P15/IRQ5/TMOE and for controlling waveform output from pin TMOE. Upon reset, PMR4 is initialized to H'0F. 146 Bit 7: Timer E output function select (TEO) Bit 6: Timer E output on/off (TEO ON) Bit 5: Fixed frequency select (FREQ) Bit 4: Variable frequency select (VRFR) Functions of pin P15/IRQ5/TMOE are switched as follows, according to the values in bits 7 to 4 of PMR4 and in bit IRQC5 of port mode register 1 (PMR1). PMR1 PMR4 Description Bit 5 IRQC5 Bit 7 TEO Bit 6 Bit 5 TEO ON FREQ Bit 4 VRFR Pin Function Pin State 0 0 0 0 0 P15 pin Standard I/O port (initial value) 0 0 * * * P15 pin Standard I/O port 0 1 0 * * TMOE output pin Low-level output (off) 0 1 1 0 0 TMOE output pin Fixed-frequency output: (on) (o/2048) 1.95 kHz (o = 4 MHz) 0.98 kHz (o = 2 MHz) 0 1 1 1 0 TMOE output pin Fixed-frequency output: (on) (o/1024) 3.9 kHz (o = 4 MHz) 1.95 kHz (o = 2 MHz) 0 1 1 * 1 TMOE output pin Variable-frequency output: (on) toggled by timer E overflow 1 * * * * IRQ5 input pin External interrupt input Note: * Don't care. Bits 3 to 0: Reserved bits Bits 3 to 0 are reserved; they are always read as 1, and cannot be modified. 147 6.6.3 Timer Operation Timer E is an 8-bit up-counter that is incremented each time a clock pulse is input. It functions as an interval or auto-reload timer. It can also output a square wave having a 50% duty cycle. Each of these operation modes is explained below. 1. Interval timer operation When bit TME7 in timer mode register E (TME) is cleared to 0, timer E functions as an 8-bit interval timer. Upon reset, timer counter E (TCE) is reset to H'00 and bit TME7 is cleared to 0, so up-counting and interval timing resume immediately after the reset. The clock input to timer E is selected from eight internal clock signals output by prescaler S. The selection is made by bits TME2 to TME0 in TME. After the count value in TCE reaches H'FF, the next clock signal input causes timer E to overflow, setting bit IRRTE to 1 in interrupt request register 2 (IRR2). If bit IENTE = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.* At overflow, TCE returns to H'00, and starts counting up again. During interval timer operation (TME7 = 0), when a value is set in timer load register E (TLE), the same value is set in TCE. Note: * For details on interrupts, see 3.2.2, Interrupts. 2. Auto-reload timer operation Setting bit TME7 in TME to 1 causes timer E to function as an 8-bit auto-reload timer. When a reload value is set in TLE, the same value is loaded into TCE, becoming the value from which TCE starts its count. After the count value in TCE reaches H'FF, the next clock signal input causes timer E to overflow. The TLE value is then loaded into TCE, and the count continues from that value. The overflow period can be set within a range from 1 to 256 input clocks, depending on the TLE value. The clock sources and interrupts in auto-reload mode are the same as for interval mode. In auto-reload mode (bit TME7 = 1), setting a new TLE value also initializes TCE. 148 3. Square wave output A 50% duty square wave can be output at pin P15/IRQ5/TMOE if this function is selected in port mode register 4 (PMR4) and bit IRQC5 in port mode register 1 (PMR1). When bit VRFR = 0 in PMR4, the square wave has a fixed frequency designated in the FREQ bit. For the frequencies that can be output, see 6.6.2 (4), Port mode register 4 (PMR4). When bit VRFR = 1, timer E overflow generates a toggle output alternating between low and high level (see figure 6-7). The overflow period is selected in timer load register E (TLE), with timer E operating in auto-reload mode (bit TME7 = 1). The operating clock can be selected by means of bits TME2 to TME0. These settings can give a waveform output of any desired frequency within the range shown in table 6-11. Timer E value = H'FF TLE value (auto-reload mode selected) TMOE output waveform Timer E interrupt request Figure 6-7 Square Wave Output Triggered by Timer E Overflow 149 Table 6-11 Frequencies of Output Waveforms Triggered by Timer E Overflow Output Waveform (o = 2 MHz) 1 Count (TLE = H'FF) x 2 256 Counts (TLE = H'00) x 2 Internal Clock Count Time Output Frequency Count Time Output Frequency o/8 (250 kHz) 8 s 125 kz 2024 s 488.3 Hz o/32 (62.5 kHz) 32 s 31.25 kHz 8192 s 122.1 Hz o/128 (15.62 kHz) 128 s 7.8125 kHz 32.768 ms 30.5 Hz o/256 (7.8125 kHz) 256 s 3.9063 kHz 65.536 ms 15.3 Hz o/512 (3.9062 kHz) 512 s 1.9531 kHz 131.072 ms 7.63 Hz o/2048 (976.5 Hz) 2.048 ms 488.3 Hz 524.288 ms 1.91 Hz o/4096 (488.2 Hz) 4.096 ms 244.1 Hz 1048.576 ms 0.95 Hz o/8192 (244.1 Hz) 8.192 ms 122.1 Hz 2097.152 ms 0.477 Hz Output Waveform (o = 4 MHz) 1 Count (TLE = H'FF) x 2 256 Counts (TLE = H'00) x 2 Internal Clock Count Time Output Frequency Count Time Output Frequency o/8 (500 kHz) 4 s 250 kz 1024 s 976.6 Hz o/32 (125 kHz) 16 s 62.5 kHz 4096 s 244.1 Hz o/128 (31.25 kHz) 64 s 15.625 kHz 16.384 ms 61.0 Hz o/256 (15.625 kHz) 128 s 7.8125 kHz 32.768 ms 30.5 Hz o/512 (7.8125 kHz) 256 s 3.9063 kHz 65.536 ms 15.3 Hz o/2048 (1.963 Hz) 1.024 ms 976.6 Hz 262.144 ms 3.8 Hz o/4096 (976.52 Hz) 2.048 ms 488.3 Hz 524.288 ms 1.91 Hz o/8192 (488.2 Hz) 4.096 ms 244.1 Hz 1048.576 ms 0.95 Hz 150 6.7 Interrupts Timer A to E interrupts are requested when a timer overflows or underflows. Each timer is assigned its own vector address. The priority of interrupts is in the order of timer A (high) to timer E (low). Further details are given in 3.2.2, Interrupts, table 3-2, Interrupt Sources. When timers A to E overflow, the corresponding bit IRRTA to IRRTE in interrupt request register 2 (IRR2) is set to 1. These interrupt flags are not cleared even if the interrupt is accepted. They must be cleared to 0 by software in the interrupt handler routine. Interrupts may be enabled or disabled independently for each timer by means of bits IENTA to IENTE in interrupt enable register 2 (IENR2). For further details see 3.2.3, Interrupt Control Registers. 6.8 Application Notes Even when the EVENT bit in port mode register 1 (PMR1) designates the P16 usage of pin P16/EVENT, reading the P16 pin may cause timer D to increment. When using timer D, be sure to clear timer counter D (TCD) by means of the CLR bit in timer mode register D (TMD). 151 Section 7 14-Bit PWM 7.1 Overview The H8/3614 and H8/3613 have an on-chip 14-bit pulse width modulator (PWM), which can be used as a D/A converter by connecting a low-pass filter. Note: The H8/3612 does not have the PWM function. 7.1.1 Features Features of the 14-bit PWM are as follows. * Choice of two conversion periods A conversion period of 32768/o, with a minimum modulation width of 2/o, or a conversion period of 16384/o, with a minimum modulation width of 1/o, can be chosen. * Pulse division method for less ripple 7.1.2 Block Diagram Figure 7-1 shows a block diagram of the 14-bit PWM. PWDRL o/2 o/4 Internal data bus PWDRU PWM waveform generator PWCR Notation: PWDRL: PWM data register L PWDRU: PWM data register U PWCR: PWM control register PMR2: Port mode register 2 Figure 7-1 Block Diagram of 14-Bit PWM 153 P90 /PWM PMR2 (bit 0) 7.1.3 Pin Configuration Table 7-1 shows the output pin assigned to the 14-bit PWM. Table 7-1 Pin Configuration Name Abbrev. I/O Function PWM waveform output pin PWM Output PWM waveform output 7.1.4 Register Configuration Table 7-2 shows the register configuration of the 14-bit PWM. Table 7-2 Register Configuration Name Abbrev. R/W Initial Value Address PWM control register PWCR W H'FE H'FFCC PWM data register U PWDRU W H'C0 H'FFCD PWM data register L PWDRL W H'00 H'FFCE 154 7.2 Register Descriptions 7.2.1 PWM Control Register (PWCR) Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- PWCR0 Initial value 1 1 1 1 1 1 1 0 Read/Write -- -- -- -- -- -- -- W PWCR is an 8-bit write-only register for input clock selection. Upon reset, PWCR is initialized to H'FE. Bits 7 to 1: Reserved bits Bits 7 to 1 are reserved; they are always read as 1, and cannot be modified. Bit 0: Clock select (PWCR0) Bit 0 selects the clock supplied to the 14-bit PWM. This bit is for writing only; it is always read as 1. Bit 0 PWCR0 Description 0 The input clock is o/2 (to = 2/o). The conversion period is 16384/o, with a minimum modulation width of 1/o. 1 The input clock is o/4 (to = 4/o). The conversion period is 32768/o, with a minimum modulation width of 2/o. Notation: to: Period of PWM input clock 155 (initial value) 7.2.2 PWM Data Registers U and L (PWDRU, PWDRL) Bit 7 6 PWDRU -- -- Initial value 1 1 0 0 0 0 0 0 Read/Write -- -- W W W W W W Bit 7 6 5 4 3 2 1 0 PWDRL 5 4 3 2 1 0 PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total highlevel width of one PWM waveform cycle. When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the PWM waveform generator, updating the PWM waveform generation data. The 14-bit data should always be written in the following sequence, first to PWDRL and then to PWDRU. 1. Write the lower 8 bits to PWDRL. 2. Write the upper 6 bits to PWDRU. PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1. Upon reset, PWDRU and L are initialized to H'C000. 156 7.3 Operation When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 2 (PMR2) to 1 so that pin P90/PWM is designated for PWM output. 2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either 32768/o (PWCR0 = 1) or 16384/o (PWCR0 = 0). 3. Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write in the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the data in these registers will be latched in the PWM waveform generator, updating PWM waveform generation in synchronization with internal signals. One conversion period consists of 64 pulses, as shown in figure 7-2. The total of the high-level pulse widths during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be represented as follows. TH = (data value in PWDRU and PWDRL + 64) x to/2 where to is the PWM input clock period, either 2/o (bit PWCR0 = 0) or 4/o (bit PWCR0 = 1). If the data value in PWDRU and PWDRL is between H'3FC0 and H'3FFF, the PWM output level will be high. Example: Settings in order to obtain a conversion period of 8,192 s: When bit PWCR0 = 0, the conversion period is 16384/o, so o must be 2 MHz. In this case tfn = 128 s, with 1/o (resolution) = 0.5 s. When bit PWCR0 = 1, the conversion period is 32768/o, so o must be 4 MHz. In this case tfn = 128 s, with 2/o (resolution) = 0.5 s. Accordingly, for a conversion period of 8,192 s, the system clock frequency (o) must be 2 MHz or 4 MHz. 157 Conversion period t f1 t H1 t f2 t H2 t f63 t H3 t H63 TH = t H1 + t H2 + t H3 + . . . + t H64 t f1 = t f2 = t f3 . . . = t f64 Figure 7-2 PWM Output Waveform 158 t f64 t H64 Section 8 SCI1 8.1 Overview Serial communication interface 1 (SCI1) is for clock-synchronous serial transfer of 8-bit or 16-bit data. 8.1.1 Features SCI1 features are as follows. * Choice of 8-bit or 16-bit data transfer * Choice of eight internal clock sources (o/1024, o/256, o/64, o/32, o/16, o/8, o/4, o/2) or an external clock * Interrupts requested at completion of transfer or when error occurs 8.1.2 Block Diagram Figure 8-1 shows a block diagram of SCI1. SMR1 System clock Prescaler S (13 bits) SPR1 SDRL1 IRRS1 Internal data bus Octal/Hexadecimal counter 1 (3 or 4 bits) SO1 SDRU1 SI 1 SCK 1 Notation: SMR1: Serial mode register 1 SPR1: Serial port register 1 SDRL1: Serial data register L1 SDRU1: Serial data register U1 IRRS1: Serial communication interface 1 interrupt request flag (interrupt request register 3) Figure 8-1 Block Diagram of SCI1 159 8.1.3 Pin Configuration Table 8-1 shows the SCI1 pin configuration. Table 8-1 Pin Configuration Name Abbrev. I/O Function SCI1 clock pin P91/SCK1 I/O SCI1 clock I/O pin SCI1 data input pin P92/SI1 Input SCI1 received data input pin SCI1 data output pin P93/SO1 Output SCI1 transmit data output pin 8.1.4 Register Configuration Table 8-2 shows the SCI1 register configuration. Table 8-2 SCI1 Registers Name Abbrev. R/W Initial Value Address Serial mode register 1 SMR1 W H'80 H'FFB0 Serial data register U1 SDRU1 R/W Not fixed H'FFB1 Serial data register L1 SDRL1 R/W Not fixed H'FFB2 Serial port register 1 SPR1 R/W Not fixed H'FFB3 Port mode register 2 PMR2 R/W H'00 H'FFEC Port mode register 3 PMR3 R/W H'97 H'FFED 160 8.2 Register Descriptions 8.2.1 Serial Mode Register 1 (SMR1) Bit 7 6 5 4 3 2 1 0 -- SMR16 SMR15 SMR14 SMR13 SMR12 SMR11 SMR10 Initial value 1 0 0 0 0 0 0 0 Read/Write -- W W W W W W W SMR1 is an 8-bit write-only register, for selecting the operation mode and the prescaler divider ratio. Another function is to initialize the internal state of the serial interface, which happens at each write access to SMR1. When SMR1 is written to, serial clock supply to serial data registers U1 and L1 (SDRU1, SDRL1) and to the octal/hexadecimal counter is stopped, and the octal/hexadecimal counter is reset to H'00. Accordingly, writing to the serial mode register while the serial interface is operating will abort data transmission or reception, and IRRS1 flag will be set to 1 in interrupt request register 3 (IRR3). Upon reset, SMR1 is initialized to H'80. Bit 7: Reserved bit Bit 7 is reserved; it is always read as 1, and cannot be modified. Bits 6 to 4: Operation mode select (SMR16 to SMR14) Bits 6 to 4 select the SCI1 operation mode. Bit 6 SMR16 Bit 5 SMR15 Bit 4 SMR14 Description 0 0 0 Continuous clock output mode 1 SMR15, SMR14 set to value other than 00 8-bit transfer mode 0 Continuous clock output mode 0 SMR15, SMR14 set to value other than 00 16-bit transfer mode 161 (initial value) Bits 3 to 0: Clock select (SMR13 to SMR10) Bits 3 to 0 select the clock supplied to SCI1. Bit 3 Bit 2 Bit 1 SMR13 SMR12 SMR11 0 0 0 1 0 1 0 1 0 1 0 * * * 0 1 1 1 0 1 1 0 * * * 1 1 Bit 0 Clock SMR10 Pin SCK1 Source 0 SCK1 output Prescaler S 0 * * * 1 1 Prescaler Divider Ratio o/1024 (initial value) o/256 o/64 o/32 o/16 o/8 o/4 o/2 -- SCK1 output SCK1 output SCK1 output SCK1 output SCK1 output SCK1 output SCK1 output Not used Prescaler S Prescaler S Prescaler S Prescaler S Prescaler S Prescaler S Prescaler S -- SCK1 input External clock -- Serial Clock Period (s) o = 4 MHz o = 2 MHz 256 512 64 16 8 4 2 1 -- -- 128 32 16 8 4 2 1 -- -- -- 8.2.2 Serial Data Register U1 (SDRU1) Bit 7 6 5 4 3 2 1 0 SDRU17 SDRU16 SDRU15 SDRU14 SDRU13 SDRU12 SDRU11 SDRU10 Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: * Not fixed SDRU1 is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit transfer (SDRL1 is used for the lower 8 bits). Data written to SDRU1 is output to SDRL1 starting from the least significant bit (LSB), in synchronization with the falling edge of the serial clock. This data is than replaced by LSB-first data input at pin SI1, synchronized with the rising edge of the serial clock. In this way data is shifted in the direction from the most significant bit (MSB) toward the LSB. SDRU1 must be written or read only after data transmission or reception is complete. If this register is read or written while a data transfer is in progress, the data contents are not guaranteed. The SDRU1 value upon reset is not fixed. 162 8.2.3 Serial Data Register L1 (SDRL1) Bit 7 6 5 4 3 2 1 0 SDRL17 SDRL16 SDRL15 SDRL14 SDRL13 SDRL12 SDRL11 SDRL10 Initial value Read/Write * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W Note: * Not fixed SDRL1 is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (SDRU1 is used for the upper 8 bits). In 8-bit transfer, data written to SDRL1 is output from pin SO1 starting from the least significant bit (LSB), in synchronization with the falling edge of the serial clock. This data is then replaced by LSB-first data input at pin SI1, synchronized with the rising edge of the serial clock. In this way data is shifted in the direction from the most significant bit (MSB) toward the LSB. In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via SDRU1. SDRL1 must be written or read only after data transmission or reception is complete. If this register is read or written while a data transfer is in progress, the data contents are not guaranteed. The SDRL1 value upon reset is not fixed. 8.2.4 Serial Port Register 1 (SPR1) Bit Initial value Read/Write 7 6 5 4 3 2 1 0 SO1 LAST BIT -- -- -- -- -- -- -- * R/W 1 1 1 1 1 1 1 -- -- -- -- -- -- -- Note: * Not fixed SPR1 is an 8-bit read/write register, bit 7 of which is connected to the last output stage of SDRL1. The SPR1 value upon reset is not fixed. 163 Bit 7: Extended data bit (SO1 LAST BIT) Bit 7 holds the last bit of transmitted data after transmission ends. Output from pin SO1 can be altered by software by modifying this bit either before or after transmission. If this bit is written during data transmission, the data contents are not guaranteed. Bit 7 SO1 LAST BIT Description 0 Output from pin SO1 is low. 1 Output from pin SO1 is high. (initial value) Bits 6 to 0: Reserved bits Bits 6 to 0 are reserved: they are always read as 1, and cannot be modified. 8.2.5 Port Mode Register 2 (PMR2) Bit 7 6 5 4 3 2 1 0 UP/ DOWN SO2 SI2 SCK2 SO1 SI1 SCK1 PWM Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PMR2 is an 8-bit read/write register, for switching the port 9 pin functions. Bits 3 to 1, in combination with SMR1, set the SCI1 operation mode. Upon reset, PMR2 is initialized to H'00. Bits 3 to 1 are explained here. For bits 7 to 4 and bit 0, see 5.7.2 (1), Port Mode Register 2 (PMR2). Bit 3: Pin P93/SO1 function switch (SO1) Bit 3 selects whether pin P93/SO1 functions as a P93 input/output pin or as the SO1 output pin. Bit 3 SO1 Description 0 Pin P93/SO1 functions as P93 I/O pin. 1 Pin P93/SO1 functions as SO1 output pin. Setting bit SCK1 to 1 and clearing bit SI1 to 0 puts SCI1 in transmit mode. 164 (initial value) Bit 2: Pin P92/SI1 function switch (SI1) Bit 2 selects whether pin P92/SI1 functions as a P92 input/output pin or as the SI1 output pin. Bit 2 SI1 Description 0 Pin P92/SI1 functions as P92 I/O pin. 1 Pin P92/SI1 functions as SI1 output pin. Setting bit SCK1 to 1 and clearing bit SO1 to 0 puts SCI1 in receive mode. (initial value) Bit 1: Pin P91/SCK1 function switch (SCK1) Bit 1 selects whether pin P91/SCK1 functions as a P91 input/output pin or as the SCK1 input/output pin. Bit 1 SCK1 Description 0 Pin P91/SCK1 functions as P91 I/O pin. 1 Pin P91/SCK1 functions as SCK1 I/O pin. The direction of clock I/O and the prescaler divider ratio are set in serial mode register 1 (SMR1). (initial value) 8.2.6 Port Mode Register 3 (PMR3) Bit 7 6 -- SO2 PMOS Initial value 1 Read/Write -- 5 4 3 2 1 0 CS -- SO1 PMOS -- -- -- 0 0 1 0 1 1 1 R/W R/W -- R/W -- -- -- PMR3 is an 8-bit read/write register, for enabling the PMOS transistors of SCI1 and SCI2 data output pins (pins SO1 and SO2), and for controlling SCI2 chip select output (pin SI2/CS). Upon reset, PMR3 is initialized to H'97. Bit 3 is explained here. For bits 6 and 5, see 9.2.5, Port Mode Register 3 (PMR3). Bit 3: Pin SO1 PMOS on/off (SO1PMOS) Bit 3 enables or disables the PMOS buffer transistor of pin P93/SO1. Bit 3 S01PMOS Description 0 The PMOS transistor of pin P93/SO1 is enabled: CMOS output. 1 The PMOS transistor of pin P93/SO1 is disabled: NMOS open-drain output. 165 (initial value) 8.3 Operation 8.3.1 Overview SCI1 sends and receives data in synchronization with clock pulses. SCI1 operation modes are set by bits 6 to 4 of serial mode register 1 (SMR1) and bits 3 to 1 of port mode register 2 (PMR2) in combination, as shown in table 8-3. Table 8-3 SCI1 Operation Mode Setting SMR1 PMR2 SMR16 SMR15 SMR14 PMR23 PMR22 PMR21 Operation Mode * * * 0 0 0 Serial communication disabled * 0 0 0 0 1 Continuous clock output mode 0 SMR15, SMR14 set to value other than 00 1 0 1 8-bit transmit mode 0 1 1 8-bit receive mode 1 1 1 8-bit transmit/receive mode 1 0 1 16-bit transmit mode 0 1 1 16-bit receive mode 1 1 1 16-bit transmit/receive mode 1 SMR15, SMR14 set to value other than 00 Note: * Don't care. Pin SCK1 and the serial clock are controlled by writing data to SMR1. SDRU1 and SDRL1 are used to write transmit data and to hold received data; these registers can be written and read by software. Data in these registers is shifted in synchronization with the serial clock, for input and output at pins SI1 and SO1. SCI1 operation starts with a dummy read of SMR1. The octal/hexadecimal counter is cleared to H'0 by this dummy read, and starts counting anew from the falling edge of the serial clock (pin SCK1), being incremented by 1 at each rising edge of the serial clock. If 8 or 16 serial clock cycles are input and the counter overflows, or if data transmission or reception is aborted, the octal/hexadecimal counter is cleared to H'0. At the same time bit IRRS1 in interrupt request register 3 (IRR3) is set to 1. For more details on interrupts, see 3.2.2, Interrupts. 166 8.3.2 Data Transfer Format Figure 8-2 shows the synchronous data transfer format. Data can be sent and received in lengths of 8 bits or 16 bits. Data is sent and received starting from the least significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial clock until the next falling edge. Receive data is latched at the rising edge of the serial clock. SCK 1 LSB SO 1 Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit n - 1 Bit n SI 1 input data latch timing n = 7: 8-bit transfer mode n = 15: 16-bit transfer mode Figure 8-2 Synchronous Data Transfer Format 8.3.3 Clock Eight internal clock sources or an external clock may be selected as the serial clock. When an internal clock is used, pin SCK1 is the clock output pin. 8.3.4 Data Transmit/Receive * Initializing SCI1 Before data is sent or received, first SCI1 must be initialized by software. This is done by writing the desired transfer conditions in serial mode register 1 (SMR1). * Transmitting A transmit operation is carried out as follows. 1 Set bit SO1 in port mode register 2 (PMR2) to 1, making pin P93/SO1 the SO1 output pin. Also set bit SCK1 in PMR2 to 1, making pin P91/SCK1 the SCK1 I/O pin. If necessary, set the SO1PMOS bit in PMR3 for NMOS open-drain output at pin SO1. 167 2 Set bit SMR16 in SMR1 to 1 or 0, and set bits SMR15 and SMR14 to a value other than 00, designating 8- or 16-bit transfer mode. Select the serial clock with bits SMR13 to SMR10. Writing data to SMR1 initializes the internal state of SCI1. 3 Write transmit data in serial data register L1 (SDRL1) and serial data register U1 (SDRU1), as follows. 8-bit transfer mode: SDRL1 16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1 4 Execute a dummy read of SMR1. SCI1 starts operating, and outputs the transmit data at pin SO1. 5 After data transmission is complete, bit IRRS1 in interrupt request register 3 (IRR3) is set to 1. When an internal clock source is used, a serial clock is output from pin SCK1 in synchronization with the transmit data. After data transmission is complete, the serial clock is not output until the next dummy read of SMR1. During this time, pin SO1 continues to output the value of the last bit transmitted. When an external clock source is used, data is transmitted in synchronization with the serial clock input at pin SCK1. After data transmission is complete, if the serial clock continues to be input, transmission resumes. Between transmissions, the output value of pin SO1 can be changed by rewriting bit 7 (SO1 LAST BIT) in serial port register 1 (SPR1). Executing a dummy read of SMR1 during transmission will cause a transmit error, setting bit IRRS1 in IRR3 to 1. * Receiving A receive operation is carried out as follows. 1 Set bit SI1 in port mode register 2 (PMR2) to 1, making pin P92/SI1 the SI1 input pin. Also set bit SCK1 in PMR2 to 1, making pin P91/SCK1 the SCK1 I/O pin. 2 Set bit SMR16 in serial mode register 1 (SMR1) to 1 or 0, and set bits SMR15 and SMR14 to a value other than 00, designating 8- or 16-bit transfer mode. Select the serial clock with bits SMR13 to SMR10. Writing data to SMR1 initializes the internal state of SCI1. 3 Execute a dummy read of SMR1. SCI1 starts operating, and receive data is input at pin SI1. 4 After data reception is complete, bit IRRS1 in interrupt request register 3 (IRR3) is set to 1. 168 5 Read the received data from SDRL1 and SDRU1, as follows. 8-bit transfer mode: SDRL1 16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1 When an internal clock source is used, a dummy read of SMR1 immediately starts a data receive operation. The serial clock is output from pin SCK1. When an external clock source is used, after the dummy read of SMR1, data is received in synchronization with the serial clock input at pin SCK1. After data reception is complete, if the serial clock continues to be input, reception resumes. Executing a dummy read of SMR1 during reception will cause a receive error, setting bit IRRS1 in IRR3 to 1. * Simultaneous transmit/receive A simultaneous transmit/receive operation is carried out as follows. 1 Set bits SO1, SI1, and SCK1 in PMR2 to 1, designating the SO1 output pin, SI1 pin, and SCK1 pin functions. If necessary, set the SO1PMOS bit in PMR3 for NMOS open-drain output at pin SO1. 2 Set bit SMR16 in SMR1 to 1 or 0, and set bits SMR15 and SMR14 to a value other than 00, designating 8- or 16-bit transfer mode. Select the serial clock with bits SMR13 to SMR10. Writing data to SMR1 initializes the internal state of SCI1. 3 Write transmit data in SDRL1 and SDRU1, as follows. 8-bit transfer mode: SDRL1 16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1 4 Execute a dummy read of SMR1. SCI1 starts operating: transmit data is output at pin SO1, and receive data is input at pin SI1. 5 After data transmission and reception are complete, bit IRRS1 in IRR3 is set to 1. 6 Read the received data from SDRL1 and SDRU1. 8-bit transfer mode: SDRL1 16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1 In simultaneous data transmit/receive, the transmit operation and receive operation described in 8.3.4 sections 2 and 3 take place at the same time. See those sections for further details. During a transmit/receive operation, a dummy read of SMR1 will result in a transmit/receive error, setting bit IRRS1 in IRR3 to 1. 169 8.3.5 SCI1 State Transitions SCI1 has three internal states, as shown in figure 8-3. In the serial start pending state, the internal state of the serial communication interface is initialized. In this state, the serial communication interface does not operate even if a serial clock signal is input. Executing a dummy read of SMR1 changes this state to the serial clock pending state. In the serial clock pending state, when a serial clock signal is input the octal/hexadecimal counter starts counting up and the serial data register starts shifting, entering the transfer state. If continuous clock output mode has been selected, however, SCI1 outputs the clock signal continuously and does not enter the transfer state. In the transfer state, when 8 or 16 transfer clock cycles are input, or if an SMR1 dummy read is executed, the octal/hexadecimal counter is reset to H'0, and SCI1 enters the serial clock pending state. Writing to SMR1 in the transfer state will reset the octal/hexadecimal counter to H'0 and change to the serial start pending state. In transitions from the transfer state to another state, the resetting of the octal/hexadecimal counter to H'0 sets bit IRRS1 in IRR3 to 1. If an internal clock source is selected, a dummy read of SMR1 starts output of the serial clock, which stops after 8 or 16 clock output cycles. After writing to SMR1 in the serial clock pending state or transfer state, it is necessary to write to SMR1 again in order to initialize the initial state of the serial communication interface. Writing to SMR1 changes the state to the serial start pending state. 170 Serial start (SMR1 dummy read) pending state octal counter = 000 or hexadecimal counter = 0000 serial clock disabled. SMR1 write SMR1 dummy read (serial start) 8 or 16 serial clock cycles (internal clock) (IRRS1 1) Serial clock Serial clock pending state SMR1 write (IRRS1 1) Transfer state octal counter =/ 000 or hexadecimal counter = / 0000 octal counter = 000 or hexadecimal counter = 0000 SMR1 dummy read (serial start) (IRRS1 1) 8 or 16 serial clock cycles (external clock) Figure 8-3 SCI1 State Transitions 8.3.6 Serial Clock Error Detection In the transfer state, if an extraneous pulse is superimposed on the normal serial clock signal due to external noise, SCI1 may function incorrectly. Serial clock errors can be detected by means of the procedure shown in figure 8-4. In the serial clock pending state, if more than the normal 8 or 16 serial clock cycles are mistakenly input, SCI1 changes from the transfer state to the serial clock pending state and then back to the transfer state. After bit IRRS1 in interrupt request register 3 (IRR3) is cleared to 0, writing a value in serial mode register 1 (SMR1) changes the state to serial start pending, and bit IRRS1 is again set to 1. 171 Transfer complete (IRRS1 1) Disable interrupts IRRS1 0 SMR1 write IRRS1 = 1? Yes Serial clock error processing No Normal completion Figure 8-4 Procedure for Detecting Serial Clock Errors 8.3.7 Interrupts SCI1 can generate interrupts for completion of transfer and for transmit/receive errors. These interrupts are assigned to the same vector address. When an SCI1 transfer is complete, or when a transmit/receive error occurs before the transfer is complete, bit IRRS1 in interrupt request register 3 (IRR3) is set to 1. SCI1 interrupt requests can be enabled or disabled in bit IENS1 of interrupt enable register 3 (IENR3). For further details, see 3.2.2, Interrupts. 172 Section 9 SCI2 9.1 Overview Serial communication interface 2 (SCI2) has a 32-byte data buffer, for synchronous serial transfer of up to 32 bytes of data in one operation. 9.1.1 Features SCI2 features are as follows. * Automatic transfer of up to 32 bytes of data * Choice of internal clock sources (o/8, o/4, o/2) or an external clock * Interrupts requested at completion of transfer or when error occurs 9.1.2 Block Diagram Figure 9-1 shows a block diagram of SCI2. System clock Prescaler S (13 bits) SCK 2 Shift clock generator circuit Bit counter SCR2 STAR Address decoder and R/W controller Byte counter Comparator circuit Data buffer (32 bytes) IRRS2 EDAR Shift register SO 2 SI2 /CS Internal data bus Notation: STAR: Start address register EDAR: End address register IRRS2: Serial communication interface 2 interrupt request flag (interrupt request register 3) Figure 9-1 Block Diagram of SCI2 173 9.1.3 Pin Configuration Table 9-1 shows the SCI2 pin configuration. Table 9-1 Pin Configuration Name Abbrev. I/O Function SCI2 clock pin SCK2 I/O SCI2 clock input/output SCI2 data input pin SI2 Input SCI2 receive data input SCI2 data output pin SO2 Output SCI2 transmit data output SCI2 chip select output pin CS Output SCI2 chip select output Note: Functions of pins P94/SCK2, P95/SI2/CS, and P96/SO2 are switched in port mode register 2 (PMR2) and port mode register 3 (PMR3). For PMR2, see 5.7.2 (1), Port mode register 2 (PMR2). 9.1.4 Register Configuration Table 9-2 shows the SCI2 register configuration. Table 9-2 SCI2 Registers Name Abbrev. R/W Initial Value Address 32-byte data buffer -- R/W Not fixed H'FF80 to H'FF9F Start address register STAR R/W H'E0 H'FFA0 End address register EDAR R/W H'E0 H'FFA1 Serial control register 2 SCR2 R/W H'E0 H'FFA2 Status register STSR R/W H'E0/H'E8 H'FFA3 Port mode register 2 PMR2 R/W H'00 H'FFEC Port mode register 3 PMR3 R/W H'97 H'FFED 174 9.2 Register Descriptions 9.2.1 Start Address Register (STAR) Bit 7 6 5 4 3 2 1 0 -- -- -- STA4 STA3 STA2 STA1 STA0 Initial value 1 1 1 0 0 0 0 0 Read/Write -- -- -- R/W R/W R/W R/W R/W STAR is an 8-bit read/write register, for designating the transfer start address in the memory area from H'FF80 to H'FF9F allocated to the 32-byte data buffer. The 32 bytes from H'00 to H'1F designated by the lower 5 bits of STAR (bits STA4 to STA0) correspond to addresses H'FF80 to H'FF9F. Data is sent or received continuously using the area defined in STAR and in the end address register (EDAR). Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Upon reset, STAR is initialized to H'E0. 9.2.2 End Address Register (EDAR) Bit 7 6 5 4 3 2 1 0 -- -- -- EDA4 EDA3 EDA2 EDA1 EDA0 Initial value 1 1 1 0 0 0 0 0 Read/Write -- -- -- R/W R/W R/W R/W R/W EDAR is an 8-bit read/write register, for designating the transfer end address in the memory area from H'FF80 to H'FF9F allocated to the 32-byte data buffer. The 32 bytes from H'00 to H'1F designated by the lower 5 bits of EDAR (bits EDA4 to EDA0) correspond to addresses H'FF80 to H'FF9F. Data is sent or received continuously using the area defined in STAR and EDAR. If the same value is designated in both STAR and EDAR, only one byte of data is transferred. Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Upon reset, EDAR is initialized to H'E0. 175 9.2.3 Serial Control Register 2 (SCR2) Bit 7 6 5 4 3 2 1 0 -- -- -- I/O GAP2 GAP1 PS1 PS0 Initial value 1 1 1 0 0 0 0 0 Read/Write -- -- -- R/W R/W R/W R/W R/W SCR2 is an 8-bit read/write register, for selecting whether SCI2 transmits or receives, for gap insertion during continuous transfer, and for serial clock selection. Upon reset, SCR2 is initialized to H'E0. Bits 7 to 5: Reserved bits Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bit 4: Transmit/receive select (I/O) Bit 4 selects SCI2 transmit or receive mode. Bit 4 I/O Description 0 SCI2 is in receive mode. 1 SCI2 is in transmit mode. (initial value) Bits 3 and 2: Gap insertion (GAP2 to GAP1) When data is transmitted or received continuously, gaps can be inserted at data divisions by holding the serial clock high for a length of time designated by bits 3 and 2. Bits 3 and 2 are valid when an internal clock source is selected as the serial clock (PS1 and 0 11). Data divisions may be placed every 8 bits or 16 bits; this is selected in bit GIT in the status register (STSR). Bit 3 GAP2 Bit 2 GAP1 Description 0 0 Serial clock keeps the same duty cycle even at data divisions. 0 1 Serial clock high level extended by one clock cycle at data divisions. 1 0 Serial clock high level extended by two clock cycles at data divisions. 1 1 Serial clock high level extended by eight clock cycles at data divisions. 176 (initial value) Bits 1 and 0: Transfer clock select (PS1 to PS0) Bits 1 and 0 select one of three internal clock sources or an external clock. Serial Clock Period PS1 PS0 Pin SCK2 Clock Source Prescaler Divider Ratio 0 0 SCK2 output Prescaler S o/2 (initial value) * 1 s 2 s 0 1 SCK2 output Prescaler S o/4 1 s 2 s 4 s 1 0 SCK2 output Prescaler S o/8 2 s 4 s 8 s 1 1 SCK2 input External clock -- -- -- -- o = 4 MHz o = 2 MHz o = 1 MHz Note: * Can be set, but operation is not guaranteed. 9.2.4 Status Register (STSR) Bit Initial value Read/Write 7 6 5 4 3 2 1 0 -- -- -- SO2 LAST BIT OVR WT GIT STF 1 1 1 0 *1 0 0 0 R/W R/W*2 R/W*2 R/W R/W -- -- -- Notes: 1. Not fixed 2. Cleared to 0 by write operation to STSR. STSR is an 8-bit register indicating the SCI2 operation state, error status, etc. Writing to this register during data transmission may cause misoperation. Upon reset, STSR is initialized to H'E0 or H'E8. Bits 7 to 5: Reserved bits Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bit 4: Extended data bit (SO2 LAST BIT) Bit 4 holds the last bit of transmitted data after transmission ends. Output from pin SO2 can be altered by software by modifying this bit either before or after transmission. Writing to this bit during data transmission may cause misoperation. 177 Bit 4 SO2 LAST BIT Description 0 Output from pin SO2 is low. 1 Output from pin SO2 is high. (initial value) Bit 3: Overrun flag (OVR) If the amount of data transferred exceeds the buffer size setting, or if an extraneous pulse is superimposed on the normal serial clock due to external noise, SCI2 overruns and bit 3 is set to 1. The initial value is not fixed. Bit 3 OVR Description 0 [Clear conditions] When STSR is written to. 1 [Set conditions] When overrun occurs. Bit 2: Waiting flag (WT) If an attempt is made to execute a read or write instruction to the 32-byte buffer during a serial data transfer, the instruction is ignored, and bit 2 is set to 1 along with bit IRRS2 in interrupt request register 3 (IRR3). Bit 2 WT 0 1 Description [Clear conditions] When STSR is written to. (initial value) [Set conditions] When a read/write to the 32-byte buffer is attempted during serial transfer. Bit 1: Gap interval flag (GIT) Bit 1 designates whether the extended serial clock high-level interval designated in bits GAP2 and GAP1 in serial control register 2 (SCR2) occurs every 8 bits or every 16 bits. This setting is valid only for internal clock operation. Bit 1 GIT Description 0 Gap specified by GAP2 and GAP1 is inserted every 16 bits. 1 Gap specified by GAP2 and GAP1 is inserted every 8 bits. 178 (initial value) Bit 0: Start/busy flag (STF) Setting bit 0 to 1 starts an SCI2 transfer operation. This bit stays at 1 during the transfer, and is cleared to 0 after the transfer is complete. It can therefore be used as a busy flag as well. Clearing this bit to 0 during a transfer aborts the transfer, initializing SCI2. The contents of the 32-byte data buffer and of registers other than STSR are unchanged when this happens. When this bit is set to 1 to start a transfer, the transfer begins from the data indicated by STAR. Bit 0 STF 0 Explanation [Read access] Indicates transfer not in progress. (initial value) [Write access] Stops transfer. 1 [Read access] Indicates transfer in progress. [Write access] Starts transfer. 9.2.5 Port Mode Register 3 (PMR3) Bit 7 6 5 4 3 2 1 0 -- SO2 PMOS CS -- SO1 PMOS -- -- -- Initial value 1 0 0 1 0 1 1 1 Read/Write -- R/W R/W -- R/W -- -- -- PMR3 is an 8-bit read/write register, for enabling the PMOS transistors of SCI1 and SCI2 data output pins (pin P93/SO1 and pin P96/SO2), and for controlling SCI2 chip select output (pin SI2/CS). Upon reset, PMR3 is initialized to H'97. For bit 3, see 8.2.6, Port Mode Register 3 (PMR3). Bit 7: Reserved bit Bit 7 is reserved; it is always read as 1, and cannot be modified. 179 Bit 6: Pin SO2 PMOS on/off (SO2PMOS) Bit 6 enables or disables the PMOS buffer transistor of pin P96/SO2. Bit 6 SO2PMOS Description 0 PMOS transistor of pin P96/SO2 is enabled: CMOS output. 1 PMOS transistor of pin P96/SO2 is disabled: NMOS open-drain output. (initial value) Bit 5: Chip select output select (CS) In combination with bit SI2 in port mode register 2 (PMR2), bit 5 selects the CS output function of pin P95/SI2/CS. The CS output pin function is valid when an internal clock source is selected as the serial clock, and only in transmit mode. PMR2 PMR3 Bit 5 SI2 Bit 5 CS Description 0 * Pin P95/SI2/CS functions as P95 I/O pin. 1 0 Pin P95/SI2/CS functions as SI2 input pin. 1 Pin P95/SI2/CS functions as CS output pin. Note: * Don't care. Bits 4 and 2 to 0: Reserved bits These bits are reserved; they are always read as 1, and cannot be modified. 180 (initial value) 9.3 Operation 9.3.1 Overview SCI2 has a 32-byte data buffer, making possible continuous transfer of up to 32 bytes of data with one operation. SCI2 transmits and receives data in synchronization with clock pulses. Selection of transmit or receive mode and of the serial clock is made in serial control register 2 (SCR2). The start address register (STAR) and end address register (EDAR) designate the area within the 32-byte data buffer for holding transfer data. The address range from H'FF80 to H'FF9F is allocated to this data buffer. The start and end positions of the transfer data area are indicated in the lower 5 bits of STAR and EDAR. After parameters have been set in port mode register 2 (PMR2), port mode register 3 (PMR3), SCR2, STAR, and EDAR, then when the STF bit of the status register (STSR) is set to 1, SCI2 begins a transfer operation. STF remains set to 1 during the transfer, and is cleared to 0 when the transfer is complete. The STF bit can therefore be used as a busy flag. Clearing the STF bit to 0 during a transfer stops the transfer operation and initializes SCI2. The contents of the data buffer and of other registers are unchanged in this case. During a transfer, the CPU cannot read or write the data buffer. If a write instruction is issued it is ignored; it has the same effect as a NOP instruction except that it takes more states. Read access during a transfer yields H'FF. When the transfer is complete, or if a data buffer read or write is attempted during the transfer, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1. In case of an overrun error or a data buffer read or write during the transfer, bit OVR or WT of STSR is set to 1. Note: If the start address is set to a value higher than the end address, the result is as shown in figure 9-2. The data transfer wraps around from address H'FF9F to address H'FF80 and continues to the end address. 181 H'FF80 H'00 End End address Start Start address H'FF9F H'1F Figure 9-2 Operation When Start Address Exceeds End Address 9.3.2 Clock Three internal clock sources or an external clock may be selected as the serial clock. When an internal clock is selected, pin SCK2 becomes the clock output pin. 9.3.3 Data Transfer Format Figure 9-3 shows the SCI2 data transfer format. Data is sent and received starting from the least significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial clock until the next falling edge. Receive data is latched at the rising edge of the clock. When SCI2 operates on an internal clock and is in transmit mode, a gap may be inserted at data divisions (every 8 bits or 16 bits). During this gap, the serial clock stays at the high level for a designated number of clock cycles (see figures 9-4 to 9-6). The CS output remains low during the gap. Gap insertion and the length of the gap are designated in bits GAP2 and GAP1 in serial control register 2 (SCR2). Bit GIT in the status register (STSR) designates whether gaps occur at 8-bit or 16-bit intervals. 182 CS SCK2 SO2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Don't care Bit 7 Held Figure 9-3 Synchronous Data Transfer Format Does not go to low level SCK 2 output Bit 14 (Bit 6) SO2 Bit 15 (Bit 7)* Bit 16 (Bit 8) Bit 17 (Bit 9) SI 2 input data latch timing Note: * When bit GIT = 1, a gap is inserted at 8-bit intervals. Figure 9-4 1-Clock Gap Insertion (Bits GAP2 and GAP1 = 01) Does not go to low level SCK 2 output Bit 14 (Bit 6) SO2 Bit 15 (Bit 7)* Bit 16 (Bit 8) SI 2 input data latch timing Note: * When bit GIT = 1, a gap is inserted at 8-bit intervals. Figure 9-5 2-Clock Gap Insertion (Bits GAP2 and GAP1 = 10) 183 Transfer clock x 8 SCK 2 output Bit 14 (Bit 6) SO2 Bit 15 (Bit 7)* Bit 16 (Bit 8) SI 2 input data latch timing Note: * When bit GIT = 1, a gap is inserted at 8-bit intervals. Figure 9-6 8-Clock Gap Insertion (Bits GAP2 and GAP1 = 11) 9.3.4 Data Transmit/Receive * Initializing SCI2 Before data is sent or received, first SCI2 must be initialized by software. This involves clearing bit STF in the status register (STSR) to 0, then selecting pin functions and transfer modes in port mode register 2 (PMR2), port mode register 3 (PMR3), the start address register (STAR), the end address register (EDAR), and serial control register 2 (SCR2). * Transmitting A transmit operation is carried out as follows. 1 Set bit SO2 in port mode register 2 (PMR2) to 1, making pin P96/SO2 the SO2 output pin. If necessary, set the SO2PMOS bit and CS bit in PMR3 for NMOS open-drain output at pin SO2 and for chip select output at pin P95/SI2/CS. 2 Write transmit data in the 32-byte data buffer (H'FF80 to H'FF9F). 3 Set the transfer start address in the lower 5 bits of STAR. 4 Set the transfer end address in the lower 5 bits of EDAR. 5 In SCR2, select transmit mode (bit I/O = 1), the serial clock, and gap insertion (internal clock operation only). 6 Select the data gap interval with bit GIT of STRS, then set bit STF to 1. Setting bit STF starts the transmit operation. 184 7 After data transmission is complete, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1, and bit STF in STSR is cleared to 0. If an internal clock source is used, a serial clock is output from pin SCK2 in synchronization with the transmit data. After data transmission is completed, the serial clock is not output until bit STF is again set. During this time, pin SO2 continues to output the value of the last bit transmitted. When an external clock source is used, data is transmitted in synchronization with the serial clock input at pin SCK2. After data transmission is completed, further transmission does not take place even if the serial clock continues to be input; pin SO2 continues to output the value of the last bit transmitted. Between transmissions, the output value of pin SO2 can be changed by rewriting bit SO2 LAST BIT in STSR. An attempt to read or write the data buffer during transmission will cause bit IRRS2 in IRR3 to be set to 1. Bit WT in STSR will also be set to 1. * Receiving A receive operation is carried out as follows. 1 Set bit SI2 in port mode register 2 (PMR2) to 1, making pin P95/SI1/CS the SI2 input pin. 2 Allocate an area to hold the received data in the 32-byte data buffer and set the start address in the lower 5 bits of the start address register (STAR). 3 Set the transfer end address in the lower 5 bits of the end address register (EDAR). 4 In serial control register 2 (SCR2), select receive mode (bit I/O = 0) and the serial clock. 5 Set bit STF of the status register (STSR) to 1, starting the receive operation. 6 After receiving is completed, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1, and bit STF is cleared to 0. 7 Read the received data from the data buffer. If an internal clock source is used, setting bit STF to 1 in STSR immediately starts a data receive operation. The serial clock is output from pin SCK2. 185 When an external clock source is used, after bit STF is set, data is received in synchronization with the clock input at pin SCK2. After receiving is completed, no further receive operations take place until bit STF is again set, even if the serial clock continues to be input. An attempt to read or write the data buffer during receiving will cause bit IRRS2 in IRR3 and bit WT in STSR to be set to 1. Bit OVR in STSR is set to 1 if an overrun error occurs. When SCI2 operates on an internal clock and is in transmit mode, a gap may be inserted at data divisions (every 8 bits or 16 bits). During this gap, serial clock stays at the high level for a designated number of clock cycles (see figures 9-4 through 9-6). Gap insertion and the length of the gap are designated in bits GAP2 and GAP1 of SCR2. Bit GIT of STSR designates whether gaps occur at 8-bit or 16-bit intervals. 9.4 Interrupts SCI2 can generate interrupts when a transfer is completed and when the data buffer is read or written during a transfer. These interrupts are assigned to the same vector address. When the above conditions occur, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1. SCI2 interrupt requests can be enabled or disabled in bit IENS2 of interrupt enable register 3 (IENR3). For further details, see 3.2.2, Interrupts. When an overrun error occurs, or when a read or write of the data buffer is attempted during a transfer, the OVR or WT bit in the status register (STSR) is set to 1. These bits can be used to determine the cause of the error. 9.5 Application Notes 1. Do not write to any register during a transfer (while bit STF of STSR is set to 1), since this can cause misoperation. 2. When receiving, set bit SI2 in port mode register 2 (PMR2) to 1 and clear bit CS in port mode register 3 (PMR3) to 0 to select the SI2 pin function. If bit CS = 1 and bit SI2 = 1, selecting the CS pin function, incorrect data will be received. 186 Section 10 A/D Converter 10.1 Overview The H8/3614 Series includes on-chip a resistance-ladder type successive-approximation A/D converter, which can convert up to eight channels of analog input. 10.1.1 Features The A/D converter has the following features. * 8-bit resolution * Eight input channels * Conversion time: 14.8 s per channel (min, at fosc = 8.38 MHz) * Built-in sample-and-hold function * Interrupt requested on completion of A/D conversion 187 10.1.2 Block Diagram Figure 10-1 shows a block diagram of the A/D converter. PMR0 (8b) AMR (4b) Port P01/AN1 Port P02/AN2 Port P03/AN3 Port P04/AN4 Port P05/AN5 Port P06/AN6 Port P07/AN7 Port MPX ADSR Internal data bus P00/AN0 + Control logic AVCC Reference voltage Control circuitry (successive approximation, interrupt request, etc.) VREF - R255 R254 Chopper-type comparator R253 R252 R251 R1 AVSS Successive approximation finds the input voltage by changing a reference voltage (VREF ). ADRR RESET LPM (low-power mode) One of 256 switches is selected by binary search. The reference voltage value resulting from eight comparisons is set in ADDR. (The eighth value is equal to the analog input voltage.) The internal ladder resistance is 35 k to 40 k typ (approximately). Upon reset and in low-power operation modes (sleep, watch, subactive, or standby modes), the ladder resistance is disconnected from AVSS by a switching transistor. The AV CC current at this time is a leakage current Alcc of 1 A or less (approximate value). Notation: PMR0: Port mode register 0 AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register IRRAD: A/D conversion end interrupt request flag (interrupt request register 3) RESET: Signal set to 1 upon reset LPM: Signal set to 1 in low-power modes Figure 10-1 Block Diagram of A/D Converter 188 Interrupt 10.1.3 Pin Configuration Table 10-1 shows the A/D converter pin configuration. Table 10-1 Pin Configuration Name Abbrev. I/O Function Analog power supply pin AVCC Input Analog power supply and reference voltage Analog ground pin AVSS Input Analog ground and reference voltage Analog input pin 0 AN0 Input Analog input channel 0 Analog input pin 1 AN1 Input Analog input channel 1 Analog input pin 2 AN2 Input Analog input channel 2 Analog input pin 3 AN3 Input Analog input channel 3 Analog input pin 4 AN4 Input Analog input channel 4 Analog input pin 5 AN5 Input Analog input channel 5 Analog input pin 6 AN6 Input Analog input channel 6 Analog input pin 7 AN7 Input Analog input channel 7 10.1.4 Register Configuration Table 10-2 shows the A/D converter register configuration. Table 10-2 Register Configuration Name Abbrev. R/W Initial Value Address A/D mode register AMR R/W H'78 H'FFBC A/D start register ADSR R/W H'7F H'FFBE A/D result register ADRR R Not fixed H'FFBD Port mode register 0 PMR0 W H'00 H'FFEF 189 10.2 Register Descriptions 10.2.1 A/D Result Register (ADRR) Bit 7 6 5 4 3 2 1 0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value * * * * * * Read/Write R R R R R * R * R R Note: * Not fixed ADRR is an 8-bit read-only register for holding the result of analog-to-digital conversion. ADRR can be read by the CPU at any time, but the ADRR value during A/D conversion is not fixed. After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data is held in ADRR until the next conversion operation starts. ADRR is not cleared on reset. 10.2.2 A/D Mode Register (AMR) Bit 7 6 5 4 3 2 1 0 AMR7 -- -- -- -- AMR2 AMR1 AMR0 Initial value 0 1 1 1 1 0 0 0 Read/Write R/W -- -- -- -- R/W R/W R/W AMR is an 8-bit read/write register for selecting the A/D conversion speed and analog input pin. Writing to AMR should be done with the A/D start flag (ADSF) cleared to 0 in the A/D start register (ADSR). Upon reset, AMR is initialized to H'78. 190 Bit 7: Clock select (AMR7) Bit 7 sets the A/D conversion speed.*1 Bit 7 AMR7 Conversion Period*2 o = 2 MHz o = 4.19 MHz 0 62/o 31 s 14.8 s 15.5 s --*1 1 31/o (initial value) Notes: 1. Operation is not guaranteed if the conversion time is less than 14.8 s. Set bit 7 for a value of at least 14.8 s. 2. A/D conversion starts after a value of 1 is written to ADSF. The conversion period starts when the start flag is set and ends when it is reset upon completion of conversion. The actual time during which sample and hold are repeated is called the conversion interval (see figure 10-2). State Instruction execution MOV B. WRITE Start flag Conversion interval Conversion period (31 or 62 states) Interrupt request flag IRQ sampling (CPU) Note: IRQ sampling: When conversion is complete, the start flag is reset and the interrupt request flag is set. An interrupt is recognized by the CPU in the last instruction execution state, and interrupt exception handling is executed after that instruction is completed. Figure 10-2 Internal Operation of A/D Converter 191 Bits 6 to 3: Reserved bits Bits 6 to 3 are reserved; they are always read as 1, and cannot be modified. Bits 2 to 0: Channel select (AMR2 to AMR0) Bits 2 to 0 select the analog input channel. Settings are also required in port mode register 0 (PMR0). See 10.2.4, Port Mode Register 0 (PMR0). Bit 2 AMR2 Bit 1 AMR1 Bit 0 AMR0 Analog Input Channel 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 (initial value) 192 10.2.3 A/D Start Register (ADSR) Bit 7 6 5 4 3 2 1 0 ADSF -- -- -- -- -- -- -- Initial value 0 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D conversion. A/D conversion is started by writing 1 to the A/D start flag (ADSF). When conversion is complete, the converted data is set in the A/D result register (ADRR), and at the same time ADSF is cleared to 0. Bit 7: A/D start flag (ADSF) Bit 7 is for controlling and confirming the start and end of A/D conversion. Bit 7 ADSF 0 Description [Read access] Indicates that A/D conversion has been completed or stopped. [Write access] Stops A/D conversion. 1 [Read access] Indicates A/D conversion in progress. [Write access] Starts A/D conversion. Bits 6 to 0: Reserved bits Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 193 (initial value) 10.2.4 Port Mode Register 0 (PMR0) Bit 7 6 5 4 3 2 1 0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PMR0 is an 8-bit write-only register for designating whether each of the port 0 pins is used as a general-purpose input pin or as an analog input channel to the A/D converter. Designation is made separately for each pin. Upon reset, PMR0 is initialized to H'00. Bit n ANn Description 0 Pin P0n/ANn is used for general-purpose input. 1 Pin P0n/ANn is an analog input channel. (initial value) (n = 0 to 7) 10.3 Operation The A/D converter operates by successive approximations, and yields its conversion result as 8-bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 3 (IRR3) to 1. An A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 3 (IENR3) is set to 1. If the conversion time or input channel needs to be changed in the A/D mode register (AMR) during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation, in order to avoid misoperation. 10.4 Interrupts When A/D conversion is complete (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 3 (IRR3) is set to 1. A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 3 (IENR3). For further details see 3.2.2, Interrupts. 194 10.5 Typical Use An example of how the A/D converter can be used is given below, using channel 1 (AN1) as the analog input channel. Figure 13-3 shows the operation timing for this example. 1. Bits AMR2 to AMR0 of the A/D mode register (AMR) are set to 001, and bits AN7 to AN0 of port mode register 0 (PMR0) are set to 00000010, making AN1 the analog input channel. The interrupt request is cleared by setting bit IRRAD to 0, A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. 2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion results are sent to the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the A/D converter goes to the idle state. 3. Bit IENAD = 1, so an A/D conversion end interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The A/D conversion result is read and processed. 6. The A/D interrupt handling routine ends. If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 10-4 and 10-5 show flow charts of procedures for using the A/D converter. 195 Figure 10-3 Typical A/D Converter Operation Timing 196 Idle A/D conversion starts A/D conversion 1 Set* Set* Idle A/D conversion result 1 Conversion result read* Note: * ( ) indicates instruction execution by software. ADRR Channel 1 (AN 1 ) operation states ADSF IENAD Interrupt A/D conversion result 2 Conversion result read * Idle When the next A/D conversion starts, the previous result is lost. A/D conversion 2 Set* Reset* START Set A/D conversion speed and input channels Disable A/D conversion end interrupt Start A/D conversion Read ADSR No ADSF = 0? Yes Read ADRR data Yes Perform A/D conversion? No END Figure 10-4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software) 197 START Set A/D converter speed and input channels Clear A/D conversion end interrupt request Enable A/D conversion end interrupt Start A/D conversion Yes A/D conversion end interrupt? No Clear bit IRRAD to 0 in IRRS Read ADRR data Yes Perform A/D conversion? No END Figure 10-5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used) 198 10.6 Application Notes 1. Data in the A/D result register (ADRR) should be read only when the A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0. 2. Changing a digital input signal at a nearby pin during A/D conversion may adversely affect conversion accuracy. 3. The pin selected as an analog input channel in the A/D mode register (AMR) must also be designated as an analog input channel in port mode register 0 (PMR0). 199 Section 11 RAM 11.1 Overview The H8/3612 has 512 bytes of high-speed static RAM on-chip. The H8/3613 and H8/3614 have 1024 bytes. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. 11.1.1 Block Diagram Figure 11-1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FB80 H'FB82 H'FF7E H'FB80 H'FB82 H'FB81 H'FB83 H'FF7E H'FF7F Even-numbered addresses Odd-numbered addresses Figure 11-1 RAM Block Diagram (H8/3614) 201 Section 12 ROM 12.1 Overview The H8/3612 has 16 kbytes of on-chip mask ROM. The H8/3613 has 24 kbytes. The H8/3614 has 32 kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. ZTATTM versions of the H8/3614 have 32 kbytes of PROM. 12.1.1 Block Diagram Figure 12-1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0002 H'0000 H'0002 H'0001 H'0003 * * Even-numbered addresses Odd-numbered addresses Note: * The last address differs as follows depending on the ROM size. Even-Numbered Address Odd-Numbered Address H8/3612 H'3FFE H'3FFF H8/3613 H'5FFE H'5FFF H8/3614 H'7DFE H'7DFF Figure 12-1 ROM Block Diagram 203 12.2 PROM Mode 12.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operations as a microcontroller and allows the PROM to be programmed in the same way as the HN27C256H. Table 12-1 shows how to select PROM mode. Table 12-1 Selection of PROM Mode Pin Name Abbrev. Setting Test pin TEST High level Mode pin MD0 (P40) Low level Mode pin MD1 (P41) Mode pin MD2 (P17) High level 12.2.2 Socket Adapter Pin Arrangement and Memory Map A standard PROM programmer can be used to program the PROM. A socket adapter is required for conversion to 28 pins, as listed in table 12-2. Figure 12-2 shows the pin-to-pin wiring of the socket adapter. Figure 12-3 shows a memory map. Table 12-2 Socket Adapter Package Socket Adapter 64-pin QFP (FP-64A) HS3614ESH01H 64-pin SDIP (DP-64S) HS3614ESS01H 204 H8/3614 FP-64A 10 42 43 44 45 46 47 48 49 26 25 24 23 22 21 20 19 50 17 52 53 54 55 56 57 51 29 30 18 31 32 33, 58 7, 3 4, 6 8 DP-64S 18 50 51 52 53 54 55 56 57 34 33 32 31 30 29 28 27 58 25 60 61 62 63 64 1 59 37 38 26 39 40 41, 2 15, 11 12, 14 16 EPROM Socket Pin Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 RES P90 P91 P92 P93 P94 P95 P96 P97 P20 P21 P22 P23 P24 P25 P26 P27 PA0 P16 PA2 PA3 PA4 PA5 PA6 PA7 PA1 P43 P42 P17 P41 P40 VCC, AVCC VSS, AVSS TEST, X1 OSC1 CEN OEN VCC VCC VCC VSS VSS VCC VSS VCC VSS Note: Pins not indicated above should be left open. Figure 12-2 Socket Adapter Pin Correspondence 205 HN27C256H 1 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 28 28 28 14 14 28 14 28 14 Address in MCU mode Address in PROM mode H'0000 H'0000 On-chip ROM H'7DFF H'7DFF Figure 12-3 Memory Map in PROM Mode 206 12.3 Programming The write, verify, and other sub-modes of PROM mode are selected as shown in table 12-3. Table 12-3 Sub-Mode Selection in PROM Mode Pin Mode CE OE VPP VCC EO7 to EO0 EA14 to EA0 Write L H VPP VCC Data input Address input Verify H L VPP VCC Data output Address input Programming disabled H H VPP VCC High impedance Address input Notation: L: Low level H: High level VPP: VPP level VCC: VCC level The specifications for writing and reading the on-chip PROM are identical to those for the standard HN27C256H EPROM. 12.3.1 Writing and Verifying An efficient, high-speed programming method is provided for writing and verifying the PROM data. This method achieves high speed without voltage stress on the device and without lowering the reliability of written data. H'FF data is written in unused address areas. The basic flow of this high-speed programming method is shown in figure 12-4. Table 12-4 and table 12-5 give the electrical characteristics in programming mode. Figure 12-5 shows a write/verify timing diagram. 207 Start Select write or verify mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0 n=0 n + 1 n Yes No Write with t PW = 1 ms 5% n < 25 No Go Address + 1 address Verify Go Write with t OPW = 3n ms Last address? No Yes Select read mode VCC = 5.0 V 0.5 V, VPP = VCC 0.6 V Error No Go Read all addresses Go End Figure 12-4 High-Speed Programming Flowchart 208 Table 12-4 DC Characteristics (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Typ Max Test Unit Conditions Input highlevel voltage EA14 to EA0, EO7 to EO0, VIH OE, CE 2.4 -- VCC + 0.3 V Input lowlevel voltage EA14 to EA0, EO7 to EO0, VIL OE, CE -0.3 -- 0.8 V Output highlevel voltage EO7 to EO0 VOH 2.4 -- -- V IOH = -200 A Output lowlevel voltage EO7 to EO0 VOL -- -- 0.45 V IOL = 1.6 mA Input leakage EO7 to EO0, EA14 to EA0, |ILI| current OE, CE -- -- 2 A VIN = 5.25 V/0.5 V VCC current ICC -- -- 40 mA VPP current IPP -- -- 40 mA Table 12-5 AC Characteristics (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0.0 V, Ta = 25C 5C) Item Symbol Min Typ Max Unit Test Conditions Address setup time tAS 2 -- -- s Figure 12-5* OE setup time tOES 2 -- -- s Data setup time tDS 2 -- -- s Address hold time tAH 0 -- -- s Data hold time tDH 2 -- -- s Data output disable time tDF 0 -- 130 ns VPP setup time tVPS 2 -- -- s Programming pulse width tPW 0.95 1.0 1.05 ms CE pulse width for overwrite programming tOPW 2.85 -- 78.75 ms VCC setup time tVCS 2 -- -- s Data output delay time tOE 0 -- 500 ns Notes: * Input pulse level: 0.8 to 2.2 V Input rise time/fall time 20 ns Timing reference levels Input: 1.0 V, 2.0 V Output: 0.8 V, 2.0 V 209 Write Verify Address t AS Data t AH Input data t DS VPP VCC Output data t DH t DF VPP VCC t VPS VCC GND t VCS CE t PW OE t OES t OE t OPW Figure 12-5 PROM Write/Verify Timing 12.3.2 Precautions When Writing 1. Use the specified programming voltage and timing. The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C256H or to Intel specifications will result in a correct VPP of 12.5 V. 2. Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before programming, be sure the chip is properly mounted in the PROM programmer. 3. Avoid touching the socket adapter or chip during programming, since this may cause contact faults and write errors. 210 12.3.3 Reliability of Written Data An effective way to assure the data holding characteristics of the programmed chips is to bake them at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early data retention failure. Figure 12-6 shows a flowchart of this screening procedure. Write program and verify written data Bake chips with power off 150C 10C, 48 Hr +8 Hr * -0 Hr Read and check program V CC = 4.5 V, 5.5 V Install Note: * Baking time is measured from when the oven reaches 150C. Figure 12-6 Recommended Screening Procedure If write errors occur repeatedly while the same PROM programmer is being used, stop programming and check for problems in the PROM programmer and socket adapter, etc. Please notify your Hitachi representative of any problems occurring during programming or in screening after high-temperature baking. 211 Section 13 Electrical Specifications 13.1 Absolute Maximum Ratings Table 13-1 gives the absolute maximum ratings for the H8/3614 Series. Table 13-1 Absolute Maximum Ratings (Provisional Values) Item Symbol Rating Unit Notes Supply voltage VCC -0.3 to +7.0 V 1, 2 Programming voltage VPP -0.3 to +14.0 V 1, 2, 3 Analog supply voltage AVCC -0.3 to +7.0 V 1, 2 Analog input voltage AVIN -0.3 to AVCC +0.3 V 1, 2 Pin voltage VT -0.3 to VCC +0.3 V 1, 2 Operating temperature Top -20 to +75 C 1, 2 Storage temperature Tstg -55 to +125 C 1, 2 Notes: 1. Operation in excess of these absolute maximum ratings may result in permanent damage to the LSI. Normally the LSI should be operated within the conditions given under electrical characteristics on the following pages, so as to avoid malfunction and assure maximum reliability. 2. All voltages are based on VSS as a reference voltage. 3. Applies to the ZTATTM version. 213 13.2 HD6473614 Electrical Characteristics 13.2.1 HD6473614 DC Characteristics Table 13-2 gives the allowable current values of the HD6473614. Table 13-3 gives the DC characteristics. Table 13-2 Allowable Output Current Values Conditions: VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Symbol Rating Unit Notes Allowable input current (into LSI) IO 2 mA 1, 2 Allowable output current (from LSI) -IO 2 mA 2, 3 Allowable output current (from LSI) -IO 20 mA 3, 4 Total allowable input current (into LSI) IO 50 mA 5 Total allowable output current (from LSI) -IO 150 mA 6 Notes: 1. Allowable input current means the maximum current that can flow from each I/O pin to VSS. 2. Applies to standard pins. 3. Allowable output current means the maximum current that can flow from VCC to each I/O pin. 4. Applies to PMOS open-drain pins. 5. Total allowable input current means the sum of current that can flow at one time from all I/O pins to VSS. 6. Total allowable output current means the sum of current that can flow from VCC to all I/O pins. 214 Table 13-3 DC Characteristics Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Input high voltage Applicable Symbol Pins VIH Rating Min Typ Max Unit 0.8 VCC -- VCC +0.3 V VCC = 2.7 to 5.5 V 0.9 VCC incl. subactive mode -- VCC +0.3 0.7 VCC VCC = 2.7 to 5.5 V incl. subactive mode -- VCC +0.3 V VCC -0.5 -- VCC +0.3 V VCC = 2.7 to 5.5 V VCC -0.3 -- incl. subactive mode VCC +0.3 P00 to P07 P10 to P17 P20 to P27 P80 to P87 P90 to P97 PA0 to PA7 VCC = 2.7 to 5.5 V 0.7 VCC incl. subactive mode -- VCC +0.3 V P40 to P45 VCC = 2.7 to 5.5 V 0.7 VCC incl. subactive mode -- VCC +0.3 V -0.3 -- 0.2 VCC V VCC = 2.7 to 5.5 V -0.3 incl. subactive mode -- 0.1 VCC VCC = 2.7 to 5.5 V -0.3 incl. subactive mode -- 0.3 VCC V -0.3 -- 0.5 V VCC = 2.7 to 5.5 V -0.3 incl. subactive mode -- 0.3 P01 to P07 P10 to P17 P20 to P27 P80 to P87 P90 to P97 PA0 to PA7 VCC = 2.7 to 5.5 V -0.3 incl. subactive mode -- 0.3 VCC V P40 to P45 VCC = 2.7 to 5.5 V -0.3 incl. subactive mode -- 0.3 VCC V RES IRQ0 to IRQ5 SCK1, SCK2 SI1, SI2 EVENT, UD Test Conditions OSC1 Input low voltage VIL RES SCK1, SCK2 IRQ0 to IRQ5 SI1, SI2 EVENT, UD OSC1 Note: Connect the TEST pin to VSS. 215 Notes Table 13-3 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Applicable Symbol Pins Output high VOH voltage Output low VOL voltage Input leakage current | IIL | Rating Test Conditions Min P10 to P15 P20 to P27 P80 to P87 P90 to P97 PWM SO1, SO2 SCK1, SCK2 PA0 to PA7 -IOH = 1.0 mA P40 to P45 P10 to P15 P20 to P27 P80 to P87 P90 to P97 PWM SO1, SO2 SCK1, SCK2 PA0 to PA7 RES Max Unit VCC -1.0 -- -- V -IOH = 0.5 mA VCC -0.5 -- -- VCC = 2.7 to 5.5 V -IOH = 0.3 mA VCC -0.5 -- -- -IOH = 15 mA VCC -3.0 -- -- -IOH = 10 mA VCC -2.0 -- -- -IOH = 4 mA VCC -1.0 -- -- VCC = 2.7 to 5.5 V -IOH = 4 mA -- VCC -1.0 -- V VCC = 4.0 to 5.5 V IOL = 1.6 mA -- -- 0.4 V VCC = 2.7 to 5.5 V IOL = 0.5 mA -- 0.4 -- V 40 A VIN = 0 to VCC 216 Typ Notes V Reference value Reference value Table 13-3 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Applicable Symbol Pins I/O leakage | IIL | current Input capacitance CIN Rating Test Conditions Min TEST SCK1, SCK2 SI1, SI2 IRQ0 to IRQ5 EVENT, UD OSC1 P00 to P07 P10 to P16 P20 to P27 P80 to P87 P90 to P97 PA0 to PA7 VIN = 0 to VCC -- P40 to P45 P17 VIN = 0.0 to VCC Max Unit -- 1 A -- -- 2 A Input pins f = 1 MHz, VIN = 0 V and I/O pins Ta = 25C other than power source pin -- -- 20 pF P16/EVENT -- -- 35 RES -- -- 70 217 Typ Notes Table 13-3 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Rating Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Notes Current dissipation when CPU operating in active mode IOPE VCC VCC = 5 V, fOSC = 8 MHz -- 17 -- mA VCC = 5 V, fOSC = 4 MHz -- 9 -- Reference value 1 VCC = 3 V, fOSC = 4 MHz -- 6 -- VCC = 5 V, fOSC = 8 MHz -- 6 9 mA 1 VCC = 5 V, fOSC = 4 MHz -- 3 5 VCC = 3 V, fOSC = 4 MHz -- 1.5 -- VCC = 5 V, fOSC = 8 MHz -- 2.5 3.5 mA 1 VCC = 5 V, fOSC = 4 MHz -- 1.5 2.0 VCC = 3 V, fOSC = 4 MHz -- 1.0 -- VCC = 2.7 V 32 kHz crystal oscillator used -- 6 20 A -- 11 -- A 2 -- 16 -- A Reference value -- 22 -- A 2 -- 3.2 6 A -- 3.8 -- A 2 -- 10 -- A Reference value -- 12 -- A 2 -- -- 10 A Current dissipation during reset in active mode IRES Current ISLEEP dissipation in sleep mode Current ISUB dissipation in subactive mode VCC VCC VCC VCC = 5.0 V 32 kHz crystal oscillator used Current IWATCH dissipation in watch mode VCC VCC = 2.7 V 32 kHz crystal oscillator used VCC = 5.0 V 32 kHz crystal oscillator used Current dissipation in standby mode ISTBY VCC 32 kHz crystal oscillator not used X1 = VCC 218 Table 13-3 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Rating Item Symbol Applicable Pins Test Conditions Min Typ Max Unit RAM data retention voltage in standby mode VSTBY VCC 2 -- -- V 32 kHz crystal oscillator not used X1 = VCC Notes Notes: 1. Does not include current flowing to output buffer. 2. Reference value when 47 F bypass capacitor is connected between VCC and VSS. 219 13.2.2 HD6473614 AC Characteristics Table 13-4 gives the control signal timing of the HD6473614. Table 13-5 gives the serial interface timing. Table 13-4 Control Signal Timing Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Symbol Clock pulse generator frequency fOSC Clock cycle time tCYC Applicable Pins Test Conditions OSC1, OSC2, VCC = 2.7 to 5.5 V OSC1, OSC2 VCC = 2.7 to 5.5 V Rating Min Typ Max Unit 2 -- 8.4 MHz 2 -- 4.2 119 -- 500 238 -- 500 238 -- 1000 1000 ns Instruction cycle time o VCC = 2.7 to 5.5 V 476 -- Subclock pulse generator frequency fx X1, X2 VCC = 2.7 to 5.5 V -- 32.768 -- kHz Subclock cycle time tsubcyc X1, X2 VCC = 2.7 to 5.5 V -- 30.5 -- s Subactive instruction cycle time oSUB VCC = 2.7 to 5.5 V -- 244.14 -- s Oscillator settling time (crystal oscillator) trc -- -- 40 ms -- -- 60 Oscillator settling time (ceramic oscillator) trc Oscillator settling time VCC = 2.7 to 5.5 V OSC1, OSC2 -- -- 20 VCC = 2.7 to 5.5 V -- -- 40 trc X1, X2 VCC = 2.7 to 5.5 V -- -- 2 s External clock pulse width (high) tCPH OSC1 40 -- -- ns External clock pulse width (low) tCPL OSC1 External clock rise time tCPr OSC1 External clock fall time tCPf OSC1 VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V 220 100 -- -- 40 -- -- 100 -- -- -- -- 20 -- -- 20 -- -- 20 -- -- 20 Figure 13-1 ns OSC1, OSC2 VCC = 2.7 to 5.5 V Reference Diagram ms ns ns ns Figure 13-1 Table 13-4 Control Signal Timing (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Rating Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Reference Diagram RES pin pulse width (low) tREL RES VCC = 2.7 to 5.5 V 10 -- -- o Figure 13-2 IRQ pin pulse width (high) tIH IRQ0 to IRQ5 VCC = 2.7 to 5.5 V 2 -- -- o oSUB Figure 13-3 IRQ pin pulse width (low) tIL IRQ0 to IRQ5 VCC = 2.7 to 5.5 V 2 -- -- o oSUB EVENT pin pulse width (high) tEVH EVENT VCC = 2.7 to 5.5 V 2 -- -- o EVENT pin pulse width (low) tEVL EVENT VCC = 2.7 to 5.5 V 2 -- -- o UD pin minimum change width tUDH tUDL UD VCC = 2.7 to 5.5 V 2 -- -- o Figure 13-4 Figure 13-5 Table 13-5 Serial Interface Timing Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Applicable Pins Test Conditions Item Symbol Output transfer clock cycle time tscyc SCK1, SCK2 Output transfer clock pulse width (high) tSCKH Output transfer clock pulse width (low) Rating Min Typ Max Unit VCC = 2.7 to 5.5 V 2 -- -- o SCK1, SCK2 VCC = 2.7 to 5.5 V 0.4 -- -- tscyc tSCKL SCK1, SCK2 VCC = 2.7 to 5.5 V 0.4 -- -- tscyc Output transfer clock rise time tSCKr SCK1, SCK2 -- -- 60 ns VCC = 2.7 to 5.5 V -- -- 80 Output transfer clock fall time tSCKf SCK1, SCK2 -- -- 60 VCC = 2.7 to 5.5 V -- -- 80 Input transfer clock cycle time tscyc SCK1, SCK2 VCC = 2.7 to 5.5 V 1 -- -- o Input transfer clock pulse width (high) tSCKH SCK1, SCK2 VCC = 2.7 to 5.5 V 0.4 -- -- tscyc 221 ns Reference Diagram Figure 13-6 Table 13-5 Serial Interface Timing (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Applicable Pins Test Conditions Item Symbol Input transfer clock pulse width (low) tSCKL SCK1, SCK2 Input transfer clock rise time tSCKr SCK1, SCK2 Input transfer clock fall time tSCKf SCK1, SCK2 Serial output data delay time tdSO SO1, SO2 Serial input data setup time tsSI SI1, SI2 Serial input data hold time thSI SI1, SI2 Transfer hold time tSCK2 SCK2 Transfer end acknowledge time VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V tCS CS Rating Min Typ Max Unit 0.4 -- -- tscyc -- -- 60 ns -- -- 80 -- -- 60 -- -- 80 -- -- 200 -- -- 350 230 -- -- 470 -- -- 230 -- -- Figure 13-6 ns ns ns ns VCC = 2.7 to 5.5 V 470 -- -- When pin SCK2 is input pin 0.2 -- 40 When pin SCK2 is input pin VCC = 2.7 to 5.5 V 0.4 -- 40 When pin SCK2 is output pin VCC = 2.7 to 5.5 V -- -- 1 tscyc VCC = 2.7 to 5.5 V 3 -- 4 o 222 Reference Diagram s Figure 13-7 13.2.3 HD6473614 A/D Converter Characteristics Table 13-6 gives the HD6473614 A/D converter characteristics. Table 13-6 A/D Converter Characteristics Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Rating Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Analog supply voltage AVCC AVCC VCC -0.3 VCC VCC +0.3 V Analog input voltage AVIN AN0 to AN7 AVSS -- AVCC V AICC AVCC AVCC = 5 V -- -- 200 A Reset and powerdown mode -- -- 10 A Analog current Analog input capacitance AISTOP CAIN AN0 to AN7 -- -- 30 pF Allowable RAIN signal source impedance AN0 to AN7 -- -- 10 k Resolution Absolute precision -- -- 8 Bit VCC = AVCC = 5 V -- -- 2.5 LSB VCC = AVCC = 4.0 to 5.5 V -- 2.5 -- 31 15.5 14.8 Conversion time 223 Notes Reference value s 13.3 HD6433613 and HD6433614 Electrical Characteristics 13.3.1 HD6433613 and HD6433614 DC Characteristics Table 13-7 gives the allowable current values of the HD6433613 and HD6433614. Table 13-8 gives the DC characteristics. Table 13-7 Allowable Output Current Values Conditions: VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Symbol Rating Unit Notes Allowable input current (into LSI) IO 2 mA 1, 2 Allowable output current (from LSI) -IO 2 mA 2, 3 Allowable output current (from LSI) -IO 20 mA 3, 4 Total allowable input current (into LSI) IO 50 mA 5 Total allowable output current (from LSI) -IO 150 mA 6 Notes: 1. Allowable input current means the maximum current that can flow from each I/O pin to VSS. 2. Applies to standard pins. 3. Allowable output current means the maximum current that can flow from VCC to each I/O pin. 4. Applies to PMOS open-drain pins. 5. Total allowable input current means the sum of current that can flow at one time from all I/O pins to VSS. 6. Total allowable output current means the sum of current that can flow from VCC to all I/O pins. 224 Table 13-8 DC Characteristics Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Input high voltage Applicable Symbol Pins VIH Rating Min Typ Max Unit 0.8 VCC -- VCC +0.3 V VCC = 2.5 to 5.5 V 0.9 VCC incl. subactive mode -- VCC +0.3 0.7 VCC VCC = 2.5 to 5.5 V incl. subactive mode -- VCC +0.3 V VCC -0.5 -- VCC +0.3 V VCC = 2.5 to 5.5 V VCC -0.3 -- incl. subactive mode VCC +0.3 P00 to P07 P10 to P16 P20 to P27 P80 to P87 P90 to P97 PA0 to PA7 VCC = 2.5 to 5.5 V 0.7 VCC incl. subactive mode -- VCC +0.3 V P40 to P45 P17 VCC = 2.5 to 5.5 V 0.7 VCC incl. subactive mode -- VCC +0.3 V -0.3 -- 0.2 VCC V VCC = 2.5 to 5.5 V -0.3 incl. subactive mode -- 0.1 VCC VCC = 2.5 to 5.5 V -0.3 incl. subactive mode -- 0.3 VCC V -0.3 -- 0.5 V VCC = 2.5 to 5.5 V -0.3 incl. subactive mode -- 0.3 P00 to P07 P10 to P16 P20 to P27 P80 to P87 P90 to P97 PA0 to PA7 VCC = 2.5 to 5.5 V -0.3 incl. subactive mode -- 0.3 VCC V P40 to P45 P17 VCC = 2.5 to 5.5 V -0.3 incl. subactive mode -- 0.3 VCC V RES IRQ0 to IRQ5 SCK1, SCK2 SI1, SI2 EVENT, UD Test Conditions OSC1 Input low voltage VIL RES SCK1, SCK2 IRQ0 to IRQ5 SI1, SI2 EVENT, UD OSC1 Note: Connect the TEST pin to VSS. 225 Notes Table 13-8 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Applicable Symbol Pins Output high VOH voltage Output low VOL voltage Input leakage current | IIL | Rating Test Conditions Min P10 to P15 P20 to P27 P80 to P87 P90 to P97 PWM SO1, SO2 PA0 to PA7 -IOH = 1.0 mA P40 to P45 P10 to P15 P20 to P27 P80 to P87 P90 to P97 PWM SO1, SO2 PA0 to PA7 RES Max Unit VCC -1.0 -- -- V -IOH = 0.5 mA VCC -0.5 -- -- VCC = 2.7 to 5.5 V -IOH = 0.3 mA VCC -0.5 -- -- -IOH = 15 mA VCC -3.0 -- -- -IOH = 10 mA VCC -2.0 -- -- -IOH = 4 mA VCC -1.0 -- -- VCC = 2.7 to 5.5 V -IOH = 4 mA -- VCC -1.0 -- V VCC = 4.0 to 5.5 V IOL = 1.6 mA -- -- 0.4 V VCC = 2.7 to 5.5 V IOL = 0.5 mA -- 0.4 -- V Mask ROM version: VIN = 0 to VCC -- -- 1 A 226 Typ Notes V Reference value Reference value Table 13-8 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Applicable Symbol Pins I/O leakage | IIL | current Pull-up MOS current -Ip Input capacitance CIN Rating Test Conditions Min TEST SCK1, SCK2 SI1, SI2 IRQ0 to IRQ5 EVENT, UD OSC1 P00 to P07 P10 to P16 P20 to P27 P80 to P87 P90 to P97 PA0 to PA7 VIN = 0 to VCC -- P40 to P47 P17 VIN = 0 to VCC P10 to P16 P20 to P27 P80 to P87 P90 to P97 PA0 to PA7 Max Unit -- 1 A -- -- 2 A VCC = 5 V, VIN = 0 V 50 -- 300 A VCC = 2.7 V, VIN = 0 V -- 25 -- Input pins f = 1 MHz, VIN = 0 V other than Ta = 25C power source pin -- -- 15 P17 -- -- 30 227 Typ pF Notes Reference value Table 13-8 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Current dissipation when CPU operating in active mode Current dissipation during reset in active mode Applicable Symbol Pins IOPE IRES Current ISLEEP dissipation in sleep mode Current ISUB dissipation in subactive mode Current IWATCH dissipation in watch mode Current dissipation in standby mode ISTBY VCC VCC VCC VCC VCC VCC Rating Test Conditions Min VCC = 5 V, fOSC = 8 MHZ -- VCC = 5 V, fOSC = 4 MHz Max Unit Notes 15 -- mA -- 8 -- Reference value 1 VCC = 3 V, fOSC = 4 MHz -- 5 -- VCC = 5 V, fOSC = 8 MHz -- 5 8 mA 1 VCC = 5 V, fOSC = 4 MHz -- 2.5 4 VCC = 3 V, fOSC = 4 MHz -- 1.3 -- VCC = 5 V, fOSC = 8 MHz -- 2 3 mA 1 VCC = 5 V, fOSC = 4 MHz -- 1 1.5 VCC = 3 V, fOSC = 4 MHz -- 0.6 -- VCC = 2.5 V 32 kHz crystal oscillator used -- 5 20 A -- 9 -- A 2 VCC = 5.0 V 32 kHz crystal oscillator used -- 13 -- A Reference value -- 20 -- A 2 VCC = 2.5 V 32 kHz crystal oscillator used -- 2.2 5 A -- 2.8 -- A 2 VCC = 5.0 V 32 kHz crystal oscillator used -- 6 -- A Reference value -- 8 -- A 2 32 kHz crystal oscillator not used X1 = VCC -- -- 5 A 228 Typ Table 13-8 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item RAM data retention voltage in standby mode Applicable Symbol Pins VSTBY VCC Rating Test Conditions Min 32 kHz crystal oscillator not used X1 = VCC 2 Typ -- Max Unit -- V Notes Notes: 1. Does not include current flowing to pull-up MOS or output buffer. 2. Reference value when 47 F bypass capacitor is connected between VCC and VSS. 229 13.3.2 HD6433613 and HD6433614 AC Characteristics Table 13-9 gives the control signal timing of the HD6433613 and HD6433614. Table 13-10 gives the serial interface timing. Table 13-9 Control Signal Timing Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Symbol Clock pulse generator frequency fOSC Clock cycle time tCYC Applicable Pins Test Conditions OSC1, OSC2 VCC = 2.7 to 5.5 V OSC1, OSC2 VCC = 2.7 to 5.5 V Rating Min Typ Max Unit 2 -- 8.4 MHz 2 -- 4.2 119 -- 500 238 -- 500 238 -- 1000 1000 ns Instruction cycle time o VCC = 2.7 to 5.5 V 476 -- Subclock pulse generator frequency fx X1, X2 VCC = 2.5 to 5.5 V -- 32.768 -- kHz Subclock cycle time tsubcyc X1, X2 VCC = 2.5 to 5.5 V -- 30.5 -- s Subactive instruction cycle time oSUB VCC = 2.5 to 5.5 V -- 244.14 -- s Oscillator setting time (crystal oscillator) trc -- -- 40 ms -- -- 60 Oscillator setting time (ceramic oscillator) trc Oscillator settling time VCC = 2.7 to 5.5 V OSC1, OSC2 -- -- 20 VCC = 2.7 to 5.5 V -- -- 40 trc X1, X2 VCC = 2.7 to 5.5 V -- -- 2 s External clock pulse width (high) tCPH OSC1 40 -- -- ns External clock pulse width (low) tCPL OSC1 External clock rise time tCPr OSC1 External clock fall time tCPf OSC1 VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V 230 100 -- -- 40 -- -- 100 -- -- -- -- 20 -- -- 20 -- -- 20 -- -- 20 Figure 13-1 ns OSC1, OSC2 VCC = 2.7 to 5.5 V Reference Diagram ms ns ns ns Figure 13-1 Table 13-9 Control Signal Timing (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Rating Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Reference Diagram RES pin pulse width (low) tREL RES VCC = 2.7 to 5.5 V 10 -- -- o Figure 13-2 IRQ pin pulse width (high) tIH IRQ0 to IRQ5 VCC = 2.7 to 5.5 V 2 -- -- o oSUB Figure 13-3 IRQ pin pulse width (low) tIL IRQ0 to IRQ5 VCC = 2.7 to 5.5 V 2 -- -- o oSUB EVENT pin pulse width (high) tEVH EVENT VCC = 2.7 to 5.5 V 2 -- -- o EVENT pin pulse width (low) tEVL EVENT VCC = 2.7 to 5.5 V 2 -- -- o UD pin minimum change width tUDH tUDL UD VCC = 2.7 to 5.5 V 2 -- -- o Figure 13-4 Figure 13-5 Table 13-10 Serial Interface Timing Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Applicable Pins Test Conditions Item Symbol Output transfer clock cycle timing tscyc SCK1, SCK2 Output transfer clock pulse width (high) tSCKH Output transfer clock pulse width (low) Rating Min Typ Max Unit VCC = 2.7 to 5.5 V 2 -- -- o SCK1, SCK2 VCC = 2.7 to 5.5 V 0.4 -- -- tscyc tSCKL SCK1, SCK2 VCC = 2.7 to 5.5 V 0.4 -- -- tscyc Output transfer clock rise time tSCKr SCK1, SCK2 -- -- 60 ns VCC = 2.7 to 5.5 V -- -- 80 Output transfer clock fall time tSCKf SCK1, SCK2 -- -- 60 VCC = 2.7 to 5.5 V -- -- 80 Input transfer clock cycle timing tscyc SCK1, SCK2 VCC = 2.7 to 5.5 V 1 -- -- o Input transfer clock pulse width (high) tSCKH SCK1, SCK2 VCC = 2.7 to 5.5 V 0.4 -- -- tscyc 231 ns Reference Diagram Figure 13-6 Table 13-10 Serial Interface Timing (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Applicable Pins Test Conditions Item Symbol Input transfer clock pulse width (low) tSCKL SCK1, SCK2 Input transfer clock rise time tSCKr SCK1, SCK2 Input transfer clock fall time tSCKf SCK1, SCK2 Serial output data delay time tdSO SO1, SO2 Serial input data setup time tsSI SI1, SI2 Serial input data hold time thSI SI1, SI2 Transfer hold time tSCK2 SCK2 Transfer end acknowledge time VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V tCS CS Rating Min Typ Max Unit 0.4 -- -- tscyc -- -- 60 ns -- -- 80 -- -- 60 -- -- 80 -- -- 200 -- -- 350 230 -- -- 470 -- -- 230 -- -- Figure 13-6 ns ns ns ns VCC = 2.7 to 5.5 V 470 -- -- When pin SCK2 is input pin 0.2 -- 40 When pin SCK2 is input pin VCC = 2.7 to 5.5 V 0.4 -- 40 When pin SCK2 is output pin VCC = 2.7 to 5.5 V -- -- 1 tscyc VCC = 2.7 to 5.5 V 3 -- 4 o 232 Reference Diagram s Figure 13-7 13.3.3 HD6433613 and HD6433614 A/D Converter Characteristics Table 13-11 gives the HD6433613 and HD6433614 A/D converter characteristics. Table 13-11 A/D Converter Characteristics Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Rating Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Analog supply voltage AVCC AVCC VCC -0.3 VCC VCC +0.3 V Analog input voltage AVIN AN0 to AN7 AVSS -- AVCC V AICC AVCC AVCC = 5 V -- -- 200 A Reset and powerdown mode -- -- 10 A Analog current Analog input capacitance AISTOP CAIN AN0 to AN7 -- -- 30 pF Allowable RAIN signal source impedance AN0 to AN7 -- -- 10 k Resolution Absolute precision -- -- 8 Bit VCC = AVCC = 5 V -- -- 2.5 LSB VCC = AVCC = 4.0 to 5.5 V -- 2.5 -- 31 15.5 14.8 Conversion time 233 Notes Reference value S 13.4 HD6433612 Electrical Characteristics 13.4.1 HD6433612 DC Characteristics Table 13-12 gives the allowable output current values of the HD6433612. Table 13-13 gives the DC characteristics. Table 13-12 Allowable Output Current Values Conditions: VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Symbol Rating Unit Notes Allowable input current (into LSI) IO 2 mA 1, 2 Allowable output current (from LSI) -IO 2 mA 2, 3 Allowable output current (from LSI) -IO 20 mA 3, 4 Total allowable input current (into LSI) IO 50 mA 5 Total allowable output current (from LSI) -IO 150 mA 6 Notes: 1. Allowable input current means the maximum current that can flow from each I/O pin to VSS. 2. Applies to standard pins. 3. Allowable output current means the maximum current that can flow from VCC to each I/O pin. 4. Applies to PMOS open-drain pins. 5. Total allowable input current means the sum of current that can flow at one time from all I/O pins to VSS. 6. Total allowable output current means the sum of current that can flow from VCC to all I/O pins. 234 Table 13-13 DC Characteristics Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Input high voltage Applicable Symbol Pins VIH Rating Min Typ Max Unit 0.8 VCC -- VCC +0.3 V VCC = 2.5 to 5.5 V 0.9 VCC incl. subactive mode -- VCC +0.3 0.7 VCC VCC = 2.5 to 5.5 V incl. subactive mode -- VCC +0.3 V VCC -0.5 -- VCC +0.3 V VCC = 2.5 to 5.5 V VCC -0.3 -- incl. subactive mode VCC +0.3 P00 to P07 P10 to P16 P20 to P27 P80 to P87 P90 to P97 PA0 to PA7 VCC = 2.5 to 5.5 V 0.7 VCC incl. subactive mode -- VCC +0.3 V P40 to P45 P17 VCC = 2.5 to 5.5 V 0.7 VCC incl. subactive mode -- VCC +0.3 V -0.3 -- 0.2 VCC V VCC = 2.5 to 5.5 V -0.3 incl. subactive mode -- 0.1 VCC VCC = 2.5 to 5.5 V -0.3 incl. subactive mode -- 0.3 VCC V -0.3 -- 0.5 V VCC = 2.5 to 5.5 V -0.3 incl. subactive mode -- 0.3 P00 to P07 P10 to P16 P20 to P27 P80 to P87 P90 to P97 PA0 to PA7 VCC = 2.5 to 5.5 V -0.3 incl. subactive mode -- 0.3 VCC V P40 to P45 P17 VCC = 2.5 to 5.5 V -0.3 incl. subactive mode -- 0.3 VCC V RES IRQ0 to IRQ5 SCK1, SCK2 SI1, SI2 EVENT, UD Test Conditions OSC1 Input low voltage VIL RES SCK1, SCK2 IRQ0 to IRQ5 SI1, SI2 EVENT, UD OSC1 Note: Connect the TEST pin to VSS. 235 Notes Table 13-13 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Applicable Symbol Pins Output high VOH voltage Output low VOL voltage Input leakage current | IIL | Rating Test Conditions Min P10 to P15 P20 to P27 P80 to P87 P90 to P97 SO1, SO2 SCK1, SCK2 PA0 to PA7 -IOH = 1.0 mA P40 to P45 P10 to P15 P20 to P27 P80 to P87 P90 to P97 SO1, SO2 SCK1, SCK2 PA0 to PA7 RES Max Unit VCC -1.0 -- -- V -IOH = 0.5 mA VCC -0.5 -- -- VCC = 2.7 to 5.5 V -IOH = 0.3 mA VCC -0.5 -- -- -IOH = 15 mA VCC -3.0 -- -- -IOH = 10 mA VCC -2.0 -- -- -IOH = 4 mA VCC -1.0 -- -- VCC = 2.7 to 5.5 V -IOH = 4 mA -- VCC -1.0 -- V VCC = 4.0 to 5.5 V IOL = 1.6 mA -- -- 0.4 V VCC = 2.7 to 5.5 V IOL = 0.5 mA -- 0.4 -- V Mask ROM version: VIN = 0 to VCC -- -- 1 A 236 Typ Notes V Reference value Reference value Table 13-13 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Applicable Symbol Pins I/O leakage | IIL | current Pull-up MOS current -Ip Input capacitance CIN Rating Test Conditions Min TEST SCK1, SCK2 SI1, SI2 IRQ0 to IRQ5 EVENT, UD OSC1 P00 to P07 P10 to P16 P20 to P27 P80 to P87 P90 to P97 PA0 to PA7 VIN = 0.0 to VCC -- P40 to P45 P17 VIN = 0.0 to VCC P10 to P16 P20 to P27 P80 to P87 P90 to P97 PA0 to PA7 Max Unit -- 1 A -- -- 2 A VCC = 5 V, VIN = 0 V 50 -- 300 A VCC = 2.7 V, VIN = 0 V -- 25 -- Input pins f = 1 MHz, VIN = 0 V and I/O pins Ta = 25C other than power source pin -- -- 15 P17 -- -- 30 237 Typ Notes Reference value pF Table 13-13 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Current dissipation when CPU operating in active mode Current dissipation during reset in active mode Applicable Symbol Pins IOPE IRES Current ISLEEP dissipation in sleep mode Current ISUB dissipation in subactive mode Current IWATCH dissipation in watch mode Current dissipation in standby mode ISTBY VCC VCC VCC VCC VCC VCC Rating Test Conditions Min VCC = 5 V, fOSC = 8 MHz -- VCC = 5 V, fOSC = 4 MHz Max Unit Notes 15 -- mA -- 8 -- Reference value 1 VCC = 3 V, fOSC = 4 MHz -- 5 -- VCC = 5 V, fOSC = 8 MHz -- 5 8 mA 1 VCC = 5 V, fOSC = 4 MHz -- 2.5 4 VCC = 3 V, fOSC = 4 MHz -- 1.3 -- VCC = 5 V, fOSC = 8 MHz -- 2 3 mA 1 VCC = 5 V, fOSC = 4 MHz -- 1 1.5 VCC = 3 V, fOSC = 4 MHz -- 0.6 -- VCC = 2.5 V 32 kHz crystal oscillator used -- 5 20 A -- 9 -- A 2 VCC = 5.0 V 32 kHz crystal oscillator used -- 13 -- A Reference value -- 20 -- A 2 VCC = 2.5 V 32 kHz crystal oscillator used -- 2.2 5 A -- 2.8 -- A 2 VCC = 5.0 V 32 kHz crystal oscillator used -- 6 -- A Reference value -- 8 -- A 2 32 kHz crystal oscillator not used X1 = VCC -- -- 5 A 238 Typ Table 13-13 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item RAM data retention voltage in standby mode Applicable Symbol Pins VSTBY VCC Rating Test Conditions Min 32 kHz crystal oscillator not used X1 = VCC 2 Typ -- Max Unit -- V Notes Notes: 1. Does not include current flowing to pull-up MOS or output buffer. 2. Reference value when 47 F bypass capacitor is connected between VCC and VSS. 239 13.4.2 HD6433612 AC Characteristics Table 13-14 gives the control signal timing of the HD6433612. Table 13-15 gives the serial interface timing. Table 13-14 Control Signal Timing Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Item Symbol Clock pulse generator frequency fOSC Clock cycle time tCYC Applicable Pins Test Conditions OSC1, OSC2 VCC = 2.7 to 5.5 V OSC1, OSC2 VCC = 2.7 to 5.5 V Rating Min Typ Max Unit 2 -- 8.4 MHz 2 -- 4.2 119 -- 500 238 -- 500 238 -- 1000 1000 ns Instruction cycle time o VCC = 2.7 to 5.5 V 476 -- Subclock pulse generator frequency fx X1, X2 VCC = 2.5 to 5.5 V -- 32.768 -- kHz Subclock cycle time tsubcyc X1, X2 VCC = 2.5 to 5.5 V -- 30.5 -- s Subactive instruction cycle time oSUB VCC = 2.5 to 5.5 V -- 244.14 -- s Oscillator setting time (crystal oscillator) trc -- -- 40 ms -- -- 60 Oscillator setting time (ceramic oscillator) trc Oscillator settling time VCC = 2.7 to 5.5 V OSC1, OSC2 -- -- 20 VCC = 2.7 to 5.5 V -- -- 40 trc X1, X2 VCC = 2.7 to 5.5 V -- -- 2 s External clock pulse width (high) tCPH OSC1 40 -- -- ns External clock pulse width (low) tCPL OSC1 External clock rise time tCPr OSC1 External clock fall time tCPf OSC1 VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V 240 100 -- -- 40 -- -- 100 -- -- -- -- 20 -- -- 20 -- -- 20 -- -- 20 Figure 13-1 ns OSC1, OSC2 VCC = 2.7 to 5.5 V Reference Diagram ms ns ns ns Figure 13-1 Table 13-14 Control Signal Timing (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Rating Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Reference Diagram RES pin pulse width (low) tREL RES VCC = 2.7 to 5.5 V 10 -- -- o Figure 13-2 IRQ pin pulse width (high) tIH IRQ0 to IRQ5 VCC = 2.7 to 5.5 V 2 -- -- o oSUB Figure 13-3 IRQ pin pulse width (low) tIL IRQ0 to IRQ5 VCC = 2.7 to 5.5 V 2 -- -- o oSUB EVENT pin pulse width (high) tEVH EVENT VCC = 2.7 to 5.5 V 2 -- -- o EVENT pin pulse width (low) tEVL EVENT VCC = 2.7 to 5.5 V 2 -- -- o UD pin minimum change width tUDH tUDL UD VCC = 2.7 to 5.5 V 2 -- -- o Figure 13-4 Figure 13-5 Table 13-15 Serial Interface Timing Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Applicable Pins Test Conditions Item Symbol Output transfer clock cycle timing tscyc SCK1, SCK2 Output transfer clock pulse width (high) tSCKH Output transfer clock pulse width (low) Rating Min Typ Max Unit VCC = 2.7 to 5.5 V 2 -- -- o SCK1, SCK2 VCC = 2.7 to 5.5 V 0.4 -- -- tscyc tSCKL SCK1, SCK2 VCC = 2.7 to 5.5 V 0.4 -- -- tscyc Output transfer clock rise time tSCKr SCK1, SCK2 -- -- 60 ns VCC = 2.7 to 5.5 V -- -- 80 Output transfer clock fall time tSCKf SCK1, SCK2 -- -- 60 VCC = 2.7 to 5.5 V -- -- 80 Input transfer clock cycle timing tscyc SCK1, SCK2 VCC = 2.7 to 5.5 V 1 -- -- o Input transfer clock pulse width (high) tSCKH SCK1, SCK2 VCC = 2.7 to 5.5 V 0.4 -- -- tscyc 241 ns Reference Diagram Figure 13-6 Table 13-15 Serial Interface Timing (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Applicable Pins Test Conditions Item Symbol Input transfer clock pulse width (low) tSCKL SCK1, SCK2 Input transfer clock rise time tSCKr SCK1, SCK2 Input transfer clock fall time tSCKf SCK1, SCK2 Serial output data delay time tdSO SO1, SO2 Serial input data setup time tsSI SI1, SI2 Serial input data hold time thSI SI1, SI2 Transfer hold time tSCK2 SCK2 Transfer end acknowledge time VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V tCS CS Rating Min Typ Max Unit 0.4 -- -- tscyc -- -- 60 ns -- -- 80 -- -- 60 -- -- 80 -- -- 200 -- -- 350 230 -- -- 470 -- -- 230 -- -- Figure 13-6 ns ns ns ns VCC = 2.7 to 5.5 V 470 -- -- When pin SCK2 is input pin 0.2 -- 40 When pin SCK2 is input pin VCC = 2.7 to 5.5 V 0.4 -- 40 When pin SCK2 is output pin VCC = 2.7 to 5.5 V -- -- 1 tscyc VCC = 2.7 to 5.5 V 3 -- 4 o 242 Reference Diagram s Figure 13-7 13.4.3 HD6433612 A/D Converter Characteristics Table 13-16 gives the HD6433612 A/D converter characteristics. Table 13-16 A/D Converter Characteristics Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C Rating Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Analog supply voltage AVCC AVCC VCC -0.3 VCC VCC +0.3 V Analog input voltage AVIN AN0 to AN7 AVSS -- AVCC V AICC AVCC AVCC = 5 V -- -- 200 A Reset and powerdown mode -- -- 10 A Analog current Analog input capacitance AISTOP CAIN AN0 to AN7 -- -- 30 pF Allowable RAIN signal source impedance AN0 to AN7 -- -- 10 k Resolution Absolute precision -- -- 8 Bit VCC = AVCC = 5 V -- -- 2.5 LSB VCC = AVCC = 4.0 to 5.5 V -- 2.5 -- 31 15.5 14.8 Conversion time 243 Notes Reference value S 13.5 Operational Timing This section provides the following timing diagrams (figures 13-1 to 13-8). o tcyc OSC1 VIH VIL tCPH tCPL tCPf tCPr Figure 13-1 System Clock Input Timing RES VIL tREL Figure 13-2 IRQ0 to IRQ5 RES Pin Pulse Width (low) VIH VIL tIL Figure 13-3 EVENT tIH IRQ Pin Input Timing VIH VIL tEVL Figure 13-4 tEVH EVENT Pin Minimum Pulse Width 244 VIH UD VIL tUDH tUDL Figure 13-5 UD Pin Minimum Change Width tscyc SCK1 SCK2 VIH or VOH* VIL or VOL* tSCKf tSCKH tSCKL tdso tSCKr SO1 VOH* SO2 VOL* tssi SI1 SI2 Note: * Output timing reference levels: Output high level: VOH: 2.0 V Output low level: VOL: 0.8 V See figure 13-8 for the output load conditions. Figure 13-6 SCI I/O Timing 245 thsi VOH* CS VOL* tSCK2 SCK2 tCS VIH or VOH* VIL or VOL* Note: * Output timing reference levels: Output high level: VOH: 2.0 V Output low level: VOL: 0.8 V See figure 13-8 for the output load conditions. Figure 13-7 Serial Communication Interface 2 Chip Select Timing VCC 2.4 k LSI output pin 30 pF 12 k Figure 13-8 Output Load Conditions 246 13.6 Differences in Electrical Characteristics between Mask ROM and ZTATTM Versions Table 13-17 shows the difference in electrical characteristics between the HD6473614 and HD6433612/HD6433613/HD6433614. Table 13-17 Differences in Electrical Characteristics between Mask ROM and ZTATTM Versions Item Mask ROM Version ZTATTM Version Min Typ Max Min Typ Max Unit Operation range in subactive mode VCC 2.5 -- 5.5 2.7 -- 5.5 V Input leakage IIL current RES -- -- 1 -- -- 40 A Input capacitance P16/EVENT -- -- 15 -- -- 35 pF Current dissipation when CPU operating in active mode Current dissipation during reset in active mode Current dissipation in sleep mode Symbol Applicable Pins CIN IOPE IRES ISLEEP Test Conditions P17 -- -- 30 -- -- 20 RES -- -- 15 -- -- 70 VCC = 5 V, fOSC = 8 MHz -- 15 -- -- 17 -- VCC = 5 V, fOSC = 4 MHz -- 8 -- -- 9 -- VCC = 3 V, fOSC = 4 MHz -- 5 -- -- 6 -- VCC = 5 V, fOSC = 8 MHz -- 5 8 -- 6 9 VCC = 5 V, fOSC = 4 MHz -- 2.5 4 -- 3 5 VCC = 3 V, fOSC = 4 MHz -- 1.3 -- -- 1.5 -- VCC = 5 V, fOSC = 8 MHz -- 2 3 -- 2.5 3.5 VCC = 5 V, fOSC = 4 MHz -- 1 1.5 -- 1.5 2 VCC = 3 V, fOSC = 4 MHz -- 0.6 -- -- 1 -- VCC VCC VCC 247 mA mA Table 13-17 Differences in Electrical Characteristics between Mask ROM and ZTATTM Versions (cont) Item Symbol Applicable Pins Current dissipation in subactive mode ISUB VCC Current dissipation in watch mode Current dissipation in standby mode IWATCH ISTBY VCC Mask ROM Version ZTATTM Version Test Conditions Min Typ Max VCC = 2.5 V (no bypass capacitor) -- 5 20 VCC = 2.5 V (47 F bypass capacitor) -- 9 -- Min Typ Max Unit A VCC = 2.7 V (no bypass capacitor) -- 6 20 VCC = 2.7 V (47 F bypass capacitor) -- 11 -- VCC = 5 V (no bypass capacitor) -- 13 -- -- 16 -- VCC = 5 V (47 F bypass capacitor) -- 20 -- -- 22 -- VCC = 2.5 V (no bypass capacitor) -- 2.2 5 VCC = 2.5 V (47 F bypass capacitor) -- 2.8 -- A VCC = 2.7 V (no bypass capacitor) -- 3.2 6 VCC = 2.7 V (47 F bypass capacitor) -- 3.8 -- VCC = 5 V (no bypass capacitor) -- 6 -- -- 10 -- VCC = 5 V (47 F bypass capacitor) -- 8 -- -- 12 -- -- -- 5 -- -- 10 VCC 248 A Appendix A CPU Instruction Set A.1 Instruction Set List Operation Notation Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) CCR Condition code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #xx:3/8/16 Immediate data (3, 8, or 16 bits) d:8/16 Displacement (8 or 16 bits) @aa:8/16 Absolute address (8 or 16 bits) + Addition - Subtraction x Multiplication / Division AND logical OR logical Exclusive OR logical -- Move Inverse logic Condition Code Notation Symbol Modified according to the instruction result * Not fixed (value not guaranteed) 0 Always cleared to 0 -- Not affected by the instruction execution result 249 A.2 Operation Code Map Table A-1 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Some pairs of instructions have identical first bytes. These instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 250 251 A.3 Number of States Required for Execution Table A-2 Instruction Set MOV.B @(d:16, Rs), Rd B @(d:16, Rs16) Rd8 MOV.B @Rs+, Rd B @Rs16 Rd8 Rs16+1 Rs16 MOV.B @aa:8, Rd B @aa:8 Rd8 MOV.B @aa:16, Rd B @aa:16 Rd8 MOV.B Rs, @Rd B Rs8 @Rd16 MOV.B Rs, @(d:16, Rd) B Rs8 @(d:16, Rd16) MOV.B Rs, @-Rd B Rd16-1 Rd16 Rs8 @Rd16 MOV.B Rs, @aa:8 B Rs8 @aa:8 MOV.B Rs, @aa:16 B Rs8 @aa:16 MOV.W #xx:16, Rd W #xx:16 Rd MOV.W Rs, Rd W Rs16 Rd16 MOV.W @Rs, Rd W @Rs16 Rd16 W @Rs16 Rd16 Rs16+2 Rs16 MOV.W @aa:16, Rd W @aa:16 Rd16 MOV.W Rs, @Rd 2 2 4 2 2 4 2 W Rs16 @Rd16 MOV.W Rs, @-Rd -- No. of States 0 -- 2 -- -- 0 -- 2 -- -- 0 -- 4 -- -- 0 -- 6 -- -- 0 -- 6 -- -- 0 -- 4 -- -- 0 -- 6 -- -- 0 -- 4 -- -- 0 -- 6 0 -- 6 2 -- -- 0 -- 4 4 -- -- 0 -- 6 -- -- 0 -- 4 2 4 2 2 4 2 4 2 W Rd16-2 Rd16 Rs16 @Rd16 I H N Z V C -- -- 4 MOV.W Rs, @(d:16, Rd) W Rs16 @(d:16, Rd16) Condition Code -- -- MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) Rd16 MOV.W @Rs+, Rd @@aa B @Rs16 Rd8 @(d:8, PC) B Rs8 Rd8 @aa:8/16 MOV.B Rs, Rd MOV.B @Rs, Rd @-Rn/@Rn+ 2 @(d:16, Rn) #xx:8/16 B #xx:8 Rd8 @Rn Operation MOV.B #xx:8, Rd Rn Mnemonic Operand Size Addressing Mode/ Instruction Length (Bytes) 4 2 -- -- 0 -- 2 -- -- 0 -- 4 -- -- 0 -- 6 -- -- 0 -- 6 -- -- 0 -- 6 -- -- 0 -- 4 -- -- 0 -- 6 -- -- 0 -- 6 MOV.W Rs, @aa:16 W Rs16 @aa:16 -- -- 0 -- 6 POP Rd W @SP Rd16 SP+2 SP 2 -- -- 0 -- 6 PUSH Rs W SP-2 SP Rs16 @SP 2 -- -- 0 -- 6 4 252 Table A-2 Instruction Set (cont) EEPMOV ADD.B #xx:8, Rd B Rd8+#xx:8 Rd8 B Rd8+Rs8 Rd8 ADD.W Rs, Rd W Rd16+Rs16 Rd16 ADDX.B #xx:8, Rd B Rd8+#xx:8 +C Rd8 I H N Z V C No. of States -- @@aa @(d:8, PC) @aa:8/16 @-Rn/@Rn+ @(d:16, Rn) Condition Code 4 -- -- -- -- -- -- -- if R4L0 then Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L=0 else next; ADD.B Rs, Rd @Rn Operation Rn #xx:8/16 Mnemonic Operand Size Addressing Mode/ Instruction Length (Bytes) -- 2 2 -- 2 2 -- 2 2 2 -- 2 2 ADDX.B Rs, Rd B Rd8+Rs8 +C Rd8 2 -- ADDS.W #1, Rd W Rd16+1 Rd16 2 -- -- -- -- -- -- 2 ADDS.W #2, Rd W Rd16+2 Rd16 2 -- -- -- -- -- -- 2 INC.B Rd B Rd8+1 Rd8 2 -- -- DAA.B Rd B Rd8 decimal adjust Rd8 2 -- * SUB.B Rs, Rd B Rd8-Rs8 Rd8 2 -- SUB.W Rs, Rd W Rd16-Rs16 Rd16 2 -- SUBX.B #xx:8, Rd B Rd8-#xx:8-C Rd8 2 -- 2 * 2 2 2 -- 2 2 SUBX.B Rs, Rd B Rd8-Rs8-C Rd8 2 -- SUBS.W #1, Rd W Rd16-1 Rd16 2 -- -- -- -- -- -- 2 SUBS.W #2, Rd W Rd16-2 Rd16 2 -- -- -- -- -- -- 2 DEC.B Rd B Rd8-1 Rd8 2 -- -- -- 2 DAS.B Rd B Rd8 decimal adjust Rd8 2 -- * * -- 2 NEG.B Rd B 0-Rd Rd 2 -- 2 CMP.B #xx:8, Rd B Rd8-#xx:8 -- 2 CMP.B Rs, Rd B Rd8-Rs8 2 -- 2 CMP.W Rs, Rd W Rd16-Rs16 2 -- 2 2 253 Table A-2 Instruction Set (cont) AND.B #xx:8, Rd B Rd8#xx:8 Rd8 AND.B Rs, Rd B Rd8Rs8 Rd8 OR.B #xx:8, Rd B Rd8#xx:8 Rd8 OR.B Rs, Rd B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 -- I H N Z V C -- -- 2 2 XOR.B #xx:8, Rd Condition Code 2 2 2 No. of States -- -- -- -- 14 @@aa 2 @(d:8, PC) B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) @aa:8/16 DIVXU.B Rs, Rd @-Rn/@Rn+ -- -- -- -- -- -- 14 @(d:16, Rn) 2 Operation @Rn B Rd8 x Rs8 Rd16 Rn MULXU.B Rs, Rd #xx:8/16 Mnemonic Operand Size Addressing Mode/ Instruction Length (Bytes) 0 -- 2 -- -- 0 -- 2 -- -- 0 -- 2 -- -- 0 -- 2 -- -- 0 -- 2 XOR.B Rs, Rd B Rd8Rs8 Rd8 2 -- -- 0 -- 2 NOT.B Rd B Rd Rd 2 -- -- 0 -- 2 SHAL.B Rd B 2 -- -- 2 -- -- 0 2 2 -- -- 0 2 2 -- -- 0 0 2 2 -- -- 0 2 2 -- -- 0 2 C 0 b7 SHAR.B Rd SHLL.B Rd C B b0 C 0 b7 SHLR.B Rd B B b0 0 C b7 ROTXL.B Rd b0 C b7 ROTXR.B Rd b0 B b7 2 b0 B b7 b0 C 254 Table A-2 Instruction Set (cont) I H N Z V C No. of States Condition Code -- @@aa @(d:8, PC) @aa:8/16 @-Rn/@Rn+ @(d:16, Rn) Operation @Rn B Rn ROTL.B Rd #xx:8/16 Mnemonic Operand Size Addressing Mode/ Instruction Length (Bytes) 2 -- -- 0 2 2 -- -- 0 2 2 -- -- -- -- -- -- 2 C b7 ROTR.B Rd b0 B C b7 BSET #xx:3, Rd b0 B (#xx:3 of Rd8) 1 BSET #xx:3, @Rd B (#xx:3 of @Rd16) 1 BSET #xx:3, @aa:8 B (#xx:3 of @aa:8) 1 BSET Rn, Rd B (Rn8 of Rd8) 1 BSET Rn, @Rd B (Rn8 of @Rd16) 1 BSET Rn, @aa:8 B (Rn8 of @aa:8) 1 BCLR #xx:3, Rd B (#xx:3 of Rd8) 0 BCLR #xx:3, @Rd B (#xx:3 of @Rd16) 0 BCLR #xx:3, @aa:8 B (#xx:3 of @aa:8) 0 BCLR Rn, Rd B (Rn8 of Rd8) 0 BCLR Rn, @Rd B (Rn8 of @Rd16) 0 BCLR Rn, @aa:8 B (Rn8 of @aa:8) 0 BNOT #xx:3, Rd B (#xx:3 of Rd8) (#xx:3 of Rd8) BNOT #xx:3, @Rd B (#xx:3 of @Rd16) (#xx:3 of @Rd16) BNOT #xx:3, @aa:8 B (#xx:3 of @aa:8) (#xx:3 of @aa:8) BNOT Rn, Rd B (Rn8 of Rd8) (Rn8 of Rd8) BNOT Rn, @Rd B (Rn8 of @Rd16) (Rn8 of @Rd16) BNOT Rn, @aa:8 B (Rn8 of @aa:8) (Rn8 of @aa:8) 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 255 -- -- -- -- -- -- 8 -- -- -- -- -- -- 8 Table A-2 Instruction Set (cont) BTST Rn, @aa:8 B (Rn8 of @aa:8) Z BLD #xx:3, Rd B (#xx:3 of Rd8) C BLD #xx:3, @Rd B (#xx:3 of @Rd16) C BLD #xx:3, @aa:8 B (#xx:3 of @aa:8) C BILD #xx:3, Rd B (#xx:3 of Rd8) C BILD #xx:3, @Rd B (#xx:3 of @Rd16) C BILD #xx:3, @aa:8 B (#xx:3 of @aa:8) C BST #xx:3, Rd B C (#xx:3 of Rd8) BST #xx:3, @Rd B C (#xx:3 of @Rd16) BST #xx:3, @aa:8 B C (#xx:3 of @aa:8) BIST #xx:3, Rd B C (#xx:3 of Rd8) BIST #xx:3, @Rd B C (#xx:3 of @Rd16) BIST #xx:3, @aa:8 B C (#xx:3 of @aa:8) BAND #xx:3, Rd B C(#xx:3 of Rd8) C 4 -- -- -- -- -- 6 4 4 -- -- -- -- -- 6 4 4 -- -- -- -- -- 6 4 4 2 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 4 -- -- -- -- -- 6 4 4 BIAND #xx:3, @aa:8 B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C -- -- -- -- -- 6 4 4 BOR #xx:3, @Rd B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C BIOR #xx:3, Rd B C(#xx:3 of Rd8) C BIOR #xx:3, @Rd B C(#xx:3 of @Rd16) C -- -- -- -- -- 6 4 4 -- -- -- -- -- 6 -- -- -- -- -- 2 2 256 -- -- -- -- -- 6 -- -- -- -- -- 2 2 BOR #xx:3, @aa:8 -- -- -- -- -- 6 -- -- -- -- -- 2 2 BOR #xx:3, Rd -- -- -- -- -- -- 8 -- -- -- -- -- 2 2 B C(#xx:3 of Rd8) C -- -- -- -- -- -- 8 -- -- -- -- -- -- 2 4 B C(#xx:3 of @Rd16) C -- -- -- -- -- 6 -- -- -- -- -- -- 2 4 BIAND #xx:3, Rd -- -- -- -- -- 6 -- -- -- -- -- 2 2 BIAND #xx:3, @Rd -- -- -- -- -- 6 -- -- -- -- -- 2 2 B C(#xx:3 of @Rd16) C -- -- -- -- -- 6 -- -- -- -- -- 2 2 B C(#xx:3 of @aa:8) C No. of States -- -- -- -- -- 6 4 BAND #xx:3, @Rd I H N Z V C -- -- -- -- -- 2 2 BAND #xx:3, @aa:8 Condition Code -- B (Rn8 of @Rd16) Z @@aa B (Rn8 of Rd8) Z BTST Rn, @Rd @(d:8, PC) BTST Rn, Rd @aa:8/16 B (#xx:3 of @aa:8) Z @-Rn/@Rn+ B (#xx:3 of @Rd16) Z BTST #xx:3, @aa:8 @(d:16, Rn) BTST #xx:3, @Rd Operation @Rn B (#xx:3 of Rd8) Z Rn BTST #xx:3, Rd #xx:8/16 Mnemonic Operand Size Addressing Mode/ Instruction Length (Bytes) 4 -- -- -- -- -- 6 Table A-2 Instruction Set (cont) BXOR #xx:3, Rd B C(#xx:3 of Rd8) C BXOR #xx:3, @Rd B C(#xx:3 of @Rd16) C BXOR #xx:3, @aa:8 B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C No. of States I H N Z V C -- -- -- -- -- 6 4 -- -- -- -- -- 2 2 BIXOR #xx:3, Rd Condition Code -- @@aa @(d:8, PC) @aa:8/16 @-Rn/@Rn+ @(d:16, Rn) Operation @Rn B C(#xx:3 of @aa:8) C Rn BIOR #xx:3, @aa:8 Branching Condition #xx:8/16 Mnemonic Operand Size Addressing Mode/ Instruction Length (Bytes) -- -- -- -- -- 6 4 -- -- -- -- -- 6 4 -- -- -- -- -- 2 2 BIXOR #xx:3, @Rd B C(#xx:3 of @Rd16) C BIXOR #xx:3, @aa:8 B C(#xx:3 of @aa:8) C BRA d:8 (BT d:8) -- PC PC+d:8 2 -- -- -- -- -- -- 4 BRN d:8 (BF d:8) -- PC PC+2 2 -- -- -- -- -- -- 4 BHI d:8 CZ=0 2 -- -- -- -- -- -- 4 CZ=1 2 -- -- -- -- -- -- 4 C=0 2 -- -- -- -- -- -- 4 C=1 2 -- -- -- -- -- -- 4 Z=0 2 -- -- -- -- -- -- 4 BEQ d:8 -- If -- condition is true -- then -- PC PC+d:8 -- else next; -- Z=1 2 -- -- -- -- -- -- 4 BVC d:8 -- V=0 2 -- -- -- -- -- -- 4 BVS d:8 -- V=1 2 -- -- -- -- -- -- 4 BPL d:8 -- N=0 2 -- -- -- -- -- -- 4 BMI d:8 -- N=1 2 -- -- -- -- -- -- 4 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 -- -- -- -- -- 6 4 -- -- -- -- -- 6 4 BGE d:8 -- NV = 0 2 -- -- -- -- -- -- 4 BLT d:8 -- NV = 1 2 -- -- -- -- -- -- 4 BGT d:8 -- Z (NV) = 0 2 -- -- -- -- -- -- 4 BLE d:8 -- Z (NV) = 1 2 -- -- -- -- -- -- 4 JMP @Rn -- PC Rn16 JMP @aa:16 -- PC aa:16 JMP @@aa:8 -- PC @aa:8 BSR d:8 -- SP-2 SP PC @SP PC PC+d:8 2 -- -- -- -- -- -- 4 4 -- -- -- -- -- -- 6 2 2 257 -- -- -- -- -- -- 8 -- -- -- -- -- -- 6 Table A-2 Instruction Set (cont) -- SP-2 SP PC @SP PC Rn16 JSR @aa:16 -- SP-2 SP PC @SP PC aa:16 JSR @@aa:8 2 No. of States I H N Z V C -- -- -- -- -- -- 6 4 SP-2 SP PC @SP PC @aa:8 Condition Code -- @@aa @(d:8, PC) @aa:8/16 @-Rn/@Rn+ @(d:16, Rn) @Rn Rn Operation JSR @Rn #xx:8/16 Mnemonic Operand Size Addressing Mode/ Instruction Length (Bytes) -- -- -- -- -- -- 8 2 -- -- -- -- -- -- 8 RTS -- PC @SP SP+2 SP 2 -- -- -- -- -- -- 8 RTE -- CCR @SP SP+2 SP PC @SP SP+2 SP 2 SLEEP -- Transit to sleep mode. LDC #xx:8, CCR B #xx:8 CCR LDC Rs, CCR B Rs8 CCR STC CCR, Rd B CCR Rd8 10 2 -- -- -- -- -- -- 2 2 2 2 2 -- -- -- -- -- -- 2 2 ANDC #xx:8, CCR B CCR#xx:8 CCR 2 2 ORC #xx:8, CCR B CCR#xx:8 CCR 2 2 XORC #xx:8, CCR B CCR#xx:8 CCR 2 2 NOP -- PC PC+2 Notes: 2 -- -- -- -- -- -- 2 Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. Set to 1 if decimal adjustment produces a carry; otherwise cleared to 0. The number of states required for execution is 4n+9 (n = value of R4L). Set to 1 if the divisor is negative; otherwise cleared to 0. Set to 1 if the divisor is zero; otherwise cleared to 0. 258 Appendix B On-Chip Registers B.1 On-Chip Registers (1) Addr. (Last Register Byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'A0 STAR -- -- -- STA4 STA3 STA2 STA1 STA0 SCI2 H'A1 EDAR -- -- -- EDA4 EDA3 EDA2 EDA1 EDA0 H'A2 SCR2 -- -- -- I/O GAP2 GAP1 PS1 PS0 H'A3 STSR -- -- -- SO2 LAST BIT OVR WT GIT STF Bit Names Not used H'A4 -- to H'AF SMR16 SMR15 SMR14 -- H'B0 SMR1 -- H'B1 SDRU1 SDRU17 SDRU16 SDRU15 SDRU14 SDRU13 SDRU12 SDRU11 SDRU10 H'B2 SDRL1 SDRL17 SDRL16 SDRL15 SDRL14 SDRL13 SDRL12 SDRL11 SDRL10 H'B3 SPR1 SO1 LAST BIT -- -- -- -- -- -- -- H'B4 -- -- -- -- -- -- -- -- -- H'B5 -- -- -- -- -- -- -- -- -- H'B6 -- -- -- -- -- -- -- -- -- H'B7 -- -- -- -- -- -- -- -- -- H'B8 -- -- -- -- -- -- -- -- -- H'B9 -- -- -- -- -- -- -- -- -- H'BA -- -- -- -- -- -- -- -- -- H'BB -- -- -- -- -- -- -- -- -- H'BC AMR AMR7 -- -- -- -- AMR2 AMR1 AMR0 H'BD ADRR ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 H'BE ADSR ADSF -- -- -- -- -- -- -- H'BF -- -- -- -- -- -- -- -- -- Notation: SCI1: Serial communication interface 1 SCI2: Serial communication interface 2 259 SMR13 SMR12 SMR11 SMR10 SCI1 -- A/D converter B.1 On-Chip Registers (1) (cont) Addr. (Last Register Byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 H'C0 TMA -- -- -- -- TMA3 TMA2 H'C1 TCA TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 H'C2 TMB TMB7 -- -- -- -- TMB2 TMB1 TMB0 H'C3 TLB/TCB TLB7/ TCB7 TLB6/ TCB6 TLB5/ TCB5 TLB4/ TCB4 TLB3/ TCB3 TLB2/ TCB2 TLB1/ TCB1 TLB0/ TCB0 H'C4 TMC TMC7 TMC6 TMC5 -- -- TMC2 TMC1 TMC0 H'C5 TLC/TCC TLC7/ TCC7 TLC6/ TCC6 TLC5/ TCC5 TLC4/ TCC4 TLC3/ TCC3 TLC2/ TCC2 TLC1/ TCC1 TLC0/ TCC0 H'C6 TMD CLR -- -- -- -- -- -- EDG H'C7 TCD TCD7 TCD6 TCD5 TCD4 TCD3 TCD2 TCD1 TCD0 H'C8 TME TME7 -- -- -- -- TME2 TME1 TME0 H'C9 TLE/TCE TLE7/ TCE7 TLE6/ TCE6 TLE5/ TCE5 TLE4/ TCE4 TLE3/ TCE3 TLE2/ TCE2 TLE1/ TCE1 TLE0/ TCE0 H'CA -- -- -- -- -- -- -- -- -- H'CB -- -- -- -- -- -- -- -- -- H'CC PWCR* -- -- -- -- -- -- -- PWCR0 H'CD PWDRU* -- -- H'CE PWDRL* PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 H'CF -- -- -- -- -- -- -- -- -- H'D0 PDR0 PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00 H'D1 PDR1 -- -- PDR15 PDR14 PDR13 PDR12 PDR11 PDR10 H'D2 PDR2 PDR27 PDR26 PDR25 PDR24 PDR23 PDR22 PDR21 PDR20 H'D3 -- -- -- -- -- -- -- -- -- Bit Names Bit 2 Bit 0 Module Name TMA1 TMA0 Timer A TCA1 TCA0 Bit 1 Timer B Timer C Timer D Timer E 14-bit PWM PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 H'D4 PDR4 -- -- PDR45 PDR44 PDR43 PDR42 PDR41 PDR40 H'D5 -- -- -- -- -- -- -- -- -- H'D6 -- -- -- -- -- -- -- -- -- H'D7 -- -- -- -- -- -- -- -- -- H'D8 PDR8 PDR87 PDR86 PDR85 PDR84 PDR83 PDR82 PDR81 PDR80 H'D9 PDR9 PDR97 PDR96 PDR95 PDR94 PDR93 PDR92 PDR91 PDR90 H'DA PDRA PDRA7 PDRA6 PDRA5 PDRA4 PDRA3 PDRA2 PDRA1 PDRA0 H'DB -- -- -- -- -- -- -- -- -- H'DC -- -- -- -- -- -- -- -- -- H'DD -- -- -- -- -- -- -- -- -- H'DE -- -- -- -- -- -- -- -- -- H'DF -- -- -- -- -- -- -- -- -- Note: * Not usable in the H8/3612. 260 I/O ports B.1 On-Chip Registers (1) (cont) Addr. (Last Register Byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'E0 -- -- -- -- -- -- -- -- -- H'E1 PCR1 -- -- PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 H'E2 PCR2 PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20 H'E3 -- -- -- -- -- -- -- -- -- H'E4 -- -- -- -- -- -- -- -- -- H'E5 -- -- -- -- -- -- -- -- -- H'E6 -- -- -- -- -- -- -- -- -- H'E7 -- -- -- -- -- -- -- -- -- H'E8 PCR8 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 H'E9 PCR9 PCR97 PCR96 PCR95 PCR94 PCR93 PCR92 PCR91 PCR90 H'EA PCRA PCRA7 PCRA6 PCRA5 PCRA4 PCRA3 PCRA2 PCRA1 PCRA0 H'EB PMR1 NOISE EVENT CANCEL IRQC5 IRQC4 IRQC3 IRQC2 IRQC1 IRQC0 H'EC PMR2 UP/ DOWN SO2 SI2 SCK2 SO1 SI1 SCK1 PWM* H'ED PMR3 -- SO2 PMOS CS -- SO1 PMOS -- -- -- H'EE PMR4 TEO TEO ON FREQ VRFR -- -- -- -- H'EF PMR0 AN7 AN6 AN4 AN3 AN2 AN1 AN0 H'F0 SYSCR1 SSBY STS2 STS1 STS0 LSON -- -- -- H'F1 SYSCR2 -- -- -- -- DTON -- -- -- H'F2 IEGR -- -- -- IEG4 -- -- IEG1 IEG0 H'F3 IENR1 -- -- IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 H'F4 IENR2 -- -- IENDT IENTE IENTD IENTC IENTB IENTA H'F5 IENR3 IENAD -- -- -- -- -- IENS2 IENS1 H'F6 IRR1 -- -- IRRI5 IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 H'F7 IRR2 -- -- IRRDT IRRTE IRRTD IRRTC IRRTB IRRTA H'F8 IRR3 IRRAD -- -- -- -- -- IRRS2 IRRS1 H'F9 -- -- -- -- -- -- -- -- -- H'FA -- -- -- -- -- -- -- -- -- H'FB -- -- -- -- -- -- -- -- -- H'FC -- -- -- -- -- -- -- -- -- H'FD -- -- -- -- -- -- -- -- -- H'FE -- -- -- -- -- -- -- -- -- H'FF -- -- -- -- -- -- -- -- -- Bit Names AN5 Note: * Not usable in the H8/3612. 261 Module Name I/O ports System control B.2 On-Chip Registers (2) Register acronym Register name AMR--A/D Mode Register Address to which register is mapped Name of on-chip peripheral module H'BC A/D Converter Bit numbers Bit Initial bit values 7 6 5 4 3 2 1 0 AMR7 -- -- -- -- AMR2 AMR1 AMR0 Initial value 0 1 1 1 1 0 0 0 Read/Write R/W -- -- -- -- R/W R/W R/W Channel Select 0 0 0 Analog input pin is AN0 1 Analog input pin is AN1 Possible types of access R Read only W Write only Bit names and positions. Dashes (--) indicate reserved bits. 1 0 Analog input pin is AN2 1 Analog input pin is AN3 1 0 0 Analog input pin is AN4 R/W Read and write Full name of bit 1 Analog input pin is AN5 1 0 Analog input pin is AN6 1 Analog input pin is AN7 Clock Select 0 Conversion period is 62/ 1 Conversion period is 31/ 262 Bit settings and descriptions STAR--Start Address Register Bit H'A0 SCI2 7 6 5 4 3 2 1 0 -- -- -- STA4 STA3 STA2 STA1 STA0 Initial value 1 1 1 0 0 0 0 0 Read/Write -- -- -- R/W R/W R/W R/W R/W Designates transfer starting address in address space H'FF80 to H'FF9F. EDAR--End Address Register Bit H'A1 SCI2 7 6 5 4 3 2 1 0 -- -- -- EDA4 EDA3 EDA2 EDA1 EDA0 Initial value 1 1 1 0 0 0 0 0 Read/Write -- -- -- R/W R/W R/W R/W R/W Designates transfer end address in address space H'FF80 to H'FF9F. SCR2--Serial Control Register 2 Bit H'A2 SCI2 7 6 5 4 3 2 1 0 -- -- -- I/O GAP2 GAP1 PS1 PS0 Initial value 1 1 1 0 0 0 0 0 Read/Write -- -- -- R/W R/W R/W R/W R/W Transmit/Receive Select Gap Insertion 0 Receive mode 0 0 No gap insertion 1 Transmit mode 0 1 1-clock gap insertion 1 0 2-clock gap insertion 1 1 8-clock gap insertion Transfer Clock Select 0 0 o/2, SCK 2 is output pin 0 1 o/4, SCK 2 is output pin 1 0 o/8, SCK 2 is output pin 1 1 External clock, SCK 2 is input pin 263 STSR--Status Register Bit Initial value Read/Write H'A3 SCI2 7 6 5 4 3 2 1 0 -- -- -- SO2 LAST BIT OVR WT GIT STF 1 1 1 0 *2 0 0 0 R/W R/W*1 R/W*1 R/W R/W -- -- -- Extended Data Bit 0 Pin SO 2 output low 1 Pin SO 2 output high Waiting Flag 0 [Clear condition] When STSR is written 1 [Set condition] When 32-byte data buffer is read or written during transfer Overrun Flag Gap Interval Flag 0 [Clear condition] When STSR is written 0 Insert gap every 16 bits 1 [Set condition] When overrun occurs 1 Insert gap every 8 bits Start/Busy Flag 0 [Read] Transfer stopped [Write] Transfer aborted 1 [Read] Transfer in progress [Write] Starts transfer Notes: 1. Cleared to 0 by write operation to STSR. 2. Not fixed 264 SMR1--Serial Mode Register 1 Bit H'B0 SCI1 7 6 5 4 3 2 1 0 -- SMR16 SMR15 SMR14 SMR13 SMR12 SMR11 SMR10 Initial value 1 0 0 0 0 0 0 0 Read/Write -- W W W W W W W Operation Mode Select Clock Select 0 0 0 0 0 0 o/1024, SCK 1 is output pin 1 o/256, SCK 1 is output pin 0 Clock continuous output mode Not 00 8-bit transfer mode 1 0 0 1 0 o/64, SCK 1 is output pin 1 o/32, SCK 1 is output pin Clock continuous output mode Not 00 16-bit transfer mode 1 0 0 o/16, SCK 1 is output pin 1 o/8, SCK 1 is output pin 1 0 o/4, SCK 1 is output pin 1 o/2, SCK 1 is output pin 1 0 0 0 Not used 1 Not used 1 0 Not used 1 Not used 1 0 0 Not used 1 Not used 1 0 Not used 1 External clock, SCK 1 is input pin SDRU1--Serial Data Register U1 Bit 7 6 H'B1 5 4 3 SCI1 2 1 0 SDRU17 SDRU16 SDRU15 SDRU14 SDRU13 SDRU12 SDRU11 SDRU10 Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Used to set transmit data and store received data. 8-bit transfer mode: not used 16-bit transfer mode: upper 8 bits of data register Note: * Not fixed 265 SDRL1--Serial Data Register L1 Bit 7 H'B2 6 5 4 3 SCI1 2 1 0 SDRL17 SDRL16 SDRL15 SDRL14 SDRL13 SDRL12 SDRL11 SDRL10 Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Used to set transmit data and store received data. 8-bit transfer mode: data register 16-bit transfer mode: lower 8 bits of data register Note: * Not fixed SPR1--Serial Port Register 1 Bit H'B3 SCI1 7 6 5 4 3 2 1 0 SO1 LAST BIT -- -- -- -- -- -- -- Initial value * 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- Extended Data Bit 0 Pin SO 1 output low 0 Pin SO 1 output high Note: * Not fixed 266 AMR--A/D Mode Register Bit H'BC A/D Converter 7 6 5 4 3 2 1 0 AMR7 -- -- -- -- AMR2 AMR1 AMR0 Initial value 0 1 1 1 1 0 0 0 Read/Write R/W -- -- -- -- R/W R/W R/W Clock Select Channel Select 0 Conversion period is 62/o 0 0 0 Analog input pin is AN0 1 Analog input pin is AN1 1 Conversion period is 31/o 1 0 Analog input pin is AN2 1 Analog input pin is AN3 1 0 0 Analog input pin is AN4 1 Analog input pin is AN5 1 0 Analog input pin is AN6 1 Analog input pin is AN7 ADRR--A/D Result Register Bit H'BD A/D Converter 7 6 5 4 3 2 1 0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value * * * * * * * * Read/Write R R R R R R R R A/D Conversion Result Note: * Not fixed 267 ADSR--A/D Start Register Bit H'BE A/D Converter 7 6 5 4 3 2 1 0 ADSF -- -- -- -- -- -- -- Initial value 0 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- A/D Start Flag 0 [Read] A/D conversion stopped or complete [Write] A/D conversion aborted 1 [Read] A/D conversion in progress [Write] Starts A/D conversion TMA--Timer Mode Register A Bit H'C0 Timer A 7 6 5 4 3 2 1 0 -- -- -- -- TMA3 TMA2 TMA1 TMA0 Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W Clock Select 0 0 0 0 Input source PSS, o/8192 1 Input source PSS, o/4096 1 0 Input source PSS, o/2048 1 Input source PSS, o/512 1 0 0 Input source PSS, o/256 1 Input source PSS, o/128 1 0 Input source PSS, o/32 1 Input source PSS, o/8 1 0 0 0 Input source PSW, 2 s 1 Input source PSW, 1 s 1 0 Input source PSW, 0.5 s 1 Input source PSW, 125 ms 1 0 0 PSW and TCA reset 1 1 0 1 268 TCA--Timer Counter A Bit H'C1 Timer A 7 6 5 4 3 2 1 0 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Count Value TMB--Timer Mode Register B Bit H'C2 Timer B 7 6 5 4 3 2 1 0 TMB7 -- -- -- -- TMB2 TMB1 TMB0 Initial value 0 1 1 1 1 0 0 0 Read/Write R/W -- -- -- -- R/W R/W R/W Clock Select 0 0 0 Internal clock, o /8192 1 Internal clock, o /2048 1 0 Internal clock, o /512 1 Internal clock, o /256 1 0 0 Internal clock, o /128 1 Internal clock, o /32 1 0 Internal clock, o /8 1 External clock, choice of rising or falling edge Auto Reload Function Select 0 Interval timer 1 Auto-reload timer 269 TCB--Timer Counter B Bit H'C3 Timer B 7 6 5 4 3 2 1 0 TCB7 TCB6 TCB5 TCB4 TCB3 TCB2 TCB1 TCB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Count Value TLB--Timer Load Register B Bit H'C3 Timer B 7 6 5 4 3 2 1 0 TLB7 TLB6 TLB5 TLB4 TLB3 TLB2 TLB1 TLB0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Reload Value Setting 270 TMC--Timer Mode Register C Bit H'C4 Timer C 7 6 5 4 3 2 1 0 TMC7 TMC6 TMC5 -- -- TMC2 TMC1 TMC0 Initial value 0 0 0 1 1 0 0 0 Read/Write R/W R/W R/W -- -- R/W R/W R/W Clock Select 0 0 0 Internal clock, o /8192 1 Internal clock, o /2048 1 0 Internal clock, o /512 1 Internal clock, o /256 1 0 0 Internal clock, o /128 1 Internal clock, o /32 1 0 Internal clock, o /8 1 External clock, choice of rising or falling edge Count-Up/Down Control 0 0 Up-counter 1 Down-counter 1 * Hardware control via pin P9 7/UD. High is down, low is up. Note: * Don't care. Auto-Reload Function Select 0 Interval timer 1 Auto-reload timer TCC--Timer Counter C Bit H'C5 Timer C 7 6 5 4 3 2 1 0 TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Count Value 271 TLC--Timer Load Register C Bit H'C5 Timer C 7 6 5 4 3 2 1 0 TLC7 TLC6 TLC5 TLC4 TLC3 TLC2 TLC1 TLC0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Reload Value Setting TMD--Timer Mode Register D Bit H'C6 Timer D 7 6 5 4 3 2 1 0 CLR -- -- -- -- -- -- EDG Initial value 0 1 1 1 1 1 1 0 Read/Write W -- -- -- -- -- -- R/W Edge Select 0 Incremented at falling edge of EVENT pin input 1 Incremented at rising edge of EVENT pin input Counter Clear 0 After this bit is set to 1 and TCD is initialized, it is automatically cleared by hardware. 1 TCD is initialized to H'00. TCD--Timer Counter D Bit H'C7 Timer D 7 6 5 4 3 2 1 0 TCD7 TCD6 TCD5 TCD4 TCD3 TCD2 TCD1 TCD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Count Value 272 TME--Timer Mode Register E Bit H'C8 Timer E 7 6 5 4 3 2 1 0 TME7 -- -- -- -- TME2 TME1 TME0 Initial value 0 1 1 1 1 0 0 0 Read/Write R/W -- -- -- -- R/W R/W R/W Auto-Reload Function Select Clock Select 0 Interval timer 0 0 0 Internal clock, o/8192 1 Internal clock, o/4096 1 Auto-reload timer 1 0 Internal clock, o/2048 1 Internal clock, o/512 1 0 0 Internal clock, o/256 1 Internal clock, o/128 1 0 Internal clock, o/32 1 Internal clock, o/8 TCE--Timer Counter E Bit H'C9 Timer E 7 6 5 4 3 2 1 0 TCE7 TCE6 TCE5 TCE4 TCE3 TCE2 TCE1 TCE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Count Value TLE--Timer Load Register E Bit H'C9 Timer E 7 6 5 4 3 2 1 0 TLE7 TLE6 TLE5 TLE4 TLE3 TLE2 TLE1 TLE0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Reload Value Setting 273 PWCR--PWM Control Register Bit H'CC 14-bit PWM 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- PWCR0 Initial value 1 1 1 1 1 1 1 0 Read/Write -- -- -- -- -- -- -- W Clock Select 0 The input clock is o/2. The conversion period is 16384/o, with a minimum modulation width of 1/o. 1 The input clock is o/4. The conversion period is 32768/o, with a minimum modulation width of 2/o. Note: Not usable in the H8/3612. PWDRU--PWM Data Register U Bit H'CD 14-bit PWM 7 6 -- -- Initial value 1 1 0 0 0 0 0 0 Read/Write -- -- W W W W W W 5 4 3 2 1 0 PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 Upper 6 Bits of Data for PWM Waveform Generation Note: Not usable in the H8/3612. PWDRL--PWM Data Register L Bit 7 6 H'CE 5 4 3 14-bit PWM 2 1 0 PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Lower 8 Bits of Data for PWM Waveform Generation Note: Not usable in the H8/3612. 274 PDR0--Port Data Register 0 Bit H'D0 I/O Ports 7 6 5 4 3 2 1 0 PDR0 7 PDR0 6 PDR0 5 PDR0 4 PDR03 PDR0 2 PDR0 1 PDR0 0 Initial value -- -- -- -- -- -- -- -- Read/Write R R R R R R R R PDR1--Port Data Register 1 Bit H'D1 I/O Ports 7 6 5 4 3 2 1 0 -- -- PDR1 5 PDR14 PDR13 PDR1 2 PDR11 PDR10 Initial value --* --* 0 0 0 0 0 0 Read/Write -- -- R/W R/W R/W R/W R/W R/W Note: * Pins P16 and P17 are input-only pins; whenever they are read, the pin level is read out. PDR2--Port Data Register 2 Bit H'D2 I/O Ports 7 6 5 4 3 2 1 0 PDR27 PDR26 PDR25 PDR24 PDR23 PDR22 PDR21 PDR20 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR4--Port Data Register 4 Bit H'D4 I/O Ports 7 6 5 4 3 2 1 0 -- -- PDR4 5 PDR44 PDR4 3 PDR4 2 PDR4 1 PDR4 0 Initial value 1 1 0 0 0 0 0 0 Read/Write -- -- R/W R/W R/W R/W R/W R/W PDR8--Port Data Register 8 Bit H'D8 I/O Ports 7 6 5 4 3 2 1 0 PDR8 7 PDR8 6 PDR8 5 PDR84 PDR8 3 PDR8 2 PDR8 1 PDR8 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 275 PDR9--Port Data Register 9 Bit H'D9 I/O Ports 7 6 5 4 3 2 1 0 PDR9 7 PDR9 6 PDR9 5 PDR94 PDR9 3 PDR9 2 PDR9 1 PDR9 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDRA--Port Data Register A Bit H'DA I/O Ports 7 6 5 4 3 2 1 0 PDRA7 PDRA6 PDRA5 PDRA4 PDRA3 PDRA2 PDRA1 PDRA0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PCR1--Port Control Register 1 Bit H'E1 I/O Ports 7 6 5 4 3 2 1 0 -- -- PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 Initial value 1 1 0 0 0 0 0 0 Read/Write -- -- W W W W W W Port 1 I/O Select 0 Input port 1 Output port PCR2--Port Control Register 2 Bit H'E2 I/O Ports 7 6 5 4 3 2 1 0 PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 2 I/O Select 0 Input port 1 Output port 276 PCR8--Port Control Register 8 Bit H'E8 I/O Ports 7 6 5 4 3 2 1 0 PCR8 7 PCR8 6 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 8 I/O Select 0 Input port 1 Output port PCR9--Port Control Register 9 Bit H'E9 I/O Ports 7 6 5 4 3 2 1 0 PCR9 7 PCR9 6 PCR95 PCR94 PCR93 PCR92 PCR91 PCR90 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 9 I/O Select 0 Input port 1 Output port PCRA--Port Control Register A Bit H'EA I/O Ports 7 6 5 4 3 2 1 0 PCRA7 PCRA6 PCRA5 PCRA4 PCRA3 PCRA2 PCRA1 PCRA0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port A I/O Select 0 Input port 1 Output port 277 PMR1--Port Mode Register 1 Bit H'EB I/O Ports 7 6 5 4 3 2 1 0 NOISE CANCEL EVENT IRQC5 IRQC4 IRQC3 IRQC2 IRQC1 IRQC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P16/EVENT Pin Function Switch P10/IRQ0 Pin Function Switch 0 P16 pin function 0 P10 pin function 1 EVENT pin function 1 IRQ0 pin function Noise Cancel P11/IRQ1 Pin Function Switch 0 IRQ0 pin noise cancel function off 0 P11 pin function 1 IRQ1 pin function 1 IRQ0 pin noise cancel function on P12/IRQ2 Pin Function Switch 0 P12 pin function 1 IRQ2 pin function P13/IRQ3 Pin Function Switch 0 P13 pin function 1 IRQ3 pin function P14/IRQ4 Pin Function Switch 0 P14 pin function 1 IRQ4 pin function P15/IRQ5 /TMOE Pin Function Switch 0 P15/TMOE pin function* 1 IRQ5 pin function Note: * For the switching between P15 and TMOE pin functions see under PMR4. 278 PMR2--Port Mode Register 2 Bit H'EC I/O Ports 7 6 5 4 3 2 1 0 UP/ DOWN SO2 SI2 SCK2 SO1 SI1 SCK1 PWM Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W *2 P96 /SO2 Pin Function Switch P9 0/PWM Pin Function Switch 0 P9 6 pin function 0 P9 0 pin function 1 SO2 pin function 1 PWM pin function P97 /UD Pin Function Switch P9 1/SCK1 Pin Function Switch 0 P97 pin function 0 P91 pin function 1 UD pin function 1 SCK 1 pin function P92 /SI 1 pin function switch 0 P92 pin function 1 SI1 pin function P9 3 /SO 1Pin Function Switch 0 P93 pin function 1 SO1 pin function P9 4/SCK2 Pin Function Switch 0 P94 pin function 1 SCK2 pin function P9 5/SI 1/CS Pin Function Switch 0 P95 pin function 1 SI 1/CS pin function*1 Notes: 1. For the switching between SI1 and CS pin functions see under PMR3. 2. Not usable (both read- and write-disabled) in the H8/3612. 279 PMR3--Port Mode Register 3 Bit 7 6 -- SO2 PMOS Initial value 1 Read/Write -- H'ED 5 I/O Ports 4 3 2 1 0 CS -- SO1 PMOS -- -- -- 0 0 1 0 1 1 1 R/W R/W -- R/W -- -- -- SO1 Pin PMOS On/Off 0 SO1 pin PMOS buffer on. CMOS output. 1 SO1 pin PMOS off. NMOS open-drain output. Chip Select Output Select PMR2 PMR3 SI2 CS P9 5/SI 2/CS pin function switch 0 0 P95 pin function 1 1 0 SI 2 pin function 1 CS pin function SO2 Pin PMOS On/Off 0 SO2 pin PMOS buffer on. CMOS output. 1 SO2 pin PMOS off. NMOS open-drain output. 280 PMR4--Port Mode Register 4 Bit H'EE I/O Ports 7 6 5 4 3 2 1 0 TEO TEO ON FREQ VRFR -- -- -- -- Initial value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/W -- -- -- -- Timer E Output Control PMR1 IRQC5 PMR4 P15 /IRQ 5/TMOE Pin TEO TEO ON FREQ VRFR Function Switch Pin Status 0 0 * * * P15 pin function 0 1 0 * * TMOE pin function (off) Low-level output Standard I/O port 0 1 1 0 0 TMOE pin function (on) Fixed-frequency output: o/2048 0 1 1 1 0 TMOE pin function (on) Fixed-frequency output: o/1024 0 1 1 * 1 1 * * * * TMOE pin function (on) Variable-frequency output: output toggles at each timer E overflow IRQ5 pin function External interrupt input Note: * Don't care. PMR0--Port Mode Register 0 Bit H'EF I/O Ports 7 6 5 4 3 2 1 0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Analog Input Select 0 POn input pin 1 ANn input pin (n = 7 to 0) 281 SYSCR1--System Control Register 1 Bit Initial value Read/Write H'F0 System Control 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 LSON -- -- -- 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W -- -- R/W *1 Low-Speed on Flag *2 0 CPU runs on system clock (o) 1 CPU runs on subclock (oSUB) Standby Timer Select 0 0 0 Wait time = 8,192 states 0 0 1 Wait time = 16,384 states 0 1 0 Wait time = 32,768 states 0 1 1 Wait time = 65,536 states 1 Wait time = 131,072 states *3 *3 Standby 0 Sleep mode entered after SLEEP instruction is executed. 1 Standby mode or watch mode entered after SLEEP instruction is executed. Notes: 1. Write is enabled in active mode only. 2. This relates to the transitions between operation modes, so functioning depends on the combination of this bit with other control bits and interrupts. For details see 3.3, System Modes. 3. Don't care. SYSCR2--System Control Register 2 Bit H'F1 System Control 7 6 5 4 3 2 1 0 -- -- -- -- DTON -- -- -- Initial value 1 1 1 1 0 1 0 0 Read/Write -- -- -- -- W* -- R/W R/W Direct Transfer On Flag 0 In subactive mode, watch mode is entered when a SLEEP instruction is executed. 1 In subactive mode, if LSON bit = 0, active mode is entered via watch mode when a SLEEP instruction is executed. Note: * Write is enabled in subactive mode only. 282 IEGR--IRQ Edge Select Register Bit H'F2 System Control 7 6 5 4 3 2 1 0 -- -- -- IEG4 -- -- IEG1 IEG0 Initial value 1 1 1 0 1 1 0 0 Read/Write -- -- -- R/W -- -- R/W R/W IRQ 4 Input Edge Select IRQ 0 Input Edge Select 0 Falling edge detected. 0 Falling edge detected. 1 Rising edge detected. 1 Rising edge detected. IRQ 1 Input Edge Select 0 Falling edge detected. 1 Rising edge detected. IENR1--Interrupt Enable Register 1 Bit H'F3 System Control 7 6 5 4 3 2 1 0 -- -- IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 Initial value 1 1 0 0 0 0 0 0 Read/Write -- -- R/W R/W R/W R/W R/W R/W IRQ 5 Interrupt Enable IRQ 0 Interrupt Enable 0 Interrupts disabled. 0 Interrupts disabled. 1 Interrupts enabled. 1 Interrupts enabled. IRQ 4 Interrupt Enable IRQ 1 Interrupt Enable 0 Interrupts disabled. 0 Interrupts disabled. 1 Interrupts enabled. 1 Interrupts enabled. IRQ 3 Interrupt Enable IRQ 2 Interrupt Enable 0 Interrupts disabled. 0 Interrupts disabled. 1 Interrupts enabled. 1 Interrupts enabled. 283 IENR2--Interrupt Enable Register 2 Bit H'F4 System Control 7 6 5 4 3 2 1 0 -- -- IENDT IENTE IENTD IENTC IENTB IENTA Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W DTON Interrupt Enable Timer A Interrupt Enable 0 Interrupts disabled. 0 Interrupts disabled. 1 Interrupts enabled. 1 Interrupts enabled. Timer E Interrupt Enable Timer B Interrupt Enable 0 Interrupts disabled. 0 Interrupts disabled. 1 Interrupts enabled. 1 Interrupts enabled. Timer D Interrupt Enable Timer C Interrupt Enable 0 Interrupts disabled. 0 Interrupts disabled. 1 Interrupts enabled. 1 Interrupts enabled. IENR3--Interrupt Enable Register 3 Bit 7 IENAD H'F5 System Control 6 5 4 3 2 1 0 --* -- -- -- -- IENS2 IENS1 Initial value 0 0 1 1 1 1 0 0 Read/Write R/W -- -- -- -- -- R/W R/W SCI1 Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled. A/D Conversion Complete Interrupt Enable 0 Interrupts disabled. SCI2 Interrupt Enable 1 Interrupts enabled. 0 Interrupts disabled. 1 Interrupts enabled. Note: * Read- and write-enabled. Always write 0 in this bit. 284 IRR1--Interrupt Request Register 1 Bit H'F6 System Control 7 6 5 4 3 2 1 0 -- -- IRRI5 IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 Initial value 1 1 0 0 0 0 0 0 Read/Write -- -- R/W* R/W* R/W* R/W* R/W* R/W* IRQ 5 Interrupt Request IRQ 0 Interrupt Request 0 No interrupt request 0 No interrupt request 1 Interrupt request 1 Interrupt request IRQ 4 Interrupt Request IRQ 1 Interrupt Request 0 No interrupt request 0 No interrupt request 1 Interrupt request 1 Interrupt request IRQ 3 Interrupt Request IRQ 2 Interrupt Request 0 No interrupt request 0 No interrupt request 1 Interrupt request 1 Interrupt request Note: * Only 0 can be written, to clear the flag. 285 IRR2--Interrupt Request Register 2 Bit H'F7 System Control 7 6 5 4 3 2 1 0 -- -- IRRDT IRRTE IRRTD IRRTC IRRTB IRRTA Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- R/W* R/W* R/W* R/W* R/W* R/W* DTON Interrupt Request Timer A Interrupt Request 0 No interrupt request 0 No interrupt request 1 Interrupt request 1 Interrupt request Timer E Interrupt Request Timer B Interrupt Request 0 No interrupt request 0 No interrupt request 1 Interrupt request raised 1 Interrupt request Timer D Interrupt Request Timer C Interrupt Request 0 No interrupt request 0 No interrupt request 1 Interrupt request 1 Interrupt request Note: * Only 0 can be written, to clear the flag. IRR3--Interrupt Request Register 3 Bit H'F8 System Control 7 6 5 4 3 2 1 0 IRRAD -- -- -- -- -- IRRS2 IRRS1 Initial value 0 0 1 1 1 1 0 0 Read/Write R/W* -- -- -- -- -- R/W* R/W* SCI1 Interrupt Request 0 No interrupt request 1 Interrupt request A/D Conversion Complete Interrupt Request 0 No interrupt request SCI2 Interrupt Request 1 Interrupt request 0 No interrupt request 1 Interrupt request Note: * Only 0 can be written, to clear the flag. 286 Appendix C I/O Port Block Diagrams C.1 Port 0 Block Diagram PMR0 (bit n) P0n Internal data bus A/D converter VIN SEL PMR0: Port mode register 0 n = 0 to 7 Figure C-1 Port 0 Block Diagram 287 C.2 Port 1 Block Diagram STBY VCC VCC Option PDR1 (bit n) P1n PMR1 (bit n) PCR1 (bit n) Internal data bus VSS IRQ P1 0 : P1 1 : P1 2 : P1 3 : P1 4 : PDR1: Port data register 1 PMR1: Port mode register 1 PCR1: Port control register 1 n = 0 to 4 Figure C-2 (a) Port 1 Block Diagram (Pins P10 to P14) 288 IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 STBY VCC Timer E VCC TMOE TEO Option PDR1 (bit 5) P15 PCR1 (bit 5) VSS PDR1: Port data register 1 PCR1: Port control register 1 TEO: Port mode register 4, bit 7 TMOE: Square wave output Figure C-2 (b) Port 1 Block Diagram (Pin P15) 289 Internal data bus STBY Option PMR1 (bit 6) P16 Internal data bus Timer D EVENT EDG (edge select) PMR1: Port mode register 1 Figure C-2 (c) Port 1 Block Diagram (Pin P16) Internal data bus P17 Figure C-2 (d) Port 1 Block Diagram (Pin P17) 290 C.3 Port 2 Block Diagram STBY VCC VCC Option PDR2 (bit n) P2n PCR2 (bit n) VSS PDR2: Port data register 2 PCR2: Port control register 2 n = 0 to 7 Figure C-3 Port 2 Block Diagram 291 Internal data bus C.4 Port 4 Block Diagram STBY VCC P4 n PDR4 (bit n) PDR4: Port data register 4 n = 0 to 5 Figure C-4 Port 4 Block Diagram 292 Internal data bus C.5 Port 8 Block Diagram STBY VCC VCC PDR8 (bit n) P8n PCR8 (bit n) GND PDR8: Port data register 8 PCR8: Port control register 8 n = 0 to 7 Figure C-5 Port 8 Block Diagram 293 Internal data bus C.6 Port 9 Block Diagram STBY VCC VCC PWM PWM Option PDR9 (bit 0) P90 PMR2 (bit 0) PCR9 (bit 0) VSS PDR9: Port data register 9 PMR2: Port mode register 2 PCR9: Port control register 9 Figure C-6 (a) Port 9 Block Diagram (Pin P90) 294 Internal data bus STBY SCI VCC EXCK VCC Option PDR9 (bit n) P9n PMR2 (bit n) PCR9 (bit n) VSS PDR9: Port data register 9 PMR2: Port mode register 2 PCR9: Port control register 9 n = 1 and 4 Figure C-6 (b) Port 9 Block Diagram (Pins P91 and P94) 295 SCKO SCKi Internal data bus STBY VCC VCC Option PDR9 (bit 2) P92 PMR2 (bit 2) PCR9 (bit 2) Internal data bus VSS SCI SI PDR9: Port data register 9 PMR2: Port mode register 2 PCR9: Port control register 9 Figure C-6 (c) Port 9 Block Diagram (Pin P92) 296 STBY VCC PMR3 P93 : bit 3 P96 : bit 6 VCC SCI SO Option PDR9 (bit n) P9n PMR2 (bit n) PCR9 (bit n) VSS PDR9: Port data register 9 PMR2: Port mode register 2 PCR9: Port control register 9 n = 3 and 6 Figure C-6 (d) Port 9 Block Diagram (Pins P93 and P96) 297 Internal data bus STBY VCC PMR3 (bit 5) VCC Option PDR9 (bit 5) P95 PMR2 (bit 5) PCR9 (bit 5) VSS PDR9: Port data register 9 PMR2: Port mode register 2 PCR9: Port control register 9 Figure C-6 (e) Port 9 Block Diagram (Pin P95) 298 SCI CS SI Internal data bus STBY VCC VCC Option PDR9 (bit 7) P97 PMR2 (bit 7) PCR9 (bit 7) Internal data bus VSS Timer C UD PDR9: Port data register 9 PMR2: Port mode register 2 PCR9: Port control register 9 Figure C-6 (f) Port 9 Block Diagram (Pin P97) 299 C.7 Port A Block Diagram STBY VCC VCC Option PDRA (bit n) PAn PCRA (bit n) VSS PDRA: Port data register A PCRA: Port control register A n = 0 to 7 Figure C-7 Port A Block Diagram 300 Internal data bus Appendix D Port States in Each Processing State Table D-1 Port States Mode Port Pins Reset Sleep Standby Watch Subactive Active P07 to P00 Hi-z Hi-z Hi-z Hi-z Hi-z Input port P17 Hi-z Hi-z Hi-z Hi-z Hi-z Input port P16 Hi-z or pull-up Hi-z or pull-up Hi-z Hi-z Hi-z Input port P15 to P10 Hi-z or pull-up prev. state Hi-z Hi-z Hi-z I/O port P45 to P40 Hi-z prev. state Hi-z Hi-z Hi-z I/O port P27 to P20 Hi-z or pull-up prev. state Hi-z Hi-z Hi-z I/O port P87 to P80 Hi-z or pull-up prev. state Hi-z Hi-z Hi-z I/O port P97 to P90 Hi-z or pull-up prev. state Hi-z Hi-z Hi-z I/O port PA7, to PA0 Hi-z or pull-up prev. state Hi-z Hi-z Hi-z I/O port Notation: Hi-z: High-impedance state Prev. state: Input pins are in high-impedance state. Output pins hold their previous output. Hi-z or pull-up: Standard ports for which the pull-up MOS mask option is chosen are in pull-up state; ports without the pull-up MOS option are in high-impedance state. Notes: 1. When pull-up MOS is chosen as a mask option with standard ports, the pull-ups are always on in active mode and sleep mode, regardless of the port control register (PCR) and port data register (PDR) settings. The pull-ups are off in power-down modes other than sleep mode. 2. The input gates of pins selected for peripheral function input remain on even in powerdown modes. This means the input levels must be fixed in order to avoid increased power dissipation. 301 Appendix E List of Mask Options HD6433612, HD6433613, and HD6433614 Please indicate the selected specifications by marking the appropriate box (with an x or mark). The shaded boxes cannot be selected. Date of order Company Address Name ROM code name LSI model no. (1) I/O Options C: No MOS pull-up P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/IRQ3 P14/IRQ4 P15/TMOE/IRQ5 P16/EVENT P17 P20 P21 P22 P23 P24 P25 P26 P27 I/O Standard pins Pin I/O option B C I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O I/O I/O (2) P40 to P45 are PMOS open-drain pins. (3) Package FP-64A DP-64S fOSC = fOSC = fOSC = Pin I/O HD6433613 I/O option B C I/O P80 I/O P81 I/O P82 I/O P83 I/O P84 I/O P85 I/O P86 I/O P87 I/O P90/PWM* I/O P91/SCK1 I/O P92/SI1 I/O P93/SO1 I/O P94/SCK2 I/O P95/SI2 I/O P96/SO2 I/O P97/UD I/O PA0 I/O PA1 I/O PA2 I/O PA3 I/O PA4 I/O PA5 I/O PA6 I/O PA7 Note: * The H8/3612 does not have a pulse width modulator. (5) Oscillator at X 1 and X2 (4) Oscillator at OSC 1 and OSC2 Crystal oscillator Ceramic oscillator External clock HD6433612 HD6433614 Standard pins B: With MOS pull-up , 19 MHz MHz MHz Used Not used fx = 32.768 kHz X1 = VCC Notes: 1. The wide temperature range specification and I specification are special specifications. There is no J specification for these products. Please contact your local Hitachi representative for details. 2. ROM data submitted in an EPROM must be written starting from address H'0000 in accordance with the memory map of the particular microcontroller. For data outside the ROM area on the memory map use H'FF. 302 Appendix F Package Dimensions Figures F-1 and F-2 show the external dimensions of the FP-64A and DP-64S packages, respectively, for H8/3614 Series. Unit: mm 17.2 0.3 14 33 48 32 0.80 17.2 0.3 49 64 17 1 0.1 +0.08 -0.05 0.17 1.6 0-5 0.1 2.70 0.15 M +0.20 -0.16 0.35 0.10 3.05 Max 16 0.8 - 0.3 Figure F-1 External Dimensions (FP-64A) Unit: mm 33 17.0 18.6 Max 64 57.6 58.50 Max 1.78 0.25 0.48 0.10 0.51 Min 32 1.0 2.54 Min 5.08 Max 1 19.05 + 0.11 0.25 - 0.05 0 - 15 Figure F-2 External Dimensions (DP-64S) 303