General Description
The MAX4843–MAX4846 overvoltage protection con-
trollers protect low-voltage systems against high-voltage
faults of up to 28V. When the input voltage exceeds the
overvoltage threshold, these devices turn off a low-cost,
external n-channel FET(s) to prevent damage to the pro-
tected components. An internal charge pump eliminates
the need for external capacitors and drives the FET gate
for a simple, robust solution.
The overvoltage trip level is set to 7.4V (MAX4843),
6.35V (MAX4844), 5.8V (MAX4845), or 4.65V
(MAX4846). When the input voltage drops below the
undervoltage lockout (UVLO) threshold, the devices
enter a low standby current mode (10µA). The
MAX4843/MAX4844/MAX4845 have a UVLO threshold
of 4.15V, the MAX4845C/MAX4845D have a UVLO
threshold of 2.2V, and the MAX4846 has a UVLO
threshold of 2.5V. In addition to the single FET configu-
ration, the devices can be configured with back-to-
back external FETs to prevent currents from being
back-driven into the adapter.
An additional feature includes a ±15kV ESD-protected
input when bypassed with a 1µF capacitor to ground.
All devices are offered in small 6-pin µDFN (1.5mm x
1.0mm) and 6-pin ultra-thin LGA (MAX4845 and
MAX4846 only) (1.5mm x 1.0mm) packages and are
specified for operation over the -40°C to +85°C temper-
ature range.
Applications
Cell Phones
Digital Still Cameras
PDAs and Palmtop Devices
MP3 Players
Features
♦Overvoltage Protection Up to 28V
♦Preset 7.4V, 6.35V, 5.8V, or 4.65V Overvoltage Trip
Level
♦Low (10µA) Undervoltage Lockout Standby
Current
♦Drives Low-Cost nMOSFET
♦Internal 50ms Startup Delay
♦Internal Charge Pump
♦Overvoltage Fault FLAG Indicator
♦6-Pin (1.5mm x 1.0mm) µDFN Package
MAX4843–MAX4846
Overvoltage Protection Controllers with
Low Standby Current
________________________________________________________________
Maxim Integrated Products
1
TOP VIEW
MAX4843–
MAX4846
N.C. GATE
1
N.C.
GND FLAG
IN
μDFN
23
654
MAX4845
MAX4846
N.C. GATE
1
N.C.
GND FLAG
IN
ULTRA-THIN LGA
23
654
PART PIN-
PACKAGE
UVLO
(V)
OVLO
(V)
TOP
MARK
MAX4843ELT 6 μDFN 4.15 7.40 BE
MAX4844ELT 6 μDFN 4.15 6.35 BF
MAX4845ELT 6 μDFN 4.15 5.80 BG
MAX4845EYT+T 6 UTLGA 4.15 5.80† AC
MAX4845CEYT+T 6 UTLGA 2.20 5.80† AP
MAX4845DEYT+T 6 UTLGA 2.20 5.80 AQ
MAX4846ELT 6 μDFN 2.50 4.65 BH
MAX4846EYT+T 6 UTLGA 2.50 4.65 AD
Pin Configurations
Ordering Information
MAX4843–
MAX4846
4
OUTPUT
GATE
FLAG
VIO
N
3
1IN
2GND
INPUT
+1.2V TO +28V
1μF
Typical Operating Circuit
19-3649; Rev 5; 12/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Note: All devices are specified over the -40°C to +85°C tem-
perature range.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
†OVLO maximum is 6.0V for the MAX4845C and 5.9V for the
MAX4845D.
MAX4843–MAX4846
Overvoltage Protection Controllers with
Low Standby Current
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = +5V for MAX4843/MAX4844/MAX4845, VIN = +4V for MAX4846, CGATE = 500pF, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN to GND ..............................................................-0.3V to +30V
GATE to GND ........................................................-0.3V to +12V
FLAG to GND ..........................................................-0.3V to +6V
Continuous Power Dissipation (TA= +70°C)
6-Pin µDFN (derate 2.1mW/°C above +70°C) .........167.7mW
6-Pin Ultra-Thin LGA (derate 2.1mW/°C
above +70°C) ...........................................................170.2mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .................................................... +150°C
Storage Temperature Range ............................-65°C to +150°C
Soldering Temperature (reflow)
6-Pin µDFN...................................................................+240°C
6-Pin Ultra-Thin LGA ....................................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Voltage Range VIN 1.2 28.0 V
MAX4843/MAX4844/MAX4845 3.9 4.15 4.4
MAX4845C/MAX4845D 1.8 2.2 2.5
Undervoltage Lockout Threshold UVLO VIN falling
MAX4846 2.3 2.5 2.7
V
MAX4843/MAX4844/MAX4845 41
Undervoltage Lockout
Hysteresis MAX4846 25
mV
MAX4843 7.0 7.4 7.8
MAX4844 6.0 6.35 6.7
MAX4845 5.5 5.8 6.1
MAX4845C 5.5 5.8 6.0
MAX4845D 5.5 5.8 5.9
Overvoltage Trip Level OVLO VIN rising
MAX4846 4.35 4.65 4.95
V
MAX4843 75
MAX4844 65
MAX4845 55
Overvoltage Lockout Hysteresis
MAX4846 50
mV
MAX4843/MAX4844/MAX4845 70 120
IN Supply Current IIN MAX4846 60 110
μA
VIN = 3.8V MAX4843/MAX4844/MAX4845 10 22
UVLO Supply Current IUVLO VIN = 2.2V MAX4846 8 18 μA
MAX4843/MAX4844/MAX4845 9 9.83 10
Gate Voltage VGATE 1μA load MAX4846 7.5 7.85 8.0
V
GATE Pulldown Current IPD V
IN > OVLO, VGATE = 5.5V 10 27 mA
FLAG Output Low Voltage VOL I
SINK = 1mA, FLAG deasserted 0.4 V
FLAG Leakage Current VFLAG = 5.5V, FLAG asserted 1 μA
MAX4843–MAX4846
Overvoltage Protection Controllers with
Low Standby Current
_______________________________________________________________________________________ 3
Note 1: All devices are 100% tested at +25°C. Electrical limits across the full temperature range are guaranteed by design and correlation.
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +5V for MAX4843/MAX4844/MAX4845, VIN = +4V for MAX4846, CGATE = 500pF, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING
Startup Delay tSTART VIN = UVLO rising to VGATE = 0.3V rising
(Figure 1) 20 50 80 ms
FLAG Blanking Time tBLANK VGATE = 0.3V rising to VFLAG = 0.3V falling
(Figure 1) 20 50 80 ms
Gate Turn-On Time tGON
VGATE = 0.3V to 8V
(MAX4843/MAX4844/MAX4845),
VGATE = 0.3V to 7V (MAX4846) (Figure 1)
10 ms
Gate Turn-Off Time tGOFF
VIN rising at 1V/μs from 5V to 8V
(MAX4843/MAX4844/MAX4845)
or from 4V to 7V (MAX4846)
to VGATE = 0.3V (Figure 2)
6 20 μs
FLAG Assertion Delay tFLAG
VIN rising at 1V/μs from 5V to 8V
(MAX4843/MAX4844/MAX4845)
or from 4V to 7V (MAX4846), to VFLAG =
2.4V, RFLAG = 10k to 3V (Figure 2)
5.8 μs
Initial Overvoltage Fault Delay tOVP
VIN rising at 1V/μs from 0V to 9V, time from
VIN = 5V to IGATE = 80% of IPD
(Figure 3)
1.5 μs
Typical Operating Characteristics
(VIN = +5V for MAX4843/MAX4844/MAX4845, VIN = +4V for MAX4846, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX4843)
MAX4843-46 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (μA)
252015105
20
40
60
80
100
0
030
REVERSE CURRENT vs. OUTPUT VOLTAGE
(MAX4843)
MAX4843-46 toc02
OUTPUT VOLTAGE (V)
REVERSE CURRENT (μA)
7
6
45
3
2
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
0.000001
1
BACK-TO-BACK FET
SINGLE FET
GATE VOLTAGE vs. INPUT VOLTAGE
(MAX4843/MAX4844/MAX4845)
MAX4843-46 toc03
INPUT VOLTAGE (V)
GATE VOLTAGE (V)
7654
3
6
9
12
15
0
38
MAX4843
MAX4844
MAX4845
MAX4843–MAX4846
Overvoltage Protection Controllers with
Low Standby Current
4 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VIN = +5V for MAX4843/MAX4844/MAX4845, VIN = +4V for MAX4846, TA= +25°C, unless otherwise noted.)
GATE VOLTAGE vs. INPUT VOLTAGE
(MAX4846)
MAX4843-46 toc04
INPUT VOLTAGE (V)
GATE VOLTAGE (V)
5432
2
4
6
8
10
0
16
GATE VOLTAGE vs. INPUT VOLTAGE
(MAX4843)
MAX4843-46 toc05
INPUT VOLTAGE (V)
GATE VOLTAGE (V)
7654
9.75
10.00
10.25
10.50
9.50
38
GATE CURRENT = 0
GATE
CURRENT = 1μA
POWER-UP RESPONSE
MAX4843-46 toc06
20ms/DIV
5V/DIV
VIN
VGATE
VFLAG
5V/DIV
0
0
5V/DIV
0
POWER-UP RESPONSE
MAX4843-46 toc07
20ms/DIV
5V/DIV
VIN
VOUT
IIN
VFLAG
5V/DIV
0
0
1A/DIV
0
5V/DIV
0
OVERVOLTAGE RESPONSE
MAX4843-46 toc08
4μs/DIV
5V/DIVVIN
VGATE
IGATE
VFLAG
10V/DIV
0
8V
0
10mA/DIV
0
5V/DIV
0
POWER-UP OVERVOLTAGE RESPONSE
MAX4843-46 toc09
20μs/DIV
5V/DIV
VIN
VGATE
VFLAG
2V/DIV
0
8V
0
5V/DIV
0
PIN
μDFN ULTRA-
THIN LGA
NAME FUNCTION
1 1 IN
Voltage Input. IN is both the power-supply input and the overvoltage sense input. Bypass IN
to GND with a 1μF capacitor or larger.
2 2 GND Ground
3 3 FLAG
Fault Indication Output. FLAG is asserted high during undervoltage lockout and overvoltage
lockout conditions. FLAG is deasserted during normal operation. FLAG is an open-drain
output.
4 4 GATE
Gate-Drive Output. GATE is the output of an on-chip charge pump. When VUVLO < VIN < VOVLO,
GATE is driven high to turn on the external n-channel MOSFET(s).
5, 6 5, 6 N.C. No Connection. Not internally connected. Do not connect.
Pin Description
MAX4843–MAX4846
Overvoltage Protection Controllers with
Low Standby Current
_______________________________________________________________________________________ 5
Functional Diagram
Figure 2. Shutdown Timing Diagram
tOVP
80%
VIN
0V
IGATE
VOVLO
MAX4843–
MAX4846
GATE DRIVER GATE
FLAG
2x CHARGE
PUMP
5.5V
REGULATOR
IN
GND
UVLO AND
OVLO
DETECTOR CONTROL
LOGIC AND
TIMER
tFLAG
tGOFF
0.3V
2.4V
VIN VOVLO
5V
VGATE
VFLAG
VUVLO
tGON
tBLANK
tSTART
5V
8V
0.3V
0.3V
VIN
VGATE
VFLAG
Figure 1. Startup Timing Diagram
Figure 3. Power-Up Overvoltage Timing Diagram
MAX4843–MAX4846
Overvoltage Protection Controllers with
Low Standby Current
6 _______________________________________________________________________________________
Detailed Description
The MAX4843–MAX4846 provide up to 28V overvoltage
protection for low-voltage systems. When the input volt-
age exceeds the overvoltage trip level, the
MAX4843–MAX4846 turn off a low-cost external n-chan-
nel FET(s) to prevent damage to the protected compo-
nents. An internal charge pump (see the
Functional
Diagram
) drives the FET gate for a simple, robust solu-
tion. On power-up, the device waits for 50ms before dri-
ving GATE high. The open-drain FLAG output is kept at
high impedance for an additional 50ms after GATE goes
high before deasserting. The FLAG output asserts high
immediately to an overvoltage fault.
Undervoltage Lockout (UVLO)
The MAX4843/MAX4844/MAX4845 have a fixed 4.15V
typical UVLO level, the MAX4845C/MAX4845D have a
2.2V typical UVLO, and the MAX4846 has a 2.5V typi-
cal UVLO. When VIN is less than the UVLO, the GATE
driver is held low and FLAG is asserted.
Overvoltage Lockout (OVLO)
The MAX4843 has a 7.4V typical OVLO; the MAX4844
has a 6.35V typical OVLO; and the MAX4845 has a
5.8V typical OVLO. The MAX4846 has a 4.65V typical
overvoltage threshold. When VIN is greater than OVLO,
the GATE driver is held low and FLAG is asserted.
FLAG Output
The open-drain FLAG output is used to signal to the
host system that there is a fault with the input voltage.
FLAG asserts immediately to an overvoltage fault.
FLAG is held high for 50ms after GATE turns on before
deasserting. Connect a pullup resistor from FLAG to
the logic I/O voltage of the host system.
GATE Driver
An on-chip charge pump is used to drive GATE above
IN, allowing the use of low-cost n-channel MOSFETs. The
charge pump operates from the internal 5.5V regulator.
The actual GATE output voltage tracks approximately
two times VIN until VIN exceeds 5.5V or the OVLO trip
level is exceeded, whichever comes first. The
MAX4843 has a 7.4V typical OVLO, therefore GATE
remains relatively constant at about 10.5V for 5.5V <
VIN < 7.4V. The MAX4845 has a 5.8V typical OVLO, but
this can be as low as 5.5V. The GATE output voltage as
a function of input voltage is shown in the
Typical
Operating Characteristics
.
Device Operation
The MAX4843–MAX4846 have an on-board state
machine to control device operation. A flowchart is
shown in Figure 4. On initial power-up, if VIN < UVLO or
if VIN > OVLO, GATE is held at 0V, and FLAG is high.
If UVLO < VIN < OVLO, the device enters startup after
a 50ms internal delay. The internal charge pump is
enabled, and GATE begins to be driven above VIN by
the internal charge pump. FLAG is held high during
startup until the FLAG blanking period expires, typically
50ms after the GATE starts going high. At this point the
device is in its on state.
At any time if VIN drops below UVLO or VIN is greater
than OVLO, FLAG is driven high and GATE is driven
to ground.
TIME STARTS
COUNTING
OVLO CHECK
GATE = 0
FLAG = HIGH
VIN < OVLO
VIN < UVLO
VIN > UVLO
t = 50ms
t = 50ms
VIN > OVLO
STARTUP
GATE DRIVEN HIGH
FLAG = HIGH
ON
GATE HIGH
FLAG = LOW
STANDBY
GATE = 0
FLAG = HIGH
Figure 4. State Diagram
Applications Information
MOSFET Configuration
The MAX4843–MAX4846 can be used with either a sin-
gle MOSFET configuration as shown in the
Typical
Operating Circuit
, or can be configured with a back-to-
back MOSFET as shown in Figure 5. The back-to-back
configuration has almost zero reverse current when the
input supply is below the output.
If reverse current leakage is not a concern, a single
MOSFET can be used. This approach has half the loss of
the back-to-back configuration when used with similar
MOSFET types and is a lower cost solution. Note that if
the input is actually pulled low, the output is also pulled
low due to the parasitic body diode in the MOSFET. If
this is a concern, the back-to-back configuration should
be used.
In a typical application of the MAX4846, an external
adapter with built-in battery charger is connected to IN
and a battery is connected to the source of the external
FET. When the adapter is unplugged, IN is directly con-
nected to the battery through the external FET. Since
the battery voltage is typically greater than 3V, the
GATE voltage stays high and the device remains pow-
ered by the battery.
MOSFET Selection
The MAX4843–MAX4846 are designed for use with
either a single n-channel MOSFET or dual back-to-back
n-channel MOSFETs. In most situations, MOSFETs with
RON specified for a VGS of 4.5V work well. If the input
supply is near the UVLO maximum of 3.5V, consider
using a MOSFET specified for a lower VGS voltage.
Also the VDS should be 30V for the MOSFET to with-
stand the full 28V IN range of the MAX4843–MAX4846.
Table 1 shows a selection of MOSFETs appropriate for
use with the MAX4843–MAX4846.
IN Bypass Considerations
For most applications, bypass IN to GND with a 1µF
ceramic capacitor. If the power source has significant
inductance due to long lead length, take care to pre-
vent overshoots due to the LC tank circuit and provide
protection if necessary to prevent exceeding the 30V
absolute maximum rating on IN.
The MAX4843–MAX4846 provide protection against
voltage faults up to 28V, but this does not include nega-
tive voltages. If negative voltages are a concern, con-
nect a Schottky diode from IN to GND to clamp
negative input voltages.
ESD Test Conditions
ESD performance depends on a number of conditions.
The MAX4843–MAX4846 are protected from ±15kV typ-
ical ESD on IN when IN is bypassed to ground with a
1µF ceramic capacitor.
MAX4843–MAX4846
Overvoltage Protection Controllers with
Low Standby Current
_______________________________________________________________________________________ 7
MAX4843–
MAX4846
4
GATE
FLAG
VIO
N
3
1IN
2GND
INPUT
+1.2V TO +28V
1μF
N
PART CONFIGURATION/
PACKAGE VDS MAX (V) RON at 4.5V (m) MANUFACTURER
Si5902DC Dual/1206-8 30 143
Si1426DH Single/SSOT-6 30 115
Vishay Siliconix
www.vishay.com
FDC6561AN Dual/SSOT-6 30 145
FDC6305N Dual/SSOT-6 20 80
Fairchild Semiconductor
www.fairchildsemi.com
Figure 5. Back-to-Back External MOSFET Configuration
Table 1. MOSFET Suggestions
MAX4843–MAX4846
Human Body Model
Figure 6 shows the Human Body Model and Figure 7
shows the current waveform it generates when dis-
charged into a low impedance. This model consists
of a 100pF capacitor charged to the ESD voltage of
interest, which is then discharged into the device
through a 1.5kΩresistor.
IEC 1000-4-2
Since January 1996, all equipment manufactured
and/or sold in the European Union has been required to
meet the stringent IEC 1000-4-2 specification. The IEC
1000-4-2 standard covers ESD testing and perfor-
mance of finished equipment; it does not specifically
refer to integrated circuits. The MAX4843–MAX4846
help users design equipment that meets Level 3 of IEC
1000-4-2, without additional ESD-protection compo-
nents.
The main difference between tests done using the
Human Body Model and IEC 1000-4-2 is higher peak
current in IEC 1000-4-2. Because series resistance is
lower in the IEC 1000-4-2 ESD test model (Figure 8),
the ESD withstand voltage measured to this standard is
generally lower than that measured using the Human
Body Model. Figure 9 shows the current waveform for
the ±8kV IEC 1000-4-2 Level 4 ESD Contact Discharge
test. The Air-Gap test involves approaching the device
with a charger probe. The Contact Discharge method
connects the probe to the device before the probe is
energized.
Overvoltage Protection Controllers with
Low Standby Current
8 _______________________________________________________________________________________
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1MΩ
RD
1.5kΩ
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 6. Human Body ESD Test Model
IP 100%
90%
36.8%
tRL TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
0
AMPERES
Figure 7. Human Body Model Current Waveform
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50MΩ TO 100MΩ
RD
330Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 8. IEC 1000-4-2 ESD Test Model
100%
90%
60ns
10%
tr = 0.7ns to 1ns
IPEAK
I
30ns t
Figure 9. IEC 1000-4-2 ESD Generator Current Waveform
MAX4843–MAX4846
Overvoltage Protection Switches with
Low Standby Current
_______________________________________________________________________________________ 9
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
6 µDFN L611-1 21-0147
6 UTLGA Y61A1-1 21-0190
MAX4843–MAX4846
Overvoltage Protection Switches with
Low Standby Current
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 4/05 Initial release —
3 2/08 Added packaging, removed SC70 1, 2, 4, 7, 9
4 8/09
Added MAX4845A and MAX4845C to Ordering Information and Electrical
Characteristics.1, 2
5 12/09
•Removed MAX4845A and added MAX4845D to Ordering Information and
Electrical Characteristics.
•Updated Undervoltage Lockout (UVLO) section under Detailed Description to
include MAX4845D.
1, 2, 6
