512Mb: x4, x8, x16 DDR SDRAM DOUBLE DATA RATE (DDR) SDRAM MT46V128M4 - 32 MEG x 4 x 4 BANKS MT46V64M8 - 16 MEG x 8 x 4 BANKS MT46V32M16 - 8 MEG x 16 x 4 BANKS For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/datasheets Features Figure 1: Pin Assignment (Top View) 66-pin TSOP * VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V * VDD = +2.6V 0.1V, VDDQ = +2.6V 0.1V (DDR400) * Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two - one per byte) * Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle * Differential clock inputs (CK and CK#) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; centeraligned with data for WRITEs * DLL to align DQ and DQS transitions with CK * Four internal banks for concurrent operation * Data mask (DM) for masking write data (x16 has two - one per byte) * Programmable burst lengths: 2, 4, or 8 * Auto Refresh and Self Refresh Modes * Longer lead TSOP for improved reliability (OCPL) * 2.5V I/O (SSTL_2 compatible) * Concurrent auto precharge option is supported * tRAS lockout supported (tRAP = tRCD) Options * Configuration 128 Meg x 4 (32 Meg x 4 x 4 banks) 64 Meg x 8 (16 Meg x 8 x 4 banks) 32 Meg x 16 (8 Meg x 16 x 4 banks) * Plastic Package 66-pin TSOP 66-pin TSOP Lead-free1 60-Ball FBGA (10 x 12.5mm) 60-Ball FBGA (10 x 12.5mm) Lead-free1 * Timing - Cycle Time 5ns @ CL = 3 (DDR400B)2 6ns @ CL = 2.5 (DDR333)3 (FBGA only) 6ns @ CL = 2.5 (DDR333)3 (TSOP only) 7.5ns @ CL = 2 (DDR266)4 7.5ns @ CL = 2 (DDR266A)5 7.5ns @ CL = 2.5 (DDR266B)6,7 * Self Refresh Standard Low-Power Self Refresh * Temperature Rating Standard Industrial Temperature (-40C to +85C) 09005aef80a1d9e7 512MBDDRx4x8x16_1.fm - Rev. H 7/04 EN x4 x8 x16 VDD VDD VDD NF DQ0 DQ0 VDDQ VDDQ VDDQ NC DQ1 NC DQ0 DQ1 DQ2 VSSQ VSSQ VssQ NC DQ3 NC NF DQ2 DQ4 VDDQ VDDQ VDDQ NC NC DQ5 DQ1 DQ3 DQ6 VSSQ VSSQ VssQ NC DQ7 NC NC NC NC VDDQ VDDQ VDDQ NC NC LDQS NC NC NC VDD VDD VDD DNU DNU DNU NC NC LDM WE# WE# WE# CAS# CAS# CAS# RAS# RAS# RAS# CS# CS# CS# NC NC NC BA0 BA0 BA0 BA1 BA1 BA1 A10/AP A10/AP A10/AP A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD Marking Configuration 128M4 64M8 32M16 Refresh Count Row Addressing Bank Addressing Column Addressing TG P FN BN 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS DNU VREF VSS UDM CK# CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x8 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x4 VSS NF VSSQ NC DQ3 VDDQ NC NF VSSQ NC DQ2 VDDQ NC NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 128 MEG x 4 64 MEG x 8 32 MEG x 16 32 Meg x 4 x 4 banks 8K 8K (A0-A12) 4(BA0, BA1) 4K (A0-A9, A11, A12) 16 Meg x 8 x 4 banks 8K 8K (A0-A12) 4(BA0, BA1) 2K (A0-A9, A11) 8 Meg x 16 x 4 banks 8K 8K (A0-A12) 4(BA0, BA1) 1K (A0-A9) Key Timing Parameters SPEED GRADE -5B -6 -6T -75E -75Z -75 -5B -6 6T -75E/ 75Z -75 NOTE: None L None IT 1 CLOCKRATE8 CL = 2 133 MHz 133 MHz 133 MHz 133 MHz CL = 2.5 167 MHz 200 MHz 167 MHz NA 167 MHz NA 133 MHz NA 100 MHz 133 MHz 1. 2. 3. 4. 5. 6. 7. 8. 9. DATA-OUT ACCESS DQS-DQ WINDOW9 WINDOW SKEW CL = 3 NA 1.6ns 2.1ns 2.0ns 2.5ns 0.70ns 0.70ns 0.70ns 0.75ns +0.40ns +0.40ns +0.45ns +0.50ns 2.5ns 0.75ns +0.50ns Contact Micron for availability of lead-free products Supports PC3200 modules with 3-3-3 timing Supports PC2700 modules with 2.5-3-3 timing Supports PC2100 modules with 2-2-2 timing Supports PC2100 modules with 2-3-3 timing Supports PC2100 modules with 2.5-3-3 timing Supports PC1600 modules with 2-2-2 timing CL = CAS (Read) Latency Minimum clock rate with a 50% Duty Cycle @ CL = 2 (-75E, 75Z) and CL = 2.5 (-6T,-75), and CL = 3 (-5B) (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 2: 512Mb DDR SDRAM Part Numbers edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full drive option outputs are SSTL_2, Class II compatible. Example Part Number: MT46V32M16TG-75Z MT46V Configuration Package Speed Special Temperature Options Operating Temp Configuration 128 Meg x4 128M4 64 Meg x8 64M8 32 Meg x16 32M16 Standard IT Special Options L Package 400 mil TSOP 400 mil TSOP Lead-Free Industrial Temp Low Power TG P 10 x 12.5mm FBGA FN 10 x 12.5mm FBGA Lead-Free BN -5B Speed Grade tCK=5ns, CL = 3 -6 tCK=6ns, CL = 2.5 -6T tCK=6ns, CL = 2.5 -75E tCK=7.5ns, CL = 2 -75Z tCK=7.5ns, CL = 2 -75 tCK=7.5ns, CL = 2.5 FBGA Part Number System Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on the Micron web site www.micron.com/decoder. General Description The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quadbank DRAM. The 512Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2nprefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-halfclock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte. The 512Mb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive 09005aef80a1d9e7 512MBDDRx4x8x16_1.fm - Rev. H 7/04 EN NOTE: 1. The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. 2. Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided into two bytes, the lower byte and upper byte. For the lower byte (DQ0 through DQ7) DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ8 through DQ15) DM refers to UDM and DQS refers to UDQS. 3. Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. 4. Any specific requirement takes precedence over a general statement. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 FBGA Part Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Power-down (CKE Not Active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 09005aef80a1d9e7 512MbDDRx4x8x16TOC.fm - Rev. H 7/04 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Pin Assignment (Top View) 66-pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 512Mb DDR SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Functional Block Diagram 128 Meg X 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Block Diagram 64 Meg X 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Functional Block Diagram 32 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Ball Assignment (Top View) 60-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK3 . . . . . . . . . . . . . . . . . . . . . .19 READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 READ Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Consecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 WRITE to READ - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 WRITE to READ - Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 WRITE to READ - Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 WRITE to PRECHARGE - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 WRITE to Precharge - Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 WRITE to PRECHARGE Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Input Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 SSTL_2 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Derating Data Valid Window (tQH - tDQSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Full Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Full Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Reduced Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Reduced Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 x4, x8 Data Output Timing - tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 x16 Data Output Timing - tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Data Output Timing - tAC and tDQSCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Initialization Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Initialize And Load Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Bank Read - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Bank Read - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Bank Write - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Bank Write - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Write - DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 66-Pin Plastic TSOP (400 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 60-Ball FBGA (10 x 12.5mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 09005aef80a1d9e7 512MbDDRx4x8x16LOF.fm - Rev. H 7/04 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Ball/Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Reserved NC Balls and Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Truth Table - Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Truth Table - DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Truth Table - CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Truth Table - Current State Bank n - Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Truth Table - Current State Bank n - Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 DC Electrical Characteristics and Operating Conditions (-6, -6T, -75E, -75Z, -75) . . . . . . . . . . . . . . .46 DC Electrical Characteristics and Operating Conditions (-5B DDR400) . . . . . . . . . . . . . . . . . . . . . . . .47 AC Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Clock Input Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Capacitance (x4, x8 TSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Capacitance (x4, x8 FBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Capacitance (x16 TSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Capacitance (x16 FBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 IDD Specifications and Conditions (x4, x8; -5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 IDD Specifications and Conditions (x4, x8; -6/-6T/-75E/-75Z/-75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 IDD Specifications and Conditions (x16; -5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 IDD Specifications and Conditions (x16; -6/-6T/-75E/-75Z/-75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 IDD Test Cycle Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Electrical Characteristics & Recommended AC Operating Conditions (-5B) . . . . . . . . . . . . . . . . . . . .57 Electrical Characteristics and Recommended AC Operating Conditions (-6/-6T/-75E) . . . . . . . . . .58 Electrical Characteristics and Recommended AC Operating Conditions (-75Z/-75) . . . . . . . . . . . . .59 Input Slew Rate Derating Values for Addresses and Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Input Slew Rate Derating Values for DQ, DQS, and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Normal Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Reduced Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 09005aef80a1d9e7 512MbDDRx4x8x16LOT.fm - Rev. H 7/04 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 3: Functional Block Diagram 128 Meg x 4 CKE CK# CK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTERS REFRESH 13 COUNTER 15 ROWADDRESS MUX 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 CK BANK0 MEMORY ARRAY (8,192 x 2,048 x 8) DLL DATA 4 8 READ LATCH SENSE AMPLIFIERS 4 MUX DRVRS 4 1 DQS GENERATOR 16384 DQ0- DQ3 COL0 I/O GATING DM MASK LOGIC 2 A0-A12, BA0, BA1 15 ADDRESS REGISTER 2 BANK CONTROL LOGIC 1 COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH DQS 1 MASK 2048 (x8) 12 DQS INPUT REGISTERS 8 11 8 WRITE FIFO & DRIVERS clk out 1 1 1 4 4 4 4 2 8 clk in DATA CK RCVRS DM 4 1 COL0 1 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 4: Functional Block Diagram 64 Meg x 8 CKE CK# CK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTERS REFRESH 13 COUNTER 15 ROWADDRESS MUX 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 CK BANK0 MEMORY ARRAY (8,192 x 1,024 x 16) READ LATCH SENSE AMPLIFIERS 8 MUX DRVRS 8 I/O GATING DM MASK LOGIC A0-A12, BA0, BA1 15 ADDRESS REGISTER 2 DQS INPUT REGISTERS 1 DQS 1 MASK COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH DQ0- DQ7 COL0 16 BANK CONTROL LOGIC 1024 (x16) 11 1 DQS GENERATOR 16384 2 DLL DATA 8 16 10 16 WRITE FIFO & DRIVERS clk out 1 1 1 8 8 8 8 2 16 clk in DATA CK RCVRS DM 8 1 COL0 1 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 5: Functional Block Diagram 32 Meg x 16 CKE CK# CK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 REFRESH COUNTER 13 MODE REGISTERS ROWADDRESS MUX 15 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 CK BANK0 MEMORY ARRAY (8,192 x 256 x 32) READ LATCH SENSE AMPLIFIERS 16 MUX DRVRS 16 2 DQS GENERATOR 16384 DQ0 DQ15 COL0 I/O GATING DM MASK LOGIC 2 A0-A12, BA0, BA1 15 ADDRESS REGISTER 2 32 2 9 32 WRITE FIFO & DRIVERS clk out LDQS UDQS 2 MASK COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH DQS INPUT REGISTERS BANK CONTROL LOGIC 512 (x32) 10 DLL DATA 16 32 2 2 2 16 16 16 16 4 32 clk in DATA CK RCVRS 16 LDM, UDM 2 COL0 1 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 1: Ball/Pin Descriptions FBGA NUMBERS TSOP NUMBERS SYMBOL TYPE DESCRIPTION G2, G3 45, 46 CK, CK# Input H3 44 CKE Input H8 24 CS# Input H7, G8, G7 3F F7, 3F 23, 22, 21 47 20, 47 RAS#, CAS#, WE# DM LDM, UDM Input J8, J7 26, 27 BA0, BA1 Input K7, L8, L7, M8, M2, L3, L2, K3, K2, J3, K8, J2,H2 29, 30, 31, 32, 35, 36, 37, 38, 39, 40, 28 41, 42 A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12 Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER- DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH, after which it becomes a SSTL_2 input only. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. For the x16, LDM is DM for DQ0-DQ7 and UDM is DM for DQ8- DQ15. Pin 20 is a NC on x4 and x8. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN Input 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 1: Ball/Pin Descriptions (Continued) FBGA NUMBERS TSOP NUMBERS A8, B9, B7, C9, C7, D9, D7, E9, E1, D3, D1, C3, C1, B3, B1, A2 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 - 14, 17, 25, 43, 53 2, 5, 8, 11, 56, 59, 62, 65 4, 7, 10, 13, 14, 16, 17, 20, 25, 43, 53, 54, 57, 60, 63, 5, 11, 56, 62 4, 7, 10, 13, 14, 16, 17, 20, 25, 43, 53, 54, 57, 60, 63 2, 8, 59, 65 A8, B7, C7, D7, D3, C3, B3, A2 B1, B9, C1, C9, D1, D9, E1, E7, E9, F7 B7, D7, D3, B3 B1, B9, C1, C9, D1, D9, E1, E7, E9, F7 A2, A8, C3, C7 E3 E7 E3 F9 51 16 51 19, 50 B2, D2, C8, 3, 9, 15, 55, E8, A9 61 A1, C2, E2, 6, 12, 52, B8, D8 58, 64 F8, M7, A7 1, 18, 33 A3, F2, M3 34, 48, 66 F1 49 Table 2: TYPE DQ0-DQ2 DQ3-DQ5 DQ6-DQ8 DQ9-DQ11 DQ12- DQ14 DQ15 NC I/O DQ0-DQ2 DQ3-DQ5 DQ6, DQ7 NC I/O DQ0-DQ2 DQ3 NC I/O - No Connect for x4 These pins should be left unconnected. NF - DQS LDQS UDQS I/O No Function for x4 These pins should be left unconnected. Data Strobe: Output with read data, input with write data. DQS is edgealigned with read data, centered in write data. It is used to capture data. For the x16, LDQS is DQS for DQ0-DQ7 and UDQS is DQS for DQ8-DQ15. Pin 16 (E7) is NC on x4 and x8. DNU VDDQ - - - DESCRIPTION Data Input/Output: Data bus for x16 No Connect for x16 These pins should be left unconnected. Data Input/Output: Data bus for x8 No Connect for x8 These pins should be left unconnected. Data Input/Output: Data bus for x4 Do Not Use: Must float to minimize noise on VREF. VSSQ Supply DQ Power Supply: +2.5V 0.2V (+2.6V 0.1V for DDR400). Isolated on the die for improved noise immunity. Supply DQ Ground. Isolated on the die for improved noise immunity. VDD VSS VREF Supply Power Supply: +2.5V 0.2V. (+2.6V 0.1V for DDR400) Supply Ground. Supply SSTL_2 reference voltage. Reserved NC Balls and Pins1 FBGA TSOP NUMBERS NUMBERS F9 SYMBOL 17 SYMBOL TYPE A13 I DESCRIPTION Address input A13 for 1Gb devices. NOTE: 1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins deemed to be of importance. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 6: Ball Assignment (Top View) 60-Ball FBGA x4 (Top View) 1 2 3 4 NF VSSQ VSS NC VDDQ DQ3 NC VSSQ NF NC VDDQ DQ2 NC VSSQ DQS VSS VREF DM CK CK# A12 CKE A11 A9 A8 A7 A6 A5 A4 VSS 5 6 7 8 VDD DQ0 NF DQ1 NC NC WE# RAS# BA1 A0 A2 VDD A B C D E F G H J K L M 9 NF VDDQ VSSQ NC VDDQ NC VSSQ NC VDDQ NC VDD NC CAS# CS# BA0 A10 A1 A3 x8 (Top View) 1 2 VSSQ DQ7 NC VDDQ NC VSSQ NC VDDQ NC VSSQ VSS VREF CK A12 A11 A8 A6 A4 3 4 VSS DQ6 DQ5 DQ4 DQS DM CK# CKE A9 A7 A5 VSS 5 6 7 8 VDD DQ1 DQ2 DQ3 NC NC WE# RAS# BA1 A0 A2 VDD A B C D E F G H J K L M 9 DQ0 VDDQ VSSQ NC VDDQ NC VSSQ NC VDDQ NC VDD NC CAS# CS# BA0 A10 A1 A3 x16 (Top View) 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 1 2 3 VSSQ DQ14 DQ12 DQ10 DQ8 VREF DQ15 VDDQ VSSQ VDDQ VSSQ VSS CK A12 A11 A8 A6 A4 VSS DQ13 DQ11 DQ9 UDQS UDM CK# CKE A9 A7 A5 VSS 4 5 A B C D E F G H J K L M 11 6 7 8 9 VDD DQ2 DQ4 DQ6 LDQS LDM WE# RAS# BA1 A0 A2 VDD DQ0 VSSQ VDDQ VSSQ VDDQ VDD CAS# CS# BA0 A10 A1 A3 VDDQ DQ1 DQ3 DQ5 DQ7 NC Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Functional Description driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200s delay prior to applying an executable command. Once the 200s delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal operation. The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The 512Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 512Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2nprefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM consists of a single 2n-bit wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. Register Definition Mode Register The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 7 on page 13. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. Initialization DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD and VDDQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VDDQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. After CKE passes through VIH, it will transition to a SSTL 2 signal and remain as such until power is cycled. Maintaining an LVCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 7: Mode Register Definition Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 7. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 Operating Mode 0* 0* 6 5 4 3 2 1 0 CAS Latency BT Burst Length * M14 and M13 (BA1 and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register). 0 0 0 Reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M12 M11 M10 M9 M8 M7 Burst Type 0 Sequential 1 Interleaved M6 M5 M4 13 Mode Register (Mx) M2 M1 M0 Burst Length M3 Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 3, Burst Definition, on page 14. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 7 Address Bus CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 (DDR400 Only) 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved M6-M0 Operating Mode 0 0 0 0 0 0 Valid Normal Operation 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - - - - - - - All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 3: Figure 8: CAS Latency Burst Definition BURST LENGTH STARTING COLUMN ADDRESS 2 T1 T2 READ NOP NOP T2n T3 T3n CK COMMAND TYPE= INTERLEAVED NOP CL = 2 A0 4 8 TYPE= SEQUENTIAL T0 CK# ORDER OF ACCESSES WITHIN A BURST DQS 0 0-1 0-1 1 1-0 1-0 A1 A0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 DQ CK# T0 T1 T2 READ NOP NOP T2n T3 T3n CK COMMAND NOP CL = 2.5 DQS A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 CK# 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 CK 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 COMMAND 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 DQ T0 T1 T2 READ NOP NOP T3 T3n NOP CL = 3 DQS DQ NOTE: 1. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ TRANSITIONING DATA 2. For a burst length of two, A1-Ai select the twodata-element block; A0 selects the first access within the block. Table 4: 3. For a burst length of four, A2-Ai select the fourdata-element block; A0-A1 select the first access within the block. CAS Latency (CL) ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) 4. For a burst length of eight, A3-Ai select the eightdata-element block; A0-A2 select the first access within the block. SPEED CL = 2 CL = 2.5 CL = 3 -5B 75 f 133 75 f 133 75 f 133 75 f 133 75 f 100 75 f 167 75 f 167 75 f 133 75 f 133 75 f 133 133 f 200 - -6/-6T Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 (DDR400 only) clocks, as shown in Figure 8. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 4, CAS Latency (CL), on page 14 indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN DON'T CARE -75E -75Z -75 Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM DLL Enable/Disable When the part is running without the DLL enabled, device functionality may be altered. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE HIGH must occur before a READ command can be issued. the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used, as unknown operation or incompatibility with future versions may result. Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, and output drive strength. These functions are controlled via the bits shown in Figure 9. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. Figure 9: Extended Mode Register Definition BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 7 6 5 Operating Mode 01 11 E12 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 3 2 1 0 Extended Mode Register (Ex) DS DLL E0 DLL 0 Enable 1 Disable Drive Strength 0 Normal 1 Reduced E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E23 Output Drive Strength The normal drive strength for all outputs are specified to be SSTL2, Class II. The x16 supports a programmable option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQ pins and DQS pins from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength. 4 E1, E0 Operating Mode 0 0 0 0 0 0 0 0 0 0 0 Valid Reserved - - - - - - - - - - - - Reserved NOTE: Address Bus 1. E14 and E13 (BA1 and BA0) must be "0, 1" to select the Extended Mode Register vs. the base Mode Register. 2. The reduced drive strength option is not supported on the x4 and x8 versions, and is only available on the x16 version. 3. The QFC# option is not supported. 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Commands Table 5 and Table 6 provide a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Table 5: Tables--Table 8 on page 42, and Table 9 on page 44-- appear following "Operations" on page 19 and provide current state/next state information. Truth Table - Commands Note 1 applies to all commands. NAME (FUNCTION) DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER CS# RAS# CAS# WE# ADDR NOTES H L L L L L L L X H L H H H L L X H H L L H H L X H H H L L L H X X Bank/Row Bank/Col Bank/Col X Code X 9 9 3 4 4 8 5 6, 7 L L L L Op-Code 2 NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A12 provide the opcode to be written to the selected mode register. 3. BA0-BA1 provide bank address and A0-A12 provide row address. 4. BA0-BA1 provide bank address; A0-Ai provide column address, (where i=9 for x16, i=9,11 for x8, and i=9,11,12 for x4) A10 HIGH enables the auto precharge feature (non persistent), and A10 LOW disables the auto precharge feature. 5. A10 LOW: BA0-BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0-BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; for within the Self Refresh mode all inputs and I/Os are "Don't Care" except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 9. DESELECT and NOP are functionally interchangeable. Table 6: Truth Table - DM Operation Note 1 applies to all commands NAME (FUNCTION) DM DQ Write Enable Write Inhibit L H Valid X NOTE: 1. Used to mask write data; provided coincident with the corresponding data. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM DESELECT being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (CS# is LOW with RAS#, CAS#, and WE# are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. LOAD MODE REGISTER The mode registers are loaded via inputs A0-A12. See mode register descriptions in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t MRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank. A precharge command must be issued before opening a different row in the same bank. Auto Precharge READ Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. This device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This "earliest valid stage" is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS (MIN), as described The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai (where i = 9 for x16, 9, 11 for x8, or 9, 11, 12 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai (where i = 9 for x16, 9, 11 for x8, or 9, 11, 12 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates. Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends tRFC later. for each burst type in "Operations" on page 19. The user must not issue another command to the same bank until the precharge time (tRP) is completed. BURST TERMINATE The BURST TERMINATE command is used to truncate read bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as shown in "Operations" on page 19. The open page which the READ burst was terminated from remains open. SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (A DLL reset and 200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are "Don't Care" during SELF REFRESH. VREF voltage is also required for the full duration of SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for tXSNR time, then a DLL Reset and NOPs for 200 additional clock cycles before applying any other command. AUTO REFRESH AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS#-BEFORERAS# (CBR) refresh in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All banks must be idle before an AUTO REFRESH command is issued. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during an AUTO REFRESH command. The 512Mb DDR SDRAM requires AUTO REFRESH cycles at an average interval of 7.8125s (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 7.8125s (70.3s). Note the JEDEC specifications only allows 8 x 7.8125s, thus the Micron specification exceeds the JEDEC requirement by one clock. This maximum 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Operations Bank/Row Activation head. The minimum time interval between successive ACTIVE commands to different banks is defined by t RRD. Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated, as shown in Figure 10. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 133 MHz clock (7.5ns period) results in 2.7 clocks rounded to 3. This is reflected in Figure 11, which covers any case where 2 < t RCD (MIN)/tCK 3. (Figure 11 also shows the same case for tRCD; the same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access over- Figure 10: Activating a Specific Row in a Specific Bank CK# CK CKE HIGH CS# RAS# CAS# WE# A0-A12 RA BA0, BA1 BA RA = Row Address BA = Bank Address Figure 11: Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK3 T0 T1 ACT NOP T2 T3 T4 T5 T6 T7 NOP NOP RD/WR NOP CK# CK COMMAND A0-A12 BA0, BA1 NOP Row ACT Row Bank x Col Bank y Bank y tRCD tRRD DON'T CARE 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM READs command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 14 on page 23. A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive read data is shown for illustration in Figure 15 on page 24. Full-speed random read accesses within a page (or pages) can be performed, as shown in Figure 16 on page 25. Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 17 on page 26. The BURST TERMINATE latency is equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure 18 on page 27. The tDQSS (NOM) case is shown; the tDQSS (MAX) case has a longer bus idle time. (tDQSS [MIN] and tDQSS [MAX] are defined in the section on WRITEs.) A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto precharge was not activated. The PRECHARGE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 19 on page 28. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until both tRAS and tRP has been met. Note that part of the row precharge time is hidden during the access of the last data elements. READ bursts are initiated with a READ command, as shown in Figure 12 on page 21. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. NOTE: For the READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of CK and CK#). Figure 13 on page 22 shows general timing for each possible CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go HighZ. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out window hold), the valid data window are depicted in Figure 40 on page 67 and Figure 41 on page 68. A detailed explanation of tDQSCK (DQS transition skew to CK) and tAC (data-out transition skew to CK) is depicted in Figure 42 on page 69. Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles after the first READ 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 12: READ Command CK# CK CKE HIGH CS# RAS# CAS# WE# x4: A0-A9, A11, A12 x8: A0-A9, A11 x16: A0-A9 CA x8: A12 x16: A11, A12 EN AP A10 DIS AP BA0,1 BA CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge DON'T CARE 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 13: READ Burst T0 T1 T2 T2n READ NOP NOP T3 T3n T4 T5 NOP NOP T4 T5 NOP NOP CK# CK COMMAND ADDRESS NOP Bank a, Col n CL = 2 DQS DO n DQ T0 T1 T2 T2n READ NOP NOP T3 T3n CK# CK COMMAND ADDRESS NOP Bank a, Col n CL = 2.5 DQS DO n DQ T0 T1 T2 T3 T3n READ NOP NOP NOP T4 T4n T5 CK# CK COMMAND ADDRESS NOP NOP Bank a, Col n CL = 3 DQS DO n DQ DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. DO n = data-out from column n. Burst length = 4. Three subsequent elements of data-out appear in the programmed order following DO n. Shown with nominal tAC, tDQSCK, and tDQSQ. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 14: Consecutive READ Bursts T0 T1 T2 T2n COMMAND READ NOP READ ADDRESS Bank, Col n T3 T3n T4 T4n T5 T5n CK# CK NOP NOP NOP Bank, Col b CL = 2 DQS DO n DQ T0 T1 T2 COMMAND READ NOP READ ADDRESS Bank, Col n DO b T2n T3 T3n T4 T4n T5 T5n CK# CK NOP NOP NOP Bank, Col b CL = 2.5 DQS DO n DQ DO b T0 T1 T2 T3 T3n COMMAND READ NOP READ NOP ADDRESS Bank, Col n T4 T4n T5 T5n CK# CK NOP NOP Bank, Col b CL = 3 DQS DO n DQ DON'T CARE DO b TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. 6. DO n (or b) = data-out from column n (or column b). Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first). Three subsequent elements of data-out appear in the programmed order following DO n. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b. Shown with nominal tAC, tDQSCK, and tDQSQ. Example applies only when READ commands are issued to same device. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 15: Nonconsecutive READ Bursts T0 T1 T2 COMMAND READ NOP NOP ADDRESS Bank, Col n T2n T3 T3n T4 T5 NOP NOP T5n T6 CK# CK READ NOP Bank, Col b CL = 2 DQS DO n DQ T0 T1 T2 COMMAND READ NOP NOP ADDRESS Bank, Col n DO b T2n T3 T3n T4 T5 NOP NOP T5n T6 CK# CK READ NOP Bank, Col b CL = 2.5 DQS DO n DQ DO b T0 T1 T2 T3 T3n COMMAND READ NOP NOP READ ADDRESS Bank, Col n T4 T4n T5 T6 NOP NOP CK# CK NOP Bank, Col b CL = 3 DQS DO n DQ DO b DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. DO n (or b) = data-out from column n (or column b). Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first). Three subsequent elements of data-out appear in the programmed order following DO n. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b. Shown with nominal tAC, tDQSCK, and tDQSQ. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 16: Random READ Accesses T0 T1 T2 T2n T3 T3n T4 COMMAND READ READ READ READ ADDRESS Bank, Col n Bank, Col x Bank, Col b Bank, Col g T4n T5 T5n CK# CK NOP NOP CL = 2 DQS DO n DQ DO n' DO x T0 T1 T2 T2n T3 COMMAND READ READ READ READ ADDRESS Bank, Col n Bank, Col x Bank, Col b Bank, Col g DO x' T3n DO b T4 DO b' T4n DO g T5 T5n CK# CK NOP NOP CL = 2.5 DQS DO n DQ DO n' T0 T1 T2 T3 COMMAND READ READ READ READ ADDRESS Bank, Col n Bank, Col x Bank, Col b Bank, Col g DO x T3n DO x' T4 DO b T4n DO b' T5 T5n CK# CK NOP NOP CL = 3 DQS DO n DQ DO n' DON'T CARE DO x DO x' DO b DO b' TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. DO n (or x or b or g) = data-out from column n (or column x or column b or column g). Burst length = 2, 4, or 8 (if 4 or 8, the following burst interrupts the previous). n' or x' or b' or g' indicates the next data-out following DO n or DO x or DO b or DO g, respectively. READs are to an active row in any bank. Shown with nominal tAC, tDQSCK, and tDQSQ. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 17: Terminating a READ Burst T0 T1 T2 T2n READ BST5 NOP T3 T4 T5 NOP NOP NOP T3 T4 T5 NOP NOP NOP T4 T5 NOP NOP CK# CK COMMAND ADDRESS Bank a, Col n CL = 2 DQS DO n DQ T0 T1 T2 T2n READ BST5 NOP CK# CK COMMAND ADDRESS Bank a, Col n CL = 2.5 DQS DO n DQ T0 T1 T2 T3 READ BST5 NOP NOP T3n CK# CK COMMAND ADDRESS Bank a, Col n CL = 3 DQS DO n DQ DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. DO n = data-out from column n. Burst length = 4. Subsequent element of data-out appears in the programmed order following DO n. Shown with nominal tAC, tDQSCK, and tDQSQ. BST = BURST TERMINATE command, page remains open. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 18: READ to WRITE T0 T1 T2 COMMAND READ BST7 NOP ADDRESS Bank, Col n T2n T3 T4 T4n T5 T5n CK# CK WRITE NOP NOP Bank, Col b tDQSS (NOM) CL = 2 DQS DO n DQ DI b DM T0 T1 T2 COMMAND READ BST7 NOP ADDRESS Bank, Col n T2n T3n T3 T4 T5 T5n CK# CK NOP WRITE NOP Bank, Col b tDQSS (NOM) CL = 2.5 DQS DO n DQ DI b DM T0 T1 T2 T3 READ BST7 NOP NOP T3n T4 T5 T5n CK# CK COMMAND ADDRESS WRITE NOP Bank a, Col n tDQSS (NOM) CL = 3 DQS DO n DQ DI b DM DON'T CARE TRANSITIONING DATA NOTE: 1. DO n = data-out from column n. 2. DI b = data-in from column b. 3. Burst length = 4 in the cases shown (applies for bursts of 8 as well; if the burst length is 2, the BST command shown can be NOP). 4. One subsequent element of data-out appears in the programmed order following DO n. 5. Data-in elements are applied following DI b in the programmed order. 6. Shown with nominal tAC, tDQSCK, and tDQSQ. 7. BST = BURST TERMINATE command, page remains open. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 19: READ to PRECHARGE T0 T1 T2 T2n READ NOP PRE T3 T3n T4 T5 NOP ACT CK# CK COMMAND6 ADDRESS Bank a, Col n NOP Bank a, (a or all) Bank a, Row tRP CL = 2 DQS DO n DQ T0 T1 T2 READ NOP PRE T2n T3 T3n T4 T5 NOP ACT CK# CK COMMAND6 ADDRESS Bank a, Col n NOP Bank a, (a or all) Bank a, Row tRP CL = 2.5 DQS DO n DQ T0 T1 T2 T3 T3n READ NOP PRE NOP T4 T4n T5 CK# CK COMMAND6 ADDRESS Bank a, Col n NOP Bank a, (a or all) ACT Bank a, Row tRP CL = 3 DQS DO n DQ DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. 6. DO n = data-out from column n. Burst length = 4, or an interrupted burst of 8. Three subsequent elements of data-out appear in the programmed order following DO n. Shown with nominal tAC, tDQSCK, and tDQSQ. READ to PRECHARGE equals two clocks, which allows two data pairs of data-out. A READ command with AUTO-PRECHARGE enabled, provided tRAS(MIN) is met, would cause a precharge to be performed at x number of clock cycles after the READ command, where x = BL / 2. 7. PRE = PRECHARGE command; ACT = ACTIVE command. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM WRITEs Figure 20: WRITE Command WRITE bursts are initiated with a WRITE command, as shown in Figure 20. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst and after the tWR time. NOTE: CK# CK CKE CS# RAS# For the WRITE commands used in the following illustrations, auto precharge is disabled. CAS# During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble. WE# x4: A0-A9, A11, A12 x8: A0-A9, A11 x16: A0-A9 CA x8: A12 x16: A11, A12 EN AP A10 The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one clock cycle). All of the WRITE diagrams show the nominal case, and where the two extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Figure 21 on page 30 shows the nominal case and the extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored. DIS AP BA0,1 DON'T CARE BA CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without truncating the WRITE burst, tWTR should be met, as shown in Figure 25 on page 34. Data for any WRITE burst may be truncated by a subsequent READ command, as shown in Figure 26 on page 35. Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in should be masked with DM, as shown in Figure 27 on page 36. Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, tWR should be me,t as shown in Figure 28 on page 37. Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figure 29 on page 38 and Figure 30 on page 39. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data-in should be masked with DM as shown in Figures 29 and 30. After the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any positive edge of clock following the previous WRITE command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued x cycles after the first WRITE command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). Figure 22 on page 31 shows concatenated bursts of 4. An example of nonconsecutive WRITEs is shown in Figure 23 on page 32. Full-speed random write accesses within a page or pages can be performed as shown in Figure 24 on page 33. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN HIGH 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 21: WRITE Burst T0 T1 T2 COMMAND WRITE NOP NOP ADDRESS Bank a, Col b T2n T3 CK# CK NOP tDQSS (NOM) DQS tDQSS DI b DQ DM tDQSS (MIN) DQS DQ tDQSS DI b DM tDQSS (MAX) DQS DQ tDQSS DI b DM DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. DI b = data-in for column b. Three subsequent elements of data-in are applied in the programmed order following DI b. An uninterrupted burst of 4 is shown. A10 is LOW with the WRITE command (auto precharge is disabled). 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 22: Consecutive WRITE to WRITE T0 T1 COMMAND WRITE NOP ADDRESS Bank, Col b T1n T2 T2n T3 T3n T4 T4n T5 CK# CK tDQSS (NOM) WRITE NOP NOP NOP Bank, Col n tDQSS DQS DQ DI b DI n DM DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. DI b, etc. = data-in for column b, etc. Three subsequent elements of data-in are applied in the programmed order following DI b. Three subsequent elements of data-in are applied in the programmed order following DI n. An uninterrupted burst of 4 is shown. Each WRITE command may be to any bank. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 23: Nonconsecutive WRITE to WRITE T0 T1 COMMAND WRITE NOP ADDRESS Bank, Col b T1n T2 T2n T3 T4 T4n T5 T5n CK# CK tDQSS (NOM) NOP WRITE NOP NOP Bank, Col n tDQSS DQS DQ DI n DI b DM DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. DI b, etc. = data-in for column b, etc. Three subsequent elements of data-in are applied in the programmed order following DI b. Three subsequent elements of data-in are applied in the programmed order following DI n. An uninterrupted burst of 4 is shown. Each WRITE command may be to any bank. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 24: Random WRITE Cycles T0 T1 T1n T2 T2n T3 T3n T4 COMMAND WRITE WRITE WRITE WRITE WRITE ADDRESS Bank, Col b Bank, Col x Bank, Col n Bank, Col a Bank, Col g T4n T5 T5n CK# CK NOP tDQSS (NOM) DQS DQ DI b DI b' DI x DI x' DI n DI n' DI a DI a' DI g DI g' DM DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. DI b, etc. = data-in for column b, etc. b', etc. = the next data-in following DI b, etc., according to the programmed burst order. Programmed burst length = 2, 4, or 8 in cases shown. Each WRITE command may be to any bank. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 25: WRITE to READ - Uninterrupting T0 T1 WRITE NOP T1n T2 T2n T3 T4 T5 T6 T6n NOP READ NOP NOP CK# CK COMMAND NOP tWTR ADDRESS Bank a, Col b tDQSS (NOM) Bank a, Col n tDQSS CL = 2 DQS DI b DQ DO n DM tDQSS (MIN) tDQSS CL = 2 DQS DI b DQ DO n DM tDQSS (MAX) tDQSS CL = 2 DQS DQ DI b DO n DM DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. DI b = data-in for column b, DO n = data-out for column n. Three subsequent elements of data-in are applied in the programmed order following DI b. An uninterrupted burst of 4 is shown. t WTR is referenced from the first positive CK edge after the last data-in pair. The READ and WRITE commands are to same device. However, the READ and WRITE commands may be to different devices, in which case tWTR is not required and the READ command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled). 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 26: WRITE to READ - Interrupting T0 T1 WRITE NOP T1n T2 T2n T3 T3n T4 T5 NOP NOP T5n T6 T6n CK# CK COMMAND NOP READ NOP tWTR ADDRESS Bank a, Col b tDQSS (NOM) Bank a, Col n tDQSS CL = 2 DQS DI b DQ DO n DM tDQSS (MIN) tDQSS CL = 2 DQS DI b DQ DO n DM tDQSS (MAX) tDQSS CL = 2 DQS DQ DI b DO n DM DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. 6. 7. DI b = data-in for column b, DO n = data-out for column n. An interrupted burst of 4 is shown; two data elements are written. One subsequent element of data-in is applied in the programmed order following DI b. tWTR is referenced from the first positive CK edge after the last data-in pair. A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T2 and T2n (nominal case) to register DM. If the burst of 8 was used, DM and DQS would be required at T3 and T3n because the READ command would not mask these two data elements. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 27: WRITE to READ - Odd Number of Data, Interrupting T0 T1 WRITE NOP T1n T2 T2n T3 T3n T4 T5 NOP NOP T5n T6 T6n CK# CK COMMAND NOP READ NOP tWTR ADDRESS Bank a, Col b tDQSS (NOM) Bank a, Col n tDQSS CL = 2 DQS DI b DQ DO n DM tDQSS (MIN) tDQSS CL = 2 DQS DI b DQ DO n DM tDQSS (MAX) tDQSS CL = 2 DQS DQ DI b DO n DM DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. 6. DI b = data-in for column b, DO n = data-out for column n. An interrupted burst of 4 is shown; one data element is written. tWTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements). A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T1n, T2, and T2n (nominal case) to register DM. If the burst of 8 was used, DM and DQS would be required at T3 - T3n because the READ command would not mask these data elements. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 28: WRITE to PRECHARGE - Uninterrupting T0 T1 WRITE NOP T1n T2 T2n T3 T4 T5 NOP PRE7 T6 CK# CK COMMAND NOP NOP tWR ADDRESS Bank a, Col b tDQSS (NOM) NOP tRP Bank, (a or all) tDQSS DQS DI b DQ DM tDQSS (MIN) tDQSS DQS DI b DQ DM tDQSS (MAX) tDQSS DQS DQ DI b DM DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. DI b = data-in for column b. Three subsequent elements of data-in are applied in the programmed order following DI b. An uninterrupted burst of 4 is shown. tWR is referenced from the first positive CK edge after the last data-in pair. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE commands may be to different devices, in which case tWR is not required and the PRECHARGE command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled). 7. PRE = PRECHARGE command. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 29: WRITE to Precharge - Interrupting T0 T1 WRITE NOP T1n T2 T2n T3 T3n T4 T4n T5 T6 CK# CK COMMAND NOP NOP PRE8 tWR ADDRESS Bank a, Col b tDQSS (NOM) NOP NOP tRP Bank, (a or all) tDQSS DQS DI b DQ DM tDQSS (MIN) tDQSS DQS DI b DQ DM tDQSS (MAX) tDQSS DQS DQ DI b DM DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. 6. 7. 8. DI b = data-in for column b. Subsequent element of data-in is applied in the programmed order following DI b. An interrupted burst of 8 is shown; two data elements are written. t WR is referenced from the first positive CK edge after the last data-in pair. A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T4 and T4n (nominal case) to register DM. If the burst of 4 was used, DQS and DM would not be required at T3, T3n, T4 and T4n. PRE = PRECHARGE command. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 30: WRITE to PRECHARGE Odd Number of Data, Interrupting T0 T1 WRITE NOP T1n T2 T2n T3 T3n T4 T4n T5 T6 CK# CK COMMAND NOP NOP PRE7 tWR ADDRESS Bank a, Col b tDQSS (NOM) NOP NOP tRP Bank, (a or all) tDQSS DQS DI b DQ DM tDQSS (MIN) tDQSS DQS DI b DQ DM tDQSS (MAX) tDQSS DQS DQ DI b DM DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. 6. 7. DI b = data-in for column b. An interrupted burst of 8 is shown; one data element is written. tWR is referenced from the first positive CK edge after the last data-in pair. A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T4 and T4n (nominal case) to register DM. If the burst of 4 was used, DQS and DM would not be required at T3, T3n, T4 and T4n. PRE = PRECHARGE command. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM PRECHARGE Power-down (CKE Not Active) The PRECHARGE command (Figure 31) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress, from the issuing of a READ or WRITE command until completion of the access. Thus a clock suspend is not supported. For READs, an access completion is defined when the Read Postamble is satisfied; for WRITEs, an access completion is defined when the Write Recovery time (tWR) is satisfied. Power-down as shown in Figure 32 on page 41, is entered when CKE is registered LOW and all Table 7 (page 41) criteria are met. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK#, and CKE. For maximum power savings, the DLL is frozen during precharge power-down mode. Exiting powerdown requires the device to be at the same voltage and frequency as when it entered power-down. However, power-down duration is limited by the refresh requirements of the device (tREFC). While in power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR SDRAM, while all other input signals are "Don't Care." The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later. Figure 31: PRECHARGE Command CK# CK CKE HIGH CS# RAS# CAS# WE# A0-A9, A11, A12 ALL BANKS A10 ONE BANK BA0,1 BA BA = Bank Address (if A10 is LOW; otherwise "Don't Care") DON'T CARE 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 32: Power-Down T0 T1 CK# T2 ( ( Ta0 Ta1 CK Ta3 VALID VALID tIS tIS CKE COMMAND Ta2 )) (( )) (( )) VALID NOP No READ/WRITE access in progress (( )) (( )) NOP Exit power-down mode Enter power-down mode DON'T CARE Table 7: Truth Table - CKE Notes: 1-6 CKEn-1 CKEn CURRENT STATE COMMANDn L L L H Power-Down Self Refresh Power-Down Self Refresh All Banks Idle Bank(s) Active All Banks Idle X X DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP AUTO REFRESH See Table 8 on page 42 H L H H ACTIONn Maintain Power-Down Maintain Self Refresh Exit Power-Down Exit Self Refresh Precharge Power-Down Entry Active Power-Down Entry Self Refresh Entry NOTES 7 NOTE: 1. 2. 3. 4. 5. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge n. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. All states and sequences not shown are illegal or reserved. CKE must not drop low during a column access. For a READ, this means CKE must stay high until after the Read Postamble time; for a WRITE, CKE must stay high until the WRITE Recovery Time (tWR) has been met. 6. Once initialized, including during self refresh mode, VREF must be powered within the specified range. 7. Upon exit of the Self Refresh mode the DLL is automatically enabled. A minimum of 200 clock cycles is needed before applying a READ command for the DLL to lock. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSNR period. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 8: Truth Table - Current State Bank n - Command to Bank n (Notes: 1-6; notes appear below and on next page) CURRENT STATE Any Idle Row Active Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled) CS# H L L L L L L L L L L L L L L RAS# CAS# X H L L L H H L H H L H H H L X H H L L L L H L L H H L L H WE# X H H H L H L L H L L L H L L COMMAND/ACTION DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) ACTIVE (select and activate row) AUTO REFRESH LOAD MODE REGISTER READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE (truncate READ burst, start PRECHARGE) BURST TERMINATE READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE (truncate WRITE burst, start PRECHARGE) NOTES 7 7 10 10 8 10 10, 12 8 9 10, 11 10 8, 11 NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 7 on page 41) and after tXSNR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/ accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 8, Truth Table - Current State Bank n - Command to Bank n, on page 42 and according to Table 9, Truth Table - Current State Bank n - Command to Bank m, on page 44. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once t RCD is met, the bank will be in the "row active" state. Read w/Auto-Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto-Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle, and bursts are not in progress. 8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank. 10. READs or WRITEs listed in the Command/Action column include Reads or Writes with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Requires appropriate DM masking. 12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 9: Truth Table - Current State Bank n - Command to Bank m (Notes: 1-6; notes appear below and on next page) CURRENT STATE Any Idle Row Activating, Active, or Precharging Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled) Read (With AutoPrecharge) Write (With AutoPrecharge) CS# RAS# CAS# WE# H L X L L L L L L L L L L L L L L L L L L L L X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H X H X H H L L H H L L H H L L H H L L H H L L COMMAND/ACTION DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE NOTES 7 7 7 7, 9 7, 8 7 7, 3a 7, 9, 3a 7, 3a 7, 3a NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/ accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet ter minated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated Read with Auto Precharge Enabled: See following text - 3a, 3b, and 3c Write with Auto Precharge Enabled: 3a. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN See following text - 3a, 3b, and 3c The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM 3b. 3c. still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or t RP) begins. This device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. In either case, all other related limitations apply (e.g., contention between read data and write data must be avoided). The minimum delay from a read or write command with auto precharge enabled, to a command to a different bank is summarized below. FROM COMMAND TO COMMAND MINIMUM DELAY (WITH CONCURRENT AUTO PRECHARGE) WRITE w/AP READ or READ w/AP [1 + (BL/2)] * tCK + tWTR WRITE or WRITE w/AP (BL/2) * tCK PRECHARGE 1 tCK ACTIVE 1 tCK READ or READ w/AP (BL/2) * tCK WRITE or WRITE w/AP [CLRU + (BL/2)] *tCK PRECHARGE 1 tCK ACTIVE 1 tCK READ w/AP NOTE: CLRU = CAS Latency (CL) rounded up to the next integer BL = Bust Length 4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. Requires appropriate DM masking. 9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Absolute Maximum Ratings VREF and Inputs Voltage Relative to VSS ..............................................-1V to +3.6V I/O Pins Voltage Relative to VSS ................................ -0.5V to VDDQ +0.5V Operating Temperature, TA (ambient, Commercial)............................... 0C to +70C Operating Temperature, TA (ambient, Industrial)................................-40C to +85C Storage Temperature (plastic) ...............-55C to +150C Short Circuit Output Current .................................50mA Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VDD Supply Voltage Relative to Vss ............................................... -1V to +3.6V VDDQ Supply Voltage Relative to VSS .............................................. -1V to +3.6V Table 10: DC Electrical Characteristics and Operating Conditions (-6, -6T, -75E, -75Z, -75) 0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 1-5, 16, notes appear on page 61-64 PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input 0V VIN VDD, VREF PIN 0V VIN 1.35V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS: Full drive option - x4, x8, x16 SYMBOL MIN MAX UNITS NOTES VDD VDDQ VREF VTT VIH(DC) VIL(DC) II 2.3 2.3 0.49 x VDDQ 2.7 2.7 0.51 x VDDQ VREF - 0.04 VREF + 0.15 VREF + 0.04 VDD + 0.3 VREF - 0.15 36, 41 36, 41 44 6, 44 7, 44 28 28 2 V V V V V V A IOZ -5 5 A IOH -16.8 - mA IOL 16.8 - mA IOHR -9 - mA IOLR 9 - mA High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) OUTPUT LEVELS: Reduced drive option - x16 only High Current (VOUT = VDDQ - 0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF, maximum VTT) 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 46 -0.3 -2 37, 39 38, 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 11: DC Electrical Characteristics and Operating Conditions (-5B DDR400) 0C TA +70C; VDDQ = +2.6V 0.1V, VDD = +2.6V 0.1V Notes: 1-5, 16, and 52; Notes appear on page 61-64 PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input 0V VIN VDD, VREF PIN 0V VIN 1.35V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS: Full drive option - x4, x8, x16 SYMBOL MIN MAX UNITS NOTES VDD VDDQ 2.4 2.4 2.7 2.7 V V VREF VTT VIH(DC) VIL(DC) II 0.49 x VDDQ 0.51 x VDDQ VREF - 0.04 VREF + 0.15 VREF + 0.04 VDD + 0.3 VREF - 0.15 2 V V V V A 36, 41, 52 36, 41 44, 52 6, 44 7, 44 28 28 IOZ -5 5 A IOH -16.8 - mA IOL 16.8 - mA IOHR -9 - mA IOLR 9 - mA High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) OUTPUT LEVELS: Reduced drive option - x16 only High Current (VOUT = VDDQ - 0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF, maximum VTT) 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 47 -0.3 -2 37, 39 38, 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 12: AC Input Operating Conditions 0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V (VDDQ = +2.6V 0.1V, VDD = +2.6V 0.1V for DDR400) Notes: 1-5, 14, 16, notes appear on page 61-64 PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage VIH(AC) VIL(AC) VREF(AC) VREF + 0.310 - - VREF - 0.310 0.51 x VDDQ V V V 14, 28, 40 14, 28, 40 6 Input Low (Logic 0) Voltage I/O Reference Voltage 0.49 x VDDQ Figure 33: Input Voltage Waveform VDDQ (2.3V minimum) VOH(MIN) (1.670V1 for SSTL2 termination) System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation) 1.560V VIHAC 1.400V VIHDC 1.300V 1.275V 1.250V 1.225V 1.200V VREF +AC Noise VREF +DC Error VREF -DC Error VREF -AC Noise 1.100V VILDC 0.940V VINAC - Provides margin between VOL (MAX) and VILAC VILAC Receiver VOL (MAX) (0.83V2 for SSTL2 termination) Transmitter NOTE: 1. VOH (MIN) with test load is 1.927V 2. VOL (MAX) with test load is 0.373V 3. For Non-DDR400 devices, numbers in diagram reflect nomimal values utilizing circuit below. VSSQ VTT 25 25 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 48 Reference Point Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 13: Clock Input Operating Conditions 0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V (VDDQ = +2.6V 0.1V, VDD = +2.6V 0.1V for DDR400) Notes: 1-5, 15, 16, 30; notes appear on page 61-64 PARAMETER/CONDITION Clock Input Mid-Point Voltage; CK and CK# Clock Input Voltage Level; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK# SYMBOL MIN MAX UNITS NOTES VMP(DC) VIN(DC) VID(DC) VID(AC) VIX(AC) 1.15 -0.3 0.36 0.7 1.35 V V V V V 6, 9 6 6, 8 8 9 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 x VDDQ - 0.2 0.5 x VDDQ + 0.2 Figure 34: SSTL_2 Clock Input 2.80V Maximum Clock Level 5 CK# X 1.45V 1.05V 3 1 VMP (DC) 1.25V VIX (AC) 2 VID (DC) 4 VID (AC) X CK Minimum Clock Level - 0.30V 5 NOTE: 1. 2. 3. 4. 5. 6. 7. This provides a minimum of 1.15V to a maximum of 1.35V, and is always half of VDDQ. CK and CK# must cross in this region. CK and CK# must meet at least VID(DC) min when static and is centered around VMP(DC) CK and CK# must have a minimum 700mv peak to peak swing. CK or CK# may not be more positive than VDDQ+ 0.3V or more negative than Vss - 0.3V. For AC operation, all DC clock requirements must also be satisfied. Numbers in diagram reflect nominal values non-DDR400 devices. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 14: Capacitance (x4, x8 TSOP) (Note: 13; notes appear on page 61-64) PARAMETER Delta Input/Output Capacitance: DQ0-DQ3 (x4), DQ0-DQ7 (x8) Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE SYMBOL MIN DCIO DCI1 DCI2 CIO CI1 CI2 CI3 - - - 4.0 2.0 2.0 2.0 SYMBOL MIN DCIO DCI1 DCI2 CIO CI1 CI2 CI3 - - - 3.5 1.5 1.5 1.5 MAX UNITS 0.50 0.50 0.25 5.0 3.0 3.0 3.0 pF pF pF pF pF pF pF NOTES 24 29 29 Table 15: Capacitance (x4, x8 FBGA) (Note: 13; notes appear on page 61-64) PARAMETER Delta Input/Output Capacitance: DQs, DQS, DM Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 50 MAX UNITS 0.50 0.50 0.25 4.5 2.5 2.5 2.5 pF pF pF pF pF pF pF NOTES 24 29 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 16: Capacitance (x16 TSOP) (Note: 13; notes appear on page 61-64) PARAMETER Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQ, LDQS, UDQS, LDM, UDM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE SYMBOL MIN MAX UNITS NOTES DCIOL DCIOU DCI1 DCI2 CIO CI1 CI2 CI3 - - - - 4.0 2.0 2.0 2.0 0.50 0.50 0.50 0.25 5.0 3.0 3.0 3.0 pF pF pF pF pF pF pF pF 24 24 29 29 SYMBOL MIN MAX UNITS NOTES DCIOL DCIOU DCI1 DCI2 CIO CI1 CI2 CI3 - - - - 3.5 1.5 1.5 1.5 0.50 0.50 0.50 0.25 4.5 2.5 2.5 2.5 pF pF pF pF pF pF pF pF 24 24 29 29 Table 17: Capacitance (x16 FBGA) (Note: 13; notes appear on page 61-64) PARAMETER Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQ, LDQS, UDQS, LDM, UDM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 18: IDD Specifications and Conditions (x4, x8; -5B) 0C TA +70C; VDDQ = +2.6V 0.1V, VDD = +2.6V 0.1V Notes: 1-5, 10, 12, 14, 46; notes appear on page 61-64; See also Table 22, IDD Test Cycle Times, on page 56 MAX PARAMETER/CONDITION SYMBOL -5B UNITS NOTES IDD0 155 mA 22, 47 IDD1 185 mA 22, 47 IDD2P 5 mA 23, 32, 49 IDD2F 55 mA 50 IDD3P 45 mA 23, 32, 49 IDD3N 60 mA 22 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R 190 mA 22, 47 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock IDD4W 195 mA 22 IDD5 IDD5A IDD6 IDD6A IDD7 345 11 5 3 450 mA mA mA mA mA 49 27, 49 11 11 22, 48 OPERATING CURRENT: One bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC =tRC(MIN) AUTO REFRESH BURST CURRENT: tREFC = SELF REFRESH CURRENT: CKE 0.2V 7.8us, Standard Low Power (L) OPERATING CURRENT: Four bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 19: IDD Specifications and Conditions (x4, x8; -6/-6T/-75E/-75Z/-75) 0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 1-5, 10, 12, 14, 46; notes appear on page 61-64; See also Table 22, IDD Test Cycle Times, on page 56 MAX PARAMETER/CONDITION SYMBOL -6/6T -75E IDD0 130 130 115 mA 22, 47 IDD1 160 160 145 mA 22, 47 IDD2P 5 5 5 mA 23, 32, 49 IDD2F 45 45 40 mA 50 IDD3P 35 35 30 mA 23, 32, 49 IDD3N 50 50 45 mA 22 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R 165 165 145 mA 22, 47 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per IDD4W 175 155 135 mA 22 IDD5 IDD5A IDD6 IDD6A IDD7 290 10 5 3 405 290 10 5 3 400 280 10 5 3 350 mA mA mA mA mA 49 27, 49 11 11 22, 48 OPERATING CURRENT: One bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs -75Z/-75 UNITS NOTES changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC =tRC(MIN) AUTO REFRESH BURST CURRENT: tREFC SELF REFRESH CURRENT: CKE 0.2V = 7.8us, Standard Low Power (L) OPERATING CURRENT: Four bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 20: IDD Specifications and Conditions (x16; -5B) C TA +70C; VDDQ = +2.6V 0.1V, VDD = +2.6V 0.1V Notes: 1-5, 10, 12, 14, 46; notes appear on page 61-64; See also Table 22, IDD Test Cycle Times, on page 56 PARAMETER/CONDITION SYMBOL -5B UNITS NOTES IDD0 155 mA 22, 47 IDD1 195 mA 22, 47 IDD2P 5 mA 23, 32, 49 IDD2F 55 mA 50 IDD3P 45 mA 23, 32, 49 IDD3N 60 mA 22 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R 210 mA 22, 47 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; IDD4W 215 mA 22 IDD5 345 11 6 4 480 mA mA mA mA mA 49 27, 49 11 11 22, 48 OPERATING CURRENT: One bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Powerdown mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC =tRC(MIN) AUTO REFRESH BURST CURRENT: tREFC = 7.8us, SELF REFRESH CURRENT: CKE 0.2V Standard Low Power (L) OPERATING CURRENT: Four bank interleaving READs IDD5A IDD6 IDD6A IDD7 (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 21: IDD Specifications and Conditions (x16; -6/-6T/-75E/-75Z/-75) 0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 1-5, 10, 12, 14, 46; notes appear on page 61-64; See also Table 22, IDD Test Cycle Times, on page 56 MAX PARAMETER/CONDITION SYMBOL -6/6T -75E -75Z/-75 UNITS NOTES IDD0 130 130 115 mA 22, 47 IDD1 160 160 145 mA 22, 47 IDD2P 5 5 5 mA 23, 32, 49 IDD2F 45 45 40 mA 50 IDD3P 35 35 30 mA 23, 32, 49 IDD3N 50 50 45 mA 22 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R 165 165 145 mA 22, 47 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once IDD4W 195 160 135 mA 22 IDD5 290 10 5 3 405 290 10 5 3 400 280 10 5 3 350 mA mA mA mA mA 49 27, 49 11 11 22, 48 OPERATING CURRENT: One bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC =tRC(MIN) AUTO REFRESH BURST CURRENT: tREFC= SELF REFRESH CURRENT: CKE 0.2V IDD5A IDD6 IDD6A IDD7 7.8us, Standard Low Power (L) OPERATING CURRENT: Four bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 22: IDD Test Cycle Times Values reflect number of clock cycles for each test. IDD TEST IDD0 IDD1 IDD4R IDD4W IDD5 IDD5A IDD7 SPEED GRADE CLOCK CYCLE TIME -75/75Z -75E -6/-6T -5B -75 -75Z -75E -6/-6T -5B -75 -75Z -75E -6/-6T -5B -75 -75Z -75E -6/-6T -5B -75/75Z -75E -6/-6T -5B -75/75Z -75E -6/-6T -5B -75 -75Z -75E -6/-6T -5B 7.5ns 7.5ns 6ns 5ns 7.5ns 7.5ns 7.5ns 6ns 5ns 7.5ns 7.5ns 7.5ns 6ns 5ns 7.5ns 7.5ns 7.5ns 6ns 5ns 7.5ns 7.5ns 6ns 5ns 7.5ns 7.5ns 6ns 5ns 7.5ns 7.5ns 7.5ns 6ns 5ns 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN t RRD NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 2/4 2/4 2 2/4 2/4 t RCD NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 3 3 3 3 3 t RAS t t 6 6 7 8 6 6 6 7 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 3 2 3 3 3 3 2 3 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 3 3 2 3 3 9 8 10 11 9 9 8 10 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 10 10 8 10 11 56 RP RC t RFC t REFI CL NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 10 9 12 14 10 9 12 14 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 10 9 12 14 1,030 1,030 1,288 1,546 NA NA NA NA NA NA NA NA NA 2.5 2 2 2.5 3 2.5 2 2 2.5 3 NA NA NA NA NA NA NA NA NA NA NA NA NA 2.5 2 2 2.5 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 23: Electrical Characteristics & Recommended AC Operating Conditions (-5B) 0C TA +70C; VDDQ = +2.6V 0.1V, VDD = +2.6V 0.1V Notes: 1-5, 14-17, 33; notes appear on page 61-64 AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time -5B SYMBOL tAC t CH t CL tCK (3) t CK (2.5) t CK (2) t DH tDS t DIPW t DQSCK tDQSH t DQSL t DQSQ tDQSS t DSS t DSH tHP t HZ t LZ tIH F t ISF t IHS tIS S t IPW t MRD tQH CL = 3 CL = 2.5 CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access WRITE command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access tQHS Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window (DVW) REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN t RAS t RAP tRC t RFC t RCD tRP t RPRE t RPST tRRD t WPRE t WPRES tWPST t WR t WTR N/A t REFC t REFI tVTD t XSNR t XSRD 57 MIN -0.70 0.45 0.45 5 6 7.5 0.40 0.40 1.75 -0.60 0.35 0.35 0.72 0.2 0.2 tCH,tCL MAX +0.70 0.55 0.55 7.5 13 13 +0.60 0.40 1.28 +0.70 -0.70 0.60 0.60 0.60 0.60 2.2 10 tHP -tQHS 0.50 40 70,000 15 55 70 15 15 0.9 1.1 0.4 0.6 10 0.25 0 0.4 0.6 15 2 tQH - tDQSQ 70.3 7.8 0 70 200 UNITS ns t CK t CK ns ns ns ns ns ns ns tCK t CK ns tCK t CK t CK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t CK t CK ns t CK ns tCK ns t CK ns s s ns ns t CK NOTES 30 30 51 45, 51 45, 51 26, 31 26, 31 31 25, 26 34 18,42 18,42 14 14 25, 26 35 49 43 43 20, 21 19 25 23 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 24: Electrical Characteristics and Recommended AC Operating Conditions (-6/-6T/-75E) 0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 1-5, 14-17, 33; notes appear on page 61-64 AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time CL=2.5 CL=2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data Hold Skew Factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window (DVW) REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN SYMBOL t AC tCH t CL t CK (2.5) tCK (2) tDH t DS t DIPW tDQSCK t DQSH t DQSL tDQSQ tDQSS -6 (FBGA) MIN MAX -0.70 +0.70 0.45 0.55 0.45 0.55 6 13 7.5 13 0.45 0.45 1.75 -0.6 +0.6 0.35 0.35 0.4 -6T (TSOP) MIN MAX -0.70 +0.70 0.45 0.55 0.45 0.55 6 13 7.5 13 0.45 0.45 1.75 -0.6 +0.6 0.35 0.35 0.45 0.75 1.25 0.75 1.25 DSS 0.2 0.2 t DSH 0.2 0.2 tHP tCH,tCL tCH,tCL t HZ +0.7 +0.7 t LZ -0.7 -0.7 tIH .75 .75 F t ISF .75 .75 t IHS 0.8 0.8 tIS 0.8 0.8 S t IPW 2.2 2.2 t MRD 12 12 tQH tHP tHP -tQHS -tQHS tQHS 0.50 0.55 t RAS 42 70,000 42 70,000 t RAP 15 15 tRC 60 60 t RFC 72 72 t RCD 15 15 tRP 15 15 t RPRE 0.9 1.1 0.9 1.1 t RPST 0.4 0.6 0.4 0.6 tRRD 12 12 t WPRE 0.25 0.25 t WPRES 0 0 tWPST 0.4 0.6 0.4 0.6 t WR 15 15 t WTR 1 1 tQH - tDQSQ tQH - tDQSQ N/A t REFC 70.3 70.3 t REFI 7.8 7.8 tVTD 0 0 t XSNR 75 75 t XSRD 200 200 t 58 -75E MIN MAX UNITS NOTES -0.75 +0.75 ns tCK 0.45 0.55 30 t 0.45 0.55 CK 30 7.5 13 ns 45, 51 7.5 13 ns 45, 51 0.5 ns 26, 31 0.5 ns 26, 31 1.75 ns 31 -0.75 +0.75 ns t 0.35 CK t 0.35 CK 0.5 ns 25, 26 0.75 0.2 0.2 tCH,tCL 1.25 tCK t CK CK ns ns ns ns ns ns ns ns ns ns t +0.75 -0.75 .90 .90 1 1 2.2 15 tHP -tQHS 0.75 40 120,000 15 60 75 15 15 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 70.3 7.8 0 75 200 ns ns ns ns ns ns ns t CK t CK ns t CK ns tCK ns t CK ns s s ns ns t CK 34 18, 42 18, 42 14 14 25, 26 35, 53 49 43 43 20, 21 19 25 23 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 25: Electrical Characteristics and Recommended AC Operating Conditions (-75Z/-75) 0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 1-5, 14-17, 33; notes appear on page 61-64 AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time Data Hold Skew Factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window (DVW) REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command -75Z -75 SYMBOL MIN MAX MIN MAX t AC -0.75 +0.75 -0.75 +0.75 tCH 0.45 0.55 0.45 0.55 t CL 0.45 0.55 0.45 0.55 t CK (2.5) 7.5 13 7.5 13 tCK (2) 7.5 13 10 13 tDH 0.5 0.5 t DS 0.5 0.5 t DIPW 1.75 1.75 tDQSCK -0.75 +0.75 -0.75 +0.75 t DQSH 0.35 0.35 t DQSL 0.35 0.35 tDQSQ 0.5 0.5 t DQSS 0.75 1.25 0.75 1.25 t DSS 0.2 0.2 tDSH 0.2 0.2 t t t HP CH,tCL CH,tCL t HZ +0.75 +0.75 tLZ -0.75 -0.75 t IHF .90 .90 t ISF .90 .90 tIH 1 1 S t ISS 1 1 t IPW 2.2 2.2 tMRD 15 15 t t t QH HP HP -tQHS -tQHS t QHS 0.75 0.75 t RAS 40 120,000 40 120,000 tRAP 20 20 t RC 65 65 t RFC 75 75 tRCD 20 20 t RP 20 20 t RPRE 0.9 1.1 0.9 1.1 tRPST 0.4 0.6 0.4 0.6 t RRD 15 15 t WPRE 0.25 0.25 tWPRES 0 0 t WPST 0.4 0.6 0.4 0.6 t WR 15 15 tWTR 1 1 t t QH - tDQSQ QH - tDQSQ N/A t REFC 70.3 70.3 tREFI 7.8 7.8 t VTD 0 0 t XSNR 75 75 tXSRD 200 200 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 59 CL=2.5 CL=2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access UNITS ns tCK t CK ns ns ns ns ns ns t CK t CK ns t CK t CK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t CK tCK ns t CK ns t CK ns tCK ns s s ns ns tCK NOTES 30 30 45, 52 45, 52 26, 31 26, 31 31 25, 26 34 18, 42 18, 42 14 14 25, 26 35 49 43 43 20, 21 19 25 23 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 26: Input Slew Rate Derating Values for Addresses and Commands 0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 14; notes appear on page 61-64 SPEED SLEW RATE -75/-75Z/-75E -75/-75Z/-75E -75/-75Z/-75E 0.500V / ns 0.400V / ns 0.300V / ns t t IS 1.00 1.05 1.15 IH UNITS 1 1 1 ns ns ns Table 27: Input Slew Rate Derating Values for DQ, DQS, and DM 0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 31; notes appear on page 61-64 SPEED SLEW RATE tDS tDH UNITS -75/-75Z/-75E -75/-75Z/-75E -75/-75Z/-75E 0.500V / ns 0.400V / ns 0.300V / ns 0.50 0.55 0.60 0.50 0.55 0.60 ns ns ns 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Notes 11. Enables on-chip refresh and address counters. 12. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 13. This parameter is sampled. VDD = +2.5V0.2V, VDDQ = +2.5V0.2V, VREF = VSS, f = 100 MHz, TA = 25C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 14. For slew rates less than 1V/ns and greater than or equal to 0.5V/ns. If the slew rate is less than 0.5V/ ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. For -5B, -6, and -6T, slew rates must be greater than or equal to 0.5V/ ns. 15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 16. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including self refresh mode, VREF must be powered within specified range. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. 17. The output timing reference level, as measured at the timing reference point (indicated in Note 3) is VTT. 18. tHZ and tLZ transitions occur in the same access time windows as data valid transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 19. The intent of the "Don't Care" state after completion of the postamble is the DQS-driven signal should either be HIGH, LOW, or high-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above VIHDC (MIN) then it must not transition LOW (below VIHDC) prior to tDQSH (MIN). 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs (except for IDD measurements) measured with equivalent load: VTT Output (VOUT) 50 Reference Point 30pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 9. The value of VIX and VMP are expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 10. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle times at CL=3 for -5B, CL=2.5 for -6/6T/-75, and CL=2 for -75E/-75Z speeds with the outputs open. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 61 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM 22. 23. 24. 25. progress, DQS could be HIGH during this time, depending on tDQSS. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. The refresh period is 64ms. This equates to an average refresh rate of 7.8125s. However, an AUTO REFRESH command must be asserted at least once every 70.3s; burst refreshing or posting by the DRAM controller greater than 8 refresh cycles is not allowed. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. The data valid window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and t QH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, because functionality is uncertain when operating beyond a 45/55 ratio. 26. 27. 28. 29. 30. The data valid window derating curves are provided in Figure 35 for duty cycles ranging between 50/50 and 45/55. Referenced to each output group: x4 = DQS with DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). The Input capacitance per pin group will not differ by more than this maximum amount for any given device. CK and CK# input slew rate must be 1V/ns ( 2V/ns if measured differentially). Figure 35: Derating Data Valid Window (tQH - tDQSQ) 3.8 3.750 3.700 3.6 3.400 3.4 3.650 3.600 3.550 3.500 3.350 3.450 3.300 3.400 3.250 3.200 3.100 ---- -75 @ tCK = 10ns 3.0 3.350 3.150 3.2 3.250 3.050 3.000 ---- -8 @ tCK = 10ns ns 3.300 2.950 ---- -75 @ tCK = 7.5ns 2.900 ---- -8 @ tCK = 8ns 2.8 2.6 2.500 2.463 2.425 2.388 2.4 2.350 2.313 2.275 2.238 2.200 2.2 2.163 2.125 2.0 1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 Clock Du ty C y c le 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 62 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM f. f ) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V. 31. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and t DH for each 100mv/ns reduction in slew rate. For -5B, -6 and -6T speed grades, slew rate must be 0.5V/ns. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VDD must not vary more than 4 percent if CKE is not active while any bank is active. 33. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. 36. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mV or 2.9V (+300mV or 2.9V maximum for -5B), whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V (2.4V for -5B), whichever is more positive. The average cannot be below the +2.5V (2.6V for -5B) minimum. 37. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 36 b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 36. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 37. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 37. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN Figure 36: Full Drive Pull-Down Characteristics 160 140 120 I OUT (mA) 100 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 VOUT (V) Figure 37: Full Drive Pull-Up Characteristics 0 -20 -40 I OUT (m A) -60 -80 -100 -120 -140 -160 -180 -200 0.0 0.5 1.0 1.5 2.0 2.5 V DD Q - V OUT (V ) 38. Reduced Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 38. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 38. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 39. 63 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM 40. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 41. VDD and VDDQ must track each other. 42. tHZ (MAX) will prevail over tDQSCK (MAX) + t RPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 43. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 44. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V, provided a minimum of 42 of series resistance is used between the VTT supply and the input pin. 45. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. 47. Random addressing changing 50 percent of data changing at every transfer. 48. Random addressing changing 100 percent of data changing at every transfer. 49. CKE must be active (HIGH) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. 50. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 51. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset followed by 200 clock cycles before any READ command. 52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz. Any noise above 20MHz at the DRAM generated from any source other than that of the DRAM itself may not exceed the DC voltage range of 2.6V 100mV. 53. The -6/-6T speed grades will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 39. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V. Figure 38: Reduced Drive Pull-Down Characteristics 80 70 60 IOUT (mA) 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2. VOUT (V) Figure 39: Reduced Drive Pull-Up Characteristics 0 -10 -20 IOUT (mA) -30 -40 -50 -60 -70 -80 0.0 0.5 1.0 1.5 2.0 2.5 VDDQ - VOUT (V) 39. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 64 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 28: Normal Output Drive Characteristics PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA) VOLTAGE (V) NOMINAL LOW NOMINAL HIGH MINIMUM MAXIMUM NOMINAL LOW NOMINAL HIGH MINIMUM MAXIMUM 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.8 63.3 63.8 64.1 64.6 64.8 65.0 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2 NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 65 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Table 29: Reduced Output Drive Characteristics PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA) VOLTAGE (V) NOMINAL LOW NOMINAL HIGH MINIMUM MAXIMUM NOMINAL LOW NOMINAL HIGH MINIMUM MAXIMUM 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3.4 6.9 10.3 13.6 16.9 19.9 22.3 24.7 26.9 29.0 30.6 31.8 32.8 33.5 34.0 34.3 34.5 34.8 35.1 35.4 35.6 35.8 36.1 36.3 36.5 36.7 36.8 3.8 7.6 11.4 15.1 18.7 22.1 25.0 28.2 31.3 34.1 36.9 39.5 42.0 44.4 46.6 48.6 50.5 52.2 53.9 55.0 56.1 57.1 57.7 58.2 58.7 59.2 59.6 2.6 5.2 7.8 10.4 13.0 15.7 18.2 20.8 22.4 24.1 25.4 26.2 26.6 26.8 27.0 27.2 27.4 27.7 27.8 28.0 28.1 28.2 28.3 28.3 28.4 28.5 28.6 5.0 9.9 14.6 19.2 23.6 28.0 32.2 35.8 39.5 43.2 46.7 50.0 53.1 56.1 58.7 61.4 63.5 65.6 67.7 69.8 71.6 73.3 74.9 76.4 77.7 78.8 79.7 -3.5 -6.9 -10.3 -13.6 -16.9 -19.4 -21.5 -23.3 -24.8 -26.0 -27.1 -27.8 -28.3 -28.6 -28.7 -28.9 -28.9 -29.0 -29.2 -29.2 -29.3 -29.5 -29.5 -29.6 -29.7 -29.8 -29.9 -4.3 -7.8 -12.0 -15.7 -19.3 -22.9 -26.5 -30.1 -33.6 -37.1 -40.3 -43.1 -45.8 -48.4 -50.7 -52.9 -55.0 -56.8 -58.7 -60.0 -61.2 -62.4 -63.1 -63.8 -64.4 -65.1 -65.8 -2.6 -5.2 -7.8 -10.4 -13.0 -15.7 -18.2 -20.4 -21.6 -21.9 -22.1 -22.2 -22.3 -22.4 -22.6 -22.7 -22.7 -22.8 -22.9 -22.9 -23.0 -23.0 -23.1 -23.2 -23.2 -23.3 -23.3 -5.0 -9.9 -14.6 -19.2 -23.6 -28.0 -32.2 -35.8 -39.5 -43.2 -46.7 -50.0 -53.1 -56.1 -58.7 -61.4 -63.5 -65.6 -67.7 -69.8 -71.6 -73.3 -74.9 -76.4 -77.7 -78.8 -79.7 NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 66 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 40: x4, x8 Data Output Timing - tDQSQ, tQH, and Data Valid Window T1 T2 T2n T3 T3n T4 CK# CK tHP5 tHP5 tHP5 tHP5 tDQSQ3 tDQSQ3 tQH4 tQH4 tHP5 tHP5 tDQSQ3 tDQSQ3 DQS1 DQ (Last data valid) DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ (First data no longer valid) tQH4 tQH4 DQ (Last data valid) T2 T2n T3 T3n DQ (First data no longer valid) T2 T2n T3 T3n All DQ and DQS, collectively6 T2 T2n T3 T3n Data Valid window Data Valid window Data Valid window Data Valid window Earliest signal transition Latest signal transition NOTE: 1. DQ transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an "early DQS," at T3 is a "nominal DQS," and at T3n is a "late DQS." 2. For a x4, only two DQ apply. 3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid DQ transition. 4. tQH is derived from tHP: tQH = tHP - tQHS. 5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active. 6. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 67 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 41: x16 Data Output Timing - tDQSQ, tQH, and Data Valid Window CK# CK T1 T2 tHP5 tHP5 T2n T3 tHP5 tHP5 tDQSQ3 tDQSQ3 tQH4 tQH4 T3n tHP5 T4 tHP5 tDQSQ3 tDQSQ3 LDQS1 tQH4 Lower Byte DQ (Last data valid)2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ (First data no longer valid)2 tQH4 DQ (Last data valid)2 T2 T2n T3 T3n DQ (First data no longer valid)2 T2 T2n T3 T3n DQ0 - DQ7 and LDQS, collectively6 T2 T2n T3 T3n Data Valid window Data Valid window Data Valid window Data Valid window tDQSQ3 tDQSQ3 tDQSQ3 tDQSQ3 UDQS1 tQH4 tQH4 tQH4 DQ (Last data valid)7 T2 T2n DQ (First data no longer valid)7 T2 T2n DQ8 - DQ15 and UDQS, collectively6 T2 T2n Data Valid window Data Valid window Upper Byte DQ (Last data valid)7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ (First data no longer valid)7 tQH4 T3 T3 T3 T3n T3n T3n Data Valid Data Valid window window NOTE: 1. DQ transitioning after DQS transition define tDQSQ window. LDQS defines the lower byte and UDQS defines the upper byte. 2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7. 3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid DQ transition. 4. tQH is derived from tHP: tQH = tHP - tQHS. 5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active. 6. The data valid window is derived for each DQS transition and is tQH minus tDQSQ. 7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 68 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 42: Data Output Timing - tAC and tDQSCK T07 T1 T2 T3 T2n T3n T4 T4n T5 T5n T6 CK# CK tDQSCK1 (MAX) tHZ(MAX) tDQSCK1 (MIN) tDQSCK1 (MAX) tDQSCK1 (MIN) tLZ (MIN) tRPST tRPRE DQS, or LDQS/UDQS2 DQ (Last data valid) T2 T2n T3 T3n T4 T4n T5 T5n DQ (First data valid) T2 T2n T3 T3n T4 T4n T5 T5n All DQ values, collectively3 T2 T2n T3 T3n T4 T4n T5 T5n tLZ (MIN) tAC4 (MIN) tAC4 (MAX) tHZ (MAX) NOTE: 1. 2. 3. 4. 5. 6. 7. tDQSCK is the DQS output window relative to CK and is the "long term" component of DQS skew. DQ transitioning after DQS transition define tDQSQ window. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC. tAC is the DQ output window relative to CK, and is the "long term" component of DQ skew. tLZ (MIN) and tAC (MIN) are the first valid signal transition. tHZ (MAX),and tAC (MAX) are the latest valid signal transition. READ command with CL = 2 issued at T0. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 69 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 43: Data Input Timing T03 T1 T1n T2 T2n T3 CK# CK tDQSS tDSH1 tDSS2 tDSH1 tDSS2 DQS tDQSL tDQSH tWPST tWPRES tWPRE DI b DQ DM tDS tDH TRANSITIONING DATA DON'T CARE NOTE: 1. 2. 3. 4. tDSH (MIN) generally occurs during tDQSS (MIN). (MIN) generally occurs during tDQSS (MAX). WRITE command issued at T0. For x16, LDQS controls the lower byte and UDQS controls the upper byte. tDSS 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 70 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Initialization Figure 44: Initialization Flow Diagram To ensure device operation the DRAM must be initialized as described below: 1. Simultaneously apply power to VDD and VDDQ. 2. Apply VREF and then VTT power. 3. Assert and hold CKE at a LVCMOS logic low. 4. Provide stable CLOCK signals. 5. Wait at least 200s. 6. Bring CKE high and provide at least one NOP or DESELECT command. At this point the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a SSTL_2 input unless a power cycle occurs. 7. Perform a PRECHARGE ALL command. 8. Wait at least tRP time, during this time NOPs or DESELECT commands must be given. 9. Using the LMR command program the Extended Mode Register (E0 = 0 to enable the DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set to 0; where n = most significant bit). 10. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 11. Using the LMR command program the Mode Register to set operating parameters and to reset the DLL. Note at least 200 clock cycles are required between a DLL reset and any READ command. 12. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 13. Issue a PRECHARGE ALL command. 14. Wait at least tRP time, only NOPs or DESELECT commands are allowed. 15. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). 16. Wait at least tRFC time, only NOPs or DESELECT commands are allowed. 17. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). 18. Wait at least tRFC time, only NOPs or DESELECT commands are allowed. 19. Although not required by the Micron device, JEDEC requires a LMR command to clear the DLL bit (set M8 = 0). If a LMR command is issued the same operating parameters should be utilized as in step 11. 20. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 21. At this point the DRAM is ready for any valid command. Note 200 clock cycles are required between step 11 (DLL RESET) and any READ command. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN Step 71 1 VDD and VDDQ Ramp 2 Apply VREF and VTT 3 CKE must be LVCMOS Low 4 Apply stable CLOCKs 5 Wait at least 200us 6 Bring CKE High with a NOP command 7 PRECHARGE ALL 8 Assert NOP or DESELECT for tRP time 9 Configure Extended Mode Register 10 Assert NOP or DESELECT for tMRD time 11 Configure Load Mode Register and reset DLL 12 Assert NOP or DESELECT for tMRD time 13 PRECHARGE ALL 14 Assert NOP or DESELECT for tRP time 15 Issue AUTO REFRESH command 16 Assert NOP or DESELECT commands for tRFC 17 Issue AUTO REFRESH command 18 Assert NOP or DESELECT for tRFC time 19 Optional LMR command to clear DLL bit 20 Assert NOP or DESELECT for tMRD time 21 DRAM is ready for any valid command Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 45: Initialize And Load Mode Registers (( )) VDD VDDQ (( )) tVTD1 (( )) VTT1 VREF (( )) CK# (( )) (( )) T1 T0 CK tCH tIS LVCMOS LOW LEVEL CKE tCL tIS Td0 Te0 Tf0 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) tIH NOP (( )) (( )) PRE tCK (( )) (( )) (( )) (( )) A0-A9, A11, A12 (( )) (( )) (( )) (( )) LMR ALL BANKS (( )) (( )) tIS tIH (( )) (( )) LMR tIS (( )) (( )) (( )) (( )) AR AR (( )) (( )) ACT5 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) RA (( )) (( )) (( )) (( )) (( )) (( )) RA (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) BA (( )) (( )) CODE (( )) (( )) (( )) (( )) CODE (( )) (( )) (( )) (( )) BA0 = L, BA1 = L tIH CODE tIS (( )) (( )) PRE tIH CODE (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) tIS BA0, BA1 Tc0 (( )) (( )) DM A10 Tb0 (( )) (( )) tIH (( )) (( )) (( )) COMMAND6 Ta0 (( )) (( )) tIH BA0 = H, BA1 = L ALL BANKS tIS tIH DQS (( )) High-Z (( )) (( )) (( )) (( )) (( )) (( )) DQ (( )) High-Z (( )) (( )) (( )) (( )) (( )) (( )) T = 200s Power-up: VDD and CK stable tRP tMRD Load Extended Mode Register tMRD tRP tRFC tRFC5 200 cycles of CK3 Load Mode Register2 DON'T CARE NOTE: 1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up. VDDQ, VTT, and VREF, must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. Once initialized, VREF must always be powered with in specified range. 2. Reset the DLL with A8 = H while programming the operating parameters. 3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued. 4. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LOAD MODE REGISTER (LMR) command at Ta0. 5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank. If another LMR command is issued, the same operating parameters, previously issued, must be used. 6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address. -5B SYMBOL tCH t CL tCK (3) tCK (2.5) t CK (2) tIH F tIS F MIN 0.45 0.45 5 6 7.5 .75 .75 MAX 0.55 0.55 7,5 13 13 -6/-6T -75E/75Z MIN MAX MIN MAX 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 NA NA NA NA 6 13 7.5 13 7.5 13 7.5 13 .75 .90 .75 .90 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN -75 -5B MIN MAX UNITS 0.45 0.55 tCK 0.45 0.55 tCK NA NA ns 7.5 13 ns 10 13 ns .90 ns .90 ns SYMBOL tIH S t ISS tMRD tRFC t RP tVTD 72 -6/-6T -75E/75Z -75 MIN MAX MIN MAX MIN MAX MIN MAX UNITS .75 0.8 1 1 ns .75 0.8 1 1 ns 15 15 15 15 ns 70 72 75 75 ns 15 15 15 20 ns 0 0 0 0 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 46: Power-Down Mode T0 T1 T2 CK# CK tCK tIS CKE tIH tCH tCL Ta0 (( )) (( )) Ta1 tIS Ta2 tIS 1 tIS COMMAND VALID2 tIS ADDR (( )) tIH NOP tIH (( )) (( )) NOP (( )) (( )) VALID DQS (( )) (( )) DQ (( )) (( )) DM (( )) (( )) VALID VALID tREFC Enter 3 Power-Down Mode Exit Power-Down Mode DON'T CARE NOTE: 1. Once initialized, VREF must always be powered with in specified range. 2. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at least one row is already active), then the power-down mode shown is active power-down. 3. No column accesses are allowed to be in progress at the time power-down is entered. -5B SYMBOL tCH t CL t CK (3) tCK (2.5) t CK (2) -6/-6T MIN MAX MIN MAX 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 5 7,5 NA NA 6 13 6 13 7.5 13 7.5 13 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN -75E/75Z -75 -5B MIN MAX MIN MAX UNITS 0.45 0.55 0.45 0.55 tCK 0.45 0.55 0.45 0.55 tCK NA NA NA NA ns 7.5 13 7.5 13 ns 7.5 13 10 13 ns SYMBOL tIH F t ISF t IHS tIS S 73 -6/-6T -75E/75Z -75 MIN MAX MIN MAX MIN MAX MIN MAX UNITS .75 .75 .90 .90 ns .75 .75 .90 .90 ns .75 0.8 1 1 ns .75 0.8 1 1 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 47: Auto Refresh Mode T0 T2 T1 T3 T4 CK# CK tIS tIH CKE tCL tIH NOP 2 PRE NOP2 NOP2 AR A0-A9, A11, A121 ALL BANKS A101 ONE BANK tIS BA0, BA11 Ta0 Ta1 (( )) (( )) VALID tIS COMMAND1 tCH CK (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) NOP2, 3 AR 6 (( )) (( )) Tb0 Tb1 Tb2 NOP2 ACT VALID NOP2, 3 (( )) (( )) (( )) (( )) RA (( )) (( )) (( )) (( )) RA (( )) (( )) (( )) (( )) BA (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) tIH Bank(s)4 DQS5 DQ5 DM5 tRP tRFC tRFC5 DON'T CARE NOTE: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address. 2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during clock positive transitions. 3. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time, CKE must be active during clock positive transitions. 4. "Don't Care" if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks). 5. DM, DQ, and DQS signals are all "Don't Care"/High-Z for operations shown. 6. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands. -5B SYMBOL t CH t CL tCK (3) t CK (2.5) t CK (2) tIH F -6/-6T MIN MAX MIN MAX 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 5 7.5 NA NA 6 13 6 13 7.5 13 7.5 13 .75 .75 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN -75E/75Z -75 -5B MIN MAX MIN MAX UNITS 0.45 0.55 0.45 0.55 tCK 0.45 0.55 0.45 0.55 tCK NA NA NA NA ns 7.5 13 7.5 13 ns 7.5 13 10 13 ns .90 .90 ns SYMBOL t ISF t IHS tIS S t RFC t RP 74 -6/-6T -75E/75Z -75 MIN MAX MIN MAX MIN MAX MIN MAX UNITS .75 .75 .90 .90 ns .75 0.8 1 1 ns .75 0.8 1 1 ns 75 72 75 75 ns 15 15 15 20 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 48: Self Refresh Mode T11 T0 CK# CK1 tCH tIS tCL tIH tIS Ta1 t IS (( )) tIH NOP Ta2 tCK tIS CKE COMMAND2 Ta01 (( )) (( )) AR (( )) (( )) NOP NOP Tb1 Tb2 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) VALID3 tIS VALID (( )) (( )) VALID (( )) (( )) VALID tIH ADDR (( )) (( )) (( )) (( )) DQS (( )) (( )) (( )) (( )) DQ (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) DM tRP4 Tc1 VALID VALID tXSNR5 tXSRD6 Enter Self Refresh Mode7 DON'T CARE Exit Self Refresh Mode7 NOTE: 1. Clock must be stable until after the self refresh command has been registered. A change in clock frequency is allowed before Ta0, provided it is within the specified tCK limits. Regardless, the clock must be stable before exiting self refresh mode. That is, the clock must be cycling within specifications by Ta0. 2. NOPs are interchangeable with DESELECT commands, AR = AUTO REFRESH command. 3. Auto Refresh is not required at this point, but is highly recommended. 4. Device must be in the all banks idle state prior to entering self refresh mode. 5. tXSNR is required before any non-READ command can be applied. That is only NOP or DESELECT commands are allowed until Tb1. 6. tXSRD (200 cycles of a valid CK and CKE = high) is required before any READ command can be applied. 7. As a general rule, any time Self Refresh Mode is exited, the DRAM may not re-enter the Self Refresh Mode until all rows have been refreshed via the Auto Refresh command at the distributed refresh rate, tREFI, or faster. However, the following exception is allowed. Self Refresh Mode may be re-entered anytime after exiting, if the following conditions are all met: a. The DRAM had been in the Self Refresh Mode for a minimum of 200ms prior to exiting. b. tXSNR and tXSRD are not violated. c. At least two Auto Refresh commands are performed during each tREFI interval while the DRAM remains out of Self Refresh mode. 8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit. 9. Once initialized, Vref must always be powered with in specified range. -5B SYMBOL t CH t CL tCK (3) t CK (2.5) t CK (2) tIH F t ISF -6/-6T MIN MAX MIN MAX 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 5 7.5 NA NA 6 13 6 13 7.5 13 7.5 13 .75 .75 .75 .75 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN -75E/75Z -75 -5B MIN MAX MIN MAX UNITS 0.45 0.55 0.45 0.55 tCK 0.45 0.55 0.45 0.55 tCK NA NA NA NA ns 7.5 13 7.5 13 ns 7.5 13 10 13 ns .90 .90 ns .90 .90 ns SYMBOL t IHS t ISS tRFC t RP t XSNR tXSRD 75 -6/-6T -75E/75Z -75 MIN MAX MIN MAX MIN MAX MIN MAX UNITS .75 0.8 1 1 ns .75 0.8 1 1 ns 75 72 75 75 ns 15 15 15 20 ns 75 75 75 75 ns tCK 200 200 200 200 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 49: Bank Read - Without Auto Precharge T1 T0 CK# T2 T3 T4 T5 T5n T6 T6n T7 T8 NOP6 ACT CK tIS tIH tIS tIH tCK tCH tCL CKE COMMAND5 NOP6 NOP6 ACT tIS x4: A0-A9, A11, A12 x8: A0-A9, A11 x16: A0-A9 RA x8: A12 x16: A11, A12 RA PRE7 NOP6 READ2 NOP6 tIH Col n RA RA tIS tIH ALL BANKS A10 RA RA 3 ONE BANK tIS BA0, BA1 tIH Bank x Bank x4 Bank x tRCD Bank x CL = 2 tRP tRAS7 tRC DM tDQSCK (MIN) Case 1: tAC (MIN) and tDQSCK (MIN) tRPST tRPRE DQS tLZ (MIN) DO n DQ1 tLZ (MIN) tAC (MIN) tDQSCK(MAX) Case 2: tAC (MAX) and tDQSCK (MAX) tRPST tRPRE DQS DO n DQ1 tAC (MAX) tHZ (MAX) DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. 6. 7. 8. DOn = data-out from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Disable auto precharge. "Don't Care" if A10 is HIGH at T5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. The PRECHARGE command can only be applied at T5 if tRAS minimum is met. Refer to Figure 40 on page 67, Figure 41 on page 68, and Figure 42 on page 69 for detailed DQS and DQ timing. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 76 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 50: Bank Read - With Auto Precharge T1 T0 CK# T2 T3 T4 T5 T5n T6 T6n T7 T8 NOP5 ACT CK tIS tIH tIS tIH tCK tCH tCL CKE COMMAND4 NOP5 NOP5 ACT tIS x4: A0-A9, A11, A12 x8: A0-A9, A11 x16: A0-A9 RA x8: A12 x16: A11, A12 RA A10 RA NOP5 NOP5 READ2,6 NOP5 tIH Col n RA RA 3 IS BA0, BA1 tIS RA tIH IH Bank x Bank x tRCD, tRAP6 Bank x CL = 2 tRP7 tRAS tRC DM Case 1: tAC (MIN) and tDQSCK (MIN) tDQSCK (MIN) tRPST tRPRE DQS tLZ(MIN) DO n DQ1 tLZ (MIN) Case 2: tAC (MAX) and tDQSCK (MAX) tAC (MIN) tDQSCK (MAX) tRPST tRPRE DQS DO n DQ1 tAC (MAX) tHZ (MAX) DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. 6. 7. 8. DOn = data-out from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Enable auto precharge. ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. The READ command can only be applied at T3 if tRAP is satisfied at T3. tRP starts only after tRAS has been satisfied. Refer to Figure 40 on page 67, Figure 41 on page 68, and Figure 42 on page 69 for detailed DQS and DQ timing. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 77 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 51: Bank Write - Without Auto Precharge T1 T0 CK# T2 T3 T4 T4n T5 T5n T6 T7 T8 NOP6 NOP6 PRE CK tIS tIH tIS tIH tCK tCH tCL CKE COMMAND5 NOP6 NOP6 ACT tIS x4: A0-A9, A11, A12 x8: A0-A9, A11 x16: A0-A9 RA x8: A12 x16: A11, A12 RA Col n tIS A10 RA tIS BA0, BA1 NOP6 NOP6 WRITE2 tIH tIH ALL BANKS 3 ONE BANK tIH Bank x Bank x4 Bank x tWR tRCD tRP tRAS tDQSS (NOM) DQS tDQSL tWPRES tWPRE tDQSH tWPST DI b DQ1 DM tDS tDH DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. 6. 7. DIn = data-in. from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Disable auto precharge. "Don't Care" if A10 is HIGH at T8. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. See Figure 43, "Data Input Timing" on page 70 for detailed DQ timing.. -5B SYMBOL t CH t CL tCK (3) t CK (2.5) t CK (2) tIH F t ISF -6/-6T MIN MAX MIN MAX 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 5 7.5 NA NA 6 13 6 13 7.5 13 7.5 13 .75 .75 .75 .75 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN -75E/75Z -75 -5B MIN MAX MIN MAX UNITS t 0.45 0.55 0.45 0.55 CK t 0.45 0.55 0.45 0.55 CK NA NA NA NA ns 7.5 13 7.5 13 ns 7.5 13 10 13 ns .90 .90 ns .90 .90 ns SYMBOL t IHS t ISS tMRD t RFC t RP tVTD 78 -6/-6T -75E/75Z -75 MIN MAX MIN MAX MIN MAX MIN MAX UNITS .75 0.8 1 1 ns .75 0.8 1 1 ns 10 15 15 15 ns 70 72 75 75 ns 15 15 15 20 ns 0 0 0 0 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 52: Bank Write - With Auto Precharge T1 T0 CK# T2 T3 T4 T4n T5 T5n T6 T7 T8 NOP5 NOP5 CK tIS tIH tIS tIH tCK tCH tCL CKE COMMAND4 NOP5 NOP5 ACT tIS NOP5 NOP5 WRITE2 NOP5 tIH x4: A0-A9, A11, A12 x8: A0-A9, A11 x16: A0-A9 RA x8: A12 x16: A11, A12 RA A10 RA Col n 3 tIS BA0, BA1 tIS tIH tIH Bank x Bank x tWR tRCD tRP tRAS tDQSS (NOM) DQS tWPRES tWPRE tDQSL tDQSH tWPST DI b DQ1 DM tDS tDH TRANSITIONING DATA DON'T CARE NOTE: 1. 2. 3. 4. 5. DIn = data-out from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Enable auto precharge. ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. 6. See Figure 43, "Data Input Timing" on page 70 for detailed DQ timing. -5B SYMBOL MIN t 0.45 CH t 0.45 CL t 5 CK (3) t CK (2.5) 6 t CK (2) 7.5 t 0.45 DH t 0.45 DS t DQSH 0.35 t DQSL 0.35 t DQSS 0.72 t 0.2 DSS -6/-6T MAX 0.55 0.55 7,5 13 13 MIN 0.45 0.45 NA 6 7.5 0.45 0.45 0.35 0.35 1.28 0.75 0.2 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN MAX 0.55 0.55 NA 13 13 -75E/75Z MIN 0.45 0.45 NA 7.5 7.5 0.5 0.5 0.35 0.35 1.25 0.75 0.2 MAX 0.55 0.55 NA 13 13 -75 MIN 0.45 0.45 NA 7.5 10 0.5 0.5 0.35 0.35 1.25 0.75 0.2 -5B MAX UNITS 0.55 tCK 0.55 tCK NA ns 13 ns 13 ns ns ns -75E/75Z -75 S ISS 0.75 RAS 40 t t 15 RCD t 15 RP tWPRE 0.25 t 0 WPRES tWPST 0.4 t 15 WR t t CK CK t CK t CK t 1.25 -6/-6T SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS t t 0.2 0.2 0.2 0.2 DSH CK t 0.75 0.8 1 1 ns IH 79 70,00 0 0.8 1 42 70,00 0 15 15 0.25 0 0.4 0.6 15 40 15 15 0.25 0 0.4 15 1 120,00 0 0.6 40 20 20 0.25 0 0.4 15 ns 120,00 0 ns ns ns tCK ns 0.6 tCK ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 53: Write - DM Operation T1 T0 CK# T2 T3 T4 T4n T5 T5n T6 T7 T8 NOP6 NOP6 PRE CK tIS tIH tIS tIH tCK tCH tCL CKE COMMAND5 NOP6 NOP6 ACT tIS x4: A0-A9, A11, A12 x8: A0-A9, A11 x16: A0-A9 RA x8: A12 x16: A11, A12 RA tIH Col n tIH tIS A10 RA tIS BA0, BA1 NOP6 NOP6 WRITE2 ALL BANKS 3 ONE BANK tIH Bank x Bank x4 Bank x tWR tRCD tRP tRAS tDQSS (NOM) DQS tDQSL tWPRES tWPRE tDQSH tWPST DI b DQ1 DM tDS tDH DON'T CARE TRANSITIONING DATA NOTE: 1. 2. 3. 4. 5. 6. DIn = data-in from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Disable auto precharge. "Don't Care" if A10 is HIGH at T8. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. 7. See Figure 43, "Data Input Timing" on page 70 for detailed DQ timing. -5B SYMBOL MIN t 0.45 CH t 0.45 CL t 5 CK (3) t 6 CK (2.5) t 7.5 CK (2) t 0.45 DH t 0.45 DS t DQSH 0.35 t DQSL 0.35 t DQSS 0.72 t 0.2 DSS MAX 0.55 0.55 7.5 13 13 -6/-6T MIN 0.45 0.45 NA 6 7.5 0.45 0.45 0.35 0.35 1.28 0.75 0.2 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN MAX 0.55 0.55 NA 13 13 -75E/75Z MIN 0.45 0.45 NA 7.5 7.5 0.5 0.5 0.35 0.35 1.25 0.75 0.2 -75 -5B MAX MIN MAX UNITS 0.55 0.45 0.55 tCK 0.55 0.45 0.55 tCK NA NA NA ns 13 7.5 13 ns 13 10 13 ns 0.5 ns 0.5 ns t 0.35 CK t 0.35 CK 1.25 0.75 1.25 tCK t 0.2 CK -6/-6T -75E/75Z -75 SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS t t 0.2 0.2 0.2 0.2 DSH CK t 0.75 0.8 1 1 ns IH S ISS 0.75 t RAS 40 t RCD tRP t WPRE t WPRES t WPST tWR 15 15 0.25 0 0.4 15 t 80 0.8 70,000 0.6 42 15 15 0.25 0 0.4 15 1 70,000 0.6 40 15 15 0.25 0 0.4 15 1 120,00 0 0.6 40 20 20 0.25 0 0.4 15 ns 120,00 0 ns ns ns t CK ns 0.6 t CK ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 54: 66-Pin Plastic TSOP (400 mil) SEE DETAIL A 22.22 0.08 0.71 0.65 TYP 0.10 (2X) 0.32 .075 TYP 11.76 0.10 10.16 0.08 +0.03 0.15 -0.02 PIN #1 ID GAGE PLANE 0.10 0.25 +0.10 -0.05 0.10 0.80 TYP 1.20 MAX 0.50 0.10 DETAIL A NOTE: 1. All dimensions in millimeters 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 81 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Figure 55: 60-Ball FBGA (10 x 12.5mm) 0.85 0.05 SEATING PLANE C 0.10 C SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3% Ag, 0.5% Cu SOLDER BALL PAD: O .33 NON SOLDER MASK DEFINED SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC 6.40 60X O .45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS O 0.40. 0.80 (TYP) BALL A1 BALL A1 ID 1.80 CTR 1.00 TYP BALL A9 BALL #1 ID 6.25 0.05 CL 11.00 12.50 0.10 5.50 0.05 CL 3.20 0.05 5.00 0.05 1.20 MAX 10.00 0.10 NOTE: All dimensions in millimeters. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef80a1d9e7 512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN 82 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000 Micron Technology, Inc. All rights reserved.