Semiconductor Components Industries, LLC, 2001
May, 2001 – Rev. 3 1Publication Order Number:
CS52843/D
CS52843
Current Mode
PWM Control Circuit
The CS52843 provides all the necessary features to implement
off–line fixed frequency current–mode control with a minimum
number of external components.
The CS52843 incorporates a new precision temperature–controlled
oscillator to minimize variations in frequency. An undervoltage
lockout ensures that VREF is stabilized before the output stage is
enabled. In the CS52843 turn on is at 8.4 V and turn of f at 7.6 V.
Other features include low start–up current, pulse–by–pulse current
limiting, and a high–current totem pole output for driving capacitive
loads, such as gate of a power MOSFET. The output is low in the off
state, consistent with N–channel devices.
Features
•Optimized for Off–Line Control
•Internally Temperature Compensated Oscillator
•VREF Stabilized before Output Stage is Enabled
•Very Low Start–Up Current 300 µA (typ)
•Pulse–by–Pulse Current Limiting
•Improved Undervoltage Lockout
•Double Pulse Suppression
•2.0% 5.0 Volt Reference
•High Current Totem Pole Output
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A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS AND
MARKING DIAGRAMS
SO–8
D SUFFIX
CASE 751
VREF
COMP
52843
1
VFB
Sense
OSC
VCC
VOUT
GND
ALYWX
Device Package Shipping
ORDERING INFORMATION
CS52843ED8 SO–8 95 Units/Rail
CS52843EDR8 SO–8
CS52843ED14 SO–14
2500 Tape & Reel
CS52843EDR14 SO–14 2500 Tape & Reel
55 Units/Rail
1
8
SO–14
D SUFFIX
CASE 751A
GNDOSC Pwr GNDNC VOUT
Sense VCC PwrNC
1
CS52843
AWLYWW
14
VCC
VFB
NCNC VREF
COMP
1
14
CS52843
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2
VOUT
Pwr GND
VREF
GND
VCC
Figure 1. Block Diagram
–
+
VCC Pwr
Internal Bias
NOR
OUTPUT
ENABLE
S
R
Current
Sensing
Comparator
1.0 V
R
2R
Oscillator
2.50 V
R
R
Error
Amplifier
8.4 V/7.6 V
34 V
VCC Undervoltage Lockout
Set/
Reset 5.0 Volt
Reference
PWM
Latch
VFB
COMP
OSC
Sense
MAXIMUM RATINGS*
Rating Value Unit
Supply Voltage (ICC < 30 mA) Self Limiting –
Supply Voltage (Low Impedance Source) 30 V
Output Current ±1.0 A
Output Energy (Capacitive Load) 5.0 µJ
Analog Inputs (VFB, VSENSE)–0.3 to 5.5 V
Error Amp Output Sink Current 10 mA
Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) 230 peak °C
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
CS52843
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3
ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ 85°C; VCC = 15 V (Note 2.); RT = 680 Ω; CT= 0.022 µF for triangle
mode, RT = 10 kΩ; CT= 3.3 nF sawtooth mode; unless otherwise specified.)
Parameter Test Conditions Min Typ Max Unit
Reference Section
Output Voltage TJ = 25°C, IREF = 1.0 mA 4.9 5.0 5.1 V
Line Regulation 12 ≤VCC ≤ 25 V – 6.0 20 mV
Load Regulation 1.0 ≤ IREF ≤ 20 mA – 6.0 25 mV
Temperature Stability Note 2. – 0.2 0.4 mV/°C
Total Output Variation Line, Load, Temp. Note 2. 4.82 – 5.18 V
Output Noise Voltage 10 Hz ≤ f ≤ 10 kHz, TJ = 25°C, Note 2. – 50 – µV
Long Term Stability TA = 125°C, 1000 Hrs. Note 2. – 5.0 25 mV
Output Short Circuit TA = 25°C –30 –100 –180 mA
Oscillator Section
Initial Accuracy Sawtooth Mode, TJ = 25°C, Note 2.
Triangle Mode, TJ = 25°C47
44 52
52 57
60 kHz
kHz
Voltage Stability 12 ≤VCC ≤ 25 V – 0.2 1.0 %
Temperature Stability Sawtooth Mode TMIN ≤ TA ≤ TMAX
T riangle Mode TMIN ≤ TA ≤ TMAX, Note 2. –
–5.0
8.0 –
–%
%
Amplitude VOSC (peak to peak) – 1.7 – V
Discharge Current TJ = 25°C
TMIN ≤ TA ≤ TMAX 7.3
6.8 8.3
–9.3
9.8 mA
mA
Error Amp Section
Input Voltage VCOMP = 2.5 V 2.42 2.50 2.58 V
Input Bias Current VFB = 0 V – –0.3 –2.0 µA
AVOL 2.0 ≤VOUT ≤ 4.0 V 65 90 – dB
Unity Gain Bandwidth Note 2. 0.7 1.0 – MHz
PSRR 12 ≤VCC ≤ 25 V 60 70 – dB
Output Sink Current VFB = 2.7 V, VCOMP = 1.1 V 2.0 6.0 – mA
Output Source Current VFB = 2.3 V, VCOMP = 5.0 V –0.5 –0.8 – mA
VOUT HIGH VFB = 2.3 V, RL = 15 kΩ to GND 5.0 6.0 – V
VOUT LOW VFB = 2.7 V, RL = 15 kΩ to VREF – 0.7 1.1 V
Current Sense Section
Gain Notes 3 & 4. 2.85 3.0 3.15 V/V
Maximum Input Signal VCOMP = 5.0 V, Note 3. 0.9 1.0 1.1 V
PSRR 12 ≤VCC ≤ 25 V, Note 3. – 70 – dB
Input Bias Current VSENSE = 0 V – –2.0 –10 µA
Delay to Output TJ = 25°C, Note 2. – 150 300 ns
2. These parameters, although guaranteed, are not 100% tested in production.
3. Parameter measured at a trip point of latch with VFB = 0.
4. Gain defined as: AVCOMP
VSENSE;0VSENSE 0.8 V
CS52843
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4
ELECTRICAL CHARACTERISTICS (continued) (–40°C ≤ TA ≤ 85°C; VCC = 15 V (Note 2.); RT = 680 Ω; CT= 0.022 µF for triangle
mode, RT = 10 kΩ; CT= 3.3 nF sawtooth mode; unless otherwise specified.)
Parameter UnitMaxTypMinTest Conditions
Output Section
Output Low Level ISINK = 20 mA
ISINK = 200 mA –
–0.1
1.5 0.4
2.2 V
V
Output High Level ISOURCE = 20 mA
ISOURCE = 200 mA 13
12 13.5
13.5 –
–V
V
Rise Time TJ = 25°C, CL = 1.0 nF, Note 5. – 50 150 ns
Fall Time TJ = 25°C, CL = 1.0 nF, Note 5. – 50 150 ns
Output Leakage UVLO Active VOUT = 0 – –0.01 –10 µA
Total Standby Current
Start–Up Current – – 300 500 µA
Operating Supply Current VFB = VSENSE = 0 V, RT = 10 kΩ; CT= 3.3 nF –11 17 mA
VCC Zener Voltage ICC = 25 mA – 34 – V
Undervoltage Lockout Section
Start Threshold – 7.8 8.4 9.0 V
Min. Operating Voltage After Turn On 7.0 7.6 8.2 V
5. These parameters, although guaranteed, are not 100% tested in production.
PACKAGE PIN DESCRIPTION
Package Lead Number
SO–8 SO–14 Lead Symbol Function
1 1 COMP Error amp output, used to compensate error amplifier.
2 3 VFB Error amp inverting input.
3 5 SENSE Noninverting i nput to Current Sense C omparator.
4 7 OSC Oscillator timing network with capacitor to ground, resistor to
VREF.
5 8 GND Ground.
– 9 Pwr GND Output driver ground.
6 10 VOUT Output drive pin.
–11 VCCPwr Output driver positive supply.
7 12 VCC Positive power suppy.
8 14 VREF Output of 5.0 V internal reference.
–2, 4, 6, 13 NC No Connection.
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5
TYPICAL PERFORMANCE CHARACTERISTICS
900
Frequency (kHz)
800
700
600
500
400
300
200
100
.0005 .001 .002 .003 .005 .01 .02 .03 .04 .05
CT (µF)
Duty Cycle (%)
100
90
80
70
60
50
40
30
20
10
RT (Ω)
Figure 2. Oscillator Frequency vs CTFigure 3. Oscillator Duty Cycle vs RT
100
200
300
400
500
700
1 k
2 k
3 k
4 k
5 k
10 k
7 k
RT = 680 Ω
RT = 1.5 kΩ
RT = 10 kΩ
VREF
COMP
VCC
VOUT
GND
VFB
Sense
OSC
CT
VREF
VCC
VOUT
GND
A
0.1 µF
0.1 µF1.0 kΩ
2N2222 RT
100 kΩ
5.0 kΩ
Sense
Adjust
4.7 kΩ
1.0 kΩ
Error Amp
Adjust
4.7 kΩ
Figure 4. Test Circuit Open Loop Laboratory Test Fixture
1.0 W
CIRCUIT DESCRIPTION
Figure 5. Startup Voltage for the CS52843
VON = 8.4 V
ON/OFF Command to reset of IC
ICC
VCC
VOFF = 7.6 V
VON VOFF VCC
< 15 mA
< 500 µA
Undervoltage Lockout
During Undervoltage Lockout (Figure 5), the output
driver is biased to sink minor amounts of current. The output
should be shunted to ground with a resistor to prevent
activating the power switch with extraneous leakage
currents.
PWM Waveform
To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal
which represents the peak output inductor current (Figure
6). An increase in VCC causes the inductor current slope to
increase, thus reducing the duty cycle. This is an inherent
feed–forward characteristic of current mode control, since
CS52843
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6
the control voltage does not have to change during changes
of input supply voltage.
When the power supply sees a sudden large output current
increase, the control voltage will increase allowing the duty
cycle to momentarily increase. Since the duty cycle tends to
exceed the maximum allowed to prevent transformer
saturation in some power supplies, the internal oscillator
waveform provides the maximum duty cycle clamp as
programmed by the selection of oscillator timing
components.
Figure 6. Timing Diagram
VOSC
OSC
RESET
Toggle
F/F Output
EA Output
Switch
Current
VCC
IO
VO
Setting the Oscillator
The times tc and td can be determined as follows:
tcRTCTlnVREF VLOWER
VREFVUPPER
tdRTCTlnVREF IdRTVLOWER
VREF IdRTVUPPER
Substituting in typical values for the parameters in the
above formulas:
VREF 5.0 V,VUPPER 2.7 V,
VLOWER 1.0 V,Id8.3 mA
then
tc0.5534RTCT
tdRTCTln2.3 0.0083RT
4.0 0.0083RT
For better accuracy RT should be ≥ 10 kΩ.
Grounding
High peak currents associated with capacitive loads
necessitate careful grounding techniques. Timing and
bypass capacitors should be connected close to GND in a
single point ground.
The transistor and 5.0 kΩ potentiometer are used to
sample the oscillator waveform and apply an adjustable
ramp to Sense.
Figure 7. Oscillator Timing Network and Parameters
VIN RT
CT
VREF
Internal Clock
VOSC
Internal Clock
Large RT (≈ 10 kΩ)
Sawtooth Mode
Triangular Mode
Small RT (≈ 700 Ω)
VUPPER
VLOWER
tctd
OSC
VREF
GND
CS52843
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7
PACKAGE DIMENSIONS
SO–8
DF SUFFIX
CASE 751–07
ISSUE W
SEATING
PLANE
1
4
58
N
J
X 45
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
–X–
–Y–
G
M
Y
M
0.25 (0.010)
–Z–
Y
M
0.25 (0.010) Z SXS
M
SO–14
D SUFFIX
CASE 751A–03
ISSUE F NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
PACKAGE THERMAL DATA
Parameter SO–8 SO–14 Unit
RΘJC Typical 45 30 °C/W
RΘJA Typical 165 125 °C/W
CS52843
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8
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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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CS52843/D
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