TEA1024/ TEA1124
TELEFUNKEN Semiconductors
Rev . A1, 24-May-96 1 (8)
Zero Voltage Switch with Fixed Ramp
Description
The monolithic integrated bipolar circuit, TEA1024/
TEA1124 is a zero voltage switch for triac control in
domestic equipments. It offers not only the control of a
triac in zero crossing mode but also the possibility of
power control. This is why the IC contains a mains
synchronized ramp generator with 640 ms (1280 ms)
duration (50 Hz). It is suitable for a typical load of 750 W
(1000 W) meeting the Flicker Standard. (values in
brackets relate to TEA1124.)
Features
D
Direct supply from the mains
D
Definite IC switching characteristics
D
Very few external components
D
Full wave drive – no dc component in the load circuit
D
Current consumption ≤ 1.5 mA
D
Output short circuit protected
D
Simple power control
D
Integrated ramp generator
D
Reference voltage variable by external resistance
D
Pulse position optimization
Package: DIP8
Block Diagram
D1
Ramp generator
TEA 1024 – 640 ms
TEA 1124 – 1280 ms Sync. logic Supply
+
–
Protection
2
1
7 4
6
5
Pulse
amplifier
Comparator
3 8
NC NC
R12 W
1N4007
C1100
m
F
16 V
Load
1000 W
L
56 k
W
100 k
W
min.
max. 43 k
W
TIC
236N
N
VM=
230 V ~
95 10871
390 k
W
(Rsync)
R2
MT2
MT1
68
W
RG
22 k
W
/
Figure 1. Typical block diagram – open loop power control
TEA1024/ TEA1124
TELEFUNKEN Semiconductors
Rev . A1, 24-May-96
2 (8)
Power Supply and its Limitations
The voltage limitation contained in the IC allows it to be
powered from mains via series resistance R1 and recti–
fying diode D1 between Pin 6 (+ Pol/
ă
) and Pin 4 (–VS).
The capacitor C1 smooths the supply voltage
(see figure 1).
An internal temperature-compensated limiting circuit
protects the module from random peaks of voltage on the
mains, and delivers a defined reference voltage during the
negative half-cycle.
Synchronization
Figure 2. Pulse position optimization
The logic function is synchronized by means of a separate
resistance R2 connected between Pin 7 and phase
(voltage-synchronization). The width of the pulse can be
varied between wide limits by choice of Rsync. The lar ger
the value chosen, the wider the output pulse is on Pin 5.
Automatic optimization of the phase of the pulse is
necessary, since the latching current of the triac exceeds
the steady current by a factor of 3.
The phase of the pulse is chosen so that ca. 1/3 of the pulse
width appears before the transition through null and 2/3
after it (see electrical characteristics and figure 2).
In order to avoid phase-clipping after the switch-on the
first third of the first pulse is automatically suppressed.
Full-Wave Logic
The full-wave logic ensures that only pairs of pulses can
be released, and that these always begin with the positive
dv/dt. The load is thus switched on for a minimum of one
complete mains cycle. This means that the triac receives
a minimum of two driving pulses, so that the unwanted
d.c. component in the load circuit is definitely eliminated.
Pulse Amplifier
The pulse amplifier connected to the output of the full-
wave logic circuit, is proof against continuos
short-circuits, and delivers negative output pulses of typ.
75 mA, via an integrated limiting resistance, to Pin 5.
Ramp Generator (Figures 3, 4)
Ramp voltage which is generated in the IC is available not
only at reference Pin 1, but also at the non-inverted input
of the comparator.
The current sink which is controlled by D/A converter
influences the internal reference voltage at Pin 1 specified
by voltage divider. The current sink is turned-off in the
reset state of the D/A converter so that the voltage at Pin 1
is primarily specified via the internal voltage divider
(ramp starting voltage).
In the maximum state of the 4 stage (5 stage – TEA1124)
D/A converter, the current sink overtakes the maximum
current, whereby the ramp’s final (end) voltage has
reached. External resistance Rx, Ry shown in figure 4 are
in position to influence the initial ramp voltage as well as
the ramp amplitude. If the external resistances ratio Rx,
Ry is the same as that of the internal ratio, the ramp
voltage at the beginning remains maintained (constant),
only the amplitude is compressed.
2.2 V
T= 640 ms
(T= 1280 ms)
V1
–1.3 V
16 stage ramp
–3.8 V
t
95 11410
Figure 3. Ramp diagram without external circuit
TEA1024/ TEA1124
TELEFUNKEN Semiconductors
Rev . A1, 24-May-96 3 (8)
–
+
Protection
50 k
W
150 k
W
A
D/A converter
D
20
Current sink
21
22
23
4 stage
ripple counter
Divider
1:2
(1:4)
Period
20 ms
(40 ms)
2
6
1
4
–VS
Rx
Ry
GND
7
Sync (50 Hz)
95 11411
Figure 4. Principle diagram – Generation and evaluation of ramp
Period
1. The time required for one complete cycle of a regular .
repeating signal, function, or series of emends.
2. The tune between two consecutive transients of the
pointer or indicating means of an electrical indicating
instrument in the same disdain the rest position.
Something called periodic fine.
Comparator
The comparison of set value and measured value is
carried out via the two comparator inputs Pin 1 and Pin 2.
Here Pin 2 is the inverting input and has a circuit pro-
tecting it against interference spikes. Figure 5 shows the
protective circuit of the comparator. Pin 1 is the non-
inverting input.
Ramp
generator
95 11412
+
–
R
T
Z
1
6
2
GND
Figure 5. Protective circuit of the comparator
Firing Pulse Width (Figures 6, 7)
It depends on the latching current as well as on the load
current of the used triacs.
whereas IL[A] = Latching current of the triac
VM[V]= Mains voltage, effective
P[W] = Power load
f[1/s] = Mains frequency
tp[s]
+
3
4
p
farcsinIL
VM
P
2
Ǹ
Firing pulse width is specified through the zero cross over
identification which can be influenced by the sync.
resistance.
Rsync [
W
]
+
VM2
Ǹ
sin
ǒ
2
3
w
tp
Ǔ
–0.6
2.5
10–5 –1.4
103
where
tp [s] = required ignition pulse width
TEA1024/ TEA1124
TELEFUNKEN Semiconductors
Rev . A1, 24-May-96
4 (8)
0.01
0.10
1.00
10.00
10 100 1000 10000
t ( ms )
P ( W )96 11939
p
IL ( mA)
100
200
50
Vmains = 230 V∼
Figure 6.
0 200 400 600 800
0
0.5
1
1.5
2
2.5
R ( M )
2
tp (
m
s )
1000
95 11
W
VMains=230V
X
Figure 7.
Ignition (Firing) Current
The necessary ignition current depends on the specified
triac. With the help of a resistance, it is possible to limit
its value:
whereas VG[V]= Gate voltage of the triac
IG[A]= Max. gate current
IP[A]= Average gate current requirement
tP[s]= Ignition pulse width
T[s]= Duration (of mains frequency)
RGmax [
W
]
[
5.7V–V
Gmax
IGmax –25
W
Ip[A]
+
IGmax
T
tp
Supply Voltage
Due to higher trigger sensitivity of the triac it is supplied
with negative signal. It can be supplied via diode and
series resistance from the negative half wave of the mains.
An internal parallel controller limits the voltage between
Pin 5 and 7 to a typical value of 6.55 V.
Dimensioning of the Series Resistance
R1 (Figures 8, 9)
VM= Mains supply
VS= Limiting voltage of the IC
Itot = Total current requirement
Ix= Current requirement for external circui
t
R1max
+
0.85 VMmin –V
Smax
2I
tot –65
W
Itot
+
IS
)
IP
)
IXP(R1)
+
(VM–V
S
)
2
2R
1
03 6 912
0
10
20
30
40
50
R ( k )
1
Itot ( mA )
15
95 10114
VMains=230V
X
W
Figure 8.
03 6 912
0
I
tot ( mA )
15
95 10116
VMains=230V
X
1
2
3
4
6
P ( W )
5
R1
Figure 9.
TEA1024/ TEA1124
TELEFUNKEN Semiconductors
Rev . A1, 24-May-96 5 (8)
Absolute Maximum Ratings
Reference point Pin 6
Parameters Symbol Value Unit
Current consumption Pin 4
t≤ 10
m
s–IS
is
30
150 mA
Sync. current Pin 7
t≤ 10
m
sISync
iSync
5
40 mA
Comparator input current Pin 2
"
II1 mA
Input voltages Pin 1,4,5
Pin 5 –VI
+VI≤VS
≤ 0.5 V
Power dissipation Tamb = 45°C
Tamb = 100°CPtot 400
125 mW
Junction temperature Tj125 °C
Ambient temperature range Tamb 0 to 100 °C
Storage temperature range Tstg –40 to + 125 °C
Thermal Resistance
Parameters Symbol Maximum Unit
Junction ambient RthJA 200 K/W
Electrical Characteristics
Supply voltage –VS = 5.6 V, Tamb = 25°C, f = 50 Hz, reference point Pin 6, unless otherwise specified
Parameters Test Conditions / Pins Symbol Min Typ Max Unit
Supply voltage limitation –I4 = 1 mA Pin 4 –VS5.7 7.4 V
Current consumption Pos. half, cycle Pin 4
Zero cross over
(Pin 5 open) Pin 4
neg. half cycle Pin 4
–IS
–IS
–IS
1
1
1.8
mA
Synchronization Pin 7
Voltage limitation ±I7 = 1 mA
"
VI1.0 1.8 V
Synchronization current
"
ISync 0.15 mA
Zero cross detection
"
ISync 25
mA
Comparator, figure 5
Input zero voltage Pin 1, 2 V10 10 mV
Input quiescent current Pin 2 IB1
mA
Common mode input
range Pin 1, 2 –VIC 1 (VS–1.6) V
TEA1024/ TEA1124
TELEFUNKEN Semiconductors
Rev . A1, 24-May-96
6 (8)
UnitMaxTypMinSymbolTest Conditions / PinsParameters
Ramp generator, figures 3, 4 Pin 1
Period TEA1024 T640 ms
TEA1124 1280
Step number n 16
Initial voltage –V11.2 1.4 1.6 V
Final voltage –V13.3 3.6 3.9 V
Internal reference
ǒ
VS
)
2.5%
4–7.5%
Ǔ
V
Temperature coefficient of
internal reference
"
TCRef 1.2 mV/K
Pulse amplifier Pin 5
Output pulse current VG ≤1.5 V –IO50 100 mA
Output pulse width VSync = 230 V
X
,
R2 = 220 k
W
t0
t1
t2
33
65
110
m
s
Applications
MT1
Ramp generator
TEA 1024 – 640 ms
TEA 1124 –1280 ms Sync. logic Supply
+
–
Protection
2
1
7 4
6
5
Pulse
amplifier
Comparator
38
NC NC
R122 k
W
/
2 W
D11N4007
C1100
m
F
16 V
Load
0.7...1.5 kW
L
TIC
236N
N
VM =
230 V ~
95 11416
390 k
W
/(Rsync)
R2
0.5 W
MT2
68
W
RG
R(25) = 10 k
W
R(30) = 8 k
W
R(10) = 20 k
W
NTC / M87
B value = 3474
Figure 10. Simple temperature regulation with maximum proportional range
TEA1024/ TEA1124
TELEFUNKEN Semiconductors
Rev . A1, 24-May-96 7 (8)
MT1
Ramp generator
TEA1024 – 640 ms
TEA1124 –1280 ms Sync. logic Supply
Protection
2
1
7 4
6
5
Pulse
amplifier
Comparator
3 8
NC NC
R122 k
W/
2 W
D11N4007
C1100
m
F
16 V
Load
0.7...1.5 kW
L
2.2 k
W
TIC
236N
N
VM=
230 V ~
95 11417
390 k
W/
(Rsync)
R2
0.5 W
MT2
68
W
RG
R(25) = 10 k
W
R(30) = 8 k
W
R(10) = 20 k
W
NTC / M87
B value = 3474
R12
10 k
W
R6
33 k
W
R4
50 k
W
Rp
+
–
Figure 11. Temperature regulation with proportional range, 10 to 30 °C/ 640 ms ramp cycle
Dimensions in mm
Package: DIP8
TEA1024/ TEA1124
TELEFUNKEN Semiconductors
Rev . A1, 24-May-96
8 (8)
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It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
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forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban
on these substances.
TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of
continuous improvements to eliminate the use of ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain
such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
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Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423
