! \ 27011 PAGE-ADDRESSED 1M (8 x 16K x 8) UV ERASABLE PROM a Paged Organization = Automatic Page Clear Reduced Physical Address Resets to Page 0 on Power-Up and Requirement On Demand with RST Signal(1) m Compatible with 28-Pin JEDEC EPROMs m High-Performance HMOS* II-E Single-Trace Modification for 200 ns Access Time Retrofitting 27128-Based Designs - Low 150 mA Active Power m No-Hardware-Change Upgrades m Standard EPROM Features Drop-in 27513 Replacement TTL Compatibility Two Line Control m Fast Programming inteligent Identifier for Automated - Quick-Pulse Programming Algorithm Programming Programming Time as Fast as m Smallest Megabit DIP Package 15 Seconds 28-Pin DIP, Minimal Footprint without Address/Data Multiplexing The Intel 27011 is a 5V-only, 1,048,576-bit Erasable Programmable Read Only Memory. It is organized as 8 pages of 16K 8-bit words. Its pin-compatibility with byte-wide JEDEC EPROMs allows retrofitting existing designs to the greater storage capacity afforded by the page-addressed organization. its 16 K-byte physical address space requirement allows the 27011 to be utilized in address-constrained system designs. When a 28-pin DIP socket is configured for 2764 or 27128 EPROMs, it is easily retrofitted to the 27011. By adding a WRITE ENABLE signal to pin 27 (DIP) or pin 31 (PLCC) (unused on 2764 and 27128), the 27011 can be used in an existing design. Thus, the 27011 enables product enhancements via additional feature sets and firmware-intensive performance upgrades. The page-addressed organization allows the use of 28-pin DIP packages, the smallest megabit EPROM footprint with applicability to all microprocessors. This provides very efficient circuit board layouts. The 27011 has an automatic page clear circuit for ease of use of its paged organization. The page-select latch is automatically cleared to the lowest order page upon system power-up. The 27011 also contains many industry-standard features such as two-line output control for simple interfacing and the intgligent Identifier feature for automated programming. It also can be programmed rapidly using Intels Quick-Pulse Program- ming Algorithm. The 27011 is manufactured using an advanced version of intels HMOS* II-E process which assures highest reliability and manufacturability. *HMOS is a patented process of Inte! Corporation. NOTE: 1. RST feature available on all devices shipped from Intel in 1989 and those shipped in 1988 with its 7-digit backside date code beginning with the number 7. October 1989 4-183 Order Number: 290107-00627011 Voc O> cE PROGRAM PGM/WE OE AND CE OE LOGIC AomA13 ADDRESS x Y . INPUTS DECODER | DECODER x SELECT DATA INPUTS/ DATA QUTPUTS OUTPUTS Ox-07 __ roy D: Vpp/RST 06162- PAGE SELECT Losic ""=GATING 131,072 CELL MATRIX PAGE 0 290107-1 Figure 1. Block Diagram 27513 27128A aoe eee 27128A 27513 27C513 270128 87064 27011 87064 270128 27C513 RST Vpp Vpp Vee 1 289 Vee Voc Voc Voc Ai2 Ai2 Ay2 Aygt2 2712 PM /WE PGM PGM WE Ar A7 A7 ays 26D Ay; N.C. Aig Ais As Ae Ag apts 25D As Aa Ag Ag As As As as C15 24 Ag Ag Ag Ag vy Ag Ag ads 23 An An An AN Ag Ag Ag A347 22 E OE OE OE/Vpp Ag Aa Aa as 21 Ato Ato Ato Ato AY Ay Ay Adds 20P) ce CE CE cE Ao Ao Ao Ao] 10 190, O7 O7 O7 Do/Og Oo Oo Do/Og 4 11 1800, Og Og 06 D/O, Oy O1 D,/0,C4 12 17D os, Os Os Os Og Og Oo 2/02 C4 13 1690, O4 O4 O4 GND GND GND GND a 14 150g 03 O3 Og 290107-~2 Figure 2. Pin Configuration 4-18427011 Pin Names Ao-Ai3 Addresses cE Chip Enable OE Output Enable WE Page-Select Write Enable Og-O7 Outputs Dy/Ox Input/Outputs (X = 0, 1, or 2) Vpp/RST | Vpp/Page Reset N.C. No Internal Connection D.U. Dont Use EXTENDED TEMPERATURE (EXPRESS) EPROMs The Intel EXPRESS EPROM family is a series of EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITIONS electrically programmable read only memories which Type Tonperatue 125 (rr) have received additional processing to enhance product characteristics. EXPRESS processing is Q 0C to + 70C 168 +8 available for several densities of EPROM, allowing T 40C to + 85C None the choice of appropriate memory size to match sys- tem applications. EXPRESS EPROM products are L 40C to + 85C 168 +8 available with 168 +8 hour, 125C dynamic burn-in using Intels standard bias configuration. This pro- cess exceeds or meets most industry specifications EXPRESS OPTIONS of burn-in. The standard EXPRESS EPROM operat- ing temperature range is 0C to 70C. Extended op- 27011 VERSIONS erating temperature range ( 40C to +85C) EX- PRESS products are available. Like all Intel Packaging Options EPROMs, the EXPRESS EPROM family is inspected Speed Versions Cerdip to 0.1% electrical AQL. This may allow the user to -250V05 QTb reduce or eliminate incoming inspection testing. Vpp/RST EY 1 - 2819 Voc Ay2Ch2 27 5) Pom /WE 30us +> 4703 260 A,; AO Agly4 25 [5 As Ag CH5 241) Ag A, M36 23 Ay Al JT LS 4;0}7 22EF OE . ate 77" aan : A:ci9 20D cE A13 990107-5 foG 10 19 pe 07 Binary Sequence from Ap to A13 required for each page. Page 09/09 wr] 11 18 [Ce-we= O changes during burn-in require the following minimum timing param- D,/0, neo 12 17 a Os eter values (e0 Page-Select A.C. Characteristics): 02/0, et] 13 16 hw 0, We e500 ne GND] 14 15 Dw 0; twa = 500 ns R tps = 500 ns 290107-4 ox = 500 ns Vpp = +8V R=1KN Voo= +5V GND = ov CE = GND Burn-in Bias and Timing Diagrams 4-185! intel 27011 ABSOLUTE MAXIMUM RATINGS* Operating Temperature Ls (-- (0 0C to + 70C Temperature Under Bias......... 10C to + 80C Storage Temperature .......... 65C to + 125C All Input or Output Voltages with Respect to Groundt.......... 0.6V to + 6.25V Voltage on Ag with Respect to Ground ........... 0.6V to + 13.5V Vpp Supply Voltage with Respect to Ground During Programming ....0.6V to + 14V Voc Supply Voltage with Respect to Ground ........ 0.6V to +7.0V READ OPERATION D.C. CHARACTERISTICS 0C < Ta < +70C *Notice: Stresses above those listed under Abso- lute Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Ex- posure to absolute maximum rating conditions for extended periods may affect device reliability. Limits Symbol Parameter Min Typ(2) Max Units Conditions tu Input Load Current 1 pA Vin = 5.5V lLo Output Leakage Current 10 pA Vout = 5.5V lLAst) Vpp/RST Load Current 500 pA Vpp/RST < Voc Isa Voc Current Standby 50 mA CE = Vin loc1 (4) Voc Current Active 150 mA CE = OE = Vi_ Vit Input Low Voltage -0.1 +0.8 Vv Vin Input High Voltage 2.0 Voct1 v Vo. Output Low Voltage 0.45 Vv lo. = 2.1 mA Vou Output High Voltage 2.4 Vv lou = 400 pA Voir Page Latch ClearVoc 3.5 4.0 Vv A.C. CHARACTERISTICS 0C < Ta < +70C Versions Veco +5% 27011-200V05 27011-25005 Units Veco + 10% 27011-200V10 27011-250V10 Symbol Characteristics Min Max Min Max tacc Address to Output Delay 200 250 ns toe CE to Output Delay 200 250 ns toe OE to Output Delay 85 400 ns tor) OE High to Output Float 0 60 0 60 ns ton Output Hold from 0 0 ns Addresses, CE or OE Whichever Occurred First NOTES: 1. Vpp/RST should be at a TTL Vip level except during programming or during page 0 reset. 2. Typical values are for Ta = 25C and nominal supply voltages. 3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer drivensee timing diagram. 4. The maximum current value is with outputs Op to O7 unloaded. 4-186| intel 27011 PAGE-SELECT WRITE AND PAGE-RESET OPERATION A.C. CHARACTERISTICS 0C < Ta < +70C Symbol Parameter Limits Units Test Min Max Conditions tow CE to End of Write 180 ns OE = Vin twp Write Pulse Width 100 ns OE = Vin twa Write Recovery Time | 20 ns tps Data Setup Time 50 ns OE = Vin too Data Hold Time 20 ns OE = Vin tes CE to Write Setup Time 0 ns OE = Vin twH WE Low from OE High Delay Time 55 ns trst Reset Low Time 250 ns trav Reset to Address Valid 250 ns CAPACITANCE(!) T, = +25C, f = 1 MHz Symbol Parameter Typ(1) | Max | Units | Conditions Cin Input Capacitance 4 6 pF Vin = OV Cout Output Capacitance 8 12 pF Vout = OV Cvpp/RST | Vep/RST Capacitance 18 25 pF j Vin = OV 1. Sampled. Not 100% tested. A.C. TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 1.3V 1N914 24 2.0 5 2.0 nas mrur X os = rest POINTS <Xe OUTPUT 3.3K0 - 290107-6 UNDER OUT TEST C, =100 pf I AC Testing inputs are driven at 2.4V for a logic 1 and 0.45V for a = logic 0. Timing measurements are made at 2.0V for a logic 1 and 290107-7 0.8V for a logic 0. CL = 100 pF C,, Includes Jig Capacitance 4-187intel 27011 A.C. WAVEFORMS FOR READ OPERATION Vin ars Vit cE Vn ADDRESSES x ADORESS Va V4 ema erinsensaerremran OE Va ben 6 0.0 memad toe3)-r OUTPUT HIGH 2, Vie Vin LH toet) aT WE vu 290107-8 A.C. WAVEFORMS FOR PAGE-SELECT WRITE OPERATION ADDRESS ADDRESSES xX DON'T CARE tow!4] ____J ADDRESS VALID AMIN TWA(2) tpl] = cE tes > PGM/WE N twe 2 51___o OE D9/Op, 01/01, 09/02 INPUT/OUTPUTS 03-07 OUTPUTS tos D> DATA IN STABLE ton l ae 290107-9 4-188i intel 27011 A.C. WAVEFORMS FOR PAGE-RESET OPERATION ADDRESSES xX ADDRESS DONT CARE x ADDRESS VALID test trav Vpp/RST \ / NOTES: 1. Typical values are for Ta = + 25C and nominal supply voltages. 2. This parameter is only sampled and is not 100% tested. 3. OE may be delayed up to tce- tog after the falling edge of CE without impact on toe. 4. Write may be terminated by either CE or WE, providing that the minimum tow requirement is met before bringing WE high or that the minimum twp requirement is met before bringing CE high. 5. OE must be high during write cycle. 290107-14 DEVICE OPERATION The modes of operation of the 27011 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for Vpp and 12V on Ag for intgligent Identifier. Table 1. Operating Modes om Pins | cE | OE pd Ag | Ao | Vpp/RST| Voc | Outputs Outputs Read Vico} Vir} Vin x(1) xX Vin 5.0V Dout Dout Output Disable Vi} Vin} Vig x |X Vin 5.0V | HighZ | HighZ Standby Vin | X x x | x Vin 5.0V | HighZ | HighZ Programming Vir | Vie} Vin X X Vpp) | Voc (3) Din Din Verify Vin} Vir | Vin X | X | Vep | Vec | Dour Dout Program Inhibit Vin | X | Vig X | X | Vpp@) | Voc] HighZ | HighZ Page-Select Write Vie | Vie} Vin x | xX Vin Voc!) | (Note 7) | Page Din Page-Reset xX xX x Xx X Vit Voc | (Note 7) X inteligent Manufacturer|) Vir] Vir} Vin | Vu | Vir Vin 5.0V 89H 89H Identifier Device Vi} Vic | Via | Vat) | Vy Vig 5.0V 85H 85H NOTES: 1. X can be Viyq or Vic. 2. Addresses are dont care for page selection. See Tabie 2 for Diy values. 3. See Table 3 for Voc and Vpp. 4. A1-Ag, A1o-At3. = ViL- 5. Page 0 is automatically selected at power-up (Vcc < 4.0V). 6. Vy = 12.0V +0.5%. 7. State of outputs depends on state of CE and OE. See Outputs State for Read, Output Disable, and Standby Modes. 4-189intel 27011 Read Mode The 27011 has three control functions, two of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (GE) is the output control and should be used to gate data from the output pins, independent of de- vice selection. Assuming that addresses are stable, the address access time (tacc) is equal to the delay from CE to output (tce). Data is available at the out- puts after a delay of tog from the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tacc-tog. WE is held high during read operations. Standby Mode EPROMs can be placed in standby mode which re- duces the maximum current of the device by apply- ing a TTL-high signal to the CE input. When in stand- by mode, the outputs are in a high impedance state, independent of the OE and WE inputs. Page-Select Write Mode The 27011 is addressed by first selecting one of eight 16 K-byte pages. Individual bytes are then se- lected by normal random access within the 16 K-byte page using the proper combination of Ao~A13 address inputs. By applying a TTL low sig- nal to the WE input with CE low and OE high, the desired page is latched in according to the combina- tion of Do/Op, 04/0, and Dz/Og. Address inputs are dont care during page selection. Care should be taken in organizing software pro- grams such that the number of page changes is min- imized. This allows maximum system performance. Also, the processors program counter status must be considered when page changes occur in the mid- dle of an opcode sequence. After a page-select write, the program counter will be incremented to the next location (or further in pipelined systems) in the new page relative to that of the page-select write opcode in the previous page. Table 2. Page Selection Data Input/Output Page Selection D2/O2 | D1/O1 | Do/Oo Select Page 0 Vit Vit ViL Select Page 1 Vit ViL Vin Select Page 2 Vit Vin VIL Select Page 3 ViL Vin Vin Select Page 4 Vin Vit ViL Select Page 5 Vin Vit Vin Select Page 6 ViH VIH Vit Select Page 7 Vin Vip Vin Page Reset The 27011 has an automatic page latch clear circuit to ensure consistent page selection during system bootstrapping. The page latch is automatically cleared to page 0 upon power-up. As the Vcc supply voltage ramps up, the page latch is cleared. After Voc exceeds the 4.0V maximum page latch clear voltage (VciRA), the latch clear circuit is disabled. This ensures an adequate safety margin (500 mV of system noise below the worst case 10% Vcc sup- ply condition) against spurious page latch clearing. All 27011 parts shipped in 1989 and those shipped in 1988 with a 7-digit backside date code beginning with the number 7 also have a page reset pin: Vpp/ RST. This pin should be tied to an active low reset line. These 2701 1s will be reset to page 0 when this line is brought to TTL Low (Vj,). Two Line Control Because EPROMs are usually used in larger memo- ry arrays, Intel has provided 2 output control lines which accommodate this multiple memory connec- tion. The two control lines for read operation allow for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To use these two control lines most efficiently, CE should be decoded and used as the primary device selecting function, while OE should be made a com- mon connection to all devices in the array and con- nected to the READ line from the system control bus. This assures that all deselected memory devic- es are in their low power standby mode and. that the output pins are active only when data is desired from a particular memory device. Similarly, CE deselects other 27011s or RAMs dur- ing page select write operation while WE is in com- mon with other devices in the array. WE is connect- ed to the WRITE system control fine. SYSTEM CONSIDERATIONS The power switching characteristics of EPROMs re- quire careful decoupling of the devices. The supply current, loc, has three segments that are of interest to the system designerthe standby current level, the active current level, and the transient current peaks that are produced by the falling and rising edges of Chip Enabie. The magnitude of these tran- sient current peaks is dependent on the output ca- pacitive and inductive loading of the device. The as- 4-190a intel - 27041 sociated transient voltage peaks can be suppressed by complying with Intels Two-Line Control and by properly selected decoupling capacitors. It is recom- mended that a 0.1 F ceramic capacitor be used on every device between Vcc and GND. This should be a high frequency capacitor of low inherent induc- tance and should be placed as close to the device as possible. In addition, a 4.7 uF bulk electrolytic capacitor should be used between Vcc and GND for every eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effects of PC board traces. This inductive effect should be further minimized through special layout considerations such as larger traces and gridding (refer to High Speed Memory System Design Using the 2147H, AP-74). In particular, the Vsgg (Ground) plane should be as stable as possible. PROGRAMMING Caution: Exceeding 14.0V on Vpp will permanent- ly damage the 27011. Initially, and after each erasure, all bits of the EPROM are in the 1 state. Data is introduced by selectively programming Os into the desired bit lo- cations. Although only Os will be programmed, both 1s and Os can be present in the data word. The only way to change a 0 to a 1 is by ultravio- let light erasure. The 27011 is in the programming mode when the Vpp input is at its programming voltage and CE is at TTL-low. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. Program Inhibit Programming of multiple 27011s in parallel with dif- ferent data is easily accomplished by using the Pro- gram Inhibit mode. A high-level CE input inhibits the other 27011s from being programmed. Except for CE, ail inputs of the parallel 27011s may be common. A TTL low-level pulse applied to the PGM/WE input with Vpp at its programming voltage will program the selected 27011. Verify A verify (read) should be performed on the pro- grammed bits to determine that they have been cor- rectly programmed. The verify is performed with OE and CE at Vi_ and Vcc is at its programming voltage Data should be verified tpy after the falling edge of CE. inteligent identifier Mode The intgligent Identifier Mode allows the reading out of a biriary code from an EPROM that will identify its manufcturer and type. This mode is intended for use by programming equipment for the purpose of auto- matically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C +5C ambient tem- perature range that is required when programming the device. To activate this mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the EPROM. Two identifier bytes may then be se- quenced from the device outputs by toggling ad- dress line AO from Vj, to Viy. All other address lines must be held at Vi_ during the intgligent Identifier Mode. Byte 0 (AO = Vj.) represents the manufacturer code and byte 1 (AO-= Vj) the device identifier code. These two identifier bytes are given in Table 1. ERASURE CHARACTERISTICS The erasure characteristics are such that erasure begins to occur upon exposure to light with wave- lengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000 A range. Data show that constant expo- sure to room level fluorescent lighting could erase the EPROM in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. !f the device is to be ex- posed to these types of lighting conditions for ex- tended periods of time, opaque labels should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose ({i.e., UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm?. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 ,.W/cm2 power rat- ing. The EPROM should be placed within 1 inch of the lamp tubes during erasure. The maximum inte- grated dose an EPROM can be exposed to without damage is 7258 Wsec/cm? (1 week @ 12000 pW/cm2). Exposure of the device to high intensity UV light for long periods may cause permanent dam- age. 4-194intel 27011 DEVICE FAILED 290107-10 Figure 4. 27011 Quick-Pulse Programming Flowchart Quick Pulse Programming Algorithm Intes 27011 EPROM is programmed using the Quick-Pulse Programming Algorithm, developed by Intel to substantially reduce the throughput time in the production programming environment. This algo- rithm allows these devices to be programmed as fast as fourteen seconds, almost a hundred fold im- provement over previous algorithms. Actual pro- gramming time is a function of the PROM program- mer being used. The Quick-Pulse Programming Algorithm uses initial pulses of 100 microseconds followed by a byte veri- fication to determine when the address byte has been successfully programmed. Up to 25 100 us pulses per byte are provided before a failure is rec- ognized. A flowchart of the Quick-Pulse Program- ming Algorithm is shown in Figure 4. For the Quick-Pulse Programming Algorithm, the en- tire sequence of programming pulses and byte verifi- cations is performed at Vcc = 6.25V and Vpp at 12.75V. When programming of the EPROM has been completed, all bytes should be compared to the original data with Voc = Vpp = 5.0V. 4-192intel 27011 D.C. PROGRAMMING CHARACTERISTICS Ta = 25C +5C Table 3 Limits Test Conditions Symbo! Parameter Min Max Units (Note 1) lu Input Current (Ail Inputs) 10 pA Vin = Vic or Vin Vi input Low Level (All Inputs) 0.1 0.8 Mv Vin Input High Level 2.0 Voct+1 Vv VoL Output Low Voltag During Verify 0.45 Vv lop = 2.1mMA | VoH Output High Voltage During Verify 2.4 Vv lou = 400 pA loc2) Voc Supply Current (Program and Verify) 150 mA Ippo Vpp Supply Current (Program) 50 mA CE = Vip Vio Ag inteligent identifier Voitage 11.5 12.5 Vv Vpp Quick-Putse Programming Algorithm 12.5 13.0 Vv Voc Quick-Pulse Programming Algorithm 6.0 6.5 Vv. A.C. PROGRAMMING CHARACTERISTICS Ta = 25C +5C (See Table 3 for Vcc and Vpp voltages.) Symbol Parameter Limits Conditions* Min | Typ | Max | Units (Note 1) tas Address Setup Time 2 ps toes OE Setup Time 2 pS tos Data Setup Time 2 Ss taH Address Hold Time 0 pS toH Data Hold Time 2 ps torp OE High to Output Float Delay 0 130 ns (Note 2) typs Vpp Setup Time 2 pS tyos Voc Setup Time 2 pS tces CE Setup Time 2 a) ; tpw PGM Program Pulse Width 95 100 105 pS Quick-Pulse Programming toe Data Valid from OE 150 ns *A.C. CONDITIONS OF TEST 1. Voc must be applied simultaneously or before Vpp and Input Rise and Fall Times (10% to 90%)... 20 ns ee ree rae cn sampled'and is not 100% tested. Input Pulse Levels ................6. 0.45V to 2.4V Output Float is defined as the point where data is no long- Input Timing Reference Level ....... 0.8V and 2.0V 3 atvorr eee timing diagram is with outputs Op-Oy un- Output Timing Reference Level ...... 0.8V and 2.0V loaded. 4-193intel 27011 PROGRAMMING WAVEFORMS VERIFY v, v2 ADDRESSES x ADDRESS STABLE Vu at ae bag tH Yor { HIGHZ f . DATA DATA IN STABLE { DATA OUT VALID v >: " tos Lig tow a] wl tore 12.750 Oe Vpp 5.0V tves 6.25V ee Veo ] , 5.0V ees Vin ce ry Vu te ee PGM/WE Vie bow toes ~~ =| toe Yn oo _ <== e \ / Va 290107-12 NOTES: 1. The Input Timing Reference Level is 0.8V for a Vi, and 2.0V for a Vin. 2. tog and tprp are characteristics of the device but must be accommodated by the programmer. 3. The proper page to be programmed must be selected by a page-select write operation prior to programming each of the four 16 Kbyte pages. See Page Select Write AC and DC Characteristics for information on page selection operations. REVISION HISTORY Number Description 06 Revised Express Options Revised Pin Configuration Added 27011-200V 10 Speed Bin 4-194