OM13069 - NXP Semiconductors

1. General description

The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory

and 4 kB of SRAM.

The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus

interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer , self wake-up

timer, and state-configurable timer, one comparator, function-configurable I/O ports

through a switch matrix, an inpu t p atter n match engin e, and up to 18 gene ra l-purp ose I/O

pins.

2. Features and benefits

System:

ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with

single-cycle multiplier and fast single-cycle I/O port.

ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

System tick timer.

Serial Wire Debug (SWD) an d JTAG bound ar y scan mo de s su pp or te d.

Micro Trace Buffer (MTB) supported.

Memory:

Up to 16 kB on-chip flash programming memo ry with 64 Byte page write an d erase.

Up to 4 kB SRAM.

ROM API support:

Boot loader.

USART drivers.

I2C drivers.

Power profiles.

Flash In-Application Programming (IAP) and In-System Progr amming (ISP).

Digital peripherals:

High-speed GPIO interface connecte d to the ARM Co rtex-M0+ IO bus with up to 18

General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and glitch filter.

High-current source output driver (20 mA) on four pins.

High-current sink driver (20 mA) on two true open-drain pins.

GPIO interrupt generation capability with boolean pattern-matching feature on eight

GPIO inputs.

Switch matrix for flexible configuration of each I/O pin function.

LPC81xM

32-bit ARM® Cortex®-M0+ microcontroller; up to 16 kB flash

and 4 kB SRAM

Rev. 4.6 — 4 April 2018 Product data sheet

Product data sheet Rev. 4.6 — 4 April 2018 2 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

State Configurable Timer/PWM (SCTimer/PWM) with input and output functions

(including capture and match) assigned to pins through the switch matrix.

Multiple-channel multi-rate timer (MRT) for repetitive interrupt generation at up to

four programmable, fixed rates.

Self Wake-up Timer (WKT) clocked from either the IRC or a low-power,

low-frequency internal oscillator.

CRC engine.

Windowed Watchdog timer (WWDT).

Analog peripherals:

Comparator with internal and external voltage references with pin functions

assigned or enabled through the switch matrix.

Serial interfaces:

Three USART interfaces with pin fu nct ion s ass ign e d thr o ug h th e switc h ma trix.

Two SPI controllers with pin functions assigned through the switch matrix.

One I2C-bus interface with pin functions assigned through the switch matrix.

Clock generation :

12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be

used as a system clock.

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.

10 kHz low-power oscillator for the WKT.

PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator, the external clock

input CLKIN, or the internal RC oscillator.

Clock output function with divider that can reflect the crystal oscillator, the main

clock, the IRC, or the watchdog oscillator.

Power control:

Integrated PMU (Power Management Unit) to minimize power consumption.

Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode.

W ake-up from Deep-sleep and Powe r-down modes on activity on USART, SPI, and

I2C peripherals.

Timer-controlled self wake-up from Deep power-down mode.

Power-On Reset (POR).

Brownout detect.

Unique device serial number for identification.

Single power supply.

Operating temperature range 40 °C to 105 °C except for the DIP8 package, wh ich is

available for a temperature range of 40 °C to 85 °C.

Available as DIP8, TSSOP16, SO20, TSSOP20, and XSON16 package.

3. Applications

8/16-bit app licat ion s Lighting

Consumer Mo to r co nt ro l

Climate control Fire and security application s

Product data sheet Rev. 4.6 — 4 April 2018 3 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

4. Ordering information

4.1 Ordering options

Table 1. Ordering information

Type number Package

Name Description Version

LPC810M021FN8 DIP8 plastic dual in-line package; 8 leads (300 mil) SOT097-2

LPC811M001JDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

LPC812M101JDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

LPC812M101JD20 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

LPC812M101JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

LPC812M101JTB16 XSON16 plastic extremely thin small outline package; no leads; 16 termina ls;

body 2.5  3.2  0.5 mm SOT1341-1

Table 2. Ordering options

Type number Flash/kB SRAM/kB USART I2C-bus SPI Comparator GPIO Package

LPC810M021FN8 4 1 2 1 1 1 6 DIP8

LPC811M001JDH16 8 2 2 1 1 1 14 TSSOP16

LPC812M101JDH16 16 4 3 1 2 1 14 TSSOP16

LPC812M101JD20 16 4 2 1 1 1 18 SO20

LPC812M101JDH20 16 4 3 1 2 1 18 TSSOP20

LPC812M101JTB16 16 4 3 1 2 1 14 XSON16

Product data sheet Rev. 4.6 — 4 April 2018 4 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

5. Marking

The LPC81xM devices typically have the following top-side marking:

LPC81x

xxxxx

xxxxxxxx

xxYWWxR[x]

The last two letters in the last line (field ‘xR’) ide nt ify the bo ot code ver sio n an d de vice

revision.

Field ‘Y’ states the year the device was manufactured. Field ‘WW’ states the week the

device was manufactured during that year.

Remark: On the TSSOP16 package, the last line includes only the date code xxYWW.

Table 3. Devic e revision table

Revision identifier (xR) Revision description

‘1A’ Initial device revision with boot code versi on 13.1

‘2A’ Device revision with boot code version 13.2

’4C’ Device revision with boot code version 13.4

Product data sheet Rev. 4.6 — 4 April 2018 5 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

6. Block diagram

Fig 1. LPC81xM block diagram

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Product data sheet Rev. 4.6 — 4 April 2018 6 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

7. Pinning information

7.1 Pinning

Fig 2. Pin configuration DIP8 package (LPC810M021JN8)

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Product data sheet Rev. 4.6 — 4 April 2018 7 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Fig 5. Pin configuration TSSOP20 package (LPC812M101JDH20)

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Fig 6. Pin configuration XSON16 package (LPC812M101JTB16)

terminal 1

index area

XSON16

aaa-009570

Transparent top view

PIO0_13

PIO0_12

RESET/PIO0_5

PIO0_4/WAKEUP/TRST

SWCLK/PIO0_3/TCK

SWDIO/PIO0_2/TMS

PIO0_11

PIO0_10

PIO0_0/ACMP_I1/TDO

PIO0_6/VDDCMP

PIO0_7

PIO0_8/XTALIN

PIO0_9/XTALOUT

PIO0_1/ACMP_I2/CLKIN/TDI

Product data sheet Rev. 4.6 — 4 April 2018 8 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

7.2 Pin description

The pin description consists of two parts showing pin functions that are fixed to a certain

package pin (see Table 4) and showing pin functions that can be assigned to any pin on

the package through the switch matrix (see Table 5).

The pin description table in Table 4 shows the pin functions that are fixed to specific pins

on each package. These fixed-pin functions are selectable between GPIO and the

comparator inputs, SWD, RESET, and the XTAL pins. By default, the GPIO function is

selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in

boundary scan mode only.

Table 5 shows the the I2C, USART, SPI, and SCT pin functions, which can be assigned

through the switch matrix to any pin that is not power or ground in place of the pin’s fixed

functions.

The following exceptions apply:

For full I2C-bus compatibility, assign the I2C functions to the open-drain pins PIO0_1 1 and

PIO0_10.

Do not assign more than one output to any pin. However, more than one input can be

assigned to a pin. Once any function is assigned to a pin, the pin’s GPIO functionality is

disabled.

Pin PIO0_4 triggers a wake-up from Deep power-down mode. If you need to wake up

from Deep power-down mode via an external pin, do not assign any movable function to

this pin.

The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to

PIO0_4 by hardware when the part is in boundary scan mode.

Table 4. Pin description table (fixed pins)

Symbol

SO20/

TSSOP20

TSSOP16

XSON16

DIP8

Type Reset

state

[1]

Description

PIO0_0/ACMP_I1/

TDO 19 16 16 8 [5] I/O I ; PU PIO0_0 — General purpose digital input/output port 0 pin 0.

In ISP mode, this is the USART0 receive pin U0_RXD.

In boundary scan mode: TDO (Test Data Out).

AI - ACMP_I1 — Anal og comparator input 1.

PIO0_1/ACMP_I2/

CLKIN/TDI 12 9 9 5 [5] I/O I; PU PIO0_1 — General purpose digital input/output pin.

In boundary scan mode: TDI (Test Data In).

ISP entry pin on chip versions 1A and 2A and on the DIP8

package (see Table 6). For these chip versions and

packages, a LOW level on this pin during reset starts the

ISP command handler.

See PIO0_12 for all other packages.

AI - ACMP_I2 — Anal og comparator input 2.

I- CLKIN — External clock input.

Product data sheet Rev. 4.6 — 4 April 2018 9 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

SWDIO/PIO0_2/TMS 7 6 6 4 [2] I/O I; PU SWDIO — Serial Wire Debug I/O. SWDIO is enabled by

default on this pin.

In boundary scan mode: TMS (Test Mode Select).

I/O - PIO0_2 — General purpose digital input/output pin.

SWCLK/PIO0_3/

TCK 6553

[2] I/O I; PU SWCLK — Serial Wire Clock. SWCLK is enabled by default

on this pin.

In boundary scan mode: TCK (Test Clock).

I/O - PIO0_3 — General purpose digital input/output pin.

PIO0_4/WAKEUP/

TRST 5442

[6] I/O I; PU PIO0_4 — General purpose digital input/ou tput pin.

In ISP mode, this is the USART0 transmit pin U0_TXD.

In boundary scan mode: TRST (Test Reset).

This pin triggers a wake-up from Deep power-down mode. If

you need to wake up from Deep power-down mode via an

external pin, do not assign any movable function to this pin.

This pin should be pul led HIGH externally before entering

Deep power-down mode. A LOW-going pulse as short as 50

ns causes the chip to exit Deep power-down mode and

wakes up the part.

RESET/PIO0_5 4 3 3 1 [4] I/O I; PU RESET — External reset input: A LOW-going pulse as short

as 50 ns on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor

execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH

externally. The RESET pin can be left unconnected or be

used as a GPIO or for any movable function if an external

RESET function is not need ed and the Deep power-down

mode is not used.

I- PIO0_5 — General purpose digital input/output pin.

PIO0_6/VDDCMP 18 15 15 - [9] I/O I; PU PIO0_6 — General purpose digital input/output pin.

AI - VDDCMP — Alternate reference voltage for the analog

comparator.

PIO0_7 17 14 14 - [2] I/O I; PU PIO0_7 — General purpose digital input/output pin.

PIO0_8/XTALIN 14 11 11 - [8] I/O I; PU PIO0_8 — General purpose digital input/output pin.

I- XTALIN — Input to the oscillator circuit an d internal clock

generator circuits. Input voltage must not exceed 1.95 V.

PIO0_9/XTALOUT 13 10 10 - [8] I/O I; PU PIO0_9 — General purpose digital input/output pin.

O- XTALOUT — Output from the oscillator circuit.

PIO0_10 9 8 8 - [3] IIAPIO0_10 — General purpose digital input/output pin. Assign

I2C functions to this pin when true open-drain pins are

needed for a signal compliant with the full I2C specification.

PIO0_11 8 7 7 - [3] IIAPIO0_11 — General purpose digital input/output pin. Assign

I2C functions to this pin when true open-drain pins are

needed for a signal compliant with the fu ll I2C specification.

Table 4. Pin description table (fixed pins)

Symbol

SO20/

TSSOP20

TSSOP16

XSON16

DIP8

Type Reset

state

[1]

Description

Product data sheet Rev. 4.6 — 4 April 2018 10 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

[1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD

level); IA = inactive, no pull-up/down enabled.

[2] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes

high-current output driver.

[3] True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode

Plus. Do not use this pad for high-speed applications such as SPI or USART. The pin requires an external pull-up to provide output

functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all

functions on this pin.

Remark: If this pin is not available on the package, prevent it from internally floating as follows: Set bits 10 and 11 in the GPIO DIR0

register to 1 to enable the output driver and write 1 to bits 10 and 11 in the GPIO CLR0 register to drive the outputs LOW internally.

[4] See Figure 11 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the W AKEUP pin to

reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down

mode.

[5] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When

configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. In Deep

power-down mode, pulling this pin LOW wakes up the chip. The wake-up pin function can be disabled and the pin can be used for other

purposes, if the WKT low power oscillator is enabled for waking up the part from Deep power-down mode.

[7] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[8] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system

oscillator. When configured as an analog I/O, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[9] The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with

configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is

disabled.

PIO0_12 3 2 2 - [2] I/O I; PU PIO0_12 — General purpose digital input/output pin. ISP

entry pin on the SO20/TSSOP20/TSSOP16/XSON16

packages starting with chip version 4C (see Table 6). A

LOW level on this pin during reset starts the ISP command

handler.

See pin PIO0_1 for the DIP8 package and chip versions 1A

and 2A.

PIO0_13 2 1 1 - [2] I/O I; PU PIO0_13 — General purpose digital input/output pin.

PIO0_14 20 - - - [7] I/O I; PU PIO0_14 — General purpose digital input/output pin.

PIO0_15 11 - - - [7] I/O I; PU PIO0_15 — General purpose digital input/output pin.

PIO0_16 10 - - - [7] I/O I; PU PIO0_16 — General purpose digital input/output pin.

PIO0_17 1 - - - [7] I/O I; PU PIO0_17 — General purpose digital input/o utput pin.

VDD 15 12 12 6 - - 3.3 V supply voltage.

VSS 16 13 13 7 - - Ground.

Table 4. Pin description table (fixed pins)

Symbol

SO20/

TSSOP20

TSSOP16

XSON16

DIP8

Type Reset

state

[1]

Description

Table 5. Mova ble functions (assign to pins PIO0_0 to PIO_17 through switch matrix)

Function name Type Description

U0_TXD O Transmitter output for USART0.

U0_RXD I Receiver input for USART0.

U0_RTS O Request To Send output for USART0.

U0_CTS I Clear To Send input for USART0.

Product data sheet Rev. 4.6 — 4 April 2018 11 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

U0_SCLK I/O Serial clock input/output for USART0 in synchronous mode.

U1_TXD O Transmitter output for USART1.

U1_RXD I Receiver input for USART1.

U1_RTS O Request To Send output for USART1.

U1_CTS I Clear To Send input for USART1.

U1_SCLK I/O Serial clock input/output for USART1 in synchronous mode.

U2_TXD O Transmitter output for USART2.

U2_RXD I Receiver input for USART2.

U2_RTS O Request To Send output for USART2.

U2_CTS I Clear To Send input for USART2.

U2_SCLK I/O Serial clock input/output for USART2 in synchronous mode.

SPI0_SCK I/O Serial clock for SPI0.

SPI0_MOSI I/O Master Out Slave In for SPI0.

SPI0_MISO I/O Master In Slave Out for SPI0.

SPI0_SSEL I/O Slave select for SPI0.

SPI1_SCK I/O Serial clock for SPI1.

SPI1_MOSI I/O Master Out Slave In for SPI1.

SPI1_MISO I/O Master In Slave Out for SPI1.

SPI1_SSEL I/O Slave select for SPI1.

CTIN_0 I SCT input 0.

CTIN_1 I SCT input 1.

CTIN_2 I SCT input 2.

CTIN_3 I SCT input 3.

CTOUT_0 O SCT output 0.

CTOUT_1 O SCT output 1.

CTOUT_2 O SCT output 2.

CTOUT_3 O SCT output 3.

I2C0_SCL I/O I2C-bus clock input/output (open-drain if assigned to pin PIO0_10).

High-current sink only if assigned to PIO0_10 and if I2C Fast-mode

Plus is selected in the I/O configuration register.

I2C0_SDA I/O I2C-bus data input/output (open-drain if assigned to pin PIO0_11).

High-current sink only if assigned to pin PIO0_11 and if I2C

Fast-mode Plus is selected in the I/O configuration register.

ACMP_O O Analog comparator digital output.

CLKOUT O Clock output.

GPIO_INT_BMAT O Output of the pattern match engine.

Table 5. Mova ble functions (assign to pins PIO0_0 to PIO_17 through switch matrix)

Function name Type Description

Product data sheet Rev. 4.6 — 4 April 2018 12 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Table 6. Pin location in ISP mode

ISP entry pin USART RXD USART TXD Marking Boot loader

version Package

PIO0_1 PIO0_0 PIO0_4 1A v 13.1 TSSOP20; SO20;

TSSOP16; DIP8;

XSON16

PIO0_1 PIO0_0 PIO0_4 2A v 13.2 TSSOP20; SO20;

TSSOP16; DIP8;

XSON16

PIO0_1 PIO0_0 PIO0_4 4C and

later v 13.4 and

later DIP8

PIO0_12 PIO0_0 PIO0_4 4C and

later v 13.4 and

later TSSOP20; SO20;

TSSOP16;

XSON16

Product data sheet Rev. 4.6 — 4 April 2018 13 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

8. Functional description

8.1 ARM Cortex-M0+ core

The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a

two-stage pipeline. Integrated in the core are the NVIC and Serial Wire Debug with four

breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O

enabled port for fast GPIO access.

The core includes a single-cycle multiplier and a system tick timer.

8.2 On-chip flash program memory

The LPC81xM contain up to 16 kB of on-chip flash program memory. The flash memory

supports a 64 Byte page size with page write and erase.

8.3 On-chip SRAM

The LPC81xM contain a total of up to 4 kB on-chip static RAM data memory.

8.4 On-chip ROM

The 8 kB on-chip ROM contains the boot loader and the following Application

Programming Interfaces (API):

•In-System Programming (ISP) and In-Application Programming (IAP) support for flash

programming

•Power profiles for configuring power consumption and PLL settings

•USART driver API routines

•I2C-bus driver API routines

8.5 Nested Vectored Interrupt Controller (NVIC)

The Nested V ecto red Interrupt Controller (NVIC) is an integral p art of the Cortex-M0+. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

8.5.1 Features

•Controls system exceptions and peripheral interrupts.

•On the LPC81xM, the NVIC support s 32 vecto red interrupt s including up to 8 e xternal

interrupt inputs selectable from all GPIO pins.

•Four programmable interrupt priority levels with hardware priority level masking.

•Software interrupt generation using the ARM exceptions SVCall and PendSV.

•Relocatable interrupt vector table using vector table offset register.

8.5.2 Interrupt sources

Each peripheral devi ce has one interrupt line conne cted to the NVIC but may have several

interrupt flags. Individual interrup t flags may also represent more than one interrupt

source.

Product data sheet Rev. 4.6 — 4 April 2018 14 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Up to eight pins, regardless of the selected function, can be programmed to gene rate an

interrupt on a level, a rising or falling edge, or both. The interrupt generating pins can be

selected from all digi tal or mixed digital/analog pins. The pin interrupt/pattern match block

controls the edge or level detection mechanism.

8.6 System tick timer

The ARM Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to

generate a dedicated SysTick exception at a fixed time interval (typically 10 ms).

8.7 Memory map

The LPC81xM incorporates several distinct memory regions. Figure 7 shows the overall

map of the entire address space from the user program viewpoint following reset. The

interrupt vector area supports address remapping.

The ARM private peripheral bus includes the ARM core registers for controlling the NVIC,

the system tick timer (SysTick), and the reduced power modes.

Product data sheet Rev. 4.6 — 4 April 2018 15 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

8.8 I/O configuration

The IOCON block controls the configuration of the I/O pins. Each digital or mixed

digital/analog pin with the PIO0_n designator (except the true open-drain pins PIO0_10

and PIO0_11) in Table 4 can be configured as follows:

•Enable or disable the weak internal pull-up and pull-down resistors.

•Select a ps eudo open-drain mode. The input cann ot be pulled up above VDD. This pin

is not 5 V tolerant when VDD = 0.

Fig 7. LPC81xM Memory map

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Product data sheet Rev. 4.6 — 4 April 2018 16 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

•Program the input glitch filter with different filter constants using one of the IOCON

divided clock signals (IOCONCLKCDIV, see Figure 10 “LPC81xM clock generation”).

You can also bypass the glitch filter.

•Invert the input signal.

•Hysteresis can be enabled or disabled.

•For pins PIO0_10 and PIO0_11, select the I2C-mode and output driver for standard

digital operation, for I2C standard and fast modes, or for I2C Fast mode+.

•On mixed digital/analog pins, enable the analog input mode. Enabling the analog

mode disconnects the digital functionality.

Remark: The functionality of each I/O pin is flexible and is determined entirely through the

switch matrix. See Section 8.9 for details.

8.8.1 Standard I/O pad configuration

Figure 8 shows the possible pin modes for standard I/O pins with analog input function:

•Digital output driver with configurable open-drain output

•Digital input: Weak pull-up resistor (PMOS device) enabled/disabled

•Digital input: Weak pull-down resistor (NMOS device) enabled/disabled

•Digital input: Repeater mode enabled/disabled

•Digital input: Input glitch filter selectable on all pins

•Analog input

Product data sheet Rev. 4.6 — 4 April 2018 17 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

8.9 Switch Matrix (SWM)

The switch matrix controls the function of each digital or mixed analog/digital pin in a

highly flexible way by allowing to connect many functions like the USART, SPI, SCT, and

I2C functions to any pin that is not power or ground. These functions are called movable

functions and are listed in Table 5.

Functions that need specialized pads like the oscillator pins XTALIN and XTALOUT can

be enabled or disabled through the switch matrix. These functions are called fixed-pin

functions and cannot move to other pins. The fixed-pin functions are listed in Table 4. If a

fixed-pin function is disabled, any other movable function can be assigned to this pin.

8.10 Fast General-Purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamica lly configured as input s or outputs. Multip le outputs

can be set or cleared in on e wr ite op e ra tio n.

LPC81xM use accelerated GPIO functions:

•GPIO registers are located on the ARM Cortex M0+ IO bus for fastest possible

single-cycle I/O timing, allowing GPIO toggling with rates of up to 15 MHz.

Fig 8. Standard I/O pa d co nfi guration

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Product data sheet Rev. 4.6 — 4 April 2018 18 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

•An entire port value can be written in one instruction.

•Mask, set, and clear operations are supported for the entire port.

All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the

switch matrix. Therefore e ach GPIO port pin is assigned to one specific pin and canno t be

moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and

RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default.

8.10.1 Features

•Bit level port registers allow a single instruction to set and clear any number of bits in

one write operation.

•Direction control of individual bits.

•All I/O default to inputs with internal pull-up resistors enabled after reset - except for

the I2C-bus true open-drain pins PIO0_2 and PIO0_3.

•Pull-up/pull-do wn configuration, re peater, and open-drain modes can be programmed

through the IOCON block for each GPIO pin (see Figure 8).

•

8.11 Pin interrupt/pattern match engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight

external interrupts connected to the NVIC.

The pattern match engine can be used, in conjunction with software, to create complex

state machines based on pin inputs.

Any digital pin, independently of the function selected through the switch matrix, can be

configured through the SYSCON block as input to the pin interrupt or pattern match

engine. The registers that control the pin interrupt or pattern match engine are located on

the IO+ bus for fast single-cycle access.

8.11.1 Features

•Pin interrupts

–Up to eight pins can be selected from all digital pins as edge- or level-sensitive

interrupt requests. Each request creates a separate interrupt in the NVIC.

–Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

–Level-sensitive interrupt pins can be HIGH- or LOW-active.

–Pin interrupt s can wa ke up the LPC81xM from sleep mode, deep- sleep mode, a nd

power-down mode.

•Pin interrupt pattern match engine

–Up to eight pins can be selected from all digital pins to contribute to a boolean

expression. The boolean expression consists of specified levels and/or transitions

on various combinations of these pins.

–Each minterm (product term) comprising the specified boolean expression can

generate its own, dedicated interrupt request.

–Any occurrence of a pattern match can be programmed to also generate an RXEV

notification to the ARM CPU. The RXEV signal can be connected to a pin.

Product data sheet Rev. 4.6 — 4 April 2018 19 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

–The pattern match engine does not facilitate wake-up.

8.12 USART0/1/2

Remark: USART0 and USART1 are available on all LPC800 parts. USART2 is available

on parts LPC812M101JTB16, LPC812M101JDH16, and LPC812M101JDH20 only.

All USART function s are movable functions and are assigned to pins through the switch

matrix.

8.12.1 Features

•Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in

synchronous mode for USART functions connected to all digit al pi ns except PIO0_ 10

and PIO0_11.

•7, 8, or 9 data bits and 1 or 2 stop bits

•Synchronous mode with master or slave operation. Includes dat a phase selection and

continuous clock option.

•Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485

possible with soft ware address detection and transceiver direction control.)

•Parity generation and checkin g: odd, even, or none.

•One transmit and one receive data buffer.

•RTS/CT S for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

•Received data and status can optionally be read from a single register

•Break generation and detection.

•Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

•Built-in Baud Rate Generator.

•A fractional rate divider is shar ed among all UARTs.

•Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

•Separate data and flow control loopback modes for testing.

•Supported by on- ch ip ROM A PI.

8.13 SPI0/1

Remark: SPI0 is available on all LPC800 parts. SPI1 is available on parts

LPC812M101JDH16 and LPC812M101JDH20 only.

All SPI functions are movable functions and are assigned to pins through the switch

matrix.

8.13.1 Features

•Maximum dat a rates o f 30 Mb it/s in maste r mod e and 25 Mb it/s in slave mode fo r SPI

functions connected to all digital pins except PIO0_10 and PIO0_11.

Product data sheet Rev. 4.6 — 4 April 2018 20 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

•Data frames of 1 to 16 bits supported directly. Larger frames supported by software.

•Master and slave operation.

•Data can be transmitte d to a slave without the need to read incomi ng data. This can

be useful while setting up an SPI memory.

•Control information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

•One Slave Select input/output with select able polarity and flexible usage.

Remark: Texas Instruments SSI and National Microwir e modes are not supported.

8.14 I2C-bus interface

The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a r eceiver-only de vice ( e.g., an LCD driver) or a tra nsmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can oper ate in eithe r master or sl ave mo de, dependin g on whe ther th e chip ha s

to initiate a data transfer or is only addressed. The I2C is a mu lti-m a ste r bu s and ca n be

controlled by more than one bus master connected to it.

The I2C-bus functions are movable functions and can be assigned through the switch

matrix to any pin. However, only the true open-drain PIO0_10 and PIO0_11 provide the

electrical characteristics to support the full I2C-bus specification (see Ref. 1).

8.14.1 Features

•Supports standard and fast mode with data rates of up to 400 kbit/s.

•Independent Master, Slave, and Monitor functions.

•Supports both Multi-mas te r and Mu lti- m ast er with Slav e fu nct ion s.

•Multiple I2C slave addresses supported in hardware.

•One slave address ca n be selectively qualified with a b it mask or an ad dress range in

order to respon d to multiple I2C bus addresses.

•10-bit addressing supported with software assist.

•Supports SMBus.

•Supported by on- ch ip ROM A PI.

•If the I2C functions are connected to the true open- drain pins (PIO0_10 and

PIO0_11), the I2C supports the full I2C-bus specification:

–Fail-safe opera tio n: When th e p ower to an I2C-bus d evice is switch ed o ff, the SDA

and SCL pins connected to the I2C-bus are floating and do not disturb the bus.

–Supports Fast-mode Plus with bit rates up to 1 Mbit/s.

8.15 State-Configurable Timer/PWM (SCTimer/PWM)

The state configurable timer (SCTimer/PWM or SCT) can perform basic 16-bit and 32-bit

timer/counter functions with match outputs and external and internal capture inputs. In

addition, the SCTimer/PWM can employ up to two different programmable states, which

can change under the control of events , to provide complex timing patterns.

Product data sheet Rev. 4.6 — 4 April 2018 21 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

All inputs and outputs of the SCTimer/PWM are movable functions and are assigned to

pins through the switch matrix.

8.15.1 Features

•Tw o 16-bit counters or one 32-bit counter.

•Counters clocked by bus clock or selected input.

•Up counters or up-down counters.

•State variable allows sequencing across multiple counter cycles.

•The following conditions define an event: a counter match cond ition, an input (or

output) condition, a combination of a match and/or and input/output condition in a

specified state, and the count direction.

•Events control outputs, interrupts, and the SCT states.

–Match register 0 can be used as an automatic limit.

–In bi-directional mode, events can be enabled based on the count direction.

–Match events can be held until an ot he r qu a lifyin g ev en t occurs.

•Selected events can limit, halt, start, or stop a counter.

•Supports:

–4 inputs

–4 outputs

–5 match/capture registers

–6 events

–2 states

8.16 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each

channel can be programmed with an independent time interval, and each channel

operates independently from the other channels.

8.16.1 Features

•31-bit interrupt timer

•Four channels independen tly counting down from individually set values

•Bus stall, repeat and one-shot interrupt modes

8.17 Windowed WatchDog Timer (WWDT)

The watchdog timer r esets the controller if software fails to periodically service it within a

programmable time window.

8.17.1 Features

•Internally resets chip if not periodically reloaded during the programmable time-out

period.

•Optional windowed operation re quires reload to occur between a minimum and

maximum time period, both programmable.

Product data sheet Rev. 4.6 — 4 April 2018 22 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

•Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

•Enabled by soft ware but requires a hardwar e reset or a watchdog reset/interrupt to be

disabled.

•Incorrect feed sequence causes reset or interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 24-bit tim er with internal prescaler.

•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in

multiples of Tcy(WDCLK) 4.

•The Watchdog Clock (WDCLK)is generated by a the dedicated watchdog oscillator

(WDOSC).

8.18 Self Wake-up Timer (WKT)

The self wake-up tim er is a 32-bit, loa d ab le do wn -c ou nt er. Writing any non-zero value to

this timer automatically enab les the counter a nd launches a count-down sequence. When

the counter is used as a wake -u p tim er, this write can occur just prior to en ter in g a

reduced power mode.

8.18.1 Features

•32-bit loadable down-counter. Counter starts automatically when a count value is

loaded. Time-out generates an interrupt/wake up request.

•The WKT resides in a separate, always-on power domain.

•The WKT supports two clock sources: the low-power oscillator and the IRC. The

low-power oscillator is located in the always-on power domain, so it can be used as

the clock source in Deep power-down mode.

•The WKT can be used for waking up the part from any reduced power mode,

including Deep power-down mode, or for general-purpose timing.

8.19 Analog comparator (ACMP)

The analog comp arator with select able hysteresis can compa re volt age levels o n external

pins and internal voltages.

After po wer- up and after switching the input channels of the comparator, the output of the

voltage ladder must be allowed to settle to its stable value before it can be used as a

comparator reference input. Settling times are given in Table 23.

The analog comparator output is a movable function and is assigned to a pin through the

switch matrix. The comparator inputs and the voltage reference are enabled or disable d

on pins PIO0_0 and PIO0_1 through the switch matrix.

Product data sheet Rev. 4.6 — 4 April 2018 23 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

8.19.1 Features

•Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input

hysteresis.

•Two selectable e xtern al volt ages ( VDD or VDDCMP on pin PIO0_6); fully configurable

on either positive or negative input channel.

•Internal voltage reference from band gap selectable on either positive or negative

input channel.

•32-stage voltage ladder with the internal reference voltage selectable on either the

positive or the negative input channel.

•Voltage ladder source voltage is selectable from an external pin or the main 3.3 V

supply voltage rail.

•Voltage ladder can be separately powered down for applications only requ irin g the

comparator function.

•Interrupt output is connected to NVIC.

•Comparator level output is connected to output pin ACMP_O.

•The comparator output can be routed internally to the SCT input through the switch

matrix.

Fig 9. Compara t or blo c k dia g ra m

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Product data sheet Rev. 4.6 — 4 April 2018 24 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

8.20 Clocking and power control

8.20.1 Crystal and internal oscillators

The LPC81xM include four independent oscillators:

1. The crystal oscillator (SysOsc) operating at frequencies between 1 MHz and 25 MHz.

2. The internal RC Oscillator (IRC) with a fixed frequency of 12 MHz, trimmed to 1%

accuracy.

3. The internal low-power, low-frequency Oscillator with a nominal frequency of 10 kHz

with 40% accuracy for use with the self wake-up timer.

4. The dedicated Watchdog Oscillator (WDOsc) with a programmable nominal

frequency betwe e n 9. 4 kH z an d 2.3 MH z wi th 40 % acc ur ac y.

Fig 10. LPC81xM clock generation

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Product data sheet Rev. 4.6 — 4 April 2018 25 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Each oscillator, except the low-frequency oscillator, can be used for more than one

purpose as required in a particular application.

Following reset, the LPC81xM will operate from the IRC until switched by software. This

allows systems to operate without an y external crystal and the bootloader code to ope rate

at a known frequency.

See Figure 10 for an overview of th e LPC81xM clock generation.

8.20.1.1 Internal RC Oscillator (IRC)

The IRC may be used as the clock source for the WWDT, and/or as the clock that drives

the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1.5 % accuracy over the entire voltage and temperature range.

The IRC can be used as a clock source for the CPU with or without using the PLL. The

IRC frequency can be boosted to a higher frequency, up to the maximum CPU operating

frequency, by the system PLL .

Upon power-up or any chip reset, the LPC81xM use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

8.20.1.2 Crystal Oscillator (SysOsc)

The crystal oscillator can be used as the clock source for the CPU, with or without using

the PLL.

The SysOsc operates at freque ncies of 1 MHz to 25 MHz. This frequency can be b oosted

to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.

8.20.1.3 Internal Low-power Oscillator and Watchdog Oscillator (WDOsc)

The nominal frequency of the WDOsc is programmable between 9.4 kHz and 2.3 MHz.

The frequency spread over silicon process variations is 40%.

The WDOsc is a dedicated oscillator for the windowed WWDT.

The internal low-power 10 kHz ( 40% accuracy) oscillator serves a the clock input to the

WKT. This oscillator can be configured to run in all low power modes.

8.20.2 Clock input

An external clock source can be supplied on the selected CLKIN pin. When selecting a

clock signal for the CLKIN pin, follow the specifications for digit al I/O pins in Table 9 “Static

characteristics” and Tab l e 16 “Dynamic characteristics: I/O pins[1]”.

An 1.8 V external clock source can be supplied on the XTALIN pins to the system

oscillator limiting the voltage of this signal ((see Section 14.2).

The maximum frequency for both clock signals is 25 MHz.

8.20.3 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

Product data sheet Rev. 4.6 — 4 April 2018 26 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

divider may be set to divide by 2, 4, 8, or 16 to produce th e ou tp ut clock. Since the

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

The PLL is turned off and bypassed following a chip reset and may be enabled by

software. The program must configure and activate the PLL, wait for the PLL to lock, and

then connect to the PLL as a clock source. The PLL settling time is nominally 100 s.

8.20.4 Clock output

The LPC81xM features a clock output function that routes the IRC, the SysOsc, the

watchdog oscillator , or the main clock to the CLKOUT function. The CLKOUT function can

be connected to any digital pin through the switch matrix.

8.20.5 Wake-up process

The LPC81xM begin operation at power-up by using the IRC as the clock source. This

allows chip operation to resume quickly. If the SysOsc, the external clock source, or the

PLL is needed by the application, software must enable these features and wait for them

to stabilize before they are used as a clock source.

8.20.6 Power control

The LPC81xM supports the ARM Cortex-M0 Sleep mode. The CPU clock rate may also

be controlled as needed by changing clock sources, reconfiguring PLL values, and/or

altering the CPU clock divider value. This allows a trade-off of power versus processing

speed based on application re quirements. In addition, a register is provided for shutting

down the clocks to individual on-chip peripherals, allowing to fine-tune power

consumption by eliminating all dynamic power use in any pe ripherals that are not required

for the application. Selecte d periphe rals have their own clock divider which provides even

better power control.

8.20.6.1 Power profiles

The power consumption in Active and Sleep modes can be optimized for the app lication

through simple calls to the power profile API. The API is accessible through the o n-chip

ROM.

The power configuratio n routine configures the LPC81xM for one of the following power

modes:

•Default mode corresponding to power configuration after reset.

•CPU performance mode corresponding to optimized processing capability.

•Efficie ncy mode corresponding to optimize d balance of current consumption and CPU

performance.

•Low-current mode corresponding to lowest power consumption.

In addition, the power profile include s routines to select the optimal PLL settings for a

given system clock and PLL input clo ck.

8.20.6.2 Sleep mode

When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep

mode does not need an y special sequence but re-enabling the clock to the ARM core.

Product data sheet Rev. 4.6 — 4 April 2018 27 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution . Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

8.20.6.3 Deep-sleep mode

In Deep-sleep mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all

clock sources are off except for the IRC and watchdog oscillator or low-power oscillator if

selected. The IRC output is disabled. In addition all analog blocks are shut down and the

flash is in stand-by mod e. In Deep-sleep mode, the application can keep the watchdog

oscillator and the BOD circuit running for self-timed wake-up and BOD protection.

The LPC81xM can wake up from Deep-sleep mode via a reset, digital pins selected as

inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C

blocks (in slave m od e).

Any interrupt used for waking up from Deep-sleep mod e must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

Deep-sleep mode saves power and allows for short wake-up times.

8.20.6.4 Power-down mode

In Power-down mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all

clock sources are off except for watchdog oscillator or low-power oscillator if selected. In

addition all analog blocks and the flash are shut down. In Power-down mode, the

application can keep the watchdog oscillator and the BOD circuit running for self-timed

wake-up and BOD protection.

The LPC81xM can wake up from Power-down mode via a reset, digital pins selected as

inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C

blocks (in slave m od e).

Any interrupt used for waking up from Power-down mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

Power-down mode reduces power consump tion compared to Deep-sleep mode at the

expense of longer wa ke-up times.

8.20.6.5 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP

pin and the self wake-up timer if enabled. Four general-purpose registers are available to

store information du ring Dee p power- down mode. T he LPC81 xM can wake up from Dee p

power-down mode via the WAKEUP pin, or without an external signal by using the

time-out of the self wake-up timer (see Section 8.18).

The LPC81xM can be prevented from entering Deep power-down mode by setting a lock

bit in the PMU b lock. Locking out Deep powe r-down mode enables the applica tion to keep

the watchdog timer or the BOD running at all times.

Product data sheet Rev. 4.6 — 4 April 2018 28 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

When entering Deep power-do wn mode, an external pull-up resistor is required on the

W AKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in

Deep power-down mode.

8.21 System control

8.21.1 Reset

Reset has four sources on the LPC81xM: the RESET pin, the Wat chd o g re se t, po we r- on

reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip re set by a ny source, on ce the opera tin g voltage attains

a usable level, starts the IRC and initializes the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, th e processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

In Deep power-down mode, an external pull-up resistor is required on the RESET pin.

8.21.2 Brownout detection

The LPC81xM includes up to four levels for monitoring the voltage on the VDD pin. If this

voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled fo r interrupt in the In terrupt Enable Register in the NVIC

to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a

dedicated statu s register. Four threshold levels can be selected to cause a forced reset of

the chip.

Fig 11. Reset pad configuration

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Product data sheet Rev. 4.6 — 4 April 2018 29 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

8.21.3 Code security (Code Read Protection - CRP)

CRP provides different levels of security in the system so that access to the on-chip flash

and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be

restricted. Programming a specific pattern into a dedicated flash location invokes CRP.

IAP commands are not affected by the CRP.

In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP. For

details, see the LPC800 user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is requ ired and flash field upda tes are needed b ut all sectors cannot

be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected, fully disables any access to the chip

via the SWD pins and the ISP. This mode effectively disables ISP override using the

ISP entry pin as well. If necessary, the application must provide a flash update

mechanism using IAP calls or using a call to the reinvoke ISP command to enable

flash update via the USART.

In addition to the three CRP levels, sampling of the ISP entry pin for valid user code can

be disabled. For deta ils, see the LPC800 user manual.

8.21.4 APB interface

The APB peripherals are located on one APB bus.

8.21.5 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0+ to the flash memory, the

main static RAM, the CRC, and the ROM.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 4.6 — 4 April 2018 30 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

8.22 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0+. Seria l wire debug functions are

supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is

configured to support up to four breakpoints and two watch points.

The Micro Trace Buffer is implemented on the LPC81xM.

The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM

SWD debug (RESET = HIGH). The ARM SWD debug port is disa bled while the LPC81xM

is in reset. The JTAG boundary scan pins are selected by hard ware when the part is in

boundary scan mode on pins PIO0_0 to PIO0_3 (see Table 4).

To perform boundary scan testing, follow these steps:

1. Erase any user code residin g in flash.

2. Power up the part with the RESET pin pulled HIGH externally.

3. Wait for at least 250 s.

4. Pull the RESET pin LOW externally.

5. Perform boundary scan operations.

6. Once the boundary scan ope rations are completed, assert the TRST pin to enable the

SWD debug mode, and release the RESET pin (pull HIGH).

Remark: The JTAG interface cannot be used for debug purposes.

Fig 12. Connecting the SWD pins to a standard SWD connector

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Product data sheet Rev. 4.6 — 4 April 2018 31 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

9. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

c) The limiting values are stress ratings only. Operating the part at these values is not recommended and proper operation is not

guaranteed. The conditions for functional operation are specified in Table 9.

[2] Maximum/minimum voltage above the maximum operating voltage (see Table 9) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] Including voltage on outputs in tri-state mode. Does not apply to pin PIO0_6.

[4] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.

[5] VDD present or not present.

[6] If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below

VDD without affecting the hysteresis range of the comparator function.

[7] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[8] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined

based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.

[9] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

Table 7. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD supply voltage (core and external rail) [2] 0.5 +4.6 V

VIinput voltage 5 V tolerant I/O pins; VDD  1.8 V [3] 0.5 +5.5 V

5 V tolerant open-drain pins PIO0_10

and PIO0_11 [4] 0.5 +5.5 V

3 V tolerant I/O pin PIO0_6 [5] 0.5 +3.6 V

VIA analog input voltage [6]

[7] 0.5 4.6 V

Vi(xtal) crystal input voltage [2] 0.5 +2.5 V

IDD supply current per supply pi n - 100 mA

ISS ground current per ground pin - 100 mA

Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD);

Tj < 125 C-100mA

Tstg storage temperature non-operating [8] 65 +150 C

Tj(max) maximum junction temperature - 150 C

Ptot(pack) total power dissipation (per package) based on package heat transfer , not

device power consumption -1.5W

VESD electrostatic discharge voltage human body model; all pins [9] - 5500 V

charged device model; TSSOP20 and

SOP20 packages - 1200 V

charged device model; TSSOP16

package - 1000 V

charged device model; XSON16

package -800V

Product data sheet Rev. 4.6 — 4 April 2018 32 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

10. Thermal characteristics

The average chip junction temperature, Tj (C), can be calculated using the following

equation:

(1)

•Tamb = ambient temperature (C),

•Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)

•PD = sum of internal and I/O power dissipation

The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of

the I/O pins is of ten small and ma ny times can b e negligible. However it can be significant

in some applications.

Table 8. Thermal resistance

Symbol Parameter Conditions Max/Min Unit

DIP8

Rth(j-a) thermal resistance from

junction to ambient JEDEC (4.5 in  4 in); still air 60 ± 15 % C/W

Single-layer (4.5 in  3 in); still air 81 ± 15 % C/W

Rth(j-c) thermal resistance from

junction to case 38 ± 15 % C/W

TSSOP16

Rth(j-a) thermal resistance from

junction to ambient JEDEC (4.5 in  4 in); still air 133 ± 15 % C/W

Single-layer (4.5 in  3 in); still air 182 ± 15 % C/W

Rth(j-c) thermal resistance from

junction to case 33 ± 15 % C/W

TSSOP20

Rth(j-a) thermal resistance from

junction to ambient JEDEC (4.5 in  4 in); still air 110 ± 15 % C/W

Single-layer (4.5 in  3 in); still air 153 ± 15 % C/W

Rth(j-c) thermal resistance from

junction to case 23 ± 15 % C/W

SO20

Rth(j-a) thermal resistance from

junction to ambient JEDEC (4.5 in  4 in); still air 87 ± 15 % C/W

Single-layer (4.5 in  3 in); still air 112 ± 15 % C/W

Rth(j-c) thermal resistance from

junction to case 50 ± 15 % C/W

XSON16

Rth(j-a) thermal resistance from

junction to ambient JEDEC (4.5 in  4 in); still air 92 ± 15 % C/W

Single-layer (4.5 in  3 in); still air 180 ± 15 % C/W

Rth(j-c) thermal resistance from

junction to case 27 ± 15 % C/W

TjTamb PDRth j a–

+=

Product data sheet Rev. 4.6 — 4 April 2018 33 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

11. Static characteristics

Table 9. Static characteristics

Tamb =





C to +105



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD supply voltage (core

and external rail) 1.8 3.3 3.6 V

IDD supply current Active mode; code

while(1){}

executed from flash;

system clock = 12 MHz; default

mode; VDD = 3.3 V [2][3][4][5] -1.4-mA

system clock = 12 MHz;

low-current mode; VDD = 3.3 V [2][3][4][5]

[6] -1.0-mA

system clock = 24 MHz;

low-current mode; VDD = 3.3 V [2][4][5][6]

[7] -2.2-mA

system clock = 30 MHz; default

mode; VDD = 3.3 V [2][4][5][8] -3.3-mA

system clock = 30 MHz;

low-current mode; VDD = 3.3 V [2][4][5][6]

[8] -3 -mA

Sleep mode

system clock = 12 MHz; default

mode; VDD = 3.3 V [2][3][4][5] -0.8-mA

system clock = 12 MHz;

low-current mode; VDD = 3.3 V [2][3][4][5]

[6] -0.7-mA

system clock = 24 MHz;

low-current mode; VDD = 3.3 V [2][4][5][6]

[7] -1.3-mA

system clock = 30 MHz; default

mode; VDD = 3.3 V [2][4][5][8] -1.8-mA

system clock = 30 MHz;

low-current mode; VDD = 3.3 V [2][4][5][6]

[8] -1.7-mA

Deep-sleep mode

VDD = 3.3 V, Tamb = 25 °C [2][9] - 150 300 A

VDD = 3.3 V, Tamb = 105 °C [2][9] - - 400 A

Power-down mode

VDD = 3.3 V, Tamb = 25 °C [2][9] -0.95A

VDD = 3.3 V, Tamb = 105 °C [2][9] -- 40A

Deep power-down mode;

Low-power oscillator and self

wakeup timer (WKT) disabled

VDD = 3.3 V, Tamb = 25 °C [10] - 170 1000 nA

VDD = 3.3 V, Tamb = 105 °C [10] -- 4A

Deep power-down mode;

Low-power oscillator and self

wakeup timer (WKT) enabled

-1 -A

Product data sheet Rev. 4.6 — 4 April 2018 34 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Standard port pins configured as digital pins, RESET; see Figure 13

IIL LOW-level input current VI= 0 V; on-chip pull-up resistor

disabled - 0.5 10 nA

IIH HIGH-level input

current VI=V

DD; on-chip pull-down

resistor disabled - 0.5 10 nA

IOZ OFF-state output

current VO=0V; V

O=V

DD; on-chip

pull-up/down resistors disabled - 0.5 10 nA

VIinput voltage VDD  1.8 V; 5 V tolerant pins

except PIO0_6 [11]

[12] 0- 5.0V

VDD  1.8 V; on 3 V tolerant pin

PIO0_6 0- 3.6

VDD = 0 V 0 - 3.6 V

VOoutput voltage output active 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage - 0.4 - V

VOH HIGH-level output

voltage 2.5 V  VDD  3.6 V; IOH =4 mA V

DD  0.4 - - V

1.8 V  VDD < 2.5 V; IOH =3 mA V

DD  0.4 - - V

VOL LOW-level output

voltage 2.5 V  VDD  3.6 V; IOL =4 mA - - 0.4 V

1.8 V  VDD < 2.5 V; IOL =3 mA - - 0.4 V

IOH HIGH-level output

current VOH =V

DD 0.4 V;

2.5 V  VDD  3.6 V 4- -mA

1.8 V  VDD < 2.5 V 3 - - mA

IOL LOW-level output

current VOL =0.4V

2.5 V  VDD  3.6 V 4- -mA

1.8 V  VDD < 2.5 V 3 - - mA

IOHS HIGH-level short-circuit

output current VOH =0V [13] -- 45mA

IOLS LOW-level short-circuit

output current VOL =V

DD [13] -- 50mA

Ipd pull-down current VI= 5 V 10 50 150 A

Ipu pull-up current VI=0V;

2.0 V  VDD  3.6 V 15 50 85 A

1.8 V  VDD < 2.0 V 10 50 85 A

VDD <V

I<5V 0 0 0 A

High-drive output pins configured as digital pins (PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13); see Figure 13

IIL LOW-level input current VI= 0 V; on-chip pull-up resistor

disabled - 0.5 10 nA

IIH HIGH-level input

current VI=V

DD; on-chip pull-down

resistor disabled - 0.5 10 nA

IOZ OFF-state output

current VO=0V; V

O=V

DD; on-chip

pull-up/down resistors disabled - 0.5 10 nA

Table 9. Static characteristics …continued

Tamb =





C to +105



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 4.6 — 4 April 2018 35 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

VIinput voltage VDD  1.8 V [11]

[12] 0- 5.0V

VDD = 0 V 0 - 3.6 V

VOoutput voltage output active 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage 0.4 - - V

VOH HIGH-level output

voltage 2.5 V  VDD  3.6 V; IOH =20 mA V

DD  0.4 - - V

1.8 V  VDD < 2.5 V; IOH =12 mA V

DD  0.4 - - V

VOL LOW-level output

voltage 2.5 V  VDD  3.6 V; IOL =4 mA - - 0.4 V

1.8 V  VDD < 2.5 V; IOL =3 mA - - 0.4 V

IOH HIGH-level output

current VOH =V

DD 0.4 V;

2.5 V  VDD  3.6 V 20 - - mA

1.8 V  VDD < 2.5 V 12 - - mA

IOL LOW-level output

current VOL =0.4V

2.5 V  VDD  3.6 V 4- -mA

1.8 V  VDD < 2.5 V 3 - - mA

IOLS LOW-level short-circuit

output current VOL =V

DD [13] -- 50mA

Ipd pull-down current VI=5V [14] 10 50 150 A

Ipu pull-up current VI=0V

2.0 V  VDD  3.6 V

[14] 15 50 85 A

1.8 V  VDD < 2.0 V 10 50 85 A

VDD <V

I<5V 0 0 0 A

I2C-bus pins (PIO0_10 and PIO0_11); see Figure 13

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage - 0.05VDD -V

IOL LOW-level output

current VOL = 0.4 V; I2C-bus pins

configured as standard mode pins

2.5 V  VDD  3.6 V

3.5 - - mA

1.8 V  VDD < 2.5 V 3 - -

IOL LOW-level output

current VOL = 0.4 V; I2C-bus pins

configured as Fast-mode Plus

pins

2.5 V  VDD  3.6 V

20 - - mA

1.8 V  VDD < 2.5 V 16 - -

ILI input leakage current VI=V

DD [15] -2 4A

VI= 5 V - 10 22 A

Table 9. Static characteristics …continued

Tamb =





C to +105



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 4.6 — 4 April 2018 36 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.

[2] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[3] IRC enabled; system oscillator disabled; system PLL disabled.

[4] BOD disabled.

[5] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to USART, CLKOUT, and IOCON disabled in system

configuration block.

[6] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[7] IRC enabled; system oscillator disabled; system PLL enabled.

[8] IRC disabled; system oscillator enabled; system PLL enabled.

[9] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.

[10] WAKEUP pin pulled HIGH externally.

[11] Including voltage on outputs in tri-state mode.

[12] 3-state outputs go into tri-state mode in Deep power-down mode.

[13] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[14] Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 8.

[15] To VSS.

Oscillator input pins (PIO0_8 and PIO0_9)

Vi(xtal) crystal input voltage 0.5 1.8 1.95 V

Vo(xtal) crystal ou tp u t v oltage 0.5 1.8 1.95 V

Table 9. Static characteristics …continued

Tamb =





C to +105



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Fig 13. Pin input/output curre nt measurement

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Product data sheet Rev. 4.6 — 4 April 2018 37 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

11.1 Power consumption

Power measurements in Active, Sleep, Deep-sleep,and Power-down modes were

performed under the following conditions:

•Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.

•Configure GPIO pins as outputs using the GPIO DIR register.

•Write 1 to the GPIO CLR register to drive the outputs LOW.

Conditions: Tamb = 25 C; active mode entered executing code

while(1){}

from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL =0x1F); all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz - 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz: IRC enabled; PLL enabled.

30 MHz: IRC disabled; SYSOSC enabled; PLL enabled.

Fig 14. Active mo de: Typical supply curr ent IDD versus supply voltage VDD

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Product data sheet Rev. 4.6 — 4 April 2018 38 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Conditions: VDD = 3.3 V; active mode entered executing code

while(1){}

from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz - 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz: IRC enabled; PLL enabled.

30 MHz: IRC disabled; SYSOSC enabled; PLL enabled.

Fig 15. Active mo de: Typical supply curr ent IDD versus temperatur e

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Product data sheet Rev. 4.6 — 4 April 2018 39 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Conditions: VDD = 3.3 V; sleep mode entered from fl ash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz - 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz: IRC enabled; PLL enabled.

30 MHz: IRC disabled; SYSOSC enabled; PLL enabled.

Fig 16. Sleep mode: Typical supply current IDD versus temperature for different sys tem

clock frequencies

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF).

Fig 17. Deep-sleep mode: Typi cal supply cu rrent IDD versus temperature for different

supply vo ltages VDD

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Product data sheet Rev. 4.6 — 4 April 2018 40 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF).

Fig 18. Power-down mode: Typi cal supply curr ent IDD versus temperature for different

supply vo ltages VDD

WKT not running.

Fig 19. Deep power-down mode: Typical supply current IDD versus temperature for

different supply voltages VDD

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Product data sheet Rev. 4.6 — 4 April 2018 41 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

11.2 CoreMark data

Conditions: VDD = 3.3 V; T amb = 25 C; active mode; all peripherals except one UART and the SCT

disabled in the SYSAHBCLKCTRL register; system clock derived from the IRC; system oscillator

disabled; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision v.4.7.

Fig 20. Active mode: CoreMark power consumption IDD

Conditions: VDD = 3.3 V; active mode; all peripherals except one UART and the SCT disabled in

the SYSAHBCLKCTRL register; internal pull-up resistors enabled; BOD disabled. Measured with

Keil uVision v.4.7.

Fig 21. CoreMark score

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Product data sheet Rev. 4.6 — 4 April 2018 42 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

11.3 Peripheral power consumption

The supply current p er peripheral is measured as the differ ence in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code is executed. Mea sured on a typical sample at Tamb =25 C. Unless

noted otherwise, the system oscillator and PLL are running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz and 30 MHz.

Table 10. Power consumption for individual analog and digital blocks

Peripheral Typical supply current in mA Notes

n/a 12 MHz 30 MHz

IRC 0.21 - - System oscillator running; PLL off; independent

of main clock frequency.

System oscillator at 12 MHz 0.28 - - IRC running; PLL off; independent of main clock

frequency.

Watchdog oscillator at

500 kHz/2 0.002 - - System oscillator running ; PLL off; independent

of main clock frequency.

BOD 0.05 - - Independent of main clock frequen cy.

Main PLL - 0.31 - -

CLKOUT - 0.06 0.09 Main clock divided by 4 in the CLKOUTDIV

ROM - 0.08 0.19 -

I2C - 0.06 0.15 -

GPIO + pin interrupt/pattern

match - 0.09 0.23 GPIO pins configured as outputs and set to

LOW. Direction and pin state are maintained if

the GPIO is disabled in the SYSAHBCLKCFG

SWM - 0.03 0.07 -

SCT - 0.17 0.42 -

WKT - 0.01 0.03 -

MRT - 0.09 0.21 -

SPI0 - 0.05 0.13 -

SPI1 - 0.06 0.14 -

CRC - 0.03 0.07 -

USART0 - 0.04 0.10 -

USART1 - 0.04 0.11 -

USART2 - 0.04 0.10 -

WWDT - 0.04 0.10 Main clock selected as clock source for the

WDT.

IOCON - 0.03 0.08 -

Comparator - 0.04 0.09 -

Product data sheet Rev. 4.6 — 4 April 2018 43 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

11.4 Electrical pin characteristics

Conditions: VDD = 3.3 V and VDD = 1.8 V; on pins PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13.

Fig 22. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level

output current IOH

Conditions: VDD = 3.3 V and VDD = 1.8 V; on pins PIO0_10 and PIO0_11.

Fig 23. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus

LOW-level output voltage VOL

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Product data sheet Rev. 4.6 — 4 April 2018 44 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins and high-drive pins PIO0_2, PIO0_3,

PIO0_7, PIO0_12, PIO0_13.

Fig 24. Typical LOW-level output current IOL versus LOW-level output voltage VOL

Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins.

Fig 25. Typical HIGH-level output voltage VOH versus HIGH-level output source current

IOH

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Product data sheet Rev. 4.6 — 4 April 2018 45 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins.

Fig 26. Typical pull-up curren t Ipu versus input voltage VI

Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins.

Fig 27. Typical pull-down current Ipd versus input voltage VI

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Product data sheet Rev. 4.6 — 4 April 2018 46 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

12. Dynamic characteristics

12.1 Power-up ramp conditions

[1] See Figure 28.

[2] The wait time specifies the time the power supply must be at levels below 200 mV before ramping up. See

the LPC81x errata sheet.

[3] Based on characterization, not tested in production.

12.2 Flash memory

Table 11. Power-up characteristics

Tamb =





C to +105



C; 1.8 V



VDD



3.6 V

Symbol Parameter Conditions Min Typ Max Unit

trrise time at t = t1: 0 < VI 200 mV [1][3] 0- 500 ms

twait wait time [1][2][3] 12 - - s

VIinput voltage at t = t1 on pin VDD [3] 0 - 200 mV

Condition: 0 < VI 200 mV at start of power-up (t = t1)

Fig 28. Power-up ramp

200 mV

wait

t = t

1aaa-017426

Table 12. Flash characteristics

Tamb =





C to +105



C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as

specified below.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance [1] 10000 100000 - cycles

Product data sheet Rev. 4.6 — 4 April 2018 47 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

[1] Number of program/erase cycles.

[2] Programming times are given for writing 64 bytes to the flash. Tamb  +85 C. Flash programming with IAP

calls (see LPC800 user manual).

12.3 External clock for the oscillator in slave mode

Remark: The input voltage on the XTAL1/2 pins must be  1.95 V (see Table 9). For

connecting the oscillator to the XTAL pins, also see Section 14.2.

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply

voltages.

tret retention time powered 10 20 - years

unpowered 20 40 - years

ter erase time page or multiple

consecutive pages,

sector or multiple

consecutive

sectors

95 100 105 ms

tprog programming

time [2] 0.95 1 1.05 ms

Table 12. Flash characteristics

Tamb =





C to +105



C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as

specified below.

Symbol Parameter Conditions Min Typ Max Unit

Table 13. Dynamic characteristic: external clock (XTALIN inputs)

Tamb =





C to +105



C; VDD over specified ranges.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc oscillator frequency 1 - 25 MHz

Tcy(clk) clock cycle time 40 - 1000 ns

tCHCX clock HIGH time Tcy(clk) 0.4 - - ns

tCLCX clock LOW time Tcy(clk) 0.4 - - ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Fig 29. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

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Product data sheet Rev. 4.6 — 4 April 2018 48 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

12.4 Internal oscillators

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply

voltages.

[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %.

[3] See the LPC81xM user manual.

Table 14. Dynamic characteristics: IRC

Tamb =





C to +105



C; 2.7 V



VDD



3.6 V[1].

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc(RC) internal RC oscillator

frequency Tamb =40 C to

+105 C11.82 12 12.18 MHz

Conditions: Frequency values are typical values. 12 MHz  1.5 % accuracy is guaranteed for

2.7 V  VDD  3.6 V and Tamb =40 C to +105 C. Variations between parts may cause the IRC to

fall outside the 12 MHz  1.5 % accuracy specification for voltages below 2.7 V.

Fig 30. Typical Internal RC oscillator frequency versus temperature

Table 15. Dynamic chara cteristics: Watchdog oscillator

Symbol Parameter Conditions Min Typ[1] Max Unit

fosc(int) internal oscillator

frequency DIVSEL = 0x1F, FREQSEL = 0x1

in the WDTOSCCTRL re gi ster; [2][3] -9.4-kHz

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTR L re gi st er [2][3] - 2300 - kHz

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Product data sheet Rev. 4.6 — 4 April 2018 49 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

12.5 I/O pins

[1] Applies to standard port pins and RESET pin.

12.6 I2C-bus

[1] See the I2C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

Table 16. Dynamic characteristics: I/O pins[1]

Tamb =





C to +105



C; 3.0 V



VDD



3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

trrise time pin configu red as output 3.0 - 5.0 ns

tffall time pin configured as output 2.5 - 5.0 ns

Table 17. Dynamic characteristic: I2C-bus pins[1]

Tamb =





C to +105



C.[2]

Symbol Parameter Conditions Min Max Unit

fSCL SCL clock

frequency Standard-mode 0 100 kHz

Fast-mode 0 400 kHz

Fast-mode Plus; on

pins PIO0_10 and

PIO0_11

01MHz

tffall time [4][5][6][7] of both SDA and

SCL signals

Standard-mode

- 300 ns

Fast-mode 20 + 0.1  Cb300 ns

Fast-mode Plus;

on pins PIO0_10

and PIO0_11

- 120 ns

tLOW LOW period of

the SCL clock Standard-mode 4.7 - s

Fast-mode 1.3 - s

Fast-mode Plus; on

pins PIO0_10 and

PIO0_11

0.5 - s

tHIGH HIGH period of

the SCL clock Standard-mode 4.0 - s

Fast-mode 0.6 - s

Fast-mode Plus; on

pins PIO0_10 and

PIO0_11

0.26 - s

tHD;DAT data hold time [3][4][8] Standard-mode 0 - s

Fast-mode 0 - s

Fast-mode Plus; on

pins PIO0_10 and

PIO0_11

0-s

tSU;DAT data set-up

time

[9][10] Standard-mode 250 - ns

Fast-mode 100 - ns

Fast-mode Plus; on

pins PIO0_10 and

PIO0_11

50 - ns

Product data sheet Rev. 4.6 — 4 April 2018 50 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] Cb = total capacitance of one bus line in pF.

[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for S tandard-mode and Fast-mode but must be less than

the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement

tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must

meet this set-up time.

Fig 31. I2C-bus pins clock timing

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Product data sheet Rev. 4.6 — 4 April 2018 51 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

12.7 SPI interfaces

The maximum data bit rate is 30 Mbit/s in master mode and 25 Mbit/s in slave mode.

Remark: SPI functions can be assigned to all dig it al pins. The characteristics are valid for

all digital pins except the open - dr ain pins PIO0_10 and PIO0 _11.

[1] Capacitance on pin SPIn_SCK CSCK < 5 pF.

[2] Tcy(clk) = DIVVAL/CCLK with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the

LPC800 User manual UM10601.

Table 18. SPI dyna mic characteristics

Tamb =





C to 105



C; 1.8 V



VDD



3.6 V. Simulated parameters sampled at the 50 % level of

the rising or falling edge; values guaranteed by design.

Symbol Parameter Conditions Min Max Unit

SPI master[1]

Tcy(clk) clock cycle time [2] 33 - ns

tDS data set-up time 0 - ns

tDH data hold time 16 - ns

tv(Q) data output valid ti me CL = 10 pF - 0.5 ns

th(Q) data output hold time CL = 10 pF 0.5 - ns

SPI slave

Tcy(clk) 40 ns

tDS data set-up time 0 - ns

tDH data hold time 16 - ns

tv(Q) data output valid ti me CL = 10 pF - 10 ns

th(Q) data output hold time CL = 10 pF 10 - ns

Product data sheet Rev. 4.6 — 4 April 2018 52 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Pin names SCK, MISO, and MOSI r e fer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 32. SPI master timing

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Product data sheet Rev. 4.6 — 4 April 2018 53 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Pin names SCK, MISO, and MOSI r e fer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 33. SPI slave timing

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Product data sheet Rev. 4.6 — 4 April 2018 54 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

12.8 USART interface

The maximum USART bit rate is 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in

synchronous mode slave and master mode.

Remark: USART functions can be assig ned to all digital pins. The characteristics are valid

for all digital pins except the open-drain pi ns PIO0_10 and PIO0_11.

[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), VDD = 3.3 V, typical

samples.

[2] Tcy(clk) = U_PCLK/BRGVA L. See the LPC800 User manual UM10601.

[3] Capacitance on pin Un_SCLK CSCLK < 5 pF.

Table 19. USART dynamic characteristics

Tamb =





C to 105



C; 1.8 V



VDD



3.6 V. Simulated parameters sampled at the 50 % level of

the falling or rising edge; values guaranteed by design.

Symbol Parameter Conditions Min Max Unit

Tcy(clk) clock cycle time [2] 100 - ns

USART master (in synchronous mode)[3]

tsu(D) data input set-up

time 44 - ns

th(D) data input hold time 0 - ns

tv(Q) data output valid time - -8 ns

th(Q) data output hold time -8 - ns

USART slave (in synchron ous mode)

tsu(D) data input set-up

time 5- ns

th(D) data input hold time 0 - ns

tv(Q) data output valid time CL = 10 pF - 40 ns

th(Q) data output hold time CL = 10 pF 40 - ns

Fig 34. USART timing

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Product data sheet Rev. 4.6 — 4 April 2018 55 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

13. Analog characteristics

13.1 BOD

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL.

[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), VDD = 3.3 V, typical

samples.

13.2 Internal voltage reference

[1] Characterized through simulation.

[2] Characterized on a typical silicon sample.

Table 20. BOD static characteristics[1]

Tamb =





C to +105



Symbol Parameter Conditions Typ[2] Unit

Vth threshold voltage interrupt level 1

assertion 2.3 V

de-assertion 2.4 V

interrupt level 2

assertion 2.6 V

de-assertion 2.7 V

interrupt level 3

assertion 2.8 V

de-assertion 2.9 V

reset level 1

assertion 2.1 V

de-assertion 2.2 V

reset level 2

assertion 2.4 V

de-assertion 2.5 V

reset level 3

assertion 2.6 V

de-assertion 2.8 V

Table 21. Internal voltage reference static and dynamic characteristics

Symbol Parameter Conditions Min Typ Max Unit

VOoutput voltage Tamb = 40 C to +105 C[1] 0.855 0.900 0.945 V

Tamb = 70 C to 105 C[2] - 0.906 - V

Tamb = 50 C[2] - 0.905 - V

Tamb = 25 C[4] 0.893 0.903 0.913 V

Tamb = 0 C[2] - 0.902 - V

Tamb = 20 C[2] - 0.899 - V

Tamb = 40 C[2] - 0.896 - V

ts(pu) power-up

settling time to 99% of VO[3] - 155 195 s

Product data sheet Rev. 4.6 — 4 April 2018 56 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

[3] Typical values are derived from nominal simulation (VDD = 3.3 V; Tamb = 27 C; nominal process models).

Maximum values are derived from worst case simulation (VDD = 2.6 V; Tamb = 105 C; slow process

models).

[4] Maximum and minimum values are measured on samples from the corners of the process matrix lot.

13.3 Comparator

VDD = 3.3 V

Fig 35. Typical internal voltage reference output voltage

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Table 22. Comparator characteristics

VDD = 3.0 V and Tamb = 27



C unless noted otherwise.

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

Vref(cmp) comparator reference

voltage pin PIO0_6/VDDCMP configured for

function VDDCMP 1.5 - 3.6 V

IDD supply current - 55 - A

VIC common-mode input

voltage 0- V

DD V

DVOoutput voltage variation 0 - VDD V

Voffset offset voltage VIC = 0.1 V - 1.9 - mV

VIC = 1.5 V - 2.1 - mV

VIC = 2.8 V - 2.0 mV

Dynamic character istics

tstartup start-up time nominal process - 4 - s

Product data sheet Rev. 4.6 — 4 April 2018 57 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

[1] CL = 10 pF; results from measurements on silicon samples over process corners and over the full temperature range Tamb = 40 C to

+105 C. Typical data are for Tamb = 27 C.

[2] Input hysteresis is relative to the reference inpu t channel and is software programmable to three levels.

[1] Maximum values are derived from worst case simulation (VDD = 2.6 V; Tamb = 105 C; slow process

models).

[2] Settling time applies to switching between comparator channels.

tPD propagation delay HIGH to LOW; VDD = 3.0 V;

VIC = 0.1 V; 50 mV overdrive input [1] - 109 121 ns

VIC = 0.1 V; rail-to-rail input [1] - 155 164 ns

VIC = 1.5 V; 50 mV overdrive input [1] -95 105ns

VIC = 1.5 V; rail-to-rail input [1] - 101 108 ns

VIC = 2.9 V; 50 mV overdrive input [1] - 122 129 ns

VIC = 2.9 V; rail-to-rail input [1] -74 82 ns

tPD propagation delay LOW to HIGH; VDD = 3.0 V;

VIC = 0.1 V; 50 mV overdrive input [1] - 246 260 ns

VIC = 0.1 V; rail-to-rail input [1] -57 59 ns

VIC = 1.5 V; 50 mV overdrive input [1] - 218 ns

VIC = 1.5 V; rail-to-rail input [1] - 146 155 ns

VIC = 2.9 V; 50 mV overdrive input [1] - 184 206 ns

VIC = 2.9 V; rail-to-rail input [1] - 250 286 ns

Vhys hysteresis voltage positive hysteresis; VDD = 3.0 V;

VIC = 1.5 V [2] - 6, 11, 21 - mV

Vhys hysteresis voltage negative hysteresis; VDD = 3.0 V;

VIC = 1.5 V [2][2] - 4, 9, 19 - mV

Rlad ladder resistance - - 1.034 - M

Table 22. Comparator characteristics …continued

VDD = 3.0 V and Tamb = 27



C unless noted otherwise.

Symbol Parameter Conditions Min Typ Max Unit

Table 23. Comparator voltage ladder dynamic charac teristics

Symbol Parameter Conditions Min Typ Max Unit

ts(pu) power-up settling

time to 99% of voltage

ladder output

value

[1] -- 30 s

ts(sw) switching settling

time to 99% of voltage

ladder output

value

[1]

[2] -- 15 s

Product data sheet Rev. 4.6 — 4 April 2018 58 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

[1] Measured over a polyresistor matrix lot with a 2 kHz input signal and overdrive < 100 V.

[2] All peripherals except comparator and IRC turned off.

Table 24. Comp arator voltage ladder reference st atic characteristics

VDD = 3.3 V; Tamb =





C to + 105



Symbol Parameter Conditions Min Typ Max[1] Unit

EV(O) output voltage error Internal VDD supply

decimal code = 00 [2] -00 %

decimal code = 08 - 0 0.4 %

decimal code = 16 - 0.2 0.2 %

decimal code = 24 - 0.2 0.2 %

decimal code = 30 - 0.1 0.1 %

decimal code = 31 - 0.1 0.1 %

EV(O) output voltage error External VDDCMP

supply

decimal code = 00 - 0 0 %

decimal code = 08 - 0.1 0.5 %

decimal code = 16 - 0.2 0.4 %

decimal code = 24 - 0.2 0.3 %

decimal code = 30 - 0.2 0.2 %

decimal code = 31 - 0.1 0.1 %

Product data sheet Rev. 4.6 — 4 April 2018 59 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

14. Application information

14.1 Typical wake-up times

[1] The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up

from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)

wake-up handler.

[2] IRC enabled, all peripherals off.

[3] Watchdog oscillator disabled, Brown-Out Detect (BOD) disabled.

[4] Self wakeup-timer disabled. Wake-up from deep power-down causes the LPC800 to go through entire reset

process. The wake-up time measured is the time between when a wake-up pin is triggered to wake the

device up from the low power modes and from when a GPIO output pin is set in the reset handler.

14.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommende d that the inpu t be coupled th rough a cap acitor wi th

Ci = 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground Cg which attenuates the input volt age by a facto r Ci/(Ci + Cg). In slave

mode, a minimum of 200 mV(RMS) is needed.

In slave mode the input clock signal should be coup led by means of a cap acitor of 100 pF

(Figure 36), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 37 and in

Table 26 and Table 27. Since the feedback resistance is integrated on chip, only a cr ystal

and the capacitances CX1 and CX2 need to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, CL and

Table 25. Typical wake-up time s (3.3 V, Temp = 25 °C)

Power modes VDD current Wake-up time

Sleep mode (12 MHz)[1][2] 0.7 mA 2.6 s

Deep-sleep mode[1][3] 150 A4 s

Power-down mode[1][3] 0.9 A 50 s

Deep Power-down mode[4] 170 nA 215 s

Fig 36. Slave mode operation of the on-chip oscillator

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Product data sheet Rev. 4.6 — 4 April 2018 60 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

RS). Capacitance CP in Figure 37 represent s the p arallel p ackage cap acitance and should

not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal

manufacturer (see Table 26).

Fig 37. Oscillator modes and models: oscillation mode of operation and external crystal

model used for CX1/CX2 evaluation

Table 26. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

1 MHz to 5 MHz 10 pF < 300 18 pF, 18 pF

20 pF < 300 39 pF, 39 pF

30 pF < 300 57 pF, 57 pF

5 MHz to 10 MHz 10 pF < 300 18 pF, 18 pF

20 pF < 200 39 pF, 39 pF

30 pF < 100 57 pF, 57 pF

10 MHz to 15 MH z 10 pF < 160 18 pF, 18 pF

20 pF < 60 39 pF, 39 pF

15 MHz to 20 MH z 10 pF < 80 18 pF, 18 pF

Table 27. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) high frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

15 MHz to 20 MH z 10 pF < 180 18 pF, 18 pF

20 pF < 100 39 pF, 39 pF

20 MHz to 25 MH z 10 pF < 160 18 pF, 18 pF

20 pF < 80 39 pF, 39 pF

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Product data sheet Rev. 4.6 — 4 April 2018 61 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

14.3 XTAL Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors Cx1,Cx2, and Cx3 in case of

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

order to keep the noise coup le d in via the PCB as sm all as po ss ible . A lso parasitics

should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

Product data sheet Rev. 4.6 — 4 April 2018 62 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

14.4 ElectroMagnetic Compatibility (EMC)

Radiated emission measurements according to the IEC61967-2 standard using the

TEM-cell method are shown for part LPC812M101FDH20.

[1] IEC levels refer to Appendix D in the IEC61967-2 Specification.

Table 28. ElectroMagnetic Compatibility (EMC) for part LPC812M101 (TEM-cell method)

VDD = 3.3 V; Tamb = 25



Parameter Frequency band System clock = Unit

12 MHz 24 MHz 30 MHz

Input clock: IRC (12 MHz)

maximum peak

level 1 MHz to 30 MHz 655dBV

30 MHz to 150 MHz -2 -1 -2 dBV

150 MHz to 1 GHz 1-1 -1 dBV

IEC level[1] - OOO-

Input clock: crystal oscillator (12 MHz)

maximum peak

level 1 MHz to 30 MHz 566dBV

30 MHz to 150 MHz 2-1 -2 dBV

150 MHz to 1 GHz 1-2 -1 dBV

IEC level[1] - OON-

Product data sheet Rev. 4.6 — 4 April 2018 63 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

15. Package outline

Fig 38. Package outline SOT097-2 (DIP8)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT97-2 MO-001

sot097-2_po

10-10-15

10-10-18

Unit(1)

mm max

nom

min

4.2

0.51

0.53

0.38

1.07

0.89

0.38

0.20

6.48

6.20

9.8

9.2 2.54 7.62

Dimensions (inch dimensions are derived from the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included

DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-2

A1b

1.73

1.14

b1b2cD

(1) E(1) ee

1LM

EMHw

0.254

Z(1)

1.15

inches max

nom

min

0.17

0.02

3.43

0.14 0.021

0.015

0.042

0.035

0.015

0.008

9.40

7.88

0.37

0.31

7.88

7.62

0.31

0.30

0.26

0.24

0.39

0.36

3.60

3.05

0.14

0.12

0.1 0.3

0.068

0.045 0.01 0.045

0 2.5 5 mm

scale

Zb1

seating plane

pin 1 index

(e1)

- - -- - -

Product data sheet Rev. 4.6 — 4 April 2018 64 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Fig 39. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 4.6 — 4 April 2018 65 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Fig 40. Package outline SOT163-1 (SO20)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 13.0

12.6 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT163-1

detail X

0.25

075E04 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.51

0.49 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

vMA

(A )

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

99-12-27

03-02-19

Product data sheet Rev. 4.6 — 4 April 2018 66 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Fig 41. Package outline SOT360-1 (TSSOP20)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 6.6

6.4 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.5

0.2 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT360-1 MO-153 99-12-27

03-02-19

0.25

110

20 11

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

max.

1.1

Product data sheet Rev. 4.6 — 4 April 2018 67 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Fig 42. Package outline SOT1341-1 (XSON16)

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT1341-1 MO-252

sot1341-1_po

12-09-05

13-02-13

Unit(1)

max

nom

min

0.5 0.05

0.00

Dimensions (mm are the original dimensions)

XSON16: plastic extremely thin small outline package; no leads; 16 terminals; body 2.5 x 3.2 x 0.5 mm

SOT1341-1

0.25

0.20

0.15

2.6

2.5

2.4

0.9

0.8

0.7

3.3

3.2

3.1

0.4 2.8

0.2

0.152

0.050

DEee

1kL

1.0

0.9

0.8

L1v

0.050.1

0.05

03 mm21

scale

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

terminal 1

index area

terminal 1

index area

B A

detail X

AA1

- - - - - -

bAC B

1 8

16 9

Product data sheet Rev. 4.6 — 4 April 2018 68 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

16. Soldering

Fig 43. Re flo w soldering of the TSSOP16 package

DIMENSIONS in mm

Ay By D1 D2 Gy HyP1 C Gx

sot403-1_fr

SOT403-1

solder land

occupied area

Footprint information for reflow soldering of TSSOP16 package

AyByGy

Generic footprint pattern

Refer to the package outline drawing for actual layout

(0.125) (0.125)

D2 (4x)

7.200 4.500 1.350 0.400 0.600 5.600 5.300 7.4505.8000.650 0.750

Product data sheet Rev. 4.6 — 4 April 2018 69 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Fig 44. Reflow soldering of the SO20 package

sot163-1_fr

occupied area

solder lands

Dimensions in mm

placement accuracy ± 0.25

1.50

0.60 (20×)

1.27 (18×)

8.00 11.00

13.40

11.40

Product data sheet Rev. 4.6 — 4 April 2018 70 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Fig 45. Re flo w soldering of the TSSOP20 package

DIMENSIONS in mm

Ay By D1 D2 Gy HyP1 C Gx

sot360-1_fr

SOT360-1

solder land

occupied area

Footprint information for reflow soldering of TSSOP20 package

AyByGy

Generic footprint pattern

Refer to the package outline drawing for actual layout

(0.125) (0.125)

D2 (4x)

7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.4507.3000.650 0.750

Product data sheet Rev. 4.6 — 4 April 2018 71 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Fig 46. Re flow soldering of the XSON16 package

627)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI;621SDFNDJH

VRWBIU

RFFXSLHGDUHD

VROGHUSDVWH

VROGHUUHVLVW

VROGHUODQGV

,VVXHGDWH

'LPHQVLRQVLQPP











  







Product data sheet Rev. 4.6 — 4 April 2018 72 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

17. Abbreviations

18. References

[1] I2C-bus specification UM10204.

Table 29. Abbreviations

Acronym Description

AHB Advanced High-performance Bus

APB Advanced Peripheral Bus

BOD B rownOut Detection

GPIO General-Purpose Input/Output

PLL Phase-Locked Loop

RC Resistor-Capacitor

SPI Serial Peripheral Interface

SMBus System Management Bus

TEM Transverse ElectroMagnetic

UART Universal Asynchronous Receiver/Transmitter

Product data sheet Rev. 4.6 — 4 April 2018 73 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

19. Revision history

Table 30. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC81XM v.4.6 20180404 Product data sheet 201804004I LPC81XM v.4.5

Modifications: •Updated table note 2 of Section 12.1 “Power-up ramp conditions”.

LPC81XM v.4.5 20160603 P roduct data sheet - LPC81XM v.4.4

Modifications: •Added Section 12.1 “Power-up ramp conditions”.

•Updated Figure 4 “Pin configura ti on SO20 package (LPC812M101JD20)”: Corrected

function of pin 12 to ACMP_I2.

•Updated the remark in Section 8.12 “USART0/1/2” to: USART2 is available on parts

LPC812M101JTB16, LPC812M101 JDH16, and LPC812M101JDH20 only.

LPC81XM v.4.4 20150619 P roduct data sheet - LPC81XM v.4.3

Modifications: •Section 14.4 “ElectroMagnetic Compatibility (EMC)” added.

LPC81XM v.4.3 20140422 P roduct data sheet - LPC81XM v.4.2

Modifications: •Section 8.20.2 “Clock input” updated for clarity.

•CLKIN signal removed from Table 13 “Dynamic characteristic: external clock (XTALIN

inputs)”.

•Name “SCT” changed to “SCTimer/PWM” for clarity.

•Remove slew rate control from GPIO features for clarity.

•MRT bus stall mode added.

•WWDT clock source corrected in Section 8.17.1.

•Pin description table updated for clarification (I2C-bus pins, WAKEUP, RESET).

•Added reflow solder diagram and thermal resistance numbers for XSON16

(SOT1341-1).

•Table 22: Added Vref(cmp) spec for PIO0_6/VDDCMP..

LPC81XM v.4.2 20131210 P roduct data sheet - LPC81XM v.4.1

Modifications: Corrected vertical axis marker in Figure 21 “CoreMark score”.

LPC81XM v.4.1 20131112 Product data sheet - LPC81XM v.4

Modifications: •Corrected XSON16 pin information in Figure 6 and Table 4.

LPC81XM v.4 20131025 P roduct data sheet - LPC81XM v.3.1

Modifications: •Added Section 14.1 “Typical wake-up times”.

•Added LPC812M101JTB16 and XSON16 package.

LPC81XM v.3.1 2013091 6 Product data sheet - LPC81XM v.3

Modifications: •Correct the pin interrupt features: Pin interrupts can wake up the part from Sleep

mode, Deep-sleep mode, and Power-down mode. See Section 8.11.1.

•Table 9 “S tatic characteristics”: Updated power numbers for Deep-sleep, Power-down,

and Deep power-down.

•Added 30 MHz data to Figure 13 “Active mode: Typical supply current IDD versus

supply voltage VDD”, Figure 14 “Active mode: Typical supply current IDD versus

temperature”, and Figure 15 “Sleep mode: Typical supply current IDD versus

temperature for different system clock frequencies”.

LPC81XM v.3 20130729 P roduct data sheet - LPC81XM v.2.1

Product data sheet Rev. 4.6 — 4 April 2018 74 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

•Operating temperature range changed to 40 °C to 105 °C.

•Type numbers upda ted to reflect the new operating temperature range. See Table 1

“Ordering information” and Table 2 “Ordering options”.

•ISP entry pin moved from PIO0_1 to PIO0_12 for TSSOP, and SSOP packages. See

Table 4 and Table 6.

•Propagation delay values updated in Table 21 “Comparator characteristics”.

•SPI characteristics updated. See Section 12.6.

•IRC characteristics up dated. See Section 12.3.

•CoreMark data updated. See Figure 19 and Figure 20.

•IRC frequency changed to 12 MHz +/- 1.5 %. See Table 13.

•Data sheet status updated to Product data sheet.

LPC81XM v.2.1 20130325 Preliminary data sheet - LPC81XM v.2

•Editorial updates (temperature sensor removed).

•CoreMark data added. See Figure 19 “Active mode: CoreMark power consumpti on

IDD” and Figure 20 “CoreMark score”.

•IDD in Deep power-down mode added for conditio n Low-power oscillator on/WKT

wake-up enabled. See Table 10.

•Table note 3 updated for Table 4 “Pin description table (fixed pins)”.

•Conditions for ter and tprog updated in Table 12 “Flash characteristics”.

•Section 13.3 “Internal voltage reference” added.

•Typical timing data added for SPI. See Section 12.6.

•Typical timing data added for USART in synchronous mode. See Section 12.7.

•BOD characterization added. See Section 13.1.

•IRC characterization added. See Section 12.3.

•Internal voltage reference characteristics added. See Section 13.3.

•Data sheet status changed to Preliminary data sheet.

LPC81XM v.2 20130128 O bjective data sheet - L PC 81XM v.1

Modifications: •MTB memory space changed to 1 kB in Figure 6.

•Electrical pin characteristics added in Table 10.

•Figure 11 “Con necting the SWD pins to a standard SWD connector” added.

•Peripheral power consumption added in Table 11.

•Table 7 updated.

•MRT implementation changed to 31-bit timer .

•Power consumption data in active and sleep mode with IRC added. See Figure 13 to

Figure 15.

•Power consumption (parameter IDD) in active and sleep mode for low-power mode at

12 MHz correc te d in Table 10.

•Power consumption (parameter IDD) in active and sleep mode at 24 MHz added in

Table 10.

•Maximum USART speed in synchronous mode changed to 10 Mbit/s.

•Section 5 “Marking” added.

LPC81XM v.1 20121112 Objective data sheet - -

Table 30. Revision history …continued

Document ID Release date Data sheet status Change notice Supersedes

Product data sheet Rev. 4.6 — 4 April 2018 75 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

20.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

20.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental ,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semicondu ctors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support , life-critical or

safety-critical systems or equipme nt, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or en vironmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with t heir

applications and products.

NXP Semiconductors does not accept any liabili ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo mer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconducto rs

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development .

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contain s t he product specification.

Product data sheet Rev. 4.6 — 4 April 2018 76 of 78

NXP Semiconductors LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

20.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 4.6 — 4 April 2018  77 of 78
continued >>
NXP Semiconductors LPC81xM
 32-bit ARM Cortex-M0+ microcontroller
Contents
General description. . . . . . . . . . . . . . . . . . . . . .  1
Features and benefits . . . . . . . . . . . . . . . . . . . .  1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2
Ordering information. . . . . . . . . . . . . . . . . . . . .  3
1  Ordering options. . . . . . . . . . . . . . . . . . . . . . . .  3
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .  5
Pinning information. . . . . . . . . . . . . . . . . . . . . .  6
1  Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6
2  Pin description . . . . . . . . . . . . . . . . . . . . . . . . .  8
Functional description . . . . . . . . . . . . . . . . . .  13
1  ARM Cortex-M0+ core . . . . . . . . . . . . . . . . . .  13
2  On-chip flash program memory . . . . . . . . . . .  13
3  On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . .  13
4  On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . .  13
5  Nested Vectored Interrupt Controller (NVIC) .  13
5.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
5.2  Interrupt sources. . . . . . . . . . . . . . . . . . . . . . .  13
6  System tick timer . . . . . . . . . . . . . . . . . . . . . .  14
7  Memory map. . . . . . . . . . . . . . . . . . . . . . . . . .  14
8  I/O configuration. . . . . . . . . . . . . . . . . . . . . . .  15
8.1  Standard I/O pad configuration. . . . . . . . . . . .  16
9  Switch Matrix (SWM) . . . . . . . . . . . . . . . . . . .  17
10  Fast General-Purpose parallel I/O (GPIO) . . .  17
10.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
11  Pin interrupt/pattern match engine . . . . . . . . .  18
11.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
12  USART0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . .  19
12.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
13  SPI0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
13.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
14  I2C-bus interface  . . . . . . . . . . . . . . . . . . . . . .  20
14.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
15 State-Configurable Timer/PWM
(SCTimer/PWM) . . . . . . . . . . . . . . . . . . . . . . .  20
15.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
16  Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . .  21
16.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
17  Windowed WatchDog Timer (WWDT) . . . . . .  21
17.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
18  Self Wake-up Ti mer (WKT). . . . . . . . . . . . . . .  22
18.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
19  Analog comparator (ACMP) . . . . . . . . . . . . . .  22
19.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
20  Clocking and power control  . . . . . . . . . . . . . .  24
20.1  Crystal and internal oscillators . . . . . . . . . . . .  24
20.1.1  Internal RC Oscillator (IRC). . . . . . . . . . . . . .   25
20.1.2  Crystal Oscillator (SysOsc) . . . . . . . . . . . . . .   25
20.1.3  Interna l Low-power Oscillator and Watchdog 
Oscillator (WDOsc) . . . . . . . . . . . . . . . . . . . .   25
20.2  Clock input. . . . . . . . . . . . . . . . . . . . . . . . . . .   25
20.3  System PLL . . . . . . . . . . . . . . . . . . . . . . . . . .   25
20.4  Clock output. . . . . . . . . . . . . . . . . . . . . . . . . .   26
20.5  Wake-up process. . . . . . . . . . . . . . . . . . . . . .   26
20.6  Power control. . . . . . . . . . . . . . . . . . . . . . . . .   26
20.6.1  Power profiles . . . . . . . . . . . . . . . . . . . . . . . .   26
20.6.2  Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . .   26
20.6.3  Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . .   27
20.6.4  Power-down mode. . . . . . . . . . . . . . . . . . . . .   27
20.6.5  Deep power-down mode . . . . . . . . . . . . . . . .   27
21  System control. . . . . . . . . . . . . . . . . . . . . . . .   28
21.1  Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   28
21.2  Brownout detection  . . . . . . . . . . . . . . . . . . . .   28
21.3  Code securi ty (Code Read Protection - CRP)  29
21.4  APB interface. . . . . . . . . . . . . . . . . . . . . . . . .   29
21.5  AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   29
22  Emulation and debugging . . . . . . . . . . . . . . .   30
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .   31
Thermal characteristics . . . . . . . . . . . . . . . . .   32
Static characteristics  . . . . . . . . . . . . . . . . . . .   33
1  Power consumption . . . . . . . . . . . . . . . . . . . .   37
2  CoreMark data. . . . . . . . . . . . . . . . . . . . . . . .   41
3  Peripheral power consumption  . . . . . . . . . . .   42
4  Electrical pin characteristics. . . . . . . . . . . . . .   43
Dynamic characteristics. . . . . . . . . . . . . . . . .   46
1  Power-up ramp conditions . . . . . . . . . . . . . . .   46
2  Flash memory  . . . . . . . . . . . . . . . . . . . . . . . .   46
3  External clock for the oscillator in slave mode  47
4  Internal oscillators . . . . . . . . . . . . . . . . . . . . .   48
5  I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   49
6 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   49
7  SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . .   51
8  USART interface . . . . . . . . . . . . . . . . . . . . . .   54
Analog characteristics . . . . . . . . . . . . . . . . . .   55
1  BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   55
2  Internal voltage reference . . . . . . . . . . . . . . .   55
3  Comparator . . . . . . . . . . . . . . . . . . . . . . . . . .   56
Application information . . . . . . . . . . . . . . . . .   59
1  Typical wake-up times . . . . . . . . . . . . . . . . . .   59
2  XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . .   59
3  XTAL Pri nted Circuit Board (PCB) layout 
guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . .   61
4  ElectroMagnetic Compatibility (EMC)  . . . . . .   62

NXP Semiconductors LPC81xM
 32-bit ARM Cortex-M0+ microcontroller
© NXP Semiconductors N.V. 2018. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 April 2018
Document identifier : LPC 81X M
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’. 
15  Package outline . . . . . . . . . . . . . . . . . . . . . . . .  63
16  Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  68
17  Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . .  72
18  References . . . . . . . . . . . . . . . . . . . . . . . . . . . .  72
19  Revision history. . . . . . . . . . . . . . . . . . . . . . . .  73
20  Legal information. . . . . . . . . . . . . . . . . . . . . . .  75
20.1  Data sheet status . . . . . . . . . . . . . . . . . . . . . .  75
20.2  Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . .  75
20.3  Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .  75
20.4  Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .  76
21  Contact information. . . . . . . . . . . . . . . . . . . . .  76
22  Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  77