CMOS, 240 MHz,
10-Bit, High Speed Video DAC
Data Sheet
ADV7127
Rev. A Document Feedback
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FEATURES
240 MSPS throughput rate
10-bit digital-to-analog converter (DAC)
RS-343A-/RS-170-compatible output
Complementary outputs
DAC output current range: 2 mA to 18.5 mA
TTL-compatible inputs
Internal voltage reference
Single supply 5 V or 3.3 V operation
24-lead thin shrink small outline package (TSSOP) package
Low power dissipation
Low power standby mode
Power-down mode
Industrial temperature range (−40°C to +85°C)
APPLICATIONS
Digital video systems (1600 × 1200 at 100 Hz)
High resolution color graphics
Digital radio modulation
Image processing
Instrumentation
Video signal reconstruction
Direct digital synthesis (DDS)
Wireless local area networks (LANs)
FUNCTIONAL BLOCK DIAGRAM
D9 TO D0
GND RSET
IOUT
IOUT
COMP
ADV7127
VREF
VOLTAGE
REFERENCE
CIRCUIT
PDOWN POWER-DOWN
MODE
VAA
10
DAC
10
DATA
REGISTER
CLOCK
PSAVE
14959-001
Figure 1.
GENERAL DESCRIPTION
The ADV7127 is a high speed, DAC on a single monolithic
chip. It consists of a 10-bit, video DAC with an on-board voltage
reference, complementary outputs, a standard TTL input
interface, and high impedance analog output current sources.
The ADV7127 has a 10-bit wide input port. A single 5 V or
3.3 V power supply and clock are all that are required to make
the device functional.
The ADV7127 is fabricated in a complementary metal-oxide
semiconductor (CMOS) process. Its monolithic CMOS
construction ensures greater functionality with low power
dissipation. The ADV7127 is available in a 24-lead TSSOP
package which includes a power-down mode and an on-board
voltage reference circuit.
PRODUCT HIGHLIGHTS
1. 240 MSPS throughput.
2. Guaranteed monotonic to 10 bits.
3. Compatible with a wide variety of high resolution color
graphics systems including RS-343A and RS-170.
ADV7127* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DOCUMENTATION
Application Notes
•AN-205: Video Formats and Required Load Terminations
•AN-213: Low Cost, Two-Chip, Voltage -Controlled
Amplifier and Video Switch
Data Sheet
•ADV7127: CMOS, 240 MHz, 10-Bit, High Speed Video DAC
Data Sheet
REFERENCE MATERIALS
Solutions Bulletins & Brochures
•Digital to Analog Converters ICs Solutions Bulletin
DESIGN RESOURCES
•ADV7127 Material Declaration
•PCN-PDN Information
•Quality And Reliability
•Symbols and Footprints
DISCUSSIONS
View all ADV7127 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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DOCUMENT FEEDBACK
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ADV7127 Data Sheet
Rev. A | Page 2 of 18
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
5 V Electrical Characteristics ...................................................... 3
3.3 V Electrical Characteristics ................................................... 4
5 V Timing Specifications ........................................................... 5
3.3 V Timing Specifications ........................................................ 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
5 V .................................................................................................. 9
3.3 V ............................................................................................. 11
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 14
Digital Inputs .............................................................................. 14
Clock Input.................................................................................. 14
Reference Input ........................................................................... 14
Digital-to-Analog Converter .................................................... 14
Analog Output ............................................................................ 15
Gray Scale Operation ................................................................. 15
Video Output Buffer .................................................................. 15
PCB Layout Considerations ...................................................... 16
Ground Planes ............................................................................ 16
Power Planes ............................................................................... 16
Supply Decoupling ..................................................................... 16
Digital Signal Interconnect ....................................................... 16
Analog Signal Interconnect....................................................... 16
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
1/2017—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Deleted SOIC_W Package ................................................. Universal
Change RS-170A to RS-170 ......................................... Throughout
Changes to Features Section............................................................ 1
Deleted 5 V SOIC Specifications Table .......................................... 2
Changes to Table 1 ............................................................................ 3
Deleted 3.3 V SOIC Specifications Table ....................................... 4
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Deleted 5 V/3.3 V Dynamic Specifications Table ........................ 6
Changes to Table 4 ............................................................................ 6
Changes to Table 6 ............................................................................ 8
Changes to Figure 9 Caption ........................................................... 9
Changes to Figure 10 to Figure 12 ................................................ 10
Changes to Figure 18 Caption ...................................................... 11
Deleted Power Management Section and Table II ..................... 12
Changes to Figure 19 to Figure 21 ................................................ 12
Changed Circuit Description and Operation Section to Theory
of Operation Section ...................................................................... 14
Changes to Video Output Buffer Section .................................... 15
Changes to Supply Decoupling Section and Analog Signal
Interconnect Section ...................................................................... 16
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
4/1998—Revision 0: Initial Version
Data Sheet ADV7127
Rev. A | Page 3 of 18
SPECIFICATIONS
5 V ELECTRICAL CHARACTERISTICS
VAA = 5 V ± 5%, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted. TJ MAX = 110°C.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits
Integral Nonlinearity (INL) –1 +0.4 +1 LSB
Differential Nonlinearity –1 +0.25 +1 LSB Guaranteed monotonic
DIGITAL AND CONTROL INPUTS
Input Voltage
High VIH 2 V
Low VIL 0.8 V
PDOWN Input Voltage
High 3 V
Low
1
V
Input Current
I
IN
–1
+1
µA
V
IN
= 0.0 V or V
AA
Pull-Up Current
PSAVE 20 µA
PDOWN 20 µA
Input Capacitance CIN 10 pF
ANALOG OUTPUTS
Output Current 2.0 18.5 mA
Output Compliance Range VOC 0 1.4 V
Output Impedance ROUT 100 kΩ
Output Capacitance COUT 10 pF IOUT = 0 mA
Offset Error –0.025 +0.025 % FSR Tested with DAC output = 0 V
Gain Error2 –5.0 +5.0 % FSR FSR = 17.62 mA
VOLTAGE REFERENCE (EXTERNAL
AND INTERNAL)3
Reference Range VREF 1.12 1.235 1.35 V
POWER DISSIPATION
Supply Current
Digital 1.5 3 mA fCLK = 50 MHz
4 6 mA fCLK = 140 MHz
6.5 10 mA fCLK = 240 MHz
Analog
23
27
mA
R
SET
= 560 Ω
5 mA RSET = 4933 Ω
Standby4 3.8 6 mA PSAVE = low, digital and control inputs at VAA
PDOWN 1 mA
Power Supply Rejection Ratio PSRR 0.1 0.5 %/%
1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz.
2 Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = VREF/RSET × K × (0x3FF) and K = 7.9896.
3 The digital supply is measured with a continuous clock, with data input corresponding to a ramp pattern, and with an input level at 0 V and VDD.
4 These typical/maximum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.
ADV7127 Data Sheet
Rev. A | Page 4 of 18
3.3 V ELECTRICAL CHARACTERISTICS
VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted. TJ MAX = 110°C.
Table 2.
Parameter2 Symbol Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE RSET = 680 Ω
Resolution (Each DAC) 10 Bits
Integral Nonlinearity (INL) –1 +0.5 +1 LSB
Differential Nonlinearity –1 +0.25 +1 LSB
DIGITAL AND CONTROL INPUTS
Input Voltage
High VIH 2.0 V
Low VIL 0.8 V
PDOWN Input Voltage
High 2.1 V
Low 0.6 V
Input Current IIN –1 +1 μA VIN = 0.0 V or VDD
PSAVE Pull-Up Current 20 μA
Input Capacitance CIN 10 pF
ANALOG OUTPUTS
Output Current 2.0 18.5 mA
Output Compliance Range VOC 0 1.4 V
Output Impedance ROUT 70 kΩ
Output Capacitance COUT 10 pF
Offset Error 0 0 % FSR Tested with DAC output = 0 V
Gain Error3 0 % FSR FSR = 17.62 mA
VOLTAGE REFERENCE (EXTERNAL)
Reference Range VREF 1.12 1.235 1.35 V
VOLTAGE REFERENCE (INTERNAL)
Reference Range VREF 1.235 V
POWER DISSIPATION
Supply Current
Digital4 1 2 mA fCLK = 50 MHz
2.5 4.5 mA fCLK = 140 MHz
4 6 mA fCLK = 240 MHz
Analog 22 25 mA RSET = 560 Ω
5 mA RSET = 4933 Ω
Standby 2.6 3 mA
PSAVE = low, digital and control inputs at VDD
PDOWN 20 μA
Power Supply Rejection Ratio PSRR 0.1 0.5 %/%
1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz and 0°C to 70°C at 240 MHz.
2 These maximum/minimum specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range.
3 Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = VREF/RSET × K × (0x3FF) and K = 7.9896.
4 The digital supply is measured with a continuous clock, with data input corresponding to a ramp pattern, and with an input level at 0 V and VDD.
Data Sheet ADV7127
Rev. A | Page 5 of 18
5 V TIMING SPECIFICATIONS
VAA = 5 V ± 5%,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted. TJ MAX = 110°C.
Table 3.
Parameter3 Symbol Min Typ Max Unit Test Conditions/Comments
ANALOG OUTPUTS
Delay t6 5.5 ns
Rise/Fall Time4 t7 1.0 ns
Transition Time5 t8 15 ns
Skew6 t9 1 2 ns Not shown in Figure 2
CLOCK CONTROL7
fCLK 0.5 50 MHz 50 MHz grade
0.5 140 MHz 140 MHz grade
0.5
240
MHz
240 MHz grade
Data and Control
Setup t1 1.5 ns
Hold t2 2.5 ns
Clock Pulse Width
High t4 1.875 1.1 ns fMAX = 240 MHz
2.85 ns fMAX = 140 MHz
8.0 ns fMAX = 50 MHz
Low t5 1.875 1.25 ns fMAX = 240 MHz
2.85 ns fMAX = 140 MHz
8.0 ns fMAX = 50 MHz
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles Not shown in Figure 2
Up Time
PSAVE6 t10 2 10 ns Not shown in Figure 2
PDOWN t11 320 ns Not shown in Figure 2
1 Maximum and minimum specifications are guaranteed over this range in Table 3.
2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz.
3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.
4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, and fall time from the 90% to 10% point of a full-scale transition.
5 Measured from 50% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified in Table 3 are guaranteed by characterization.
ADV7127 Data Sheet
Rev. A | Page 6 of 18
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V to 3.6 V,1 VREF = 1.235 V, RSET = 560 Ω. All specifications TMIN to TMAX,2 unless otherwise noted. TJ MAX = 110°C.
Table 4.
Parameter3 Symbol Min Typ Max Unit Test Conditions/Comments
ANALOG OUTPUTS
Delay t6 7.5 ns
Rise/Fall Time4 t7 1.0 ns
Transition Time5 t8 15 ns
Skew6 t9 1 2 ns Not shown in Figure 2
CLOCK CONTROL7
fCLK 50 MHz 50 MHz grade
140 MHz 140 MHz grade
240
MHz
240 MHz grade
Data and Control
Setup6 t1 1.5 ns
Hold6 t2 2.5 ns
Clock Period6 t3 2.5 ns fMAX = 240 MHz
Clock Pulse Width
High t4 1.1 ns fMAX = 240 MHz
t46 2.85 ns fMAX = 140 MHz
t46 8.0 ns fMAX = 50 MHz
Low6 t5 1.4 ns fMAX = 240 MHz
t5 2.85 ns fMAX = 140 MHz
t5 8.0 ns fMAX = 50 MHz
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles Not shown in Figure 2
Up Time
PSAVE6 t10 4 10 ns Not shown in Figure 2
PDOWN t11 320 ns Not shown in Figure 2
1 The values stated in Table 4 were obtained using VAA in the range of 3.0 V to 3.6 V.
2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz.
3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.
4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, and fall time from the 90% to 10% point of a full-scale transition.
5 Measured from 50% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 125 MHz and 3.3 V. Limits specified in Table 4 are guaranteed by characterization.
CLOCK
DATA
t4t5
t7
t8
NOTES
1. O UTPUT DELAY (t6) MEAS URE D FRO M THE 50% POI NT O F T HE RISING
EDGE OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (t7) MEASURE D BE TW E E N THE 10% AND
90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (t8) MEASURED FRO M THE 50% P OI NT O F F ULL - S CALE
TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
t2
DIGITAL INPUTS
D9 TO D0
t3
t1
t6
ANALOG OUTPUTS
IOUT, IOUT
14959-002
Figure 2. Timing Diagram
Data Sheet ADV7127
Rev. A | Page 7 of 18
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
VAA to GND 7 V
Voltage on Any Digital Pin
GND − 0.5 V to V
AA
+ 0.5 V
Ambient Operating Temperature Range
(TA)
−40°C to +85°C
Storage Temperature Range(TS) −65°C to +150°C
Junction Temperature (TJ) 150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase Soldering (1 Minute)
220°C
IOUT to GND1 0 V to VAA
1 Analog output short circuit to any power supply or common can be of an
indefinite duration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
ADV7127 Data Sheet
Rev. A | Page 8 of 18
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DNC
CLOCK
GND
GND
V
AA
D0
PSAVE
R
SET
V
REF
I
OUT
COMP
I
OUT
DNC
PDOWN
D8
D7
D6
V
AA
D1
D2
D5
D4
D3
D9
14959-003
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
19
18
17
16
15
14
1312
11
DNC = DO NOT CONNECT
ADV7127
(Not to Scale)
TOP VIEW
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 9,
24
D0 to D9 Data Inputs (TTL-Compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit.
Unused data inputs are connected to either the regular printed circuit board (PCB) power or ground plane. Data
inputs are red, green, or blue pixel inputs.
10, 17 VAA Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7127 must be connected.
11 PDOWN Power-Down Control Pin. The ADV7127 completely powers down, including the voltage reference circuit, when
PDOWN is low.
12, 13 DNC Do Not Connect. Do not connect to these pins.
14 CLOCK
Clock Input (TTL-Compatible). The rising edge of CLOCK latches D0 to D9 where D0 to D9 can be red, green, or
blue pixel data inputs (TTL-compatible). CLOCK is typically the pixel clock rate of the video system. CLOCK is driven
by a dedicated TTL buffer.
15, 16 GND Ground. All GND pins must be connected.
18 IOUT Differential Current Output. This pin is capable of directly driving a doubly terminated 75 Ω load. If not required,
this output is tied to ground.
19 IOUT Current Output. This high impedance current source is capable of directly driving a doubly terminated 75 Ω coaxial
cable.
20 COMP
Compensation Pin. COMP is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and VAA.
21 VREF Voltage Reference Input. An external 1.23 V voltage reference must be connected to this pin. The use of an external
resistor divider network is not recommended. A 0.1 μF decoupling ceramic capacitor is connected between VREF
and VAA.
22 RSET Full-Scale Adjust Control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-
scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The
relationship between RSET and the full-scale output current on IOUT is given by IOUT (mA) = 7968 × VREF (V)/RSET (Ω).
23 PSAVE Power Save Control Pin. The device is put into standby mode when PSAVE is low. The internal voltage reference
circuit is still active.
Data Sheet ADV7127
Rev. A | Page 9 of 18
TYPICAL PERFORMANCE CHARACTERISTICS
5 V
VAA = 5 V, V REF = 1.235 V, IOUT = 17.62 µA, 50 Ω doubly terminated load, differential output loading, TA = 25°C, unless otherwise noted.
OUT P UT F RE QUENCY (MHz)
70
0100.000.10 1.00 2.51 5.04 20.20 40.40
60
50
40
20
10
30
SFDR (dBc)
14959-005
SFDR (SINGLE-ENDED)
SFDR (DIFFERENTIAL)
Figure 4. SFDR vs. Output Frequency (fOUT) at fCLOCK = 140 MHz (Single-Ended
and Differential)
OUT P UT F RE QUENCY (MHz) 100.000.10 1.00 2.51 5.04 20.20 40.40
80
0
70
40
30
20
10
60
50
SFDR (SINGLE-ENDED)
SFDR (DIFFERENTIAL)
SFDR (dBc)
14959-006
Figure 5. SFDR vs. Output Frequency (fOUT) at fCLOCK = 50 MHz (Single-Ended
and Differential)
TEMPERATURE ( °C)
72.0
71.8
70.4
71.2
71.0
70.8
70.6
71.6
71.4
72.2
SF DR ( dBc)
14959-007
Figure 6. SFDR vs. Temperature at fCLOCK = 50 MHz (fOUT = 1 MHz)
fCLOCK (MHz)
76
74
58 160050 100 140
68
64
62
60
72
70
66
FOURTH HARM ONI C
SECO ND HARMONIC
THIRD HARMO NIC
THD ( dBc)
14959-008
Figure 7. THD vs. fCLOCK at fOUT = 2 MHz (Second, Third, and Fourth Harmonics)
I
OUT
(mA)
1.0
0.9
020.00017.622.00
0.4
0.3
0.2
0.1
0.6
0.5
0.8
0.7
LINEARITY (LS Bs)
14959-009
Figure 8. Linearity vs. IOUT
1.0
0.5
–1.0
0
–0.5
CODE ( INL)
1023
0.75
–0.16
ERROR (LS B)
14959-010
Figure 9. Error vs. Code
ADV7127 Data Sheet
Rev. A | Page 10 of 18
VAA = 5V
1
2
–5
–45
–85 0kHz
START 35.0MHz 70.0MHz
STOP
SF DR ( dBm)
14959-011
Figure 10. Single Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 2 MHz)
–5
–45
–85 0kHz
START 35.0MHz 70.0MHz
STOP
SFDR (dBm)
1
2
VAA = 5V
14959-012
Figure 11. Single Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 20 MHz)
0kHz
START 35.0MHz 70.0MHz
STOP
V
AA
= 5V
1
–5
–45
–85
SF DR ( dBc)
14959-013
Figure 12. Dual Tone SFDR at fCLOCK = 140 MHz
(fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz)
Data Sheet ADV7127
Rev. A | Page 11 of 18
3.3 V
VAA = 3 V, VREF = 1.235 V, IOUT = 17.62 µA, 50 Ω doubly terminated load, differential output loading, TA = 25°C, unless otherwise noted.
OUTPUT FREQUENCY (MHz)
70
02.51 5.04 20.20 40.40 100.000.10
60
50
40
20
10
30
SFDR (SINGLE-ENDED)
SFDR (DIFFERENTIAL)
SFDR (dBc)
14959-014
Figure 13. SFDR vs. Output Frequency (fOUT) at fCLOCK = 140 MHz (Single-Ended
and Differential)
OUTPUT FREQUENCY (MHz)
80
70
02.51 5.04 20.20 40.40 100.000.10
0.1
60
50
40
20
10
30
SFDR (dBc)
14959-015
SFDR (SINGLE-ENDED)
SFDR (DIFFERENTIAL)
Figure 14. SFDR vs. Output Frequency (fOUT) at fCLOCK = 50 MHz (Single-Ended
and Differential)
TEMPERATURE (°C)
72.0
71.8
70.4 0
71.2
71.0
70.8
70.6
71.6
71.4
SF DR ( dBc)
1651458520
14959-016
Figure 15. SFDR vs. Temperature at fCLOCK = 50 MHz, (fOUT = 1 MHz)
OUTPUT FREQUENCY (MHz)
76
74
56 160050 100 140
68
62
60
58
72
70
64
66
FOURTH HARMONIC
THIRD HARMONIC
SECO ND HARM ONI C
THD ( dBc)
14959-017
Figure 16. THD vs. fCLOCK at Output Frequency
fOUT = 2 MHz (Second, Third, and Fourth Harmonics)
I
OUT
(mA)
1.0
0.9
020.00
017.622.00
0.4
0.3
0.2
0.1
0.6
0.5
0.8
0.7
LINEARITY (LS Bs)
14959-018
Figure 17. Linearity vs. IOUT
1.0
0.5
0
–0.5
0.75
1023
–0.42
ERROR (LS B)
–1.0 CODE (INL )
14959-019
Figure 18. Error vs. Code
ADV7127 Data Sheet
Rev. A | Page 12 of 18
V
AA
= 3.3V
1
–5
–45
–85 0kHz
START 35.0MHz 70.0MHz
STOP
SF DR ( dBm)
2
14959-020
Figure 19. Single Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 2 MHz)
0kHz
START 35.0MHz 70.0MHz
STOP
V
AA
= 3.3V
1
–5
–45
–85
SF DR ( dBm)
2
14959-021
Figure 20. Single Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 20 MHz)
V
AA
= 3.3V
1
–5
–45
–85
SFDR (dBm)
2
0kHz
START 35.0MHz 70.0MHz
STOP
14959-022
Figure 21. Dual Tone SFDR at fCLOCK = 140 MHz
(fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz)
Data Sheet ADV7127
Rev. A | Page 13 of 18
TERMINOLOGY
Color Video (RGB)
Color video (RGB) usually refers to the technique of combining
the three primary colors of red, green, and blue to produce color
pictures within the usual spectrum. In RGB monitors, three DACs
are required, one for each color.
Gray Scale
Gray scale is the discrete levels of video signal between the
reference black and reference white levels. A 10-bit DAC
contains 1024 different levels, whereas an 8-bit DAC contains 256.
Raster Scan
Raster scan is the most basic method of sweeping a CRT one
line at a time to generate and display images.
Reference Black Level
Reference black level is the maximum negative polarity
amplitude of the video signal.
Reference White Level
Reference white level is the maximum positive polarity
amplitude of the video signal.
Video Signal
Video signal is the portion of the composite video signal that varies
in gray scale levels between reference white and reference black.
It is also referred to as the picture signal, which is the portion
that can be visually observed.
ADV7127 Data Sheet
Rev. A | Page 14 of 18
THEORY OF OPERATION
The ADV7127 contains one 10-bit DAC, with one input
channel containing a 10-bit register. A reference amplifier is
also integrated on board the device.
DIGITAL INPUTS
Ten bits of data (color information), D0 to D9, are latched into
the device on the rising edge of each clock cycle. This data is
presented to the 10-bit DAC and is then converted to an analog
output waveform (see Figure 22).
CLOCK
DATA
ANALOG OUTPUTS
I
OUT
, I
OUT
DIGITAL INPUTS
D0 TO D9
14959-023
Figure 22. Video Data Input/Output
All of these digital inputs are specified to accept TTL logic levels.
CLOCK INPUT
The CLOCK input of the ADV7127 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and therefore the required CLOCK frequency, is determined by
the onscreen resolution, according to the following equation:
Dot Rate = (Horizontal Resolution × Vertical Resolution ×
Refresh Rate)/Retrace Factor
where:
Horizontal Resolution is the number of pixels per line.
Ver tical Resolution is the number of lines per frame.
Refresh Rate is the horizontal scan rate at which the screen must
be refreshed, typically 60 Hz for a noninterlaced system or
30 Hz for an interlaced system.
Retrace Factor is the total blank time factor, which takes into
account that the display is blanked for a certain fraction of the
total duration of each frame (for example, 0.8).
If there is a graphics system with a 1024 × 1024 resolution, a
noninterlaced 60 Hz refresh rate, and a retrace factor of 0.8, then
Dot Rate = (1024 × 1024 × 60)/0.8 = 78.6 MHz
The required CLOCK frequency is 78.6 MHz.
All video data and control inputs are latched into the ADV7127 on
the rising edge of CLOCK, as previously described in the Digital
Inputs section. It is recommended that the CLOCK input to the
ADV7127 be driven by a TTL buffer (for example, 74F244).
I
OUT
mA V
17.61 0.66
0 0 BLACK
LEVEL
WHITE
LEVEL
100 IRE
14959-024
Figure 23. IOUT RS-343A Video Output Waveform
Table 7. Video Output Truth Table (RSET = 560 Ω, RLOAD =
37.5 Ω)
Description Data IOUT (Ω) IOUT (Ω) DAC Input
White Level 17.62 0 0x3FF
Video Video 17.62 − Video Data
Black Level 0 17.62 0x000
REFERENCE INPUT
The ADV7127 has an on-board voltage reference. The VREF pin
is normally terminated to VAA through a 0.1 µF capacitor.
Alternatively, the device can, if required, be overdriven by an
external 1.23 V reference (AD1580).
A resistance RSET connected between the RSET pin and the GND
pin determines the amplitude of the output video level according to
the following equation:
IOUT (mA) = (7968 × VREF (V))/RSET (Ω)
Using a variable value of RSET allows accurate adjustment of the
analog output video levels. Use of a fixed 560 Ω RSET resistor
yields the analog output levels quoted in Specifications section.
These values typically correspond to the RS-343A video
waveform values shown in Figure 23.
DIGITAL-TO-ANALOG CONVERTER
The ADV7127 contains a 10-bit DAC. The DAC is designed using
an advanced, high speed, segmented architecture. The bit currents
corresponding to each digital input are routed to either the analog
output (bit = 1) or GND (bit = 0) by a sophisticated decoding
scheme. The use of identical current sources in a monolithic design
guarantees monotonicity and low glitch. The on-board operational
amplifier stabilizes the full-scale output current against temperature
and power supply variations.
Data Sheet ADV7127
Rev. A | Page 15 of 18
ANALOG OUTPUT
The analog output of the ADV7127 is a high impedance current
source. The current output is capable of directly driving a 37.5 Ω
load, such as a doubly terminated 75 Ω coaxial cable. Figure 24
shows the required configuration for the output connected into
a doubly terminated 75 Ω load. This arrangement develops
RS-343A video output voltage levels across a 75 Ω monitor.
I
OUT
Z
O
= 75Ω
(CABLE)
Z
S
= 75Ω
(SOURCE
TERMINATION)
Z
L
= 75Ω
(MONITOR)
DAC
14959-025
Figure 24. Analog Output Termination for RS-343A
A suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 25. The output current level of the
DAC remains unchanged, but the source termination resistance,
ZS, on the DAC is increased from 75 Ω to 150 Ω.
I
OUT
Z
O
= 75Ω
(CABLE)
Z
S
= 150Ω
(SOURCE
TERMINATION)
Z
L
= 75Ω
(MONITOR)
DAC
14959-026
Figure 25. Analog Output Termination for RS-170
More detailed information regarding load terminations for
various output configurations, including RS-343A and RS-170,
is available in the AN-205 Application Note, Video Formats and
Required Load Terminations.
Figure 23 shows the video waveforms associated with the
current output driving the doubly terminated 75 Ω load of
Figure 24.
GRAY SCALE OPERATION
The ADV7127 can be used for standalone, gray scale (mono-
chrome), or composite video applications (that is, only one
channel used for video information).
VIDEO OUTPUT BUFFER
The ADV7127 is specified to drive transmission line loads, which is
what most monitors are rated as. The analog output configurations
to drive such loads are shown in Figure 26. However, in some
applications, it may be required to drive long transmission line
cable lengths. Cable lengths greater than 10 meters can attenuate
and distort high frequency analog output pulses. The inclusion of
the output buffers compensates for some cable distortion. Buffers
with large full power bandwidths and gains between two and four
are required. These buffers need to be able to supply sufficient
current over the complete output voltage swing. Analog Devices,
Inc., produces a range of suitable op amps for such applications.
These include the AD843/AD844/AD847 series of monolithic op
amps. In very high frequency applications (80 MHz), the AD8061
is recommended. More information on line driver buffering
circuits is given in the relevant op amp data sheets.
Use of buffer amplifiers also allows implementation of other video
standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit results in any desired video level.
AD848
0.1µF
I
OUT
Z
1
Z
2
Z
O
= 75Ω
(CABLE)
Z
S
= 75Ω
(SOURCE
TERMINATION)
Z
L
= 75Ω
(MONITOR)
DAC
75Ω
–V
S
+V
S
0.1µF
GAIN (G) = 1 + Z
1
Z
2
14959-027
Figure 26. AD848 As an Output Buffer
ADV7127 Data Sheet
Rev. A | Page 16 of 18
PCB LAYOUT CONSIDERATIONS
The ADV7127 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7127, it is imperative
that great care be given to the PCB layout. Figure 27 shows a
recommended connection diagram for the ADV7127.
The PCB layout is optimized for lowest noise on the ADV7127
power and ground lines. Radiated and conducted noise can be
achieved by shielding the digital inputs and providing good
decoupling. The lead length between groups of VAA and GND
pins is minimized to inductive ringing.
GROUND PLANES
The ADV7127 and associated analog circuitry have a separate
ground plane referred to as the analog ground plane. This
ground plane connects to the regular PCB ground plane at a
single point through a ferrite bead, as illustrated in Figure 27.
The ferrite bead is located as close as possible (within 3 inches)
to the ADV7127.
The analog ground plane encompasses all ADV7127 ground
pins, voltage reference circuitry, power supply bypass circuitry,
the analog output traces, and any output amplifiers. The regular
PCB ground plane area encompasses all the digital signal traces,
excluding the ground pins, leading up to the ADV7127.
POWER PLANES
The PCB layout has two distinct power planes: one for analog
circuitry and one for digital circuitry. The analog power plane
encompasses the ADV7127 (VAA) and all associated analog
circuitry. This power plane is connected to the regular PCB
power plane (VCC) at a single point through a ferrite bead, as
illustrated in Figure 27. This bead is located within 3 inches of
the ADV7127.
The PCB power plane provides power to all digital logic on the
PCB, and the analog power plane provides power to all
ADV7127 power pins, voltage reference circuitry, and any
output amplifiers. The PCB power and ground planes do not
overlay portions of the analog power plane. Keeping the PCB
power and ground planes from overlaying the analog power
plane contributes to a reduction in plane to plane noise
coupling.
SUPPLY DECOUPLING
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors (see Figure 27).
Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of the two groups of VAA is individually
decoupled to ground. The VAA pins (Pin 10 and Pin 17) must be
decoupled with capacitors to GND. Decouple the pins by
placing the capacitors as close as possible to the device with the
capacitor leads as short as possible between the VAA and GND
pins, thus minimizing lead inductance.
It is important to note that while the ADV7127 contains
circuitry to reject power supply noise, this rejection decreases
with frequency. If a high frequency switching power supply is
used, the designer must pay close attention to reducing power
supply noise. A dc power supply filter (Murata BNX002)
provides an electromagnetic interface (EMI) suppression
between the switching power supply and the main PCB.
Alternatively, consider using a 3-terminal voltage regulator.
DIGITAL SIGNAL INTERCONNECT
The digital signal lines to the ADV7127 must be isolated as
much as possible from the analog outputs and other analog
circuitry. Digital signal lines must not overlay the analog power
plane.
Due to the high clock rates used, long clock lines to the
ADV7127 must be avoided to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
are connected to the regular PCB power plane (VCC) and not the
analog power plane.
ANALOG SIGNAL INTERCONNECT
The ADV7127 is located as close as possible to the output
connectors, which minimizes noise pickup and reflections due
to impedance mismatch.
The video output signals overlay the ground plane and not the
analog power plane, thereby maximizing the high frequency
power supply rejection.
For optimum performance, the analog outputs each have a
source termination resistance to ground of 75 Ω (doubly
terminated 75 Ω configuration). This termination resistance
must be as close as possible to the ADV7127 to minimize
reflections.
Additional information on PCB design is available in the
AN-333 Application Note, Design and Layout of a Video
Graphics System for Reduced EMI.
Data Sheet ADV7127
Rev. A | Page 17 of 18
GND
R
SET
I
OUT
GROUND
ADV7127
C3
0.1µF
C5
0.1µF
R1
75Ω
C1
33µF
C2
10µF
COMP
C6
0.1µF ANALOG POWER PLANE
L2 (FERRITE BEAD)
D0
D9
CLOCK
VIDEO
DATA
INPUTS ANALOG GROUND PLANE
C4
0.1µF L1 (FERRITE BEAD)
V
AA
V
REF
+5V (V
CC
)
R
SET
560Ω
COMPONENT DESCRIPTION VENDOR PART NUMBER
C1 33µF TANTALUM CAPACITOR
C2 10µF TANTALUM
C3, C4, C5, C6 0.1µF CERAMIC CAPACITOR
L1, L2 FERRITE BEAD FAIR-RITE 274300111 OR MURATA BL01/02/03
R1 75Ω 1% METAL FILM RESISTOR
R
SET
560Ω 1% METAL FILM RESISTOR
DALE CMF-55C
DALE CMF-55C
VIDEO
OUTPUT
PSAVE
PDOWN
14959-028
Figure 27. Typical Connection Diagram and Component List
ADV7127 Data Sheet
Rev. A | Page 18 of 18
OUTLINE DIMENSIONS
24 13
121
6.40 BSC
4.50
4.40
4.30
PIN 1
7.90
7.80
7.70
0.15
0.05
0.30
0.19
0.65
BSC 1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 28. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Speed
Options Temperature Range Package Description Package Option
ADV7127JRUZ240 240 MHz 0°C to 70°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
ADV7127KRUZ50 50 MHz −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
ADV7127KRUZ50-REEL 50 MHz −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
ADV7127KRUZ140 140 MHz −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
ADV7127KRU50 50 MHz −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
ADV7127KRU50-REEL 50 MHz −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
ADV7127KRU140 140 MHz −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
1 Z = RoHS Compliant Part.
©1998–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14959-0-1/17(A)
