© Semiconductor Components Industries, LLC, 2012
June, 2012 − Rev. 6
1Publication Order Number:
NB7L14M/D
NB7L14M
2.5V/3.3V Differential 1:4
Clock/Data Fanout Buffer/
Translator with CML
Outputs and Internal
Termination
Description
The NB7L14M is a differential 1−to−4 clock/data distribution chip
with internal source terminated CML output structures, optimized for
minimal skew and jitter. Device produces four identical output copies
of clock or data operating up to 8 GHz or 12 Gb/s, respectively. As
such, NB7L14M is ideal for SONET, GigE, Fiber Channel, Backplane
and other clock/data distribution applications.
Inputs incorporate internal 50 W termination resistors and accept
LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6).
Differential 16 mA CML outputs provide matching internal 50 W
terminations, and 400 mV output swings when externally terminated
with 50 W to VCC (See Figure 14).
The device is offered in a low profile 3x3 mm 16−pin QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
•Maximum Input Clock Frequency up to 8 GHz Typical
•Maximum Input Data Rate up to 12 Gb/s Typical
•< 0.5 ps of RMS Clock Jitter
•< 10 ps of Data Dependent Jitter
•30 ps Typical Rise and Fall Times
•110 ps Typical Propagation Delay
•6 ps Typical Within Device Skew
•Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
•CML Output Level (400 mV Peak−to−Peak Output) Differential
Output Only
•50 W Internal Input and Output Termination Resistors
•Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
•These are Pb−Free Devices
Figure 1. Logic Diagram
50 W
50 W
VTCLK
CLK
CLK
VTCLK
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
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*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
QFN−16
MN SUFFIX
CASE 485G
16
NB7L
14M
ALYWG
G
1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
1
NB7L14M
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2
VEE Q3 Q3 VCC
VEE Q0 Q0 VCC
Q1
Q1
Q2
Q2
VTCLK
CLK
CLK
VTCLK
5678
16 15 14 13
12
11
10
9
1
2
3
4
NB7L14M
Exposed Pad (EP)
Figure 2. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 VTCLK −Internal 50 W Termination Pin for CLK.
2 CLK LVPECL, CML,
LVCMOS, LVTTL,
LVDS
Inverted Differential Clock/Data Input. (Note 1)
3 CLK LVPECL, CML,
LVCMOS, LVTTL,
LVDS
Non−inverted Differential Clock/Data Input. (Note 1)
4 VTCLK −Internal 50 W Termination Pin for CLK.
5,16 VEE Power Supply Negative Supply Voltage. All VEE pins must be externally connected to a Power Supply to
guarantee proper operation.
6 Q3 CML Output Inverted Differential Output 3 with Internal 50 W Source Termination Resistor. (Note 2)
7 Q3 CML Output Non−inverted Differential Output 3 with Internal 50 W Source Termination Resistor. (Note 2)
8,13 VCC Power Supply Positive Supply Voltage. All VCC pins must be externally connected to a Power Supply to
guarantee proper operation.
9 Q2 CML Output Inverted Differential Output 2 with Internal 50 W Source Termination Resistor. (Note 2)
10 Q2 CML Output Non−inverted Differential Output 2 with Internal 50 W Source Termination Resistor. (Note 2)
11 Q1 CML Output Inverted Differential Output 1 with Internal 50 W Source Termination Resistor. (Note 2)
12 Q1 CML Output Non−inverted Differential Output 1 with Internal 50 W Source Termination Resistor. (Note 2)
14 Q0 CML Output Inverted Differential Output 0 with Internal 50 W Source Termination Resistor. (Note 2)
15 Q0 CML Output Non−inverted Differential Output 0 with Internal 50 W Source Termination Resistor. (Note 2)
−EP −Exposed Pad. Thermal pad on the package bottom must be attached to a heatsinking
conduit to improve heat transfer. It is recommended to connect the EP to the lower
potential (VEE).
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK and CLK, then the device will be susceptible to self−oscillation.
2. CML outputs require 50 W receiver termination resistors to VCC for proper operation.
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Table 2. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 1500 V
> 50 V
> 500 V
Moisture Sensitivity (Note 3) Pb Pkg Pb−Free Pkg
QFN−16 Level 1 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 387
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Units
VCC Positive Power Supply VEE = 0 V 3.6 V
VIInput Voltage VEE = 0 V VEE v VI v VCC 3.6 V
VINPP Differential Input Voltage |CLK − CLK| VCC − VEE w 2.8 V
VCC − VEE < 2.8 V
2.8
|VCC − VEE|
V
V
IIN Input Current Through RT (50 W Resistor) Static
Surge
45
80
mA
mA
Iout Output Current Continuous
Surge
25
50
mA
mA
TAOperating Temperature Range QFN−16 −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient)
(Note 4)
0 lfpm
500 lfpm
QFN−16
QFN−16
42
36
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 4) QFN−16 3 to 4 °C/W
Tsol Wave Solder Pb
Pb−Free
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs (VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = −40°C to +85°C)
(Note 5)
Symbol Characteristic Min Typ Max Unit
ICC Power Supply Current (Inputs and Outputs Open) 140 190 mA
VOH Output HIGH Voltage (Note 6) VCC − 60 VCC − 20 VCC mV
VOL Output LOW Voltage (Note 6) VCC − 530 VCC − 420 VCC − 360 mV
Differential Input Driven Single−Ended (see Figures 10 & 12) (Note 8)
Vth Input Threshold Reference Voltage Range (Note 7) 800 VCC − 75 mV
VIH Single−ended Input HIGH Voltage 1200 VCC mV
VIL Single−ended Input LOW Voltage VEE VCC − 150 mV
VISE Single−Ended Input Voltage (VIH – VIL) 150 2500 mV
Differential Inputs Driven Differentially (see Figures 11 & 13) (Note 9)
VIHCLK Differential Input HIGH Voltage 1200 VCC mV
VILCLK Differential Input LOW Voltage VEE VCC − 75 mV
VCMR Input Common Mode Range (Differential Configuration) (Note 10) 800 VCC – 38 mV
VID Differential Input Voltage (VIHCLK − VILCLK) 75 2500 mV
IIH Input HIGH Current CLK / CLK (VTCLK/VTCLK Open) 0 25 100 mA
IIL Input LOW Current CLK / CLK (VTCLK/VTCLK Open) −10 0 10 mA
RTIN Internal Input Termination Resistor 45 50 55 W
RTOUT Internal Output Termination Resistor 45 50 55 W
RTemp Coef Internal I/O Termination Resistor Temperature Coefficient 6.38 mW/°C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC.
6. CML outputs require 50 W receiver termination resistors to VCC for proper operation.
7. Vth is applied to the complementary input when operating in single−ended mode. Vth = (VIH − VIL)/2.
8. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10.VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input
signal.
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Table 5. AC CHARACTERISTICS (VCC = 2.375 V to 3.465 V, VEE = 0 V; Note 11)
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
VOUTPP Output Voltage Amplitude (@VINPPmin)f
in ≤ 6 GHz
(See Figure 4) fin ≤ 8 GHz
280
125
400
300
280
125
400
300
280
125
400
300
mV
fdata Maximum Operating Data Rate 10 12 10 12 10 12 Gb/s
tPLH,
tPHL
Propagation Delay to Output Differential 70 110 150 70 110 150 70 110 150 ps
tSKEW Duty Cycle Skew (Note 12)
Within−Device Skew
Device−to−Device Skew (Note 13)
2.0
6.0
20
5.0
15
50
2.0
6.0
20
5.0
15
50
2.0
6.0
20
5.0
15
50
ps
tJITTER RMS Random Clock Jitter (Note 14) fin = 6 GHz
fin = 8 GHz
Peak/Peak Data Dependent Jitter fin = 2.488 Gb/s
(Note 15) fdata = 5 Gb/s
fdata = 10 Gb/s
0.2
0.2
2.0
5.0
6.0
0.5
0.5
5.0
8.0
10
0.2
0.2
2.0
5.0
6.0
0.5
0.5
5.0
8.0
10
0.2
0.2
2.0
5.0
6.0
0.5
0.5
5.0
8.0
10
ps
VINPP Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 16)
75 400 2500 75 400 2500 75 400 2500 mV
tr
tf
Output Rise/Fall Times @ 1 GHz Q, Q
(20% − 80%)
30 60 30 60 30 60 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured by forcing VINPP (TYP) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC.
Input edge rates 40 ps (20% − 80%).
12.Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @1 GHz.
13.Device to device skew is measured between outputs under identical transition @ 1 GHz.
14.Additive RMS jitter with 50% duty cycle clock signal at 10 GHz.
15.Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 2^23−1.
16.VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode.
INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) at Ambient Temperature (Typical)
(VINPP = 400 mV)
OUTPUT VOLTAGE AMPLITUDE (mV)
450
300
250
200
150
100
50
0121110987654321
350
400
VCC = 3.3 V
VCC = 2.5 V
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Figure 4. Typical Output Waveform at 2.488 Gb/s
with PRBS 2^23−1 (Vinpp = 75 mV)
Figure 5. Typical Output Waveform at 5 Gb/s
with PRBS 2^23−1 (Vinpp = 75 mV)
Figure 6. Typical Output Waveform at 10.7 Gb/s
with PRBS 2^23−1 (Vinpp = 75 mV)
Figure 7. Typical Output Waveform at 12 Gb/s
with PRBS 2^23−1 (Vinpp = 75 mV)
Time (80 ps/div) Time (40 ps/div)
Time (18 ps/div) Time (18.2 ps/div)
Voltage (50 mV/div)
Voltage (50 mV/div)
Voltage (50 mV/div)
Voltage (50 mV/div)
DDJ = 1.6 ps* DDJ = 2.8 ps**
DDJ = 2 ps*** DDJ = 6 ps***
*Input signal DDJ = 6.4 ps
***Input signal DDJ = 11 ps
**Input signal DDJ = 7.2 ps
***Input signal DDJ = 13 ps
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Figure 8. AC Reference Measurement
CLK
CLK
Q
Q
tPHL
tPLH
VINPP = VIH(CLK) − VIL(CLK)
VOUTPP = VOH(Q) − VOL(Q)
NB7L14M Receiver
Device
Q CLK
Figure 9. Typical Termination for 16 mA Output Driver and Device Evaluation
(Refer to Application Notes AND8020/D and AND8173/D)
Q CLK
VCC
50 W50 W
VCC
50 W50 W
Z = 50 W
Z = 50 W
Figure 10. Differential Input Driven
Single−Ended
Figure 11. Differential Inputs Driven
Differentially
Figure 12. Vth Diagram Figure 13. VCMR Diagram
CLK
VCC
GND
VIH
VIHmin
VIHmax
Vthmax
Vth
Vth
Vthmin VCMmax
VCMmax
CLK
VCMR
VCC
GND
CLK
CLK
Vth
Vth
CLK
CLK
VILmax
VIL
VILmin
CLK
VILCLKmax
VIHCLKmax
V(CLK) = VIHCLK − VILCLK
VILCLKtyp
VIHCLKtyp
VILCLKmin
VIHCLKmin
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Q
Q
VCC
16 mA
50 W50 W
Figure 14. CML Output Structure
VEE
Table 6. INTERFACING OPTIONS
INTERFACING OPTIONS CONNECTIONS
CML Connect VTCLK and VTCLK to VCC
LVDS Connect VTCLK, VTCLK Together for CLK Input
AC−COUPLED Bias VTCLK, VTCLK Inputs within (VCMR) Common Mode Range
RSECL, LVPECL Standard ECL Termination Techniques. See AND8020/D.
LVTTL, LVCMOS An external voltage should be applied to the unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS inputs.
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Application Information
All NB7L14M inputs can accept PECL, CML, LVTTL,
LVCMOS and LVDS signal levels. The limitations for
differential input signal (LVDS, PECL, or CML) are
minimum input swing of 75 mV and the maximum input
swing of 2500 mV. Within these conditions, the input
voltage can range from VCC to 1.2 V. Examples interfaces are
illustrated below in a 50 W environment (Z = 50 W).
50 W
VCC
CLK
CLK
50 WNB7L14M
VCC VTCLK
VEE
VCC
Q
50 W50 W
CML Driver
VEE
Figure 15. CML to CML Interface
Z
Q
Z
Figure 16. PECL to CML Receiver Interface
50 W
Z
Z
VCC VCC
PECL
Driver
CLK
CLK
50 W
NB7L14M
VEE
VBias VTCLK
VEE
RT
RT
VEE
VCC RT
5.0 V 290 W
3.3 V 150 W
2.5 V 80 W
Recommended RT Values
50 W
50 W
VTCLK
VCC
VTCLK
VBias
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50 W
Z
VCC VCC
LVDS
Driver
CLK
CLK
50 W
NB7L14M
VEE
VTCLK
VEE
VTCLK
Z
Figure 17. LVDS to CML Receiver Interface
Figure 18. LVCMOS/LVTTL to CML Receiver Interface
50 W
Z
VCC VCC
LVTTL/
LVCMOS
Driver
CLK
CLK
50 W
NB7L14M
VEE
VTCLK
VCC
VREF
LVCMOS VCC − VEE
2
LVTTL 1.5 V
Recommended VREF Values
VTCLK
VREF
No Connect*
No Connect
*or 60 pF to GND
ORDERING INFORMATION
Device Package Shipping†
NB7L14MMNG QFN−16
(Pb−Free)
123 Units/Rail
NB7L14MMNR2G QFN−16
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE F
ÇÇÇ
ÇÇÇ
ÇÇÇ
16X
SEATING
PLANE
L
D
E
0.10 C
A
A1
e
D2
E2
b
1
4
8
9
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
A
0.10 CTOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN 1
LOCATION
0.05 C
0.05 C
(A3)
C
NOTE 4
16X
0.10 C
0.05 C
A B
NOTE 3
K
16X
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
ÉÉ
ÉÉ
ÇÇ
A1
A3
L
ÉÉÉ
ÉÉÉ
ÉÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
DETAIL A
DETAIL B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
RECOMMENDED
2X
0.50
PITCH
1.84 3.30
1
DIMENSIONS: MILLIMETERS
0.58
16X
2X
0.30
16X
OUTLINE
PACKAGE
2X
2X
0.10 C A B
e/2
SOLDERING FOOTPRINT*
DIM MIN NOM MAX
MILLIMETERS
A0.80 0.90 1.00
A1 0.00 0.03 0.05
A3 0.20 REF
b0.18 0.24 0.30
D3.00 BSC
D2 1.65 1.75 1.85
E3.00 BSC
E2 1.65 1.75 1.85
e0.50 BSC
K0.18 TYP
L0.30 0.40 0.50
L1 0.00 0.08 0.15
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reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NB7L14M/D
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