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automotive, industrial, smart home appliances, consumer electronics and medical products.
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MB90350 Series
F2MC-16LX 16-bit Microcontroller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-07872 Rev. *A Revised May 31, 2017
The MB90350-series with 1 channel FULL-CAN interface and Flash ROM is especially designed for automotive and industrial appli-
cations. Its main feature is the on-board CAN interface, which conforms to V2.0 Part A and Part B, while supporting a very flexible
message buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35μm CMOS technology,
Cypress now offers on-chip Flash-ROM program memory up to 128 Kbytes.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a major advantage in terms
of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external 4 MHz clock. Also,
the clock monitor function can monitor main clock and sub clock independently.
As the peripheral resources, the unit features a 4-channel Output Compare Unit, 6-channel Input Capture Unit, 2 separate 16-bit
freerun timers, 2-channel UART and 15-channel 8/10-bit A/D converter.
Features
Clock
■Built-in PLL clock frequency multiplication circuit
■Selection of machine clocks (PLL clocks) is allowed among
frequency division by two on oscillation clock, and multiplication
of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock,
4 MHz to 24 MHz).
■Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock
divided by two) is allowed. (devices without S-suffix only)
■Minimum execution time of instruction : 42 ns (when operating
with 4-MHz oscillation clock, and 6-time multiplied PLL clock).
■Built-in clock modulation circuit
16 Mbytes CPU memory space
■24-bit internal addressing
Clock monitor function (MB90x356x and MB90x357x
only)
■Main clock or sub clock is monitored independently.
■Internal CR oscillation clock (100 kHz typical) can be used as
sub clock.
Instruction system best suited to controller
■Wide choice of data types (bit, byte, word, and long word)
■Wide choice of addressing modes (23 types)
■Enhanced multiply-divide instructions with sign and RETI
instructions
■Enhanced high-precision computing with 32-bit accumulator
Instruction system compatible with high-level
language (C language) and multitask
■Employing system stack pointer
■Enhanced various pointer indirect instructions
■Barrel shift instructions
Increased processing speed
■4-byte instruction queue
Powerful interrupt function
■Powerful 8-level, 34-condition interrupt feature
■Up to 8 channels external interrupts are supported.
Automatic data transfer function independent of CPU
■Extended intelligent I/O service function (EI2OS) : up to 16
channels
■DMA: up to 16 channels
Low power consumption (standby) mode
■Sleep mode (a mode that halts CPU operating clock)
■Main timer mode (a timebase timer mode switched from the
main clock mode)
■PLL timer mode (a timebase timer mode switched from the PLL
clock mode)
■Watch mode (a mode that operates sub clock and watch timer
only)
■Stop mode (a mode that stops oscillation clock and sub clock)
■CPU intermittent operation mode
Process
■CMOS technology
I/O port
■General-purpose input/output port (CMOS output)
❐49 ports (devices without S-suffix : devices that correspond
to sub clock)
❐51 ports (devices with S-suffix : devices that do not corre-
spond to sub clock)
Document Number: 002-07872 Rev. *A Page 2 of 83
MB90350 Series
Sub clock pin (X0A, X1A)
■Yes (using the external oscillation) : devices without S-suffix
■No (using the sub clock mode at internal CR oscillation) :
devices with S-suffix
Timer
■Timebase timer, watch timer, watchdog timer: 1 channel
■8/16-bit PPG timer: 8-bit × 10 channels or 16-bit × 6 channels
■16-bit reload timer: 4 channels
■16- bit input/output timer
❐16-bit freerun timer : 2 channels (FRT0: ICU0/1, FRT1: ICU
4/5/6/7, OCU 4/5/6/7)
❐16- bit input capture: (ICU): 6 channels
❐16-bit output compare: (OCU): 4 channels
FULL-CAN interface 1 channel
■Compliant with Ver2.0 part A and Ver2.0 part B CAN specifica-
tions
■Flexible message buffering (mailbox and FIFO buffering can
be mixed)
■CAN wake-up function
UART (LIN/SCI): 2 channels
■Equipped with full-duplex double buffer
■Clock-asynchronous or clock-synchronous serial transmission
is available.
I2C interface: 1 channel
■Up to 400 Kbit/s transfer rate
DTP/External interrupt: 8 channels, CAN wakeup: 1
channel
■Module for activation of extended intelligent I/O service
(EI2OS), DMA, and generation of external interrupt by external
input.
Delay interrupt generator module
■Generates interrupt request for task switching.
8/10-bit A/D converter: 15 channels
■Resolution is selectable between 8-bit and 10-bit.
■Activation by external trigger input is allowed.
■Conversion time: 3 μs (at 24-MHz machine clock, including
sampling time)
Program patch function
■Address matching detection for 6 address pointers.
Capable of changing input voltage level for port
■Automotive/CMOS-Schmitt (initial level is Automotive in single
chip mode)
■TTL level (corresponds to external bus pins only, initial level of
these pins is TTL in external bus mode)
Low voltage/CPU operation detection reset (devices
with T-suffix)
■Detects low voltage (4.0 V 0.3 V) and resets automatically
■Resets automatically when program is runaway and counter is
not cleared within interval time (approx. 262 ms : external 4
MHz)
Dual operation flash memory (only flash memory
devices with A-suffix)
■Erase/write and read can be executed in the different bank
(Upper Bank/Lower Bank) at the same time.
Models that support 125 °C
■Devices without A-suffix (excluding evaluation device)
: The maximum operating frequency is 16 MHz
(at TA 125 °C) .
■Devices with A-suffix (excluding evaluation device)
: The maximum operating frequency is 24 MHz
(at TA 125 °C) .
Flash security function
■Protects the content of Flash memory (MB90F352x and
MB90F357x only)
External bus interface
■4 Mbytes external memory space
Document Number: 002-07872 Rev. *A Page 3 of 83
MB90350 Series
Contents
Product Lineup 1 ............................................................. 4
Product Lineup 2 ............................................................. 6
Product Lineup 3 ............................................................. 8
Product Lineup 4 ........................................................... 10
Packages and Product Correspondence ..................... 12
Pin Assignments ............................................................ 13
Pin Description ...............................................................14
I/O Circuit Type ...............................................................18
Handling Devices ............................................................22
Preventing latch-up ...................................................22
Handling unused pins ................................................22
Using external clock ..................................................23
Precautions for when not using a sub clock signal .... 23
Notes on during operation of PLL clock mode .......... 23
Power supply pins (VCC/VSS) ................................. 23
Pull-up/down resistors ............................................... 23
Crystal Oscillator Circuit ............................................23
Turning-on Sequence of Power Supply to
A/D Converter and Analog Inputs .............................. 24
Connection of Unused Pins of A/D Converter if
A/D Converter is not used ......................................... 24
Notes on Energization ...............................................24
Stabilization of power supply voltage ........................ 24
Initialization ................................................................ 24
Port 0 to port 3 output during Power-on
(External-bus mode) .................................................. 24
Notes on using CAN Function ................................... 24
Flash security Function ............................................. 25
Correspondence with TA 105 °C or more ........... 25
Low voltage/CPU operation reset circuit ................... 25
Internal CR oscillation circuit ..................................... 26
Block Diagrams ..............................................................27
Memory Map .................................................................... 31
I/O Map ............................................................................ 32
CAN Controllers .............................................................. 40
Interrupt Factors, Interrupt Vectors,
Interrupt Control Register .............................................. 46
Electrical Characteristics ............................................... 48
Absolute Maximum Ratings ....................................... 48
Recommended Operating Conditions ....................... 50
DC Characteristics .................................................... 51
AC Characteristics ..................................................... 56
A/D Converter ............................................................ 71
Definition of A/D Converter Terms ........................... 74
Flash Memory Program/Erase Characteristics .......... 76
Ordering Information ..................................................... 77
Package Dimensions ...................................................... 79
Major Changes ................................................................ 81
Document History ........................................................... 82
Sales, Solutions, and Legal Information ...................... 83
Document Number: 002-07872 Rev. *A Page 4 of 83
MB90350 Series
1. Product Lineup 1
(Continued)
Part Number
Parameter
MB90F351,
MB90F352
MB90F351S,
MB90F352S
MB90F351A,
MB90F352A
MB90F351TA,
MB90F352TA
MB90F351AS,
MB90F352AS
MB90F351TAS,
MB90F352TAS
CPU F2MC-16LX CPU
System clock On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)
ROM
Flash memory
64Kbytes :MB90F351(S)
128Kbytes :MB90F352(S)
Dual operation flash memory
64Kbytes :MB90F351A(S), MB90F351TA(S)
128Kbytes :MB90F352A(S), MB90F352TA(S)
RAM 4 Kbytes
Emulator-specific power
supply* —
Sub clock pin
(X0A, X1A)
(Max 100 kHz)
Yes No Yes No
Clock monitor
function No
Low voltage/CPU
operation detection
reset
No No Yes No Yes
Operating
voltage range
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter/Flash programming
4.5 V to 5.5 V : at using external bus
Operating
temperature range
40 °C to 105 °C (125 °C up to
16 MHz machine clock) 40 °C to 125 °C
Package LQFP-64
UART
2 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 Kbps) 1 channel
A/D Converter
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
16-bit I/O Timer
(2 channels)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock frequency)
16-bit Output
Compare
4 channels
Signals an interrupt when 16-bit I/O Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
16-bit Input Capture 6 channels
Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.
Document Number: 002-07872 Rev. *A Page 5 of 83
MB90350 Series
(Continued)
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
Part Number
Parameter
MB90F351,
MB90F352
MB90F351S,
MB90F352S
MB90F351A,
MB90F352A
MB90F351TA,
MB90F352TA
MB90F351AS,
MB90F352AS
MB90F351TAS,
MB90F352TAS
8/16-bit
Programmable Pulse
Generator
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters × 12
8-bit reload registers for L pulse width × 12
8-bit reload registers for H pulse width × 12
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 μs@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
CAN Interface
1 channel
Conforms to CAN Specification Version 2.0 Part A and B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID
Supports multiple messages.
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
External Interrupt
8 channels
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
D/A converter —
I/O Ports
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
Bit-wise settable as input/output or peripheral signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
Flash Memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block.
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash (MB90F352x only)
Corresponding EVA
name
MB90V340A-
102
MB90V340A-
101 MB90V340A-102 MB90V340A-101
Document Number: 002-07872 Rev. *A Page 6 of 83
MB90350 Series
2. Product Lineup 2
(Continued)
Part Number
Parameter
MB90351A,
MB90352A
MB90351TA,
MB90352TA
MB90351AS,
MB90352AS
MB90351TAS,
MB90352TAS
MB90V340A-
101
MB90V340A-
102
CPU F2MC-16LX CPU
System clock On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)
ROM
MASK ROM
64Kbytes :MB90351A(S), MB90351TA(S)
128Kbytes :MB90352A(S), MB90352TA(S)
External
RAM 4 Kbytes 30 Kbytes
Emulator-specific power
supply* —Yes
Sub clock pin
(X0A, X1A)
(Max 100 kHz)
Yes No No Yes
Clock monitor
function No
Low voltage/CPU
operation detection
reset
No Yes No Yes No
Operating
voltage range
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter
4.5 V to 5.5 V : at using external bus
5 V 10%
Operating
temperature range 40 °C to 125 °C —
Package LQFP-64 PGA-299
UART
2 channels 5 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 Kbps) 1 channel 2 channels
A/D Converter
15 channels 24 channels
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
16-bit I/O Timer
(2 channels)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
I/O Timer 1 (clock input FRCK1) corresponds to
ICU 4/5/6/7, OCU 4/5/6/7.
I/O Timer 0 corresponds to ICU
0/1/2/3, OCU 0/1/2/3.
I/O Timer 1 corresponds to ICU
4/5/6/7, OCU 4/5/6/7.
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock frequency)
16-bit Output
Compare
4 channels 8 channels
Signals an interrupt when 16-bit I/O Timer matches output compare registers.
A pair of compare registers can be used to generate an output signal.
16-bit Input Capture 6 channels 8 channels
Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.
Document Number: 002-07872 Rev. *A Page 7 of 83
MB90350 Series
(Continued)
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
Part Number
Parameter
MB90351A,
MB90352A
MB90351TA,
MB90352TA
MB90351AS,
MB90352AS
MB90351TAS,
MB90352TAS
MB90V340A-
101
MB90V340A-
102
8/16-bit
Programmable Pulse
Generator
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters × 12
8-bit reload registers for L pulse width × 12
8-bit reload registers for H pulse width × 12
8 channels (16-bit)/
16 channels (8-bit)
8-bit reload counters × 16
8-bit reload registers for
L pulse width × 16
8-bit reload registers for
H pulse width × 16
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 μs@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
CAN Interface
1 channel 3 channels
Conforms to CAN Specification Version 2.0 Part A and B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID
Supports multiple messages.
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
External Interrupt
8 channels 16 channels
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
D/A converter — 2 channels
I/O Ports
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
Bit-wise settable as input/output or peripheral signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
Flash Memory —
Corresponding EVA
name MB90V340A-102 MB90V340A-101 —
Document Number: 002-07872 Rev. *A Page 8 of 83
MB90350 Series
3. Product Lineup 3
(Continued)
Part Number
Parameter
MB90F356A,
MB90F357A
MB90F356TA,
MB90F357TA
MB90F356AS,
MB90F357AS
MB90F356TAS,
MB90F357TAS
CPU F2MC-16LX CPU
System clock On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)
ROM
Dual operation flash memory
64Kbytes :MB90F356A(S), MB90F356TA(S)
128Kbytes :MB90F357A(S), MB90F357TA(S)
RAM 4 Kbytes
Emulator-specific power
supply* —
Sub clock pin
(X0A, X1A) Yes
No
(internal CR oscillation can be used as
sub clock)
Clock monitor
function Yes
Low voltage/CPU
operation detection
reset
No Yes No Yes
Operating
voltage range
3.5 V to 5.5 V : at normal operating (not using A/D converter)
3.5 V to 5.5 V : at using A/D converter/Flash programming
3.5 V to 5.5 V : at using external bus
Operating
temperature range 40 °C to 125 °C
Package LQFP-64
UART
2 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 Kbps) 1 channel
A/D Converter
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
16-bit I/O Timer
(2 channels)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock frequency)
16-bit Output
Compare
4 channels
Signals an interrupt when 16-bit I/O Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
16-bit Input Capture 6 channels
Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.
Document Number: 002-07872 Rev. *A Page 9 of 83
MB90350 Series
(Continued)
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
Part Number
Parameter
MB90F356A,
MB90F357A
MB90F356TA,
MB90F357TA
MB90F356AS,
MB90F357AS
MB90F356TAS,
MB90F357TAS
8/16-bit
Programmable Pulse
Generator
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters × 12
8-bit reload registers for L pulse width × 12
8-bit reload registers for H pulse width × 12
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 μs@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
CAN Interface
1 channel
Conforms to CAN Specification Version 2.0 Part A and B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID
Supports multiple messages.
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
External Interrupt
8 channels
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
D/A converter —
I/O Ports
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
Bit-wise settable as input/output or peripheral module signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
Flash Memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block.
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash (MB90F357x only)
Corresponding EVA
name MB90V340A-104 MB90V340A-103
Document Number: 002-07872 Rev. *A Page 10 of 83
MB90350 Series
4. Product Lineup 4
(Continued)
Part Number
Parameter
MB90356A,
MB90357A
MB90356TA,
MB90357TA
MB90356AS,
MB90357AS
MB90356TAS,
MB90357TAS
MB90V340A-
103
MB90V340A-
104
CPU F2MC-16LX CPU
System clock On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)
ROM
MASK ROM
64Kbytes :MB90356A(S), MB90356TA(S)
128Kbytes :MB90357A(S), MB90357TA(S)
External
RAM 4 Kbytes 30 Kbytes
Emulator-specific power
supply* —Yes
Sub clock pin
(X0A, X1A) Yes
No
(internal CR oscillation can be
used as sub clock)
No
(internal CR
oscillation can
be used as sub
clock)
Yes
Clock monitor
function Yes
Low voltage/CPU
operation detection
reset
No Yes No Yes No
Operating
voltage range
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter
4.5 V to 5.5 V : at using external bus
5 V 10%
Operating
temperature range 40 °C to 125 °C —
Package LQFP-64 PGA-299
UART
2 channels 5 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 Kbps) 1 channel 2 channels
A/D Converter
15 channels 24 channels
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
16-bit I/O Timer
(2 channels)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
I/O Timer 1 (clock input FRCK1) corresponds to
ICU 4/5/6/7, OCU 4/5/6/7.
I/O Timer 0 corresponds to ICU
0/1/2/3, OCU 0/1/2/3.
I/O Timer 1 corresponds to ICU
4/5/6/7, OCU 4/5/6/7.
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock frequency)
16-bit Output
Compare
4 channels 8 channels
Signals an interrupt when 16-bit I/O Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
Document Number: 002-07872 Rev. *A Page 11 of 83
MB90350 Series
(Continued)
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
Part Number
Parameter
MB90356A,
MB90357A
MB90356TA,
MB90357TA
MB90356AS,
MB90357AS
MB90356TAS,
MB90357TAS
MB90V340A-
103
MB90V340A-
104
16-bit Input Capture 6 channels 8 channels
Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.
8/16-bit
Programmable Pulse
Generator
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters × 12
8-bit reload registers for L pulse width × 12
8-bit reload registers for H pulse width × 12
8 channels (16-bit)/16 channels
(8-bit)
8-bit reload counters × 16
8-bit reload registers for
L pulse width × 16
8-bit reload registers for
H pulse width × 16
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 μs@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
CAN Interface
1 channel 3 channels
Conforms to CAN Specification Version 2.0 Part A and B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID
Supports multiple messages.
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
External Interrupt
8 channels 16 channels
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
D/A converter — 2 channels
I/O Ports
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
Bit-wise settable as input/output or peripheral module signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
Flash Memory —
Corresponding EVA
name MB90V340A-104 MB90V340A-103 —
Document Number: 002-07872 Rev. *A Page 12 of 83
MB90350 Series
5. Packages and Product Correspondence
* : This device is under development.
: Yes, × : No
Note : Refer to “Package Dimensions” for detail of each package.
Package
MB90V340A
-101
-102
-103
-104
MB90F351
MB90F351S
MB90F352
MB90F352S
MB90F351A (S) , MB90F351TA (S)
MB90F352A (S) , MB90F352TA (S)
MB90F356A (S) , MB90F356TA (S)
MB90F357A (S) , MB90F357TA (S)
MB90351A (S) , MB90351TA (S)
MB90352A (S) , MB90352TA (S)
MB90356A (S) , MB90356TA (S)
MB90357A (S) , MB90357TA (S)
PGA-299C-A01 × ×
FPT-64P-M23
(12 mm , 0.65 mm pitch) ×
FPT-64P-M24
(10 mm , 0.50 mm pitch) × × *
Document Number: 002-07872 Rev. *A Page 13 of 83
MB90350 Series
6. Pin Assignments
■MB90F351(S), MB90F352(S),MB90F351A(S), MB90F351TA(S), MB90F352A(S), MB90F352TA(S),
MB90F356A(S), MB90F356TA(S), MB90F357A(S), MB90F357TA(S),MB90351A(S), MB90351TA(S),
MB90352A(S), MB90352TA(S),MB90356A(S), MB90356TA(S), MB90357A(S), MB90357TA(S),
(TOP VIEW)
(LQFP-64P)
(FPT-64P-M23, FPT-64P-M24)
* : Devices without S-suffix : X0A, X1A
Devices with S-suffix : P40, P41
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVcc
P61/AN1
P60/AN0
P37/CLK/OUT7
P36/RDY/OUT6
P35/HAK/OUT5
P34/HRQ/OUT4
P32/WRL/WR/INT10R
P31/RD/IN5
P30/ALE/IN4
P45/SCL0/FRCK1
P44/SDA0/FRCK0
P25/A21/IN1/ADTG
C
Vcc
P33/WRH
10 11 12 13 14 15 161234567 98
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/INT13
P04/AD04/INT12
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
MD0
MD1
MD2
P41/X1A*
P40/X0A*
Vss
P43/IN7/TX1
Vss
X0
X1
RST
P24/A20/IN0
P23/A19/PPGF(E)
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P20/A16/PPG9(8)
P17/AD15
P16/AD14
P15/AD13
P14/AD12/SCK3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P11/AD09/TOT1
AVss
AVRH
P64/AN4/PPG8(9)
P65/AN5/PPGA(B)
P66/AN6/PPGC(D)
P67/AN7/PPGE(F)
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
P56/AN14
P55/AN13
P54/AN12/TOT3
P62/AN2/PPG4(5)
P63/AN3/PPG6(7)
P42/IN6/RX1/INT9R
Document Number: 002-07872 Rev. *A Page 14 of 83
MB90350 Series
7. Pin Description
(Continued)
Pin No. Pin name Circuit
type Function
LQFP64*
46 X1 AOscillation output pin
47 X0 Oscillation input pin
45 RST E Reset input pin
3 to 8
P62 to P67
I
General purpose I/O ports
AN2 to AN7 Analog input pins for A/D converter
PPG4 (5) , 6 (7) , 8
(9) , A (B) , C (D) , E
(F)
Output pins for PPGs
9
P50
O
General purpose I/O port
AN8 Analog input pin for A/D converter
SIN2 Serial data input pin for UART2
10
P51
I
General purpose I/O port
AN9 Analog input pin for A/D converter
SOT2 Serial data output pin for UART2
11
P52
I
General purpose I/O port
AN10 Analog input pin for A/D converter
SCK2 Serial clock I/O pin for UART2
12
P53
I
General purpose I/O port
AN11 Analog input pin for A/D converter
TIN3 Event input pin for reload timer3
13
P54
I
General purpose I/O port
AN12 Analog input pin for A/D converter
TOT3 Output pin for reload timer3
14, 15 P55, P56 IGeneral purpose I/O ports
AN13, AN14 Analog input pins for A/D converter
16
P42
F
General purpose I/O port
IN6 Data sample input pin for input capture ICU6
RX1 RX input pin for CAN1
INT9R External interrupt request input pin for INT9
17
P43
F
General purpose I/O port
IN7 Data sample input pin for input capture ICU7
TX1 TX output pin for CAN1
19, 20
P40, P41 F General purpose I/O ports
(devices with S-suffix and MB90V340A-101/103)
X0A, X1A B
X0A : Oscillation input pins for sub clock
X1A : Oscillation output pins for sub clock
(devices without S-suffix and MB90V340A-102/104)
24 to 31
P00 to P07
G
General purpose I/O ports. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
AD00 to AD07 Input/output pins of external address data bus lower 8 bits. This function is enabled
when the external bus is enabled.
INT8 to INT15 External interrupt request input pins for INT8 to INT15
Document Number: 002-07872 Rev. *A Page 15 of 83
MB90350 Series
(Continued)
Pin No. Pin name Circuit
type Function
LQFP64*
32
P10
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
AD08 Input/output pin for external bus address data bus bit 8.
This function is enabled when external bus is enabled.
TIN1 Event input pin for reload timer1
33
P11
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
AD09 Input/output pin for external bus address data bus bit 9. This function is enabled when
external bus is enabled.
TOT1 Output pin for reload timer1
34
P12
N
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
AD10 Input/output pin for external bus address data bus bit 10. This function is enabled when
external bus is enabled.
SIN3 Serial data input pin for UART3
INT11R External interrupt request input pin for INT11
35
P13
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
AD11 Input/output pin for external bus address data bus bit 11.
This function is enabled when external bus is enabled.
SOT3 Serial data output pin for UART3
36
P14
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
AD12 Input/output pin for external bus address data bus bit 12.
This function is enabled when external bus is enabled.
SCK3 Clock input/output pin for UART3
37
P15
N
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
AD13 Input/output pin for external bus address data bus bit 13.
This function is enabled when external bus is enabled.
38
P16
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
AD14 Input/output pin for external bus address data bus bit 14.
This function is enabled when external bus is enabled.
39
P17
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
AD15 Input/output pin for external bus address data bus bit 15.
This function is enabled when external bus is enabled.
40 to 43
P20 to P23
G
General purpose I/O ports. The register can be set to select whether to use a pull-up
resistor. In external bus mode, the pins are enabled as a general purpose I/O port when
the corresponding bit in the external address output control register (HACR) is 1.
A16 to A19
Output pins for A16 to A19 of the external address data bus.
When the corresponding bit in the external address output control register (HACR) is 0,
the pins are enabled as high address output pins A16 to A19.
PPG9 (8) ,
PPGB (A) ,
PPGD (C) ,
PPGF (E)
Output pins for PPGs
Document Number: 002-07872 Rev. *A Page 16 of 83
MB90350 Series
(Continued)
Pin No. Pin name Circuit
type Function
LQFP64*
44
P24
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. In external bus mode, the pin is enabled as a general-
purpose I/O port when the corresponding bit in the external address output control
register (HACR) is 1.
A20
Output pin for A20 of the external address data bus. When the corresponding bit in the
external address output control register (HACR) is 0, the pin is
enabled as high address output pin A20.
IN0 Data sample input pin for input capture ICU0
51
P25
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. In external bus mode, the pin is enabled as a general-
purpose I/O port when the corresponding bit in the external address output control
register (HACR) is 1.
A21
Output pin for A21 of the external address data bus. When the corresponding bit in the
external address output control register (HACR) is 0, the pin is enabled as high address
output pin A21.
IN1 Data sample input pin for input capture ICU1
ADTG Trigger input pin for A/D converter
52
P44
H
General purpose I/O port
SDA0 Serial data I/O pin for I2C 0
FRCK0 Input pin for the 16-bit I/O Timer 0
53
P45
H
General purpose I/O port
SCL0 Serial clock I/O pin for I2C 0
FRCK1 Input pin for the 16-bit I/O Timer 1
54
P30
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
ALE Address latch enable output pin. This function is enabled when external bus is enabled.
IN4 Data sample input pin for input capture ICU4
55
P31
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
RD Read strobe output pin for data bus. This function is enabled when external bus is
enabled.
IN5 Data sample input pin for input capture ICU5
56
P32
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode or with the WR/WRL pin
output disabled.
WR/WRL
Write strobe output pin for the data bus. This function is enabled when both the external
bus and the WR/WRL pin output are enabled. WRL is used to write-strobe 8 lower bits
of the data bus in 16-bit access. WR is used to write-strobe 8 bits of the data bus in 8-bit
access.
INT10R External interrupt request input pin for INT10
57
P33
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode, in
external bus 8-bit mode or with the WRH pin output disabled.
WRH
Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when
the external bus is enabled, when the external bus 16-bit mode is selected, and when
the WRH output pin is enabled.
Document Number: 002-07872 Rev. *A Page 17 of 83
MB90350 Series
* : FPT-64P-M23, FPT-64P-M24
Pin No. Pin name Circuit
type Function
LQFP64*
58
P34
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode or with the hold function
disabled.
HRQ Hold request input pin. This function is enabled when both the external bus and the hold
function are enabled.
OUT4 Waveform output pin for output compare OCU4
59
P35
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode or with the hold function
disabled.
HAK Hold acknowledge output pin. This function is enabled when both the
external bus and the hold function are enabled.
OUT5 Waveform output pin for output compare OCU5
60
P36
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode or with the external ready
function disabled.
RDY Ready input pin. This function is enabled when both the external bus and the external
ready function are enabled.
OUT6 Waveform output pin for output compare OCU6
61
P37
G
General purpose I/O port. The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode or with the CLK output
disabled.
CLK CLK output pin. This function is enabled when both the external bus and CLK output are
enabled.
OUT7 Waveform output pin for output compare OCU7
62, 63 P60, P61 IGeneral purpose I/O ports
AN0, AN1 Analog input pins for A/D converter
64 AVCC KV
CC power input pin for analog circuits
2AVRHL
Reference voltage input for the A/D converter. This power supply must be turned on or
off while a voltage higher than or equal to AVRH is applied to AVCC.
1AV
SS KV
SS power input pin for analog circuits
22, 23 MD1, MD0 C Input pins for specifying the operating mode
21 MD2 D Input pin for specifying the operating mode
49 VCC — Power (3.5 V to 5.5 V) input pin
18, 48 VSS — Power (0 V) input pins
50 C K This is the power supply stabilization capacitor pin. It should be connected to a higher
than or equal to 0.1 μF ceramic capacitor.
Document Number: 002-07872 Rev. *A Page 18 of 83
MB90350 Series
8. I/O Circuit Type
(Continued)
Type Circuit Remarks
A
Oscillation circuit
• High-speed oscillation feedback
resistor = approx. 1 M
B
Oscillation circuit
• Low-speed oscillation feedback
resistor = approx. 10 M
C
Mask ROM device:
• CMOS hysteresis input pin
Flash memory device:
• CMOS input pin
D
Mask ROM device:
• CMOS hysteresis input pin
• Pull-down resistor value: approx. 50 k
Flash memory device:
• CMOS input pin
• No Pull-down
E
CMOS hysteresis input pin
• Pull-up resistor value: approx. 50 k
Standby control signal
X1
X0
Xout
Standby control signal
X1A
X0A
Xout
CMOS
hysteresis
inputs
R
Pull-up
resistor
CMOS
hysteresis
inputs
R
Document Number: 002-07872 Rev. *A Page 19 of 83
MB90350 Series
(Continued)
Type Circuit Remarks
F
•CMOS level output
(IOL = 4 mA, IOH 4 mA)
• CMOS hysteresis inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time input
shutdown function)
G
•CMOS level output
(IOL = 4 mA, IOH 4 mA)
• CMOS hysteresis inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time input
shutdown function)
• TTL input (With the standby-time input shut-
down function)
• Programmable pull-up resistor:
approx. 50 k
H
•CMOS level output
(IOL = 3 mA, IOH 3 mA)
• CMOS hysteresis inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time input
shutdown function)
CMOS
hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Pout
Nout
R
P-ch
N-ch
Pull-up control
CMOS
hysteresis inputs
Automotive inputs
TTL input
Standby control for
input shutdown
Pull-up
resistor Pout
Nout
R
P-chP-ch
N-ch
CMOS
hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Pout
Nout
R
P-ch
N-ch
Document Number: 002-07872 Rev. *A Page 20 of 83
MB90350 Series
(Continued)
Type Circuit Remarks
I
• CMOS level output
(IOL = 4 mA, IOH = 4 mA)
• CMOS hysteresis inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time input
shutdown function)
• A/D analog input
K
• Power supply input protection circuit
L
• A/D converter reference voltage power supply
input pin, with the protection circuit
• Flash memory devices do not have a
protection circuit against VCC for pin
AVRH.
CMOS
hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
Pout
Nout
R
P-ch
N-ch
P-ch
N-ch
ANE
AVR
ANE
P-ch
N-ch
Document Number: 002-07872 Rev. *A Page 21 of 83
MB90350 Series
(Continued)
Type Circuit Remarks
N
•CMOS level output
(IOL = 4 mA, IOH 4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time input
shutdown function)
• TTL input (With the standby-time input shut-
down function)
• Programmable pull-up resistor:
approx. 50 k
O
•CMOS level output
(IOL = 4 mA, IOH 4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time input
shutdown function)
• A/D analog input
pull-up control
CMOS inputs
Automotive inputs
TTL input
Standby control for
input shutdown
pull-up
resistor
Pout
Nout
R
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Analog input
P-ch
N-ch
Pout
Nout
R
Document Number: 002-07872 Rev. *A Page 22 of 83
MB90350 Series
9. Handling Devices
Special care is required for the following when handling the device :
■Preventing latch-up
■Treatment of unused pins
■Using external clock
■Precautions for when not using a sub clock signal
■Notes on during operation of PLL clock mode
■Power supply pins (VCC/VSS)
■Pull-up/down resistors
■Crystal Oscillator Circuit
■Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
■Connection of Unused Pins of A/D Converter
■Notes on Energization
■Stabilization of power supply voltage
■Initialization
■Port0 to port3 output during Power-on (External-bus mode)
■Notes on using CAN Function
■Flash security Function
■Correspondence with TA 105 °C or more
■Low voltage/CPU operation detection reset circuit
■Internal CR oscillation circuit
9.1 Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
■A voltage higher than VCC or lower than VSS is applied to an input or output pin.
■A voltage higher than the rated voltage is applied between VCC pin and VSS pin.
■The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
In using the devices, take sufficient care to avoid exceeding maximum ratings.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage.
9.2 Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they
must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kΩ.
Unused I/O pins should be set to the output state and can be left open, or the input state with the above described connection.
Document Number: 002-07872 Rev. *A Page 23 of 83
MB90350 Series
9.3 Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
9.4 Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open.
9.5 Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempts to be working with the self-oscillating circuit even when there is no
external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
9.6 Power supply pins (VCC/VSS)
■If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected inside
of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard
for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally.
Connect VCC and VSS pins to the device from the current supply source at a low impedance.
■As a measure against power supply noise, connect a capacitor of about 0.1 μF as a bypass capacitor between VCC and VSS pins
in the vicinity of VCC and VSS pins of the device.
9.7 Pull-up/down resistors
The MB90350 series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors). Use external compo-
nents where needed.
9.8 Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest
distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of
oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the
operation.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
X0
X1
MB90350 Series
Open
Vcc
Vss
Vss
Vcc
Vss
Vcc
MB90350
Series
Vcc Vss
Vcc
Vss
Document Number: 002-07872 Rev. *A Page 24 of 83
MB90350 Series
9.9 Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN14) after turning-on the digital power
supply (VCC) .
Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make sure that the voltage
does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
9.10 Connection of Unused Pins of A/D Converter if A/D Converter is not used
Connect unused pins of A/D converter to AVCC VCC, AVSS AVRH VSS.
9.11 Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 μs or more (0.2 V to 2.7 V) .
9.12 Stabilization of power supply voltage
A sudden change in the power supply voltage may cause the device to malfunction even within the specified VCC power supply voltage
operating range. Therefore, the VCC power supply voltage should be stabilized.
For reference, the power supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at commercial
frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC power supply voltage and the coefficient of fluctuation does not
exceed 0.1 V/ms at instantaneous power switching.
9.13 Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, turn on the power
again.
9.14 Port 0 to port 3 output during Power-on (External-bus mode)
As shown below, when power is turned on in external-bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable.
9.15 Notes on using CAN Function
To use CAN function, please set “1” to DIRECT bit of CAN direct mode register (CDMR).
If DIRECT bit is set to “0” (initial value), wait states will be performed when accessing CAN registers.
Note : Please refer to section “22.15 CAN Direct Mode Register” in Hardware Manual of MB90350 series for detail of CAN direct mode
register.
Port0 to Port3
Port0 to Port3 outputs
might be unstable. Port0 to Port3 outputs = Hi-Z
V
CC
1/2 V
CC
Document Number: 002-07872 Rev. *A Page 25 of 83
MB90350 Series
9.16 Flash security Function
The security byte is located in the area of the flash memory.
If protection code 01H is written in the security byte, the flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security byte.
9.17 Correspondence with TA 105 °C or more
If used exceeding TA 105 °C, please contact sales representatives for reliability limitations.
9.18 Low voltage/CPU operation reset circuit
The low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when a voltage drops below
a given voltage level. When a low voltage condition is detected, an internal reset signal is generated.
The CPU operation detection reset circuit is a 20-bit counter that uses oscillation as a count clock and generates an internal reset
signal if not cleared within a given time after startup.
9.18.1 Low voltage detection reset circuit
When a low voltage condition is detected, the low voltage detection flag (LVRC: LVRF) is set to “1” and an internal reset signal is output.
Because the low voltage detection reset circuit continues to operate even in stop mode, detection of a low voltage condition generates
an internal reset and releases stop mode.
During an internal RAM write cycle, low voltage reset is generated after the completion of writing. During the output of this internal
reset, the reset output from the low voltage detection reset circuit is suppressed.
9.18.2 CPU operation detection reset circuit
The CPU operation detection reset circuit is a counter that prevents program runaway. The counter starts automatically after a
power-on reset, and must be continually cleared within a given time. If the given time interval elapses and the counter has not been
cleared, a cause such as infinite program looping is assumed and an internal reset signal is generated. The internal reset generated
from the CPU operation detection circuit has a width of 5 machine cycles.
* : This value assumes the interval time at an oscillation clock frequency of 4 MHz.
During recovery from standby mode, the detection period is the maximum interval plus 20 μs.
This circuit does not operate in modes where CPU operation is stopped.
The CPU operation detection reset circuit counter is cleared under any of the following conditions.
■“0” writing to CL bit of LVRC register
■Internal reset
■Main oscillation clock stop
■Transit to sleep mode
■Transit to timebase timer mode and watch mode
Flash memory size Address for security bit
MB90F352(S)
MB90F352A(S)
MB90F352TA(S)
MB90F357A(S)
MB90F357TA(S)
Embedded 1 Mbit Flash Memory FE0001H
Detection voltage
4.0 V 0.3 V
Interval time
220/FC (approx. 262 ms*)
Document Number: 002-07872 Rev. *A Page 26 of 83
MB90350 Series
9.19 Internal CR oscillation circuit
Parameter Symbol Value Unit
Min Typ Max
Oscillation frequency fRC 50 100 200 kHz
Oscillation stabilization wait time tstab — — 100 μs
Document Number: 002-07872 Rev. *A Page 27 of 83
MB90350 Series
10. Block Diagrams
■MB90V340A-101/102
AVCC
SCL0,SCL1
SDA0,SDA1
PPGF to PPG0
DA00,DA01
ADTG
AVRH
AVRL
AN23 to AN0
AVSS
SIN4 to SIN0
SCK4 to SCK0
SOT4 to SOT0
X0
X0A*
FRCK0
IN7 to IN0
OUT7 to OUT0
FRCK1
RX2 to RX0
TX2 to TX0
TIN3 to TIN0
TOT3 to TOT0
AD15 to AD00
A21 to A16
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
INT15 to INT8
INT7 to INT0
CKOT
(INT11R to INT9R)
RST
DMAC
16LX CPU
X1
X1A*
Clock
controller
RAM
30 Kbytes
Prescaler
5 channels
UART
5 channels
I/O Timer 0
Input
Capture
8 channels
Output
Compare
8 channels
I/O Timer 1
CAN
Controller
3 channels
16-bit
Reload Timer
4 channels
10-bit
A/D
Converter
24 channels
10-bit
D/A
Converter
2 channels
8/16-bit
PPG
16 channels
I2C interface
2 channels External
Interrupt
External
Bus
Interface
F2MC-16 bus
* : MB90V340A-102 only
Clock
Monitor
Document Number: 002-07872 Rev. *A Page 28 of 83
MB90350 Series
■MB90V340A-103/104
AVCC
SCL1, SCL0
SDA1, SDA0
PPGF to PPG0
DA01, DA00
ADTG
AVRH
AN23 to AN0
AVSS
SIN4 to SIN0
SCK4 to SCK0
SOT4 to SOT0
X0
X0A *
FRCK0
IN7 to IN0
OUT7 to OUT0
FRCK1
RX2 to RX0
TX2 to TX0
TIN3 to TIN0
TOT3 to TOT0
AD15 to AD00
A23 to A16
ALE
HRQ
RDY
CLK
INT15 to INT8
(INT15R to INT8R)
RST
DMA
HAK
WRH
WRL
RD
AVRL
CKOT
INT7 to INT0
X1
X1A*
Clock
controller/Monit
or
CR oscillation
circuit
UART
5 channels
I/O Timer 0
Input
Capture
8 channels
Output
Compare
8 channels
I/O Timer 1
CAN
Controller
3 channels
16-bit
Reload
Timer
4 channels
8/10-bit
A/D
Converter
24 channels
10-bit
D/A
Converter
2 channels
8/16-bit
PPG
16 channels
I2C interface
2 channels DTP/External
Interrupt
External
Bus
Interface
Internal Data Bus
* : MB90V340A-104 only
Clock
Monitor
RAM
30 Kbytes
Prescaler
5 channels
F2MC-16LX
Core
Document Number: 002-07872 Rev. *A Page 29 of 83
MB90350 Series
■MB90F352 (S) , MB90F351 (S) , MB90F352A (S) , MB90F352TA (S) , MB90F351A (S) , MB90F351TA (S) , MB90352A (S) ,
MB90352TA (S) , MB90351A (S) , MB90351TA (S)
AVCC
SCL0
SDA0
PPG6, PPG4
PPGF to PPG8
ADTG
AVRH
AN14 to AN0
AVSS
SIN3, SIN2
SCK3, SCK2
SOT3, SOT2
FRCK0
IN7 to IN4,
IN1, IN0
OUT7 to OUT4
FRCK1
RX1
TX1
TIN3, TIN1
TOT3, TOT1
AD15 to AD00
A21 to A16
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
INT15 to INT8
(INT11R to INT9R)
DMAC
16LX CPU
X0
X0A *
1
RST
X1
X1A*
1
Clock
controller
Low voltage/
CPU operation
detection
reset*2
Prescaler
2 channels
UART
2 channels
I/O Timer 0
Input
Capture
6 channels
Output
Compare
4 channels
I/O Timer 1
CAN
Controller
1 channel
16-bit
Reload Timer
4 channels
8/10-bit
A/D
Converter
15 channels
8/16-bit
PPG
10/6 channels
I2C interface
1 channel
External
Interrupt
External
Bus
Interface
F2MC-16 bus
*1 : Only for devices without “S”-suffix
*2 : Only for devices with “T”-suffix
RAM
4 Kbytes
ROM/Flash
128 K/64
Kbytes
Document Number: 002-07872 Rev. *A Page 30 of 83
MB90350 Series
■MB90F357A (S) , MB90F357TA (S) , MB90F356A (S) , MB90F356TA (S) , MB90357A (S) , MB90357TA (S) , MB90356A (S) ,
MB90356TA (S)
AVCC
SCL0
SDA0
PPG6, PPG4
PPGF to PPG8
ADTG
AVRH
AN14 to AN0
AVSS
SIN3, SIN2
SCK3, SCK2
SOT3, SOT2
X0
X0A*1
RST
FRCK0
IN7 to IN4,
IN1, IN0
OUT7 to OUT4
FRCK1
RX1
TX1
TIN3, TIN1
TOT3, TOT1
AD15 to AD00
A21 to A16
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
INT15 to INT8
(INT11R to INT9R)
DMAC
16LX CPU
X1
X1A*1
Clock
controller/
monitor
CR
oscillation
circuit
Prescaler
2 channels
UART
2 channels
I/O Timer 0
Input
Capture
6 channels
Output
Compare
4 channels
I/O Timer 1
CAN
Controller
1 channel
16-bit
Reload Timer
4 channels
8/10-bit
A/D
Converter
15 channels
8/16-bit
PPG
10/6 channels
I2C interface
1 channel External
Interrupt
External
Bus
Interface
F2MC-16 bus
*1 : Only for devices without “S”-suffix
*2 : Only for devices with “T”-suffix
RAM
4 Kbytes
ROM/Flash
128 K/64 K
bytes
Low voltage detector*2
CPU operation
detector*2
Document Number: 002-07872 Rev. *A Page 31 of 83
MB90350 Series
11. Memory Map
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective.
Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer
declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF7FFFH is visible
only in bank FF.
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
C00100H
00FFFFH
008000H
007FFFH
007900H
000100H
0010FFH
001100H
0000EFH
000000H
MB90351A (S)
MB90351TA (S)
MB90356A (S)
MB90356TA (S)
MB90F351A (S)
MB90F351TA (S)
MB90F356A (S)
MB90F356TA (S)
MB90F351 (S)
MB90352A (S)
MB90352TA (S)
MB90357A (S)
MB90357TA (S)
MB90F352A (S)
MB90F352TA (S)
MB90F357A (S)
MB90F357TA (S)
MB90F352 (S)
FFFFFFH
FF0000H
FDFFFFH
C00100H
00FFFFH
008000H
007FFFH
007900H
000100H
0010FFH
0000EFH
000000H
FFFFFFH
MB90V340A-101
MB90V340A-102
MB90V340A-103
MB90V340A-104
FEFFFFH
FF0000H
FDFFFFH
FE0000H
FCFFFFH
FD0000H
FBFFFFH
FC0000H
FAFFFFH
FB0000H
F9FFFFH
FA0000H
F8FFFFH
F90000H
007FFFH
008000H
0078FFH
007900H
000000H
0000EFH
F80000H
00FFFFH
000100H
ROM (FF bank) ROM (FF bank) ROM (FF bank)
ROM (FB bank)
ROM (FC bank)
Peripheral
ROM (F8 bank)
ROM (image of
FF bank)
ROM (FD bank)
ROM (FE bank)
ROM (FA bank)
ROM (F9 bank)
RAM 30 Kbytes
Peripheral
ROM (FE bank)
External access
area
ROM (image of
FF bank)
Peripheral
RAM 4 Kbytes
External access area
Peripheral
External access
area
ROM (image of
FF bank)
Peripheral
RAM 4 Kbytes
External access area
Peripheral
: No access
Document Number: 002-07872 Rev. *A Page 32 of 83
MB90350 Series
12. I/O Map
(Continued)
Address Register Abbreviation Access Resource name Initial value
00HPort 0 Data Register PDR0 R/W Port 0 XXXXXXXXB
01HPort 1 Data Register PDR1 R/W Port 1 XXXXXXXXB
02HPort 2 Data Register PDR2 R/W Port 2 XXXXXXXXB
03HPort 3 Data Register PDR3 R/W Port 3 XXXXXXXXB
04HPort 4 Data Register PDR4 R/W Port 4 XXXXXXXXB
05HPort 5 Data Register PDR5 R/W Port 5 XXXXXXXXB
06HPort 6 Data Register PDR6 R/W Port 6 XXXXXXXXB
07H to 0AHReserved
0BHPort 5 Analog Input Enable Register ADER5 R/W Port 5, A/D 11111111B
0CHPort 6 Analog Input Enable Register ADER6 R/W Port 6, A/D 11111111B
0DHReserved
0EHInput Level Select Register 0 ILSR0 R/W Ports 00000000B
0FHInput Level Select Register 1 ILSR1 R/W Ports 00000000B
10HPort 0 Direction Register DDR0 R/W Port 0 00000000B
11HPort 1 Direction Register DDR1 R/W Port 1 00000000B
12HPort 2 Direction Register DDR2 R/W Port 2 XX000000B
13HPort 3 Direction Register DDR3 R/W Port 3 00000000B
14HPort 4 Direction Register DDR4 R/W Port 4 XX000000B
15HPort 5 Direction Register DDR5 R/W Port 5 X0000000B
16HPort 6 Direction Register DDR6 R/W Port 6 00000000B
17H to 19HReserved
1AHSIN input Level Setting Register DDRA W UART2, UART3 X00XXXXXB
1BHReserved
1CHPort 0 Pull-up Control Register PUCR0 R/W Port 0 00000000B
1DHPort 1 Pull-up Control Register PUCR1 R/W Port 1 00000000B
1EHPort 2 Pull-up Control Register PUCR2 R/W Port 2 00000000B
1FHPort 3 Pull-up Control Register PUCR3 R/W Port 3 00000000B
20H to 37HReserved
38HPPG 4 Operation Mode Control Register PPGC4 W, R/W
16-bit Programmable
Pulse Generator 4/5
0X000XX1B
39HPPG 5 Operation Mode Control Register PPGC5 W, R/W 0X000001B
3AHPPG 4/5 Count Clock Select Register PPG45 R/W 000000X0B
3BHAddress Detect Control Register 1 PACSR1 R/W Address Match
Detection 1 00000000B
3CHPPG 6 Operation Mode Control Register PPGC6 W, R/W
16-bit Programmable
Pulse Generator 6/7
0X000XX1B
3DHPPG 7 Operation Mode Control Register PPGC7 W, R/W 0X000001B
3EHPPG 6/7 Count Clock Select Register PPG67 R/W 000000X0B
3FHReserved
40HPPG 8 Operation Mode Control Register PPGC8 W, R/W
16-bit Programmable
Pulse Generator 8/9
0X000XX1B
41HPPG 9 Operation Mode Control Register PPGC9 W, R/W 0X000001B
42HPPG 8/9 Count Clock Select Register PPG89 R/W 000000X0B
43HReserved
Document Number: 002-07872 Rev. *A Page 33 of 83
MB90350 Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
44HPPG A Operation Mode Control Register PPGCA W, R/W
16-bit Programmable
Pulse Generator A/B
0X000XX1B
45HPPG B Operation Mode Control Register PPGCB W, R/W 0X000001B
46HPPG A/B Count Clock Select Register PPGAB R/W 000000X0B
47HReserved
48HPPG C Operation Mode Control Register PPGCC W,R/W
16-bit Programmable
Pulse Generator C/D
0X000XX1B
49HPPG D Operation Mode Control Register PPGCD W,R/W 0X000001B
4AHPPG C/D Count Clock Select Register PPGCD R/W 000000X0B
4BHReserved
4CHPPG E Operation Mode Control Register PPGCE W,R/W
16-bit Programmable
Pulse Generator E/F
0X000XX1B
4DHPPG F Operation Mode Control Register PPGCF W,R/W 0X000001B
4EHPPG E/F Count Clock Select Register PPGEF R/W 000000X0B
4FHReserved
50HInput Capture Control Status Register 0/1 ICS01 R/W Input Capture 0/1 00000000B
51HInput Capture Edge Register 0/1 ICE01 R/W, R XXX0X0XXB
52H, 53HReserved
54HInput Capture Control Status Register 4/5 ICS45 R/W Input Capture 4/5 00000000B
55HInput Capture Edge Register 4/5 ICE45 R XXXXXXXXB
56HInput Capture Control Status Register 6/7 ICS67 R/W Input Capture 6/7 00000000B
57HInput Capture Edge Register 6/7 ICE67 R/W, R XXX000XXB
58H to 5BHReserved
5CHOutput Compare Control Status Register 4 OCS4 R/W Output Compare 4/5 0000XX00B
5DHOutput Compare Control Status Register 5 OCS5 R/W 0XX00000B
5EHOutput Compare Control Status Register 6 OCS6 R/W Output Compare 6/7 0000XX00B
5FHOutput Compare Control Status Register 7 OCS7 R/W 0XX00000B
60HTimer Control Status Register 0 TMCSR0 R/W 16-bit Reload Timer 0 00000000B
61HTimer Control Status Register 0 TMCSR0 R/W XXXX0000B
62HTimer Control Status Register 1 TMCSR1 R/W 16-bit Reload Timer 1 00000000B
63HTimer Control Status Register 1 TMCSR1 R/W XXXX0000B
64HTimer Control Status Register 2 TMCSR2 R/W 16-bit Reload Timer 2 00000000B
65HTimer Control Status Register 2 TMCSR2 R/W XXXX0000B
66HTimer Control Status Register 3 TMCSR3 R/W 16-bit Reload Timer 3 00000000B
67HTimer Control Status Register 3 TMCSR3 R/W XXXX0000B
68HA/D Control Status Register 0 ADCS0 R/W
A/D Converter
000XXXX0B
69HA/D Control Status Register 1 ADCS1 R/W 0000000XB
6AHA/D Data Register 0 ADCR0 R 00000000B
6BHA/D Data Register 1 ADCR1 R XXXXXX00B
6CHADC Setting Register 0 ADSR0 R/W 00000000B
6DHADC Setting Register 1 ADSR1 R/W 00000000B
6EH
Low Voltage/CPU Operation Detection Reset
Control Register LVRC R/W, W
Low Voltage/CPU
Operation Detection
Reset
00111000B
Document Number: 002-07872 Rev. *A Page 34 of 83
MB90350 Series
(Continued)
Address Register Abbrevia-
tion Access Resource name Initial value
6FHROM Mirror Function Select Register ROMM W ROM Mirror XXXXXXX1B
70H to 7FHReserved
80H to 8FHReserved for CAN Interface 1. Refer to “CAN Controllers”
90H to 9AHReserved
9BH
DMA Descriptor Channel Specification
Register DCSR R/W
DMA
00000000B
9CHDMA Status Register L DSRL R/W 00000000B
9DHDMA Status Register H DSRH R/W 00000000B
9EHAddress Detect Control Register 0 PACSR0 R/W Address Match
Detection 0 00000000B
9FHDelayed Interrupt/Release Register DIRR R/W Delayed Interrupt XXXXXXX0B
A0H
Low-power Consumption Mode Control
Register LPMCR W,R/W Low Power Consumption
Control Circuit 00011000B
A1HClock Selection Register CKSCR R,R/W Low Power Consumption
Control Circuit 11111100B
A2H, A3HReserved
A4HDMA Stop Status Register DSSR R/W DMA 00000000B
A5HAutomatic Ready Function Selection Register ARSR W
External Memory
Access
0011XX00B
A6HExternal Address Output Control Register HACR W 00000000B
A7HBus Control Signal Selection Register ECSR W 0000000XB
A8HWatchdog Control Register WDTC R,W Watchdog Timer XXXXX111B
A9HTimebase Timer Control Register TBTC W,R/W Timebase timer 1XX00100B
AAHWatch Timer Control Register WTC R,R/W Watch Timer 1X001000B
ABHReserved
ACHDMA Enable Register L DERL R/W DMA 00000000B
ADHDMA Enable Register H DERH R/W 00000000B
AEH
Flash Control Status Register
(Flash Devices only. Otherwise reserved) FMCS R,R/W Flash Memory 000X0000B
AFHReserved
Document Number: 002-07872 Rev. *A Page 35 of 83
MB90350 Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
B0HInterrupt Control Register 00 ICR00 W,R/W
Interrupt Control
00000111B
B1HInterrupt Control Register 01 ICR01 W,R/W 00000111B
B2HInterrupt Control Register 02 ICR02 W,R/W 00000111B
B3HInterrupt Control Register 03 ICR03 W,R/W 00000111B
B4HInterrupt Control Register 04 ICR04 W,R/W 00000111B
B5HInterrupt Control Register 05 ICR05 W,R/W 00000111B
B6HInterrupt Control Register 06 ICR06 W,R/W 00000111B
B7HInterrupt Control Register 07 ICR07 W,R/W 00000111B
B8HInterrupt Control Register 08 ICR08 W,R/W 00000111B
B9HInterrupt Control Register 09 ICR09 W,R/W 00000111B
BAHInterrupt Control Register 10 ICR10 W,R/W 00000111B
BBHInterrupt Control Register 11 ICR11 W,R/W 00000111B
BCHInterrupt Control Register 12 ICR12 W,R/W 00000111B
BDHInterrupt Control Register 13 ICR13 W,R/W 00000111B
BEHInterrupt Control Register 14 ICR14 W,R/W 00000111B
BFHInterrupt Control Register 15 ICR15 W,R/W 00000111B
C0H to C9HReserved
CAHExternal Interrupt Enable Register 1 ENIR1 R/W
External Interrupt 1
00000000B
CBHExternal Interrupt Source Register 1 EIRR1 R/W XXXXXXXXB
CCHExternal Interrupt Level Register 1 ELVR1 R/W 00000000B
CDHExternal Interrupt Level Register 1 ELVR1 R/W 00000000B
CEHExternal Interrupt Source Select Register EISSR R/W 00000000B
CFHPLL/Sub clock Control register PSCCR W PLL XXXX0000B
D0HDMA Buffer Address Pointer L BAPL R/W
DMA
XXXXXXXXB
D1HDMA Buffer Address Pointer M BAPM R/W XXXXXXXXB
D2HDMA Buffer Address Pointer H BAPH R/W XXXXXXXXB
D3HDMA Control Register DMACS R/W XXXXXXXXB
D4HI/O Register Address Pointer L IOAL R/W XXXXXXXXB
D5HI/O Register Address Pointer H IOAH R/W XXXXXXXXB
D6HData Counter L DCTL R/W XXXXXXXXB
D7HData Counter H DCTH R/W XXXXXXXXB
D8HSerial Mode Register 2 SMR2 W,R/W
UART2
00000000B
D9HSerial Control Register 2 SCR2 W,R/W 00000000B
DAHReception/Transmission Data Register 2 RDR2/TDR2 R/W 00000000B
DBHSerial Status Register 2 SSR2 R,R/W 00001000B
DCHExtended Communication Control Register 2 ECCR2 R,W,
R/W 000000XXB
DDHExtended Status/Control Register 2 ESCR2 R/W 00000100B
DEHBaud Rate Generator Register 20 BGR20 R/W 00000000B
DFHBaud Rate Generator Register 21 BGR21 R/W 00000000B
E0H to EFHReserved
Document Number: 002-07872 Rev. *A Page 36 of 83
MB90350 Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
F0H to FFHExternal area
7900H to
7907H
Reserved
7908HReload Register L4 PRLL4 R/W
16-bit Programmable
Pulse
Generator 4/5
XXXXXXXXB
7909HReload Register H4 PRLH4 R/W XXXXXXXXB
790AHReload Register L5 PRLL5 R/W XXXXXXXXB
790BHReload Register H5 PRLH5 R/W XXXXXXXXB
790CHReload Register L6 PRLL6 R/W
16-bit Programmable
Pulse
Generator 6/7
XXXXXXXXB
790DHReload Register H6 PRLH6 R/W XXXXXXXXB
790EHReload Register L7 PRLL7 R/W XXXXXXXXB
790FHReload Register H7 PRLH7 R/W XXXXXXXXB
7910HReload Register L8 PRLL8 R/W
16-bit Programmable
Pulse
Generator 8/9
XXXXXXXXB
7911HReload Register H8 PRLH8 R/W XXXXXXXXB
7912HReload Register L9 PRLL9 R/W XXXXXXXXB
7913HReload Register H9 PRLH9 R/W XXXXXXXXB
7914HReload Register LA PRLLA R/W
16-bit Programmable
Pulse
Generator A/B
XXXXXXXXB
7915HReload Register HA PRLHA R/W XXXXXXXXB
7916HReload Register LB PRLLB R/W XXXXXXXXB
7917HReload Register HB PRLHB R/W XXXXXXXXB
7918HReload Register LC PRLLC R/W
16-bit Programmable
Pulse
Generator C/D
XXXXXXXXB
7919HReload Register HC PRLHC R/W XXXXXXXXB
791AHReload Register LD PRLLD R/W XXXXXXXXB
791BHReload Register HD PRLHD R/W XXXXXXXXB
791CHReload Register LE PRLLE R/W
16-bit Programmable
Pulse
Generator E/F
XXXXXXXXB
791DHReload Register HE PRLHE R/W XXXXXXXXB
791EHReload Register LF PRLLF R/W XXXXXXXXB
791FHReload Register HF PRLHF R/W XXXXXXXXB
7920HInput Capture Register 0 IPCP0 R
Input Capture 0/1
XXXXXXXXB
7921HInput Capture Register 0 IPCP0 R XXXXXXXXB
7922HInput Capture Register 1 IPCP1 R XXXXXXXXB
7923HInput Capture Register 1 IPCP1 R XXXXXXXXB
7924H to
7927H
Reserved
7928HInput Capture Register 4 IPCP4 R
Input Capture 4/5
XXXXXXXXB
7929HInput Capture Register 4 IPCP4 R XXXXXXXXB
792AHInput Capture Register 5 IPCP5 R XXXXXXXXB
792BHInput Capture Register 5 IPCP5 R XXXXXXXXB
Document Number: 002-07872 Rev. *A Page 37 of 83
MB90350 Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
792CHInput Capture Register 6 IPCP6 R
Input Capture 6/7
XXXXXXXXB
792DHInput Capture Register 6 IPCP6 R XXXXXXXXB
792EHInput Capture Register 7 IPCP7 R XXXXXXXXB
792FHInput Capture Register 7 IPCP7 R XXXXXXXXB
7930H to
7937H
Reserved
7938HOutput Compare Register 4 OCCP4 R/W
Output Compare 4/5
XXXXXXXXB
7939HOutput Compare Register 4 OCCP4 R/W XXXXXXXXB
793AHOutput Compare Register 5 OCCP5 R/W XXXXXXXXB
793BHOutput Compare Register 5 OCCP5 R/W XXXXXXXXB
793CHOutput Compare Register 6 OCCP6 R/W
Output Compare 6/7
XXXXXXXXB
793DHOutput Compare Register 6 OCCP6 R/W XXXXXXXXB
793EHOutput Compare Register 7 OCCP7 R/W XXXXXXXXB
793FHOutput Compare Register 7 OCCP7 R/W XXXXXXXXB
7940HTimer Data Register 0 TCDT0 R/W
I/O Timer 0
00000000B
7941HTimer Data Register 0 TCDT0 R/W 00000000B
7942HTimer Control Status Register 0 TCCSL0 R/W 00000000B
7943HTimer Control Status Register 0 TCCSH0 R/W 0XXXXXXXB
7944HTimer Data Register 1 TCDT1 R/W
I/O Timer 1
00000000B
7945HTimer Data Register 1 TCDT1 R/W 00000000B
7946HTimer Control Status Register 1 TCCSL1 R/W 00000000B
7947HTimer Control Status Register 1 TCCSH1 R/W 0XXXXXXXB
7948HTimer Register 0/Reload Register 0 TMR0/TMRL
R0
R/W 16-bit Reload Timer 0 XXXXXXXXB
7949HR/W XXXXXXXXB
794AHTimer Register 1/Reload Register 1 TMR1/TMRL
R1
R/W 16-bit Reload Timer 1 XXXXXXXXB
794BHR/W XXXXXXXXB
794CHTimer Register 2/Reload Register 2 TMR2/TMRL
R2
R/W 16-bit Reload Timer 2 XXXXXXXXB
794DHR/W XXXXXXXXB
794EHTimer Register 3/Reload Register 3 TMR3/TMRL
R3
R/W 16-bit Reload Timer 3 XXXXXXXXB
794FHR/W XXXXXXXXB
7950HSerial Mode Register 3 SMR3 W, R/W
UART3
00000000B
7951HSerial Control Register 3 SCR3 W, R/W 00000000B
7952HReception/Transmission Data Register 3 RDR3/TDR3 R/W 00000000B
7953HSerial Status Register 3 SSR3 R,R/W 00001000B
7954HExtended Communication Control Register 3 ECCR3 R,W,
R/W 000000XXB
7955HExtended Status/Control Register 3 ESCR3 R/W 00000100B
7956HBaud Rate Generator Register 30 BGR30 R/W 00000000B
7957HBaud Rate Generator Register 31 BGR31 R/W 00000000B
7958H,
7959H
Reserved
Document Number: 002-07872 Rev. *A Page 38 of 83
MB90350 Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
7960HClock Monitor Function Control Register CSVCR R, R/W Clock Monitor 00011100B
7961H to
796DH
Reserved
796EHCAN Direct Mode Register CDMR R/W CAN Clock Sync XXXXXXX0B
796FHReserved
7970HI2C Bus Status Register 0 IBSR0 R
I2C Interface 0
00000000B
7971HI2C Bus Control Register 0 IBCR0 W,R/W 00000000B
7972HI2C 10-bit Slave Address Register 0 ITBAL0 R/W 00000000B
7973HITBAH0 R/W 00000000B
7974HI2C 10-bit Slave Address Mask Register 0 ITMKL0 R/W 11111111B
7975HITMKH0 R/W 00111111B
7976HI2C 7-bit Slave Address Register 0 ISBA0 R/W 00000000B
7977HI2C 7-bit Slave Address Mask Register 0 ISMK0 R/W 01111111B
7978HI2C data register 0 IDAR0 R/W 00000000B
7979H,
797AH
Reserved
797BHI2C Clock Control Register 0 ICCR0 R/W I2C Interface 0 00011111B
797CH to
79A1H
Reserved
79A2HFlash Write Control Register 0 FWR0 R/W
Dual Operation
Flash
00000000B
79A3HFlash Write Control Register 1 FWR1 R/W 00000000B
79A4HSector Change Setting Register SSR0 R/W 00XXXXX0B
79A5H to
79C1H
Reserved
79C2HSetting Prohibited
79C3H to
79DFH
Reserved
79E0HDetect Address Setting Register 0 PADR0 R/W
Address Match
Detection 0
XXXXXXXXB
79E1HDetect Address Setting Register 0 PADR0 R/W XXXXXXXXB
79E2HDetect Address Setting Register 0 PADR0 R/W XXXXXXXXB
79E3HDetect Address Setting Register 1 PADR1 R/W XXXXXXXXB
79E4HDetect Address Setting Register 1 PADR1 R/W XXXXXXXXB
79E5HDetect Address Setting Register 1 PADR1 R/W XXXXXXXXB
79E6HDetect Address Setting Register 2 PADR2 R/W XXXXXXXXB
79E7HDetect Address Setting Register 2 PADR2 R/W XXXXXXXXB
79E8HDetect Address Setting Register 2 PADR2 R/W XXXXXXXXB
79E9H to
79EFH
Reserved
Document Number: 002-07872 Rev. *A Page 39 of 83
MB90350 Series
(Continued)
Notes :
■Initial value of “X” represents unknown value.
■Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results reading “X”.
Address Register Abbreviation Access Resource name Initial value
79F0HDetect Address Setting Register 3 PADR3 R/W
Address Match
Detection 1
XXXXXXXXB
79F1HDetect Address Setting Register 3 PADR3 R/W XXXXXXXXB
79F2HDetect Address Setting Register 3 PADR3 R/W XXXXXXXXB
79F3HDetect Address Setting Register 4 PADR4 R/W XXXXXXXXB
79F4HDetect Address Setting Register 4 PADR4 R/W XXXXXXXXB
79F5HDetect Address Setting Register 4 PADR4 R/W XXXXXXXXB
79F6HDetect Address Setting Register 5 PADR5 R/W XXXXXXXXB
79F7HDetect Address Setting Register 5 PADR5 R/W XXXXXXXXB
79F8HDetect Address Setting Register 5 PADR5 R/W XXXXXXXXB
79F9H to
7BFFH
Reserved
7C00H to
7CFFH
Reserved for CAN Interface 1. Refer to “CAN Controllers”
7D00H to
7DFFH
Reserved for CAN Interface 1. Refer to “CAN Controllers”
7E00H to
7FFFH
Reserved
Document Number: 002-07872 Rev. *A Page 40 of 83
MB90350 Series
13. CAN Controllers
The CAN controller has the following features :
■Conforms to CAN Specification Version 2.0 Part A and B
❐ Supports transmission/reception in standard frame and extended frame formats
■Supports transmitting of data frames by receiving remote frames
■16 transmitting/receiving message buffers
❐ 29-bit ID and 8-byte data
❐ Multi-level message buffer configuration
■Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance
mask
❐ Two acceptance mask registers in either standard frame format or extended frame formats
■Bit rate programmable from 10 Kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers
(Continued)
Address Register Abbreviation Access Initial Value
CAN1
000080HMessage buffer enable register BVALR R/W 00000000B
00000000B
000081H
000082HTransmit request register TREQR R/W 00000000B
00000000B
000083H
000084HTransmit cancel register TCANR W 00000000B
00000000B
000085H
000086HTransmission complete register TCR R/W 00000000B
00000000B
000087H
000088HReceive complete register RCR R/W 00000000B
00000000B
000089H
00008AHRemote request receiving register RRTRR R/W 00000000B
00000000B
00008BH
00008CHReceive overrun register ROVRR R/W 00000000B
00000000B
00008DH
00008EHReception interrupt
enable register RIER R/W 00000000B
00000000B
00008FH
007D00HControl status register CSR R/W, W
R/W, R
0XXXX0X1B
00XXX000B
007D01H
007D02HLast event indicator register LEIR R/W 000X0000B
XXXXXXXXB
007D03H
007D04HReceive/transmit error counter RTEC R 00000000B
00000000B
007D05H
007D06HBit timing register BTR R/W 11111111B
X1111111B
007D07H
007D08HIDE register IDER R/W XXXXXXXXB
XXXXXXXXB
007D09H
007D0AHTransmit RTR register TRTRR R/W 00000000B
00000000B
007D0BH
Document Number: 002-07872 Rev. *A Page 41 of 83
MB90350 Series
(Continued)
Address Register Abbreviation Access Initial Value
CAN1
007D0CHRemote frame receive waiting
register RFWTR R/W XXXXXXXXB
XXXXXXXXB
007D0DH
007D0EHTransmit interrupt
enable register TIER R/W 00000000B
00000000B
007D0FH
007D10H
Acceptance mask
select register AMSR R/W
XXXXXXXXB
XXXXXXXXB
007D11H
007D12HXXXXXXXXB
XXXXXXXXB
007D13H
007D14H
Acceptance mask register 0 AMR0 R/W
XXXXXXXXB
XXXXXXXXB
007D15H
007D16HXXXXXXXXB
XXXXXXXXB
007D17H
007D18H
Acceptance mask register 1 AMR1 R/W
XXXXXXXXB
XXXXXXXXB
007D19H
007D1AHXXXXXXXXB
XXXXXXXXB
007D1BH
Document Number: 002-07872 Rev. *A Page 42 of 83
MB90350 Series
List of Message Buffers (ID Registers)
(Continued)
Address Register Abbreviation Access Initial Value
CAN1
007C00H
to
007C1FH
General-purpose RAM — R/W
XXXXXXXXB
to
XXXXXXXXB
007C20H
ID register 0 IDR0 R/W
XXXXXXXXB
XXXXXXXXB
007C21H
007C22HXXXXXXXXB
XXXXXXXXB
007C23H
007C24H
ID register 1 IDR1 R/W
XXXXXXXXB
XXXXXXXXB
007C25H
007C26HXXXXXXXXB
XXXXXXXXB
007C27H
007C28H
ID register 2 IDR2 R/W
XXXXXXXXB
XXXXXXXXB
007C29H
007C2AHXXXXXXXXB
XXXXXXXXB
007C2BH
007C2CH
ID register 3 IDR3 R/W
XXXXXXXXB
XXXXXXXXB
007C2DH
007C2EHXXXXXXXXB
XXXXXXXXB
007C2FH
007C30H
ID register 4 IDR4 R/W
XXXXXXXXB
XXXXXXXXB
007C31H
007C32HXXXXXXXXB
XXXXXXXXB
007C33H
007C34H
ID register 5 IDR5 R/W
XXXXXXXXB
XXXXXXXXB
007C35H
007C36HXXXXXXXXB
XXXXXXXXB
007C37H
007C38H
ID register 6 IDR6 R/W
XXXXXXXXB
XXXXXXXXB
007C39H
007C3AHXXXXXXXXB
XXXXXXXXB
007C3BH
007C3CH
ID register 7 IDR7 R/W
XXXXXXXXB
XXXXXXXXB
007C3DH
007C3EHXXXXXXXXB
XXXXXXXXB
007C3FH
007C40H
ID register 8 IDR8 R/W
XXXXXXXXB
XXXXXXXXB
007C41H
007C42HXXXXXXXXB
XXXXXXXXB
007C43H
Document Number: 002-07872 Rev. *A Page 43 of 83
MB90350 Series
(Continued)
Address Register Abbreviation Access Initial Value
CAN1
007C44H
ID register 9 IDR9 R/W
XXXXXXXXB
XXXXXXXXB
007C45H
007C46HXXXXXXXXB
XXXXXXXXB
007C47H
007C48H
ID register 10 IDR10 R/W
XXXXXXXXB
XXXXXXXXB
007C49H
007C4AHXXXXXXXXB
XXXXXXXXB
007C4BH
007C4CH
ID register 11 IDR11 R/W
XXXXXXXXB
XXXXXXXXB
007C4DH
007C4EHXXXXXXXXB
XXXXXXXXB
007C4FH
007C50H
ID register 12 IDR12 R/W
XXXXXXXXB
XXXXXXXXB
007C51H
007C52HXXXXXXXXB
XXXXXXXXB
007C53H
007C54H
ID register 13 IDR13 R/W
XXXXXXXXB
XXXXXXXXB
007C55H
007C56HXXXXXXXXB
XXXXXXXXB
007C57H
007C58H
ID register 14 IDR14 R/W
XXXXXXXXB
XXXXXXXXB
007C59H
007C5AHXXXXXXXXB
XXXXXXXXB
007C5BH
007C5CH
ID register 15 IDR15 R/W
XXXXXXXXB
XXXXXXXXB
007C5DH
007C5EHXXXXXXXXB
XXXXXXXXB
007C5FH
Document Number: 002-07872 Rev. *A Page 44 of 83
MB90350 Series
List of Message Buffers (DLC Registers and Data Registers)
(Continued)
Address Register Abbreviation Access Initial Value
CAN1
007C60HDLC register 0 DLCR0 R/W XXXXXXXXB
007C61H
007C62HDLC register 1 DLCR1 R/W XXXXXXXXB
007C63H
007C64HDLC register 2 DLCR2 R/W XXXXXXXXB
007C65H
007C66HDLC register 3 DLCR3 R/W XXXXXXXXB
007C67H
007C68HDLC register 4 DLCR4 R/W XXXXXXXXB
007C69H
007C6AHDLC register 5 DLCR5 R/W XXXXXXXXB
007C6BH
007C6CHDLC register 6 DLCR6 R/W XXXXXXXXB
007C6DH
007C6EHDLC register 7 DLCR7 R/W XXXXXXXXB
007C6FH
007C70HDLC register 8 DLCR8 R/W XXXXXXXXB
007C71H
007C72HDLC register 9 DLCR9 R/W XXXXXXXXB
007C73H
007C74HDLC register 10 DLCR10 R/W XXXXXXXXB
007C75H
007C76HDLC register 11 DLCR11 R/W XXXXXXXXB
007C77H
007C78HDLC register 12 DLCR12 R/W XXXXXXXXB
007C79H
007C7AHDLC register 13 DLCR13 R/W XXXXXXXXB
007C7BH
007C7CHDLC register 14 DLCR14 R/W XXXXXXXXB
007C7DH
007C7EHDLC register 15 DLCR15 R/W XXXXXXXXB
007C7FH
007C80H
to
007C87H
Data register 0
(8 bytes) DTR0 R/W
XXXXXXXXB
to
XXXXXXXXB
Document Number: 002-07872 Rev. *A Page 45 of 83
MB90350 Series
Address Register Abbreviation Access Initial Value
CAN1
007C88H
to
007C8FH
Data register 1
(8 bytes) DTR1 R/W
XXXXXXXXB
to
XXXXXXXXB
007C90H
to
007C97H
Data register 2
(8 bytes) DTR2 R/W
XXXXXXXXB
to
XXXXXXXXB
007C98H
to
007C9FH
Data register 3
(8 bytes) DTR3 R/W
XXXXXXXXB
to
XXXXXXXXB
007CA0H
to
007CA7H
Data register 4
(8 bytes) DTR4 R/W
XXXXXXXXB
to
XXXXXXXXB
007CA8H
to
007CAFH
Data register 5
(8 bytes) DTR5 R/W
XXXXXXXXB
to
XXXXXXXXB
007CB0H
to
007CB7H
Data register 6
(8 bytes) DTR6 R/W
XXXXXXXXB
to
XXXXXXXXB
007CB8H
to
007CBFH
Data register 7
(8 bytes) DTR7 R/W
XXXXXXXXB
to
XXXXXXXXB
007CC0H
to
007CC7H
Data register 8
(8 bytes) DTR8 R/W
XXXXXXXXB
to
XXXXXXXXB
007CC8H
to
007CCFH
Data register 9
(8 bytes) DTR9 R/W
XXXXXXXXB
to
XXXXXXXXB
007CD0H
to
007CD7H
Data register 10
(8 bytes) DTR10 R/W
XXXXXXXXB
to
XXXXXXXXB
007CD8H
to
007CDFH
Data register 11
(8 bytes) DTR11 R/W
XXXXXXXXB
to
XXXXXXXXB
007CE0H
to
007CE7H
Data register 12
(8 bytes) DTR12 R/W
XXXXXXXXB
to
XXXXXXXXB
007CE8H
to
007CEFH
Data register 13
(8 bytes) DTR13 R/W
XXXXXXXXB
to
XXXXXXXXB
007CF0H
to
007CF7H
Data register 14
(8 bytes) DTR14 R/W
XXXXXXXXB
to
XXXXXXXXB
007CF8H
to
007CFFH
Data register 15
(8 bytes) DTR15 R/W
XXXXXXXXB
to
XXXXXXXXB
Document Number: 002-07872 Rev. *A Page 46 of 83
MB90350 Series
14. Interrupt Factors, Interrupt Vectors, Interrupt Control Register
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Interrupt cause
EI2OS
corre-
sponding
DMA ch
number
Interrupt vector Interrupt control
register
Number Address Number Address
Reset N — #08 FFFFDCH——
INT9 instruction N — #09 FFFFD8H——
Exception N — #10 FFFFD4H——
Reserved N — #11 FFFFD0HICR00 0000B0H
Reserved N — #12 FFFFCCH
CAN 1 RX / Input Capture 6 Y1 — #13 FFFFC8HICR01 0000B1H
CAN 1 TX/NS / Input Capture 7 Y1 — #14 FFFFC4H
I2C N — #15 FFFFC0HICR02 0000B2H
Reserved N — #16 FFFFBCH
16-bit Reload Timer 0 Y1 0 #17 FFFFB8HICR03 0000B3H
16-bit Reload Timer 1 Y1 1 #18 FFFFB4H
16-bit Reload Timer 2 Y1 2 #19 FFFFB0HICR04 0000B4H
16-bit Reload Timer 3 Y1 — #20 FFFFACH
PPG 4/5 N — #21 FFFFA8HICR05 0000B5H
PPG 6/7 N — #22 FFFFA4H
PPG 8/9/C/D N — #23 FFFFA0HICR06 0000B6H
PPG A/B/E/F N — #24 FFFF9CH
Timebase Timer N — #25 FFFF98HICR07 0000B7H
External Interrupt 8 to 11 Y1 3 #26 FFFF94H
Watch Timer N — #27 FFFF90HICR08 0000B8H
External Interrupt 12 to 15 Y1 4 #28 FFFF8CH
A/D Converter Y1 5 #29 FFFF88HICR09 0000B9H
I/O Timer 0 / I/O Timer 1 N — #30 FFFF84H
Input Capture 4/5 Y1 6 #31 FFFF80HICR10 0000BAH
Output Compare 4/5 Y1 7 #32 FFFF7CH
Input Capture 0/1 Y1 8 #33 FFFF78HICR11 0000BBH
Output Compare 6/7 Y1 9 #34 FFFF74H
Reserved N 10 #35 FFFF70HICR12 0000BCH
Reserved N 11 #36 FFFF6CH
UART 3 RX Y2 12 #37 FFFF68HICR13 0000BDH
UART 3 TX Y1 13 #38 FFFF64H
UART 2 RX Y2 14 #39 FFFF60HICR14 0000BEH
UART 2 TX Y1 15 #40 FFFF5CH
Flash Memory N — #41 FFFF58HICR15 0000BFH
Delayed interrupt N — #42 FFFF54H
Document Number: 002-07872 Rev. *A Page 47 of 83
MB90350 Series
Notes :
■The peripheral resources sharing the ICR register have the same interrupt level.
■When two peripheral resources share the ICR register, only one can use EI2OSat a time.
■When either of the two peripheral resources sharing the ICR register specifies EI2OS, the other one cannot use interrupts.
Document Number: 002-07872 Rev. *A Page 48 of 83
MB90350 Series
15. Electrical Characteristics
15.1 Absolute Maximum Ratings
(Continued)
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage*1
VCC VSS 0.3 VSS 6.0 V
AVCC VSS 0.3 VSS 6.0 V VCC AVCC*2
AVRH VSS 0.3 VSS 6.0 V AVCC ≥ AVRH*2
Input voltage*1VIVSS 0.3 VSS 6.0 V *3
Output voltage*1VOVSS 0.3 VSS 6.0 V *3
Maximum Clamp Current ICLAMP 4.0 4.0 mA *5
Total Maximum Clamp Current |ICLAMP|— 40 mA*5
“L” level maximum output current IOL —15mA*4
“L” level average output current IOLAV —4mA*4
“L” level maximum overall output current IOL —100mA*4
“L” level average overall output current IOLAV —50mA*4
“H” level maximum output current IOH —15 mA *4
“H” level average output current IOHAV —4mA*4
“H” level maximum overall output current IOH —100 mA *4
“H” level average overall output current IOHAV —50 mA *4
Power consumption PD
—240mW
MB90F351(S), MB90F352(S)
105 °C < TA ≤ 125 °C,
Normal operation : maximum
frequency 16 MHz
—320mW
MB90F351(S), MB90F352(S)
40 °C < TA ≤ 105 °C,
Normal operation : maximum
frequency 24 MHz
— 320 mW Device other than above
Operating temperature TA
40 105 °C
40 125 °C *6
Storage temperature TSTG 55 150 °C
Document Number: 002-07872 Rev. *A Page 49 of 83
MB90350 Series
(Continued)
*1: This parameter is based on VSS AVSS 0 V
*2: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs
does not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from
an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.
*4: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67
*5: • Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45,
P50 to P56 (for evaluation device : P50 to P55) , P60 to P67
• Use within recommended operating conditions.
• Use at DC voltage (current)
•The
B signal should always be applied a limiting resistance placed between the B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the B signal is applied the input current to the microcontroller
pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the B input potential may pass
through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
• Note that if a B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided
from the pins, so that incomplete operation may result.
• Note that if the B input is applied during power-on, the power supply is provided from the pins and the resulting power supply
voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the B input pin open.
• Sample recommended circuits:
*6 : If used exceeding TA 105 °C, be sure to contact sales for reliability limitations.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
V
CC
R
■Input/output equivalent circuits
B input (0 V to 16 V)
Limiting
resistance
Protective diode
Document Number: 002-07872 Rev. *A Page 50 of 83
MB90350 Series
15.2 Recommended Operating Conditions
(VSS AVSS 0 V)
* : If used exceeding TA 105 °C, be sure to contact sales for reliability limitations.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Typ Max
Power supply voltage VCC,
AVCC
4.0 5.0 5.5 V Under normal operation
3.5 5.0 5.5 V Under normal operation, when not using the A/D
converter and not Flash programming.
4.5 5.0 5.5 V When External bus is used.
3.0 — 5.5 V Maintains RAM data in stop mode
Smooth capacitor CS0.1 — 1.0 μF
Use a ceramic capacitor or capacitor of better AC
characteristics. Bypass capacitor at the VCC pin
should be greater than this capacitor.
Operating temperature TA
40 — 105 °C MB90F352(S) fCP ≤ 24MHz
40 — 125 °C *, MB90F352(S) fCP ≤ 16MHz,
Devices with A-suffix
C
CS
■C Pin Connection Diagram
24
16
− 40 +105 +125
Operation guaranteed range
Operation temperature T
A
(°C)
Internal clock f
CP
(MHz)
MB90F351(S),
MB90F352(S)
Device other
than above
Document Number: 002-07872 Rev. *A Page 51 of 83
MB90350 Series
15.3 DC Characteristics
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(Continued)
Parameter Symbol Pin Condition Value Unit Remarks
Min Typ Max
Input H
voltage
(At VCC
5 V 10%)
VIHS — — 0.8 VCC —V
CC 0.3 V
Pin inputs if CMOS
hysteresis input levels are
selected (except P12, P15,
P44, P45, P50)
VIHA — — 0.8 VCC —V
CC 0.3 V
Pin inputs if
AUTOMOTIVE input
levels are selected
VIHT ——2.0—V
CC 0.3 V Pin inputs if TTL input levels
are selected
VIHS — — 0.7 VCC —V
CC 0.3 V P12, P15, P50 inputs if CMOS
input levels are selected
VIHI — — 0.7 VCC —V
CC 0.3 V
P44, P45 inputs if CMOS
hysteresis input levels are
selected
VIHR — — 0.8 VCC —V
CC 0.3 V RST input pin (CMOS
hysteresis)
VIHM ——V
CC 0.3 — VCC 0.3 V MD input pin
Input L
voltage
(At VCC
5 V 10%)
VILS ——V
SS 0.3 — 0.2 VCC V
Pin inputs if CMOS
hysteresis input levels are
selected (except P12, P15,
P44, P45, P50)
VILA ——V
SS 0.3 — 0.5 VCC V
Pin inputs if
AUTOMOTIVE input
levels are selected
VILT ——V
SS 0.3 — 0.8 V Pin inputs if TTL
input levels are selected
VILS ——V
SS 0.3 — 0.3 VCC VP12, P15, P50 inputs if CMOS
input levels are selected
VILI ——V
SS 0.3 — 0.3 VCC V
P44, P45 inputs if CMOS
hysteresis input levels are
selected
VILR ——V
SS 0.3 — 0.2 VCC VRST input pin (CMOS
hysteresis)
VILM ——V
SS 0.3 — VSS 0.3 V MD input pin
Output H
voltage VOH
Normal
outputs
VCC 4.5 V,
IOH 4.0 mA VCC 0.5 — — V
Output H
voltage VOHI
I2C current
outputs
VCC 4.5 V,
IOH 3.0 mA VCC 0.5 — — V
Document Number: 002-07872 Rev. *A Page 52 of 83
MB90350 Series
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(Continued)
Parameter Symbol Pin Condition Value Unit Remarks
Min Typ Max
Output L
voltage VOL
Normal
outputs
VCC 4.5 V,
IOL 4.0 mA ——0.4V
Output L
voltage VOLI
I2C current
outputs
VCC 4.5 V,
IOL 3.0 mA ——0.4V
Input leak
current IIL —VCC 5.5 V,
VSS<VI<VCC
1— 1 µA
Pull-up
resistance RUP
P00 to P07,
P10 to P17,
P20 to P25,
P30 to P37,
RST
— 25 50 100 kΩ
Pull-down
resistance RDOWN MD2 — 25 50 100 kΩExcept Flash
memory devices
Power supply
current
ICC
VCC
VCC 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
—4860mA
VCC 5.0 V,
Internal frequency : 24 MHz,
At writing FLASH memory.
—5365mA
Flash memory
devices
VCC 5.0 V,
Internal frequency : 24 MHz,
At erasing FLASH memory.
—5870mA
Flash memory
devices
ICCS
VCC 5.0 V,
Internal frequency : 24 MHz,
At Sleep mode.
—2535mA
ICTS
VCC 5.0 V,
Internal frequency : 2 MHz,
At Main Timer mode
—0.30.8mA
Devices
without
“T”-suffix
—0.41.0mA
Devices
with “T”-suffix
ICTSPLL
6
VCC 5.0 V,
Internal frequency : 24 MHz,
At PLL Timer mode,
external frequency 4 MHz
—4 7mA
ICCL
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
monitor function,
At sub clock operation
TA = 25C
— 70 140 μA
MB90F351
MB90F352
MB90F351A
MB90F352A
MB90F356A
MB90F357A
MB90351A
MB90352A
MB90356A
MB90357A
Document Number: 002-07872 Rev. *A Page 53 of 83
MB90350 Series
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(Continued)
Parameter Symbol Pin Condition Value Unit Remarks
Min Typ Max
Power supply
current
ICCL
VCC
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
monitor function,
At sub clock operation
TA = 25C
— 100 200 µA
MB90F356A
MB90F357A
MB90356A
MB90357A
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At sub clock operation
TA = 25C
— 100 200 µA
MB90F356AS
MB90F357AS
MB90356AS
MB90357AS
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
monitor function,
At sub clock operation
TA = 25C
— 120 240 µA
MB90F351TA
MB90F352TA
MB90F356TA
MB90F357TA
MB90351TA
MB90352TA
MB90356TA
MB90357TA
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
monitor function,
At sub clock operation
TA = 25C
— 150 300 µA
MB90F356TA
MB90F357TA
MB90356TA
MB90357TA
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At sub clock operation
TA = 25C
— 150 300 µA
MB90F356TAS
MB90F357TAS
MB90356TAS
MB90357TAS
ICCLS
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
monitor function,
At sub sleep
TA = 25C
—2050μA
MB90F351
MB90F352
MB90F351A
MB90F352A
MB90F356A
MB90F357A
MB90351A
MB90352A
MB90356A
MB90357A
Document Number: 002-07872 Rev. *A Page 54 of 83
MB90350 Series
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(Continued)
Parameter Symbol Pin Condition Value Unit Remarks
Min Typ Max
Power supply
current
ICCLS
VCC
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock monitor
function,
At sub sleep
TA = 25C
— 60 200 μA
MB90F356A
MB90F357A
MB90356A
MB90357A
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At sub sleep
TA = 25C
— 60 200 μA
MB90F356AS
MB90F357AS
MB90356AS
MB90357AS
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
monitor function,
At sub sleep
TA = 25C
— 70 150 μA
MB90F351TA
MB90F352TA
MB90F356TA
MB90F357TA
MB90351TA
MB90352TA
MB90356TA
MB90357TA
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
monitor function,
At sub sleep
TA = 25C
— 110 300 μA
MB90F356TA
MB90F357TA
MB90356TA
MB90357TA
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At sub sleep
TA = 25C
— 110 300 μA
MB90F356TAS
MB90F357TAS
MB90356TAS
MB90357TAS
ICCT
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
monitor function,
At watch mode
TA = 25C
—1035μA
MB90F351
MB90F352
MB90F351A
MB90F352A
MB90F356A
MB90F357A
MB90351A
MB90352A
MB90356A
MB90357A
Document Number: 002-07872 Rev. *A Page 55 of 83
MB90350 Series
(Continued)
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Parameter Symbol Pin Condition Value Unit Remarks
Min Typ Max
Power supply
current
ICCT
VCC
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock monitor
function,
At watch mode
TA = 25C
— 25 150 μA
MB90F356A
MB90F357A
MB90356A
MB90357A
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At watch mode
TA = 25C
— 25 150 μA
MB90F356AS
MB90F357AS
MB90356AS
MB90357AS
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
monitor function,
At watch mode
TA = 25C
— 60 140 μA
MB90F351TA
MB90F352TA
MB90F356TA
MB90F357TA
MB90351TA
MB90352TA
MB90356TA
MB90357TA
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock monitor
function,
At watch mode
TA = 25C
— 80 250 μA
MB90F356TA
MB90F357TA
MB90356TA
MB90357TA
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At watch mode
TA = 25C
— 80 250 μA
MB90F356TAS
MB90F357TAS
MB90356TAS
MB90357TAS
ICCH
VCC 5.0 V,
At Stop mode,
TA 25C
—725μA
Devices
without
“T”-suffix
— 60 130 μADevices
with “T”-suffix
Input capacity CIN
Other than C, AVCC, AVSS,
AVRH, VCC, VSS, ——515pF
Document Number: 002-07872 Rev. *A Page 56 of 83
MB90350 Series
15.4 AC Characteristics
15.4.1 Clock Timing
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(Continued)
Parameter Symbol Pin Value Unit Remarks
Min Typ Max
Clock frequency fC
X0, X1
3—16MHz
1/2 (at PLL stop)
When using an oscillation circuit
4—16MHz
1 multiplied PLL
When using an oscillation circuit
4—12MHz
2 multiplied PLL
When using an oscillation circuit
4—8MHz
3 multiplied PLL
When using an oscillation circuit
4—6MHz
4 multiplied PLL
When using an oscillation circuit
—— 4MHz
6 multiplied PLL
When using an oscillation circuit
X0
3—24MHz
1/2 (at PLL stop),
When using an external clock
4—24MHz
1 multiplied PLL
When using an external clock
4—12MHz
2 multiplied PLL
When using an external clock
4—8MHz
3 multiplied PLL
When using an external clock
4—6MHz
4 multiplied PLL
When using an external clock
—— 4MHz
6 multiplied PLL
When using an external clock
fCL X0A, X1A — 32.768 100 kHz
Clock cycle time tCYL
X0, X1 62.5 — 333 ns When using an oscillation circuit
X0 41.67 — 333 ns When using an external clock
tCYLL X0A, X1A 10 30.5 — s
Input clock pulse width PWH, PWL X0 10 — — ns Duty ratio is about 30% to 70%.
PWHL, PWLL X0A 5 15.2 — s
Input clock rise and fall
time tCR, tCF X0 — — 5 ns When using an external clock
Document Number: 002-07872 Rev. *A Page 57 of 83
MB90350 Series
(Continued)
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Parameter Symbol Pin Value Unit Remarks
Min Typ Max
Internal operating clock
frequency
(machine clock)
fCP —
1.5 —
24
MHz
MB90F352/(S), MB90F351/(S)
When using main clock
(TA ≤ 105 °C)
16
MB90F352/(S), MB90F351/(S)
When using main clock
(TA ≤ 125 °C)
1.5 — 24 MHz Device other than above,
When using main clock
fCPL — — 8.192 50 kHz When using sub clock
Internal operating clock
cycle time
(machine clock)
tCP —
41.67
— 666 ns
MB90F352/(S), MB90F351/(S)
When using main clock
(TA ≤ 105 °C)
62.5
MB90F352/(S), MB90F351/(S)
When using main clock
(TA ≤ 125 °C)
41.67 — 666 ns Device other than above,
When using main clock
tCPL — 20 122.1 — s When using sub clock
X0
t
CYL
t
CF
t
CR
0.8 V
CC
0.2 V
CC
P
WH
P
WL
X0A
t
CYLL
t
CF
t
CR
0.8 V
CC
0.2 V
CC
P
WHL
P
WLL
■Clock Timing
Document Number: 002-07872 Rev. *A Page 58 of 83
MB90350 Series
■ PLL guaranteed operation range
Guaranteed operation range of MB90350 series
*1 : Guaranteed 1 multiplied PLL operation range is 4.0 MHz to 20 MHz.
*2 : When using crystal oscillator or ceramic oscillator, the maximum clock frequency is 16 MHz.
External clock frequency and internal operation clock frequency
5.5
3.5
41.5 24
4.5
820
Guaranteed A/D converter
operation range
Guaranteed PLL operation range (CS2=0)
Guaranteed PLL operation range (CS2=1)
Guaranteed operation range
Power supply voltage VCC (V)
Internal clock fCP (MHz)
20
16
12
8
4.0
1.5
34 8 24
12 20
×1/2
(PLL off)
16
Guaranteed oscillation frequency range
4 multiplied
(CS=11)
3 multiplied
(CS=10)
2 multiplied
(CS=01)
1 multiplied
(CS=00)
Internal clock fCP (MHz)
External clock fC (MHz) *1
CS2(bit0 of PSCCR register) = 0
24
16
12
8
4.0
1.5
34 8 24
12 16
×1/2
(PLL off)
Guaranteed oscillation frequency range
6 multiplied
(CS=10)
4 multiplied
(CS=01)
2 multiplied
(CS=00)
Internal clock fCP (MHz)
External clock fC (MHz) *2
CS2(bit0 of PSCCR register) = 1
Document Number: 002-07872 Rev. *A Page 59 of 83
MB90350 Series
15.4.2 Reset Standby Input
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
* : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillators, the oscillation time
is between hundreds of μs to several ms. With an external clock, the oscillation time is 0 ms.
Parameter Symbol Pin Value Unit Remarks
Min Max
Reset input time tRSTL RST
500 — ns Under normal operation
Oscillation time of oscillator*
100 μs—μs
In Stop mode, Sub Clock
mode, Sub Sleep mode and
Watch mode
100 — μsIn Main timer mode and PLL
timer mode
tRSTL
0.2 VCC 0.2 VCC
RST
X0
90% of
amplitude
Instruction execution
Oscillation stabilization
waiting time
Oscillation time
of oscillator
Internal operation
clock
Internal reset
100 μs
0.2 VCC
RST
tRSTL
0.2 VCC
Under normal operation:
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
Document Number: 002-07872 Rev. *A Page 60 of 83
MB90350 Series
15.4.3 Power On Reset
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
15.4.4 Clock Output Timing
(TA 40 °C to 105 °C, VCC 5.0 V 10%, VSS 0.0 V, fCP ≤ 24 MHz)
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Power on rise time tRVCC —0.05 30 ms
Power off time tOFF VCC 1 — ms Due to repetitive operation
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Cycle time tCYC CLK — 62.5 — ns fCP 16 MHz
41.67 — ns fCP 24 MHz
CLK ↑ → CLK ↓tCHCL CLK — 20 — ns fCP 16 MHz
13 — ns fCP 24 MHz
VCC
VCC
VSS
3 V
tR
tOFF
2.7 V
0.2 V 0.2 V0.2 V
Holds RAM data
If you change the power supply voltage too rapidly, a power on reset may occur.
We recommend that you start up smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However, if voltage drops are within 1 V/s, you can
operate while using the PLL clock.
We recommend the slope for
a rise of 50 mV/ms maximum.
CLK 2.4 V
t
CYC
2.4 V
0.8 V
t
CHCL
Document Number: 002-07872 Rev. *A Page 61 of 83
MB90350 Series
15.4.5 Bus Timing (Read)
(TA = –40C to +105C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
* : n: number of ready cycles
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
ALE pulse width tLHLL ALE
—
tCP/2 10 — ns
Valid address → ALE time tAVLL
ALE, A21 to
A16, AD15 to
AD00
tCP/2 20 — ns
ALE → Address valid time tLLAX
ALE, AD15 to
AD00 tCP/2 15 — ns
Valid address → RD time tAVRL
A21 toA16,
AD15 to AD00,
RD
tCP 15 — ns
Valid address → Valid data input tAVDV
A21 to A16,
AD15 to AD00 —5 t
CP/2 60 ns
RD pulse width tRLRH RD (n*+3/2) tCP 20 — ns
RD → Valid data input tRLDV
RD, AD15 to
AD00 —(n*+3/2) t
CP 50 ns
RD → Data hold time tRHDX
RD, AD15 to
AD00 0—ns
RD → ALE time tRHLH RD, ALE tCP/2 15 — ns
RD → Address valid time tRHAX RD, A21 to A16 tCP/2 10 — ns
Valid address → CLK time tAVCH
A21 to A16,
AD15 to AD00,
CLK
tCP/2 16 — ns
RD → CLK time tRLCH RD, CLK tCP/2 15 — ns
ALE → RD time tLLRL ALE, RD tCP/2 15 — ns
Document Number: 002-07872 Rev. *A Page 62 of 83
MB90350 Series
A21 to A16
0.8 V
2.4 V
2.4 V
0.8 V
tRHAX
AD15 to AD00 0.8 V
2.4 V 2.4 V
0.8 V Address VIL
VIH VIH
VIL
Read data
tRHDX
tRLDV
tAVDV
CLK
tAVCH
2.4 V
tRLCH
2.4 V
ALE 2.4 V
tLHLL
2.4 V
tRHLH
0.8 V
tLLAX
2.4 V
tAVLL
RD
tLLRL
tRLRH
0.8 V
2.4 V
tAVRL
For 1 cycle of auto-ready
Document Number: 002-07872 Rev. *A Page 63 of 83
MB90350 Series
15.4.6 Bus Timing (Write)
(TA = –40C to +105C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
* : n: Number of ready cycles
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Valid address → WR time tAVWL
A21 to A16, AD15
to AD00, WR
—
tCP15 — ns
WR pulse width tWLWH WR (n*+3/2)tCP 20 — ns
Valid data output → WR time tDVWH
AD15 to AD00,
WR (n*+3/2)tCP 20 — ns
WR → Data hold time tWHDX
AD15 to AD00,
WR 15 — ns
WR → Address valid time tWHAX A21 to A16, WR tCP/2 10 — ns
WR → ALE time tWHLH WR, ALE tCP/2 15 — ns
WR → CLK time tWLCH WR, CLK tCP/2 15 — ns
CLK
tWLCH
2.4 V
ALE
tWHLH
2.4 V
WR (WRL, WRH)
tWLWH
0.8 V
2.4 V
tAVWL
A21 to A16
0.8 V
2.4 V
2.4 V
0.8 V
tWHAX
AD15 to AD00 2.4 V
0.8 V Address 0.8 V
2.4 V
Write data
tDVWH
0.8 V
2.4 V
tWHDX
For 1 cycle of auto-ready
Document Number: 002-07872 Rev. *A Page 64 of 83
MB90350 Series
15.4.7 Ready Input Timing
(TA = –40C to +105C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Note : If the RDY set-up time is insufficient, use the auto-ready function.
Parameter Symbol Pin Condition Value Units Remarks
Min Max
RDY set-up time tRYHS RDY —
45 — ns fCP 16 MHz
32 — ns fCP 24 MHz
RDY hold time tRYHH RDY 0 — ns
CLK 2.4 V
ALE
RD/WR
RDY
(When WAIT is not used.)
VIH VIH
tRYHH
RDY
(When WAIT is used.)
tRYHS
VIL
Document Number: 002-07872 Rev. *A Page 65 of 83
MB90350 Series
15.4.8 Hold Timing
(TA = –40C to +105C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Note : There is more than 1 machine cycle from when HRQ pin reads in until the HAK is changed.
Parameter Symbol Pin Condition Value Units Remarks
Min Max
Pin floating → HAK time tXHAL HAK —30 tCP ns
HAK time → Pin valid time tHAHV HAK tCP 2 tCP ns
HAK
Each pin
Hi-Z
tHAHV
tXHAL
2.4 V
0.8 V
2.4 V 2.4 V
0.8 V 0.8 V
Document Number: 002-07872 Rev. *A Page 66 of 83
MB90350 Series
15.4.9 UART 2/3
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
* : Refer to “ (1) Clock timing” rating for tCP (internal operating clock cycle time).
Notes :
■AC characteristic in CLK synchronized mode.
■CL is load capacity value of pins when testing.
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Serial clock cycle time tSCYC SCK2, SCK3
Internal shift clock
mode output pins are
CL 80 pF 1 TTL
8 tCP*— ns
SCK ↓ → SOT delay time tSLOV
SCK2, SCK3,
SOT2, SOT3 80 80 ns
Valid SIN → SCK ↑tIVSH
SCK2, SCK3,
SIN2, SIN3 100 — ns
SCK ↑ → Valid SIN hold time tSHIX
SCK2, SCK3,
SIN2, SIN3 60 — ns
Serial clock “H” pulse width tSHSL SCK2, SCK3
External shift clock
mode output pins are
CL 80 pF 1 TTL
4 tCP —ns
Serial clock “L” pulse width tSLSH SCK2, SCK3 4 tCP —ns
SCK ↓ → SOT delay time tSLOV
SCK2, SCK3,
SOT2, SOT3 — 150 ns
Valid SIN → SCK ↑tIVSH
SCK2, SCK3,
SIN2, SIN3 60 — ns
SCK ↑ → Valid SIN hold time tSHIX
SCK2, SCK3,
SIN2, SIN3 60 — ns
■Internal Shift Clock Mode
SCK 2.4 V
tSCYC
0.8 V
SOT
0.8 V
2.4 V
0.8 V
tSLOV
SIN VIL
VIH
tIVSH
VIL
VIH
tSHIX
Document Number: 002-07872 Rev. *A Page 67 of 83
MB90350 Series
15.4.10 Trigger Input Timing
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Input pulse width tTRGH
tTRGL
INT8 to INT15,
INT9R to INT11R,
ADTG
—5 t
CP —ns
■External Shift Clock Mode
SCK VIH
tSLSH
VIL
SOT
0.8 V
2.4 V
tSLOV
SIN VIL
VIH
tIVSH
VIL
VIH
tSHIX
VIH
VIL
tSHSL
VIL
VIH
tTRGH
VIL
VIH
tTRGL
INT8 to INT15,
INT9R to INT11R,
ADTG
Document Number: 002-07872 Rev. *A Page 68 of 83
MB90350 Series
15.4.11 Timer Related Resource Input Timing
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
15.4.12 Timer Related Resource Output Timing
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Input pulse width
tTIWH TIN1, TIN3,
IN0, IN1,
IN4 to IN7
—4 t
CP —ns
tTIWL
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
CLK → TOUT change time tTO
TOT1, TOT3,
PPG4, PPG6,
PPG8 to PPGF
—30—ns
VIL
VIH
tTIWH
VIL
VIH
tTIWL
TIN1, TIN3,
IN0, IN1,
IN4 to IN7
CLK 2.4 V
0.8 V
2.4 V
tTO
TOT1, TOT3,
PPG4, PPG6
PPG8 to PPGF
Document Number: 002-07872 Rev. *A Page 69 of 83
MB90350 Series
15.4.13 I2C Timing
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, VCC AVCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, VCC AVCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(Device other than above: TA 40 °C to 125 °C, VCC AVCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT has only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C -bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
*5 : Refer to “Note of SDA, SCL set-up time”.
Parameter Symbol Condition Standard-mode Fast-mode*4
Unit
Min Max Min Max
SCL clock frequency fSCL
R 1.7 kΩ,
C 50 pF*1
0 100 0 400 kHz
Hold time for (repeated) START condition
SDA↓→SCL↓tHDSTA 4.0 — 0.6 — μs
“L” width of the SCL clock tLOW 4.7 — 1.3 — μs
“H” width of the SCL clock tHIGH 4.0 — 0.6 — μs
Set-up time for a repeated START condition
SCL↑→SDA↓tSUSTA 4.7 — 0.6 — μs
Data hold time
SCL↓→SDA↓↑ tHDDAT 0 3.45*200.9*
3μs
Data set-up time
SDA↓↑→SCL↑tSUDAT 250*5—100*
5—ns
Set-up time for STOP condition
SCL↑→SDA↑tSUSTO 4.0 — 0.6 — μs
Bus free time between STOP condition and START
condition tBUS 4.7 — 1.3 — μs
SDA
SCL
6 tcp
■Note of SDA, SCL set-up time
Input data set-up time
Document Number: 002-07872 Rev. *A Page 70 of 83
MB90350 Series
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on the load capacitance
or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be satisfied.
SDA
SCL
tBUF
tLOW
fSCL
tHDDAT tHIGH
tSUDAT
tHDSTA tSUSTA
tHDSTA
tSUSTO
■Timing definition
Document Number: 002-07872 Rev. *A Page 71 of 83
MB90350 Series
15.5 A/D Converter
(MB90F352(S)/MB90F351(S): TA 40 °C to 105 °C, 3.0 V ≤ AVRH, VCC AVCC 5.0 V 10%, fCP ≤ 24 MHz, VSS AVSS 0 V)
(MB90F352(S)/MB90F351(S): TA 40 °C to 125 °C, 3.0 V ≤ AVRH, VCC AVCC 5.0 V 10%, fCP ≤ 16 MHz, VSS AVSS 0 V)
(
Device other than above: TA
40 °C
to
125 °C
,
3.0 V ≤ AVRH, VCC
AVCC
5.0 V
10%
,
fCP ≤ 24 MHz, VSS
AVSS
0 V
)
* : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC AVCC AVRH 5.0 V) .
Parameter Symbol Pin Value Unit Remarks
Min Typ Max
Resolution — — — — 10 bit
Total error — — — — 3.0 LSB
Nonlinearity error — — — — 2.5 LSB
Differential
nonlinearity error —— — — 1.9 LSB
Zero reading
voltage VOT AN0 to AN14 AVSS
1.5 LSB
AVSS
0.5 LSB
AVSS
2.5 LSB V
Full scale reading
voltage VFST AN0 to AN14 AVRH
3.5 LSB
AVRH
1.5 LSB
AVRH
0.5 LSB V
Compare time — — 1.0 — 16,500 s4.5 V ≤ AVCC ≤ 5.5 V
2.0 4.0 V ≤ AVCC < 4.5 V
Sampling time — — 0.5 —¥s4.5 V ≤ AVCC ≤ 5.5 V
1.2 4.0 V ≤ AVCC < 4.5 V
Analog port input
current IAIN AN0 to AN14 0.3 — +0.3 A
Analog input
voltage range VAIN AN0 to AN14 AVSS —AVRHV
Reference
voltage range —AVRHAV
SS 2.7 — AVCC V
Power supply
current
IAAVCC —3.57.5mA
IAH AVCC —— 5μA*
Reference
voltage supply
current
IRAVRH — 600 900 μA
IRH AVRH — — 5 μA*
Offset between
input channels — AN0 to AN14 — — 4 LSB
Document Number: 002-07872 Rev. *A Page 72 of 83
MB90350 Series
Notes on A/D Converter Section
■About the external impedance of the analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage
charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship between the external
impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external
impedance so that the sampling time is longer than the minimum value. Also if the sampling time cannot be sufficient, connect a
capacitor of about 0.1 μF to the analog input pin.
· Analog input equivalence circuit
ON at sampling
Note : The value is reference value.
R
C
CR
Analog input Comparator
MB90F352(S), MB90F351A(S), MB90F352A(S), MB90F351TA(S), MB90F352TA(S),
MB90F356A(S), MB90F357A(S), MB90F356TA(S), MB90F357TA(S),
4.5 V AVCC 5.5 V 2.0 kΩ (Max) 16.0 pF (Max)
4.0 V AVCC 4.5 V 8.2 kΩ (Max) 16.0 pF (Max)
CR
MB90V340A-101/102/103/104, MB90351A(S), MB90352A(S), MB90351TA(S), MB90352TA(S),
MB90356A(S), MB90357A(S), MB90356TA(S), MB90357TA(S),
4.5 V AVCC 5.5 V 2.0 kΩ (Max) 14.4 pF (Max)
4.0 V AVCC 4.5 V 8.2 kΩ (Max) 14.4 pF (Max)
Document Number: 002-07872 Rev. *A Page 73 of 83
MB90350 Series
■Flash memory device
■MASK ROM device
■About the error
Values of relative errors grow larger, as |AVRH AVSS| becomes smaller.
· Relation between External impedance and minimum sampling time
4.5 V AVCC 5.5 V
[External impedance = 0 kΩ to 100 kΩ]
Minimum sampling time [μs]
External impedance [kΩ]
05 101520253035
10
20
30
40
50
60
70
80
90
100
4.0 V AVCC 4.5 V
4.5 V AVCC 5.5 V
[External impedance = 0 kΩ to 20 kΩ]
Minimum sampling time [μs]
External impedance [kΩ]
012345678
2
4
6
8
10
12
14
16
18
20
4.0 V AVCC 4.5 V
(MB90F352(S), MB90F351A(S), MB90F352A(S), MB90F351TA(S), MB90F352TA(S), MB90F356A(S),
MB90F357A(S), MB90F356TA(S), MB90F357TA(S))
00
· Relation between External impedance and minimum sampling time
4.5 V AVCC 5.5 V
[External impedance = 0 kΩ to 100 kΩ]
Minimum sampling time [μs]
External impedance [kΩ]
05 101520253035
10
20
30
40
50
60
70
80
90
100
4.0 V AVCC 4.5 V
4.5 V AVCC 5.5 V
[External impedance = 0 kΩ to 20kΩ]
Minimum sampling time [μs]
External impedance [kΩ]
012345678
2
4
6
8
10
12
14
16
18
20
4.0 V AVCC 4.5 V
(MB90V340A-101/102/103/104, MB90351A(S), MB90352A(S), MB90351TA(S), MB90352TA(S),
MB90356A(S), MB90357A(S), MB90356TA(S), MB90357TA(S))
00
Document Number: 002-07872 Rev. *A Page 74 of 83
MB90350 Series
15.6 Definition of A/D Converter Terms
(Continued)
Resolution : Analog variation that is recognized by an A/D converter.
Non linearity error : Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” ) and full-scale
transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion characteristics.
Differential
linearity error : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Tot al e r ro r : Difference between an actual value and a theoretical value. A total error includes zero transition error,
full-scale transition error, and linear error.
3FFH
3FEH
3FDH
004H
003H
002H
001H
AVSS AVRH
VNT
1.5 LSB
0.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
Actual conversion
characteristics
(Actual measurement value)
Actual conversion
characteristics
Ideal characteristics
Digital output
Analog input
Total error
Total error of digital output “N” VNT {1 LSB × (N 1) 0.5 LSB}
1 LSB [LSB]
1 LSB (Ideal value) AVRH AVSS
1024 [V]
VOT (Ideal value) AVSS 0.5 LSB [V]
VFST (Ideal value) AVRH 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N 1) to N.
N : A/D converter digital output value
Document Number: 002-07872 Rev. *A Page 75 of 83
MB90350 Series
(Continued)
3FFH
3FEH
3FDH
004H
003H
002H
001H
AVSS AVRH AVSS AVRH
N + 1
N
N − 1
N − 2
VOT (actual measurement value)
{1 LSB × (N − 1)
+ VOT }
Actual conversion
characteristics
VFST (actual
measurement
value)
VNT (actual
measurement value)
Actual conversion
characteristics
Ideal characteristics
Actual conversion
characteristics
Actual conversion
characteristics
Ideal
characteristics
Digital output
Digital output
Analog inputAnalog input
VNT
(actual measurement value)
V (N + 1) T
(actual measurement
value)
Non linearity error Differential linearity error
Non linearity error of digital output N VNT {1 LSB × (N 1) VOT}
1 LSB [LSB]
Differential linearity error of digital output N V (N+1) T VNT
1 LSB 1 LSB [LSB]
VFST VOT
1022 [V]1 LSB
N : A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
Document Number: 002-07872 Rev. *A Page 76 of 83
MB90350 Series
15.7 Flash Memory Program/Erase Characteristics
Flash Memory
* : This value comes from the technology qualification.
(Using Arrhenius equation to translate high temperature measurements into normalized value at 85 °C)
Dual Operation Flash Memory
* : This value comes from the technology qualification.
(Using Arrhenius equation to translate high temperature measurements into normalized value at 85 °C)
Parameter Conditions Value Unit Remarks
Min Typ Max
Sector erase time
TA 25 °C
VCC 5.0 V
—115s
Excludes programming prior to
erasure
Chip erase time — 9 — s Excludes programming prior to
erasure
Word (16-bit width)
programming time —163,600μsExcept for the overhead time of
the system level
Program/Erase cycle — 10,000 — — cycle
Flash Memory Data
Retention Time
Average
TA 85 °C 20 — — year *
Parameter Conditions Value Unit Remarks
Min Typ Max
Sector erase time
(4 Kbytes sector)
TA 25 °C
VCC 5.0 V
—0.20.5s
Excludes programming prior to
erasure
Sector erase time
(16 Kbytes sector) —0.57.5s
Excludes programming prior to
erasure
Chip erase time — 4.6 — s Excludes programming prior to
erasure
Word (16-bit width)
programming time — 64 3,600 μsExcept for the overhead time of
the system level
Program/Erase cycle — 10,000 — — cycle
Flash Memory Data
Retention Time
Average
TA 85 °C 20 — — year *
Document Number: 002-07872 Rev. *A Page 77 of 83
MB90350 Series
16. Ordering Information
(Continued)
Part number Package Remarks
MB90F351PMC
64-pin plastic LQFP
FPT-64P-M23
12mm, 0.65mm pitch
Flash memory products
(64 Kbytes)
MB90F351SPMC
MB90F352PMC Flash memory products
(128 Kbytes)
MB90F352SPMC
MB90F351APMC
64-pin plastic LQFP
FPT-64P-M23
12mm, 0.65mm pitch
Dual operation
Flash memory products
(64 Kbytes)
MB90F351ASPMC
MB90F351TAPMC
MB90F351TASPMC
MB90F356APMC
MB90F356ASPMC
MB90F356TAPMC
MB90F356TASPMC
MB90F352APMC
64-pin plastic LQFP
FPT-64P-M23
12mm, 0.65mm pitch
Dual operation
Flash memory products
(128 Kbytes)
MB90F352ASPMC
MB90F352TAPMC
MB90F352TASPMC
MB90F357APMC
MB90F357ASPMC
MB90F357TAPMC
MB90F357TASPMC
MB90351APMC
64-pin plastic LQFP
FPT-64P-M23
12mm, 0.65mm pitch
MASK ROM products
(64 Kbytes)
MB90351ASPMC
MB90351TAPMC
MB90351TASPMC
MB90356APMC
MB90356ASPMC
MB90356TAPMC
MB90356TASPMC
MB90352APMC
64-pin plastic LQFP
FPT-64P-M23
12mm, 0.65mm pitch
MASK ROM products
(128 Kbytes)
MB90352ASPMC
MB90352TAPMC
MB90352TASPMC
MB90357APMC
MB90357ASPMC
MB90357TAPMC
MB90357TASPMC
Document Number: 002-07872 Rev. *A Page 78 of 83
MB90350 Series
(Continued)
* : These devices are under development.
Part number Package Remarks
MB90F351APMC1
64-pin plastic LQFP
FPT-64P-M24
10 mm , 0.50 mm pitch
Dual operation
Flash memory products*
(64 Kbytes)
MB90F351ASPMC1
MB90F351TAPMC1
MB90F351TASPMC1
MB90F356APMC1
MB90F356ASPMC1
MB90F356TAPMC1
MB90F356TASPMC1
MB90F352APMC1
64-pin plastic LQFP
FPT-64P-M24
10 mm , 0.50 mm pitch
Dual operation
Flash memory products*
(128 Kbytes)
MB90F352ASPMC1
MB90F352TAPMC1
MB90F352TASPMC1
MB90F357APMC1
MB90F357ASPMC1
MB90F357TAPMC1
MB90F357TASPMC1
MB90351APMC1
64-pin plastic LQFP
FPT-64P-M24
10 mm , 0.50 mm pitch
MASK ROM products*
(64 Kbytes)
MB90351ASPMC1
MB90351TAPMC1
MB90351TASPMC1
MB90356APMC1
MB90356ASPMC1
MB90356TAPMC1
MB90356TASPMC1
MB90352APMC1
64-pin plastic LQFP
FPT-64P-M24
10 mm , 0.50 mm pitch
MASK ROM products*
(128 Kbytes)
MB90352ASPMC1
MB90352TAPMC1
MB90352TASPMC1
MB90357APMC1
MB90357ASPMC1
MB90357TAPMC1
MB90357TASPMC1
MB90V340A-101
299-pin ceramic PGA
PGA-299C-A01 Device for evaluation
MB90V340A-102
MB90V340A-103
MB90V340A-104
Document Number: 002-07872 Rev. *A Page 79 of 83
MB90350 Series
17. Package Dimensions
(Continued)
64-pin plastic LQFP Lead pitch 0.65 mm
Package width ×
package length 12.0 × 12.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 0.47 g
Code
(Reference) P-LQFP64-12×12-0.65
64-pin plastic LQFP
(FPT-64P-M23)
(FPT-64P-M23)
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F64034S-c-1-4
0.65(.026)
0.10(.004)
116
17
3249
64
3348
*12.00±0.10(.472±.004)SQ
14.00±0.20(.551±.008)SQ
INDEX
0.32±0.05
(.013±.002)
M
0.13(.005)
0.145±0.055
(.006±.002)
"A"
.059
–
.004
+.008
–
0.10
+0.20
1.50
0~8°
0.25(.010)
(Mounting height)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
Document Number: 002-07872 Rev. *A Page 80 of 83
MB90350 Series
(Continued)
64-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 10.0 mm × 10.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Code
(Reference) P-LFQFP64-10×10-0.50
64-pin plastic LQFP
(FPT-64P-M24)
(FPT-64P-M24)
LEAD No. "B"
0.08(.003)
(.006±.002)
0.145±0.055
0.08(.003)M
(.008±.002)
0.20±0.05
0.50(.020)
12.00±0.20(.472±.008)SQ
*10.00±0.10(.394±.004)SQ
INDEX
49
64
3348
17
32
16
1
2006-2010 FUJITSUSEMICONDUCTOR LIMITED F64036S-1c(D)-1-3
C
"A"
NOM.
11.00(.433)
0.15(.006)
MAX
MAX
0.40(.016)
Details of "A" part
(Stand off)
Details of "B" part
(.004±.004)
0.10±0.10
(.024±.006)
0.60±0.15
(.020±.008)
0.50±0.20
(Mounting height)
0.25(.010)
.059
–.004
+.008
–0.10
+0.20
1.50
0~8°
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
Document Number: 002-07872 Rev. *A Page 81 of 83
MB90350 Series
18. Major Changes
Spansion Publication Number: DS07-13737-6E
NOTE: Please see “Document History” about later revised information.
Page Section Change Results
——
Deleted the following package.
FPT-64P-M09
13 5. Packages and Product Correspon-
dence
Changed the correspondence package for MB90F351, MB90F351S,
MB90F352 and MB90F352S.
FPT-64P-M09 → FPT-64P-M23
26 9. Handling Devices Corrected a typo in number 10.
“is used”→ “is not used”
64
15. Electrical Characteristics
15.4. AC Characteristics
15.4.4. Clock Output Timing
Changed the Minimum value of cycle time.
41.76 → 41.67
75 15.5. A/D Converter Changed the notation of “Zero reading voltage” and “Full scale reading voltage”.
81 16. Ordering Information
Changed the part numbers and the package.
MB90F351PFM → MB90F351PMC
MB90F351SPFM → MB90F351SPMC
MB90F352PFM → MB90F352PMC
MB90F352SPFM → MB90F352SPMC
FPT-64P-M09 → FPT-64P-M23
Document Number: 002-07872 Rev. *A Page 82 of 83
MB90350 Series
Document History
Document Title: MB90350 Series F2MC-16LX 16-bit Microcontroller
Document Number: 002-07872
Revision ECN Orig. of
Change
Submission
Date Description of Change
** —AKFU 09/29/2003 Migrated to Cypress and assigned document number 002-07872.
No change to document contents or format.
*A 5755299 AKFU 05/31/2017 Updated to Cypress format.
Document Number: 002-07872 Rev. *A Revised May 31, 2017 Page 83 of 83
© Cypress Semiconductor Corporation, 2003-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
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