M29F010B70K6F - Micron Technology Inc.

November 2006 Rev 5 1/35

M29F010B

1 Mbit (128Kb x8, unifor m block) single supply Flash memory

Feature summary

■Single 5V±10% supply voltage for Program,

Erase and Read operations

■Access tim e: 45 ns

■Programming time

– 8 µs per byte typical

■8 uniform 16 Kbytes m emo ry blo cks

■Program/Erase controller

– Embedded byte Program algorithm

– Embedded multi-b lock/Chip Erase

algorithm

– Status Register Polling and Toggle bits

■Erase Susp end and Resume modes

– Read and Program another block during

Erase Suspend

■Unlock Bypass Program command

– Faster Production/Batch programming

■Low power consumption

– Standby and Automatic Standby

■100,000 Program/Erase cycles per block

■20 years data retention

■Defectivity below 1 ppm/year

■Electronic signature

– Manufac turer code: 20h

– Device code: 20h

■ECOPACK® packages available

TSOP32 (N)

8 x 20mm

PLCC32 (K)

www.st.com

Contents M29F010B

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Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Address Inputs (A0-A16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.7 Vss Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.6 Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.7 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.8 Block Protection and Blocks Unprotection . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.4 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.6 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.7 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.8 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.9 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.10 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

M29F010B Contents

3/35

5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 Data Polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3 Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.4 Erase Timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.5 Alternative Toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

List of tables M29F010B

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List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Uniform block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. Program Erase times and Program Erase Endurance cycles. . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 8. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 9. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 10. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 11. Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 12. Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 13. Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 14. PLCC32 – 32 lead Plastic Leaded Chip Carrier, package mechanical data. . . . . . . . . . . . 31

Table 15. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, package mechanical data . . . . 32

Table 16. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 17. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

M29F010B List of figures

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List of figures

Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. PLCC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Data Polling flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 5. Data Toggle flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 6. AC testing Input/Output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 7. AC testing load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 8. Read Mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 9. Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 10. Write AC waveforms, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 11. PLCC32 – 32 lead Plastic Leaded Chip Carrier, package outline . . . . . . . . . . . . . . . . . . . 31

Figure 12. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, package outline . . . . . . . . . . . . 32

Summary description M29F010B

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1 Summary description

The M29F010B is a 1 Mbit (128Kb x8) non-volatile memory that can be read, erased and

reprogrammed. These op erations can be performed using a sing le 5V supply. On powe r-up

the memory defaults to its Read mode where it can be read in the same way as a ROM or

EPROM.

The memory is divided into blocks that can be erased independently so it is possible to

preserve valid data while old data is erased. Each block can be protected independently to

prev ent accidental Prog ram or Erase commands from modifying the memory. Program and

Erase commands are written to the Command Interface of the memory. An on-chip

Program/Erase Controller simplifies the process of programming or erasing the memory by

taking care of all o f the sp ecial operations that are required to upd ate the memory contents.

The end of a program or erase operation can be detected and an y error conditions

identified. The command set required to control the memory is consistent with JEDEC

standards.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the

memory. They allow simple conne ction to most microprocessors, often without additiona l

logic.

The memory is off ered in PLCC32, TSOP32 ( 8 x 20mm) p ac kag es and it is supplied wit h all

the bits erased (set to ’1’).

In order to meet environment al requirements , ST offers the M29F010B in ECOPACK®

packages. ECOPACK packages are Lead-free. The category of second Level Inter connect

is marked on the package and on the inner box label, in compliance with JEDEC Standard

JESD97.

The maximum r atings related to soldering conditions ar e also marked on the inner bo x label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

M29F010B Summary description

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Figure 1. Logic diagram

Table 1. Signal names

A0-A16 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

EChip Enable

GOutput Enable

WWrite Enable

VCC Supply voltage

VSS Ground

NCI Not Connected Internally

AI02735

A0-A16

DQ0-DQ7

VCC

M29F010B

VSS

Summary description M29F010B

8/35

Figure 2. PLCC connections

Figure 3. TSOP connections

AI02737

A13

A10

DQ5

DQ0

DQ1

DQ2

DQ3

DQ4

A16

DQ7

A12

A14

VCC

M29F010B

A15

A11

DQ6

VSS

DQ0

A4 A3

A13

A10

DQ7

A14

A11 G

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A16

A12

VCC

A15

AI02738

M29F010B

16 17

VSS

M29F010B Summary description

9/35

Table 2. Uniform block addresses

# Size (Kbytes) Address range

7 16 1C000h-1FFFFh

6 16 18000h-1BFFFh

5 16 14000h-17FFFh

4 16 10000h-13FFFh

3 16 0C000h-0FFFFh

2 16 08000h-0BFFFh

1 16 04000h-07FFFh

0 16 00000h-03FFFh

Signal descriptions M29F010B

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2 Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals

connected to this device.

2.1 Address Inputs (A0-A16)

The Address Inputs select the cells in the me mory array to access during Bus Read

operations. During Bus Write operations they control the commands sent to the Command

Interface of the internal state machine .

2.2 Data Inputs/Outputs (DQ0-DQ7)

The Data Inputs/Outputs output the data stored at the selected address during a Bus Read

operat ion. During Bus Write operations t hey r epresent the command s sent to the Command

Interface of the internal state machine .

2.3 Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to

be performed. When Chip Enable is High, VIH, all other pins are ignored.

2.4 Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memo ry.

2.5 Write Enable (W)

The Write Enab le , W, controls the Bus Write operation of the me mory’s Command Inte rface .

2.6 VCC supply voltage

The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout

Voltage , VLKO. This prevents Bus Write operations from accidentally damaging the data

during pow er up, power down and power surges. If the Prog ram/Erase Cont roller is

progr amming or erasin g during this time then th e operation abo rts and the memory contents

being altered will be invalid.

A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS

Ground pin to decouple the current surges from the power supply. The PCB trac k widths

must be sufficient to carry the currents required during program and erase operations, ICC4.

M29F010B Bus operations

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2.7 Vss Ground

The VSS Ground is the reference for all voltage measurements .

3 Bus operations

There are five standard bus operations that control the device. These are Bus Read, Bus

Write, Output Disable, Standby and Automatic Standby. See Table 3: Bus operations, for a

summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored b y

the memory and do not affect bus operations.

3.1 Bus Read

Bus Read operations read from the memory cells, or specific registers in the Command

Interface . A valid Bus Read operation involves setting the desired address on the Address

Inputs , applying a Low signal, VIL, to Chip Enable and Output Enable and k eeping Write

Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 8: Read Mode

AC waveforms and Table 11: Read AC characteristics, for details of when the output

becomes valid.

3.2 Bus Write

Bus Write operations write to the Command I nterf ace. A v alid Bus Write operat ion begins b y

setting the desire d address on the Address Inp uts. The Address In puts are latched by the

Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs

last. The Data Inputs/Outputs are latche d by the Command Interface on the rising edge of

Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,

durin g the who le Bu s Write operation. See Figure 9: Write AC waveforms, Write Enable

controlled, Figure 10: Write AC waveforms, Chip Enable controlled, Table 12: Write AC

characteristics, Write Enable controlled and Table 13: Write A C characteristics, Chip Enable

controlled, for details of the t iming requirements.

3.3 Output Disable

The Data Inputs/Outputs are in the high impeda nce state when Output Enable is High, VIH.

Bus operations M29F010B

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3.4 Standby

When Chip Enable is High, VIH, the Data Inputs/Outputs pins are placed in the high-

impedance state and the Supply Current is reduced to the Standby level.

When Chip Enable is at VIH the Supply Current is reduced to the TTL Standby Supply

Current ICC2. To further reduce the Supply Current to the CMOS Standby Supply Current,

ICC3, Chip Enable should be held within VCC ± 0.2V. For Standby current levels see

Table 10: DC characteristics.

During program or erase operations the memory will continue to use the Program/Erase

Supply Current, ICC4, for Program or Erase operations until the operation completes.

3.5 Automatic Standby

If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or

more the memory enters A utomatic Standb y where the inte rnal Supply Current is reduced to

the CMOS Standby Supply Curren t, ICC3. The Data Inputs/Outputs will still output data if a

Bus Read operation is in progress.

3.6 Special bus operations

Additional bus operations can be performed to read the Electronic Signature and also to

apply and remov e Block Protection. These bus operations are intended for use by

programming equipment and are not usually used in applications. They require VID to b e

applied to some pins.

3.7 Electronic Signature

The memory has two codes, the manufacturer code and the device co de, that can be read

to identify the memory. These codes can be read by applying the signals listed in Table 3:

Bus operations.

3.8 Block Protection and Blocks Unprotection

Each block can be separately protected against accidental Program or Erase. Protected

blocks can be unprotect ed to allow data to be changed. Block Protection and Blocks

Unprotection operations must only be performed on programming equipment. For further

information refe r to Applicat ion No te AN1122, Applying Pr ot ecti on and Unp rot ect ion to M29

Series Flash memory.

M29F010B Bus operations

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Table 3. Bus operations(1)

1. X = VIL or VIH.

Operation E G W Address Inputs Data

Inputs/Outputs

Bus Read VIL VIL VIH Cell address Data Output

Bus Write VIL VIH VIL Command address Data Input

Output Disable X VIH VIH XHi-Z

Standby VIH XXX Hi-Z

Read Manufacturer code VIL VIL VIH A0 = VIL, A1 = VIL,

A9 = VID, others VIL or VIH 20h

Read Device code VIL VIL VIH A0 = VIH, A1 = VIL,

A9 = VID, others VIL or VIH 20h

Command interface M29F010B

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4 Command interface

All Bus Write operations to the memory are interpreted by the Command Interface.

Commands consist of one or more sequential Bus Write operations. Failur e to obse rve a

v alid sequence of Bus Write operations will result in the memory returning to Read mode.

The long command sequences are imposed to maximize data security.

The commands are summariz ed in Table 4: Commands. Ref er to Table 4 in conjunction with

the text descriptions below.

4.1 Read/Reset command

The Read/Reset command returns the memory to its Read mode where it behaves like a

RO M or EPROM. It also resets the errors in the Status Register. Either one or three Bus

Write operations can be used to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Erase operation or following a

Programming or Erase error then the memory will take upto 10µs to abort. During the abort

period no v alid data can be read f rom the memory. Issuing a Read/Rese t command during a

Block Erase operation will leave invalid data in the memory.

4.2 Auto Select command

The Auto Select command is used to read the Manufacturer code, the Device code and the

Block Protection status. Three consecutive Bus Write operations are required to issue the

Auto Select command. Once the Auto Select command is issued the memory remains in

Auto Select mode until another command is issued.

F ro m the A uto Select mode the Ma nuf acture r code can be read using a Bus Read oper ation

with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The

Manufacturer code for STMicroelectronics is 20h.

The Device code can be read using a Bus Read op eration with A0 = VIH and A1 = VIL. The

other address bits may be set to either VIL or VIH. The Device code for the M29F010B is

20h.

The Block Protection status of each block can be read using a Bus Read operation with A0

= VIL, A1 = VIH, and A14-A16 specifying the address of the block. The other address bits

ma y be set to either VIL or VIH. If the ad dressed b lo c k is pr otected t hen 01h is ou tput on the

Data Inputs/Outputs, otherwise 00h is output.

M29F010B Command interface

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4.3 Program command

The Prog ram command can be used to prog ram a v alue to one address in the memory arra y

at a time. The command requir es f our Bus Write operat ions, the final write oper ation latches

the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data

remains unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to

issue any command to abort or pause the operation. Typical program times are given in

Table 5: Program Erase times and Program Erase Endurance cycles. Bus Read operations

during the program operation will output the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more details.

After the progr am operation has completed the memory will return to the Read mode , unless

an error has occurred. When an error occurs the memory will continue to output the Status

Read mode.

Note that the Prog r am command ca nnot cha nge a bit set at ’0’ bac k to ’1’. One of the Er ase

Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

4.4 Unlock Bypass command

The Unloc k Bypass command is used in conjunction with the Unlock Bypass Program

command to program the memory. When the access time to the device is long (as with

some EPROM programmers) considerable time saving can b e made by using these

commands. Thr ee Bus Write oper at ions ar e requir ed to issue t he Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock

Bypass Program command and th e Unlo ck Bypass Reset comm a nd . The mem o ry can be

read as if in Read mode.

4.5 Unlock Bypass Program command

The Unlock Bypass Program command can be used to prog ram one address in memory at

a time. The command requires two Bus Write opera tions, the final write operation latches

the address and data in the internal state machine and starts the Program/Erase Controller.

The Program operation u sing the Unlock Bypass Program comma nd behaves identically to

the Program operati on using the Program command. A protected block cannot be

programmed; the operation cannot be aborted and the Status Register is read. Errors must

be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode.

See the Program command for details on the behavior.

4.6 Unlock Bypass Reset command

The Unlock Bypass Reset command can be used to return to Read/Reset mode from

Unloc k Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass

Reset command.

Command interface M29F010B

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4.7 Chip Erase command

The Chip Erase comman d can be used to erase the entire chip. Six Bus Write operations

are required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected th en these are ignored and all the ot he r blocks are erased. If all

of the blocks are protected the Chip Erase operation appears to start but will terminate

within about 100µs , leaving the dat a unchanged. No error cond ition is giv en when pro tected

blocks are ignored.

During the erase operation the memory will ignore all commands. It is not possible to issue

any command to abort the operation. Typical chip erase times are giv en in Table 5: Program

Erase times and Program Erase Endurance cycles. All Bus Read operations during the Chip

Erase operation will output the Status Register on the Data Inputs/Outputs. See the section

on the Status Register for more details.

After the Chip Erase operation has completed the memory will return to the Read Mode,

unless an error has occurred. When an error occurs the memory will continue to output the

Status Register. A Read/Reset command must be issued to reset the error condition and

return to Read Mode.

The Chip Erase Comm and set s all of th e bits in unpr ot ected blocks of the memory to ’1’. All

previous data is lost.

4.8 Block Erase command

The Block Erase command can be used t o erase a list of one or m ore blocks. Six Bus Write

operat ions are required to select the first b loc k in the list. Each additional bl ock in the list can

be selected by repeating the sixth Bus Write operation using the address of the additional

bl ock. The Block Erase operation starts the Program/Era se Controller about 50µs after the

last Bus Write operation. Once the Program/Erase Controller starts it is not possible to

select any more blocks. Each additional block must therefore be selected within 50µs of the

last b loc k. The 50µs timer rest arts when an additio nal bl ock is select ed. The Status Regist er

can be read after the sixth Bus Write operation. See the Status Register for details on how

to identify if the Program/Erase Controller has started the Block Erase op eration.

If an y selected b l oc ks are prote cted then t hese are ignored and all the other selected b locks

are erased. If all of the selected blocks are protected the Block Erase operation appears to

start but will terminate within about 100µs, lea ving the data unchanged. No error condition is

given when protected blocks are ignored.

During the Block Erase oper ation the memory will ignore all commands except the Erase

Suspend and Read/Reset commands. Typical block erase times are given in Table 5:

Program Erase times and Program Er ase Endurance cycles. All Bus Read operations

during the Block Erase operation will output the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more details.

After the Block Erase operation has completed the memory will return to the Read Mode,

unless an error has occurred. When an error occurs the memory will continue to output the

Status Register. A Read/Reset command must be issued to reset the error condition and

return to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All

previous data in the selected blocks is lost.

M29F010B Command interface

17/35

4.9 Erase Suspend command

The Erase Suspend Command may be used to temporarily suspend a Block Erase

operation and return the memory to Read mode. The command requir es one Bus Write

operation.

The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command

being issued. Once the Program/Erase Controller has stopped the memory will be set to

Read mode and the Erase will be suspended. If the Erase Suspend command is issued

during the period when the memory is waiting for an additional block (before the

Program/Erase Controller starts) then the Erase is suspended immediately and will start

immediately when the Erase Resume Command is issued. It will not be possible to select

any further blocks for erasure after the Erase Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being

erased; both Read and Program operations beha ve as normal on these blocks. Reading

from blocks that are being erased will output the Status Register. It is also possible to enter

the A uto Select mode: the memory will behave as in the A uto Select mode on all bloc ks until

a Read/Reset command returns the memory to Erase Suspend mode.

4.10 Erase Resume command

The Erase Resume command must be used to restart the Program/Erase Controller from

Erase Suspend. An erase can be suspended and resumed more than once.

Command interface M29F010B

18/35

Table 4. Commands(1)

1. All values in the table are in hexadecimal. X Don’t Care, PA Program Address, PD Program Data, BA Any

address in the Block. The Command Interface only uses address bits A0-A10 to verify the commands, the

upper address bits are Don’t Care.

Command

Length

Bus Writ e op er a t ions

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset(2)

2. After a Read/Reset command, read the memory as normal until another command is issued.

1X F0

3555AA2AA55 X F0

Auto Select(3)

3. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.

3 555 AA 2AA 55 555 90

Program(4)

4. After Program, Unlock Bypass Program, Chip Erase, and Block Erase commands read the Status Register until the

Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during

Block Erase Command with additional Bus Write Operations until the Timeout bit is set.

4 555 AA 2AA 55 555 A0 PA PD

Unlock

Bypass(5)

5. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.

3 555 AA 2AA 55 555 20

Unlock Bypass

Program(4) 2 X A0 PA PD

Unlock Bypass

Reset(6)

6. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

2X 90 X 00

Chip Erase(4) 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase(4) 6

+555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase

Suspend(7)

7. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and

Program commands on non-erasing blocks as normal.

1X B0

Erase

Resume(8)

8. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until

the Erase Controller completes and the memory returns to Read Mode.

1X 30

M29F010B Command interface

19/35

)

Table 5. Program Erase times and Program Erase Endurance cycles(1)

1. TA = 0 to 70°C, –40 to 85°C.

Parameter Min Typ(2)

2. TA = 25°C, VCC = 5V.

T ypical after 100k

W/E cycles(2) Max Unit

Chip Erase (all bits in the memory set to ‘0’) 0.6 0.6 sec

Chip Erase 1.3 1.3 6 sec

Block Erase (16 Kbytes) 0.3 0.3 2 sec

Program 8 8 150 µs

Chip Program 1.2 1.2 4.5 sec

Program/Erase cycles (per block) 100,000 cycles

Status Register M29F010B

20/35

5 Status Register

Bus Read oper ations from any a ddress alwa ys read the Stat us Register during Program a nd

Erase operations. It is also read during Erase Suspend when an address within a block

being erased is accessed.

The bits in the Status Register are summarized in Table 6: Status Register bits.

5.1 Data Polling bit (DQ7)

The Data Polling bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Erase Suspend. The Data

Polling bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling bit outputs the complement of the bit being

programmed to DQ7. After su ccessful completion of the Program operation the memory

returns to Read mode and Bus Read operations from the address just programmed output

DQ7, not its complement.

During Erase operations the Data Polling bit outputs ’0’, the complement of the er ased state

of DQ7. After successful completion of the Erase operation the memory returns to Read

Mode.

In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read operation

within a block being erased. The Data Polling bit will change from a ’0’ to a ’1’ when the

Program/Erase Controller has suspended the Erase operation.

Figure 4: Data P o lling flowchart, giv e s an e xa mple of ho w to use the Dat a Polling bit. A Valid

Address is the address bein g programmed or an address within the block being erased.

5.2 Toggle bit (DQ6)

The Toggle bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Er ase Suspend. The Toggle

bit is output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations at any address . After successful completion of the

operation the memory returns to Read mode.

During Erase Suspend mode the Toggle bit will output when addressing a cell within a bloc k

being erased. The Toggle bit will stop toggling when the Progr am/Erase Controller has

suspended the Erase operation.

Figure 5: Data Toggle flowchart, gives an example of how to use the Data Toggle bit.

M29F010B Status Register

21/35

5.3 Error bit (DQ5)

The Error bit can be used to identify errors detected by the Pro gram/Erase Controller. The

Error bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the

correct data to the memory. If the Error bit is set a Read/Reset command must be issued

before other commands are issued. The Error bit is output on DQ5 when the Status Register

is read.

Note that the Prog ram command cannot change a bit se t a t ’0’ back to ’1’ and att emptin g t o

do so may or may not set DQ5 at ‘1’. In both cases, a successive Bus Read operation will

show the bit is still ’0’. One of the Er ase commands must be used to set all the bits in a b lock

or in the whole memory from ’0’ to ’1’.

5.4 Erase Timer bit (DQ3)

The Erase Timer bit can be used to identify the start of Program/Erase Controller operation

during a Bloc k Erase command. Once the Program/Erase Controller starts erasing the

Erase Timer bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer bit

is set to ’0’ and additional blocks to be erased may be written to the Command Interface.

The Erase Timer bi t is output on DQ3 when the Status Register is read.

5.5 Alternative Toggle bit (DQ2)

The Alternative Toggle bit can be used to monitor the Prog ram/Erase controller during Erase

operations. The Alternative Toggle bit is output on DQ2 when the Status Register is read.

During Chip Erase and Block Erase opera tions the Toggle bit changes from ’0’ to ’1’ to ’0’,

etc., with successive Bus Read operations from addresses within the blocks being erased.

Once the oper ation completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle bit changes from ’0’ to ’1’ to ’0’, etc. with

successive Bus Read ope r at ion s f rom addre sses within the blocks being erased. Bu s Read

operations to addresses within bloc ks not being erased will output the memory cell data as if

in Read mode.

After an Er a se op eration that cau ses the Err or bit to be set th e Alternative Toggle bit can be

used to identify which block or blocks have caused the error. The Alternative Toggle bit

changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses

within blocks that have not erased correctly. The Alternative Toggle bit does not change if

the addressed block has erased correctly.

Status Register M29F010B

22/35

Figure 4. Data Polling flowchart

Table 6. Status Register bit s(1)

1. Unspecified data bits should be ignored.

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2

Program Any address DQ7 Toggle 0 – –

Program during Erase Suspend Any address DQ7 Toggle 0 – –

Program Error Any address DQ7 Toggle 1 – –

Chip Erase Any address 0 Toggle 0 1 Toggle

Block Erase before timeout Erasing block 0 Toggle 0 0 Toggle

Non-Erasing block 0 Toggle 0 0 No toggle

Block Erase Erasing block 0 Toggle 0 1 Tog gle

Non-Erasing block 0 Toggle 0 1 No toggle

Erase Suspend Erasing block 1 No toggle 0 – Toggle

Non-Erasing block Data read as nor m al

Erase Error Good block address 0 Toggle 1 1 No toggle

Faulty block address 0 Toggle 1 1 Toggle

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI03598

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

M29F010B Status Register

23/35

Figure 5. Data Toggle flowchart

READ DQ6

START

READ DQ6

TWICE

FAIL PASS

AI01370B

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

Maximum rating M29F010B

24/35

6 Maximum rating

Except for the rating "Operating Temperature Range", stresses above those listed in

Table 7: Absolute maximum ratings ma y cause permanent damage to the device. These are

stress rati ngs only an d op er at io n of th e device at these or any other conditions above those

indicated in the op erating se ctio ns of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability. Refer also to

the STMicroelectronics SURE Program and other relevant quality documents.

Table 7. Absolute maximum ratings

Symbol Parameter Value Unit

TAAmbient Operating temperature (Temperature Range 1) 0 to 70 °C

Ambient Operating temperature (Temperature Range 6) –40 to 85 °C

TBIAS Temperature under Bias –50 to 125 °C

TSTG Storage temperature –65 to 150 °C

VIO(1)

1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

Input or Output voltage –0.6 to 6 V

VCC Supply voltage –0.6 to 6 V

VID Identification voltage –0.6 to 13.5 V

M29F010B DC and AC parameters

25/35

7 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics Tables that

follow, are derived from tests performed under the measurement conditions summarized in

Table 8: AC m easu rem ent co nd itio ns. Design ers shou ld check that the oper ating con ditions

in their circuit match t he operating conditions when relying on the quoted parameters.

Figure 6. AC testing Input/Output waveform

Table 8. AC measurement conditions

Parameter 45 70/90/120

AC test conditions High speed Standard

Load capacitance (CL) 30pF 100pF

Input Rise and Fall times ≤ 10ns ≤ 10ns

Input pulse voltages 0 to 3V 0.45 to 2.4V

Input and Output Timing Ref. v oltages 1.5V 0.8V and 2V

AI01275B

High Speed

1.5V

2.4V

Standard

0.45V

2.0V

0.8V

DC and AC parameters M29F010B

26/35

Figure 7. AC testing load circuit

Table 9. Capacitance(1)(2)

1. TA = 25 °C, f = 1 MHz.

2. Sampled only, not 100% tested.

Symbol Pa rameter Test condition Min Max Unit

CIN Input capacitance VIN = 0V 6 pF

COUT Output capacitance VOUT = 0V 12 pF

AI03027

1.3V

OUT

CL = 30pF or 100pF

CL includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

M29F010B DC and AC parameters

27/35

Table 10. DC characteristics(1)

1. TA = 0 to 70°C, –40 to 85°C.

Symbol Parameter Test condition M in Typ (2)

2. TA = 25°, VCC = 5V.

Max Unit

ILI Input Leakage current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply current (Read) E = VIL, G = VIH,

f = 6MHz 515mA

ICC2 Supply current (Standby) TTL E = VIH 1mA

ICC3 Supply current (Standby) CMOS E = VCC ±0.2V 30 100 µA

ICC4(3)

3. Sampled only, not 100% tested.

Supply current (Program/Erase) Program/Erase

controller active 20 mA

VIL Input Low voltage –0.5 0.8 V

VIH Input High voltage 2 VCC +0.5 V

VOL Output Low voltage IOL = 5.8mA 0.45 V

VOH Output High voltage TTL IOH = –2.5mA 2.4 V

Output High voltage CMOS IOH = –100µA VCC –0.4 V

VID Identification voltage 11.5 12.5 V

IID Identification current A9 = VID 100 µA

VLKO(3) Program/Erase Lockout supply

voltage 3.2 4.2 V

DC and AC parameters M29F010B

28/35

Figure 8. Read Mode AC waveforms

Table 11. Read AC characteristics(1)

1. TA = 0 to 70°C, –40 to 85°C.

Symbol Alt Parameter Test condition 45 70/90/120 Unit

tAVAV tRC Address Valid to Next

Address Valid E = VIL, G = VIL Min 45 70 ns

tAVQV tACC Address Valid to Output

Valid E = VIL, G = VIL Max 45 70 ns

tELQX(2)

2. Sampled only, not 100% tested.

tLZ Chip Enable Low to Output

Transition G = VIL Min 0 0 ns

tELQV tCE Chip Enable Low to Output

Valid G = VIL Max 45 70 ns

tGLQX(2) tOLZ Output Enable Low to

Output Transition E = VIL Min 0 0 ns

tGLQV tOE Output Enable Low to

Output Valid E = VIL Max 25 30 ns

tEHQZ(2) tHZ Chip Enable High to Output

Hi-Z G = VIL Max 15 20 ns

tGHQZ(2) tDF Output Enable High to

Output Hi-Z E = VIL Max 15 20 ns

tEHQX, tGHQX,

tAXQX tOH

Chip Enable, Output Enable

or Address Transition to

Output Transition Min 0 0 ns

AI0

tAVAV

tAVQV tAXQ

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

-A16

0-DQ7

tELQV tEHQ

tGHQZ

VALID

M29F010B DC and AC parameters

29/35

Figure 9. Write AC waveforms, Write Enable controlled

Table 12. Write AC characteristics, Write Enable controlle d(1)

1. TA = 0 to 70 °C, –40 to 85 °C.

Symbol Alt Parameter 45 70/90/120 Unit

tAVAV tWC Address Valid to Next Address Valid Min 45 70 ns

tELWL tCS Chip Enab le Low to Write Enable Low Min 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 40 45 ns

tDVWH tDS Input Valid to Write Enable High Min 25 30 ns

tWHDX tDH Wri te Enable High to Input Transition Min 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 40 45 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 ns

tWHGL tOEH Wri te Enable High to Output Enable Low Min 0 0 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs

AI02927

A0-A16

DQ0-DQ7

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

DC and AC parameters M29F010B

30/35

Figure 10. Write AC waveforms, Chip Enable controlled

Table 13. Write AC characteristics, Chip Enable controlled(1)

1. TA = 0 to 70 °C, –40 to 85 °C.

Symbol Alt Parameter 45 70/90/120 Unit

tAVAV tWC Address Valid to Next Address Valid Min 45 70 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 40 45 ns

tDVEH tDS Input Valid to Chip Enable High Min 25 30 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 ns

tAVEL tAS Address Vali d to Chip Enable Low Min 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 40 45 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs

AI02928

A0-A16

DQ0-DQ7

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

M29F010B Package mechanical

31/35

8 Package mechanical

Figure 11. P LCC32 – 32 lead Plastic Leaded Chip Carri er, package outline

1. Drawing is not to scale.

Table 14. PLCC32 – 32 lead Plastic Leaded Chip Carrier, package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 3.17 3.56 0.125 0.140

A1 1.53 2.41 0.060 0.095

A2 0.38 – 0.015 –

B 0.33 0.53 0.013 0.021

B1 0.66 0.81 0.026 0.032

CP 0.10 0.004

D 12.32 12.57 0.485 0.495

D1 11.35 11.51 0.447 0.453

D2 4.78 5.66 0.188 0.223

D3 7.62 – – 0.300 – –

E 14.86 15.11 0.585 0.595

E1 13.89 14.05 0.547 0.553

E2 6.05 6.93 0.238 0.273

E3 10.16 – – 0.400 – –

e1.27– –0.050– –

F 0.00 0.13 0.000 0.005

N32 32

R 0.89 – – 0.035 – –

PLCC-A

E3 E1 E

1 N

0.51 (.020)

1.14 (.045)

D2 D2

Package mechanical M29F010B

32/35

Figure 12. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, package outline

Note: Drawing is not to scale.

Table 15. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.20 0.0472

A1 0.05 0.15 0.0020 0.0059

A2 0.95 1.05 0.0374 0.0413

B 0.17 0.25 0.0067 0.0098

C 0.10 0.21 0.0039 0.0083

D 19.80 20.20 0.7795 0.7953

D1 18.30 18.50 0.7205 0.7283

E 7.90 8.10 0.3110 0.3189

e0.50– –0.0197– –

L 0.50 0.70 0.0197 0.0276

α0° 5° 0° 5°

N 32 32

CP 0.10 0.0039

TSOP-a

N/2

DIE

LA1 α

M29F010B Part numbering

33/35

9 Part numbering

For a list of a vailable options (Speed, Pack age, etc...) or fo r further information on any

aspect of this device, please cont act the ST Sales Office nearest to you.

Table 16. Ordering information scheme(1)

1. The last two characters of the ordering code may be replaced by a letter code for preprogrammed parts,

otherwise devices are shipped from the factory with the memory content bits erased to ’1’.

Example: M29 F010B 70 N 1 T

Device type

M29

Operatin g voltage

F = VCC = 5V ± 10%

Device function

010B = 1 Mbit (128Kb x8), unif orm bloc k

Speed

45 = 45 ns

70 = 70 ns

90 = 90 ns

120 = 120ns

Package

K = PLCC32

N = TSOP32: 8 x 20 mm

Temperature range

1 = 0 to 70°C

6 = –40 to 85°C

Option

Blank = Standard packing

T = Tape & Reel packing

E = ECOPACK Package, standard packing

F = ECOPACK Package, Tape & Reel packing

Revision history M29F010B

34/35

10 Revision history

Table 17. Revision history

Date Revision Revision details

July 1999 -01 First Issue

28-Jul-2000 -02

New document template

Document type: from Preliminary Data to Data Sheet

Status Register bit DQ5 clarification

Data Polling Flowchart diagram change (Figure 4)

Data Toggl e Flowchart diagram change (Figure 5)

Program/Erase Times specification change (Table 5)

ICC1 and ICC3 Typ. specification added (Table 10)

22-Apr-2002 -03 PLCC32 package mechanical data modified

19-Sep-2005 4.0

PDIP32 package removed.

Table 16: Ordering information sch eme : standard package added and

ECOPACK version added for both standard package, and Ta pe & Reel

packing.

06-Nov-2006 5 Converted document to new template; updated package mechanical

data in Section 8: Pac kage mechanical; removed temperature range 3

(–40 to 125°C) from entire document.

M29F010B

35/35

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