NCL30100ASLDGEVB - ON Semiconductor

January, 2011 − Rev. 3

1Publication Order Number:

NCL30100/D

NCL30100

Fixed Off Time Switched

Mode LED Driver Controller

The NCL30100 is a compact switching regulator controller intended

for space constrained constant current high−brightness LED driver

applications where efficiency and small size are important. The

controller is based on a peak current, quasi fixed−off time control

architecture optimized for continuous conduction mode step−down

(buck) operation. This allows the output filter capacitor to be

eliminated. In this configuration, a reverse buck topology is used to

control a cost effective N−type MOSFET. Moreover, this controller

employs negative current sensing thus minimizing power dissipation

in the current sense resistor. The off time is user adjustable through the

selection of a small external capacitor, thus allowing the design to be

optimized for a given switching frequency range. The control loop is

designed to operate up to 700 kHz allowing the designer the flexibility

to use a very small inductor for space constrained applications.

The device has been optimized to provide a flexible inductive

step−down converter to drive one or more high power LED(s). The

controller can also be used to implement non−isolated buck−boost

driver topologies.

Features

•Quasi−Fixed OFF Time, Peak Current Control Method

•N−FET Based Controller Architecture

•Up to 700 kHz Switching Frequency

•Up to >95% Efficiency

•No Output Capacitor Needed

•VCC Operation from 6.35 − 18 V

•Adjustable Current Limit with Negative Sensing

•Inherent Open LED Protected

•Very Low Current Consumption at Startup

•Undervoltage Lockout

•Compact Thin TSOP−6 Pb−Free Package

•−40 to + 125°C Operating Temperature Range

•This is a Pb−Free Device

Typical Applications

•Low Voltage Halogen LED Replacement (MR 16)

•LED Track Lighting

•Landscape Lighting

•Solar LED Applications

•Transportation Lighting

•12 V LED Bulb Replacement

•Outdoor Area Lighting

•LED Light Bars

PIN CONNECTIONS

MARKING

DIAGRAM

TSOP−6

(SOT23−6, SC59−6)

SN SUFFIX

CASE 318G

3IVC

2GND

CT 4

Gate

(Top View)

5VCC

ORDERING INFORMATION

Device Package Shipping†

TSOP−6

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

http://onsemi.com

NCL30100SNT1G 3000 / Tape & Reel

AAA = Specific Device Code

A =Assembly Location

Y = Year

W = Work Week

G= Pb−Free Package

AAAAYWG

(Note: Microdot may be in either location)

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IC1

Figure 1. Typical Application Example of the LED Converter

GND

DRV

VCC

IVC

R2R1

LED1

LED2

LEDX

6.5 – 24 V

NCL30100

−

PIN FUNCTION DESCRIPTION

Pin N5Pin Name Function Pin Description

1 CS Current sense input A resistor divider consisting of R3 and R4 is used to set the peak current

sensed through the MOSFET switch

2 GND Ground Power ground.

3 CTTiming capacitor Capacitor to establish the off time duration

4 IVC Input voltage compensation The current injected into the input varies the switch off time and IPK allowing for

feedforward compensation.

5 VCC Input supply Supply input for the controller. The input is rated to 18 V but as illustrated

Figure 1, a simple zener diode and resistor can allow the LED string to be

powered from a higher voltage

6 DRV Driver output Output drive for an external power MOSFET

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Figure 2. Simplified Circuit Architecture

IVC

GND

VCC

DRV

Input Voltage

Regulator

0−3.9 V

50 mA

12.5−50 mA

SET

CLR

Reset

Set

Reference

Regulator

VDD

Iref

Undervoltage

Lockout

6.35/5.85 V

OFF Time

Comparator

VOffset

Current Sense

Comparator

Gate Driver

MAXIMUM RATINGS

Rating Symbol Value Unit

Power Supply Voltage VCC 18 V

IVC Pins Voltage Range IVC −0.3 to 18 V

CS and CT Pin Voltage Range Vin −0.3 to 10 V

Thermal Resistance, Junction−to−Air RqJA 178 °C/W

Junction Temperature TJ150 °C

Storage Temperature Range Tstg −60 to +150 °C

ESD Voltage Protection, Human Body Model (HBM) VESD−HBM 2 kV

ESD Voltage Protection, Machine Model (MM) VESD−MM 200 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device(s) contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per JEDEC Standard JESD22−A114E

Machine Model 200 V per JEDEC Standard JESD22−A115−A

2. This device meets latchup tests defined by JEDEC Standard JESD78.

3. Moisture Sensitivity Level (MSL) 1.

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ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, unless

otherwise noted)

SUPPLY SECTION

Parameter Conditions Symbol Min Typ Max Unit

INPUT VOLTAGE COMPENSATION

Offset Voltage V(offset) 1.10 1.30 1.45 V

CT Pin Voltage IVC Current = 25 mA (Including V(offset)) VCT−25mA 1.69 2.08 2.47 V

CT Pin Voltage IVC Current = 50 mA (Including V(offset)) VCT−50mA2.12 2.6 3.05 V

IVC pin internal resistance (Note 4) RIVC 17 kW

CT PIN – OFF TIME CONTROL

Source Current CT Pin Grounded, 0 v TJ v 85°C ICT 47.25 50 52.75 mA

Source Current CT Pin Grounded, −40 v TJ v 125°C ICT 45.25 50 52.75 mA

Source Current Maximum Voltage Capab-

ility (Note 4)

VCT(max) −4.3 −V

Minimum CT Pin Voltage (Note 4) Pin Unloaded, Discharge Switch Turned

VCT(min) − − 20 mV

Pin to ground capacitance (Note 4) CCT −8−pF

Propagation Delay (Note 4) CT Reach VCT Threshold to Gate Output CTdelay −220 −ns

CURRENT SENSE

Minimum Source Current IVC = 180 mA, CT Pin Grounded,

0 v TJ v 85°C

ICS(min) 11. 75 12.5 13.25 mA

Minimum Source Current IVC = 180 mA, CT Pin Grounded,

−40 v TJ v 125°C

ICS(min) 11.35 12.5 13.25 mA

Maximum Source Current IVC = 0 mA, CT Pin Grounded,

0 v TJ v 85°C

ICS(max) 47.25 50 52.75 mA

Maximum Source Current IVC = 0 mA, CT Pin Grounded,

−40 v TJ v 125°C

ICS(max) 45.25 50 52.75 mA

Comparator Threshold Voltage (Note 4) Vth −38 −mV

Propagation Delay CS Falling Edge to Gate Output CSdelay −215 310 ns

GATE DRIVER

Sink Resistance Isink = 30 mA ROL 5 15 40 W

Source Resistance Isource = 30 mA ROH 20 60 100 W

POWER SUPPLY

Startup Threshold VCC increasing VCC(on) −6.35 6.65 V

Minimum Operating Voltage VCC decreasing VCC(off) 5.45 5.85 −V

Vcc Hysteresis (Note 4) VCC(hyst) −0.5 −V

Startup Current Consumption VCC = 6 V ICC1 −22 35 mA

Steady State Current Consumption

(Note 4)

CDRV = 0 nF, fSW = 100 kHz, IVC = open,

VCC = 7 V

ICC2 300 mA

Steady State Current Consumption CDRV = 1 nF, fSW = 100 kHz, IVC = open,

VCC = 7 V

ICC2 0.5 1 1.15 mA

4. Guaranteed by design

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−40 −20 0 20 40 60 80 100 120

6.235

6.240

6.245

6.250

6.255

6.260

VCC(on) (V)

Figure 3. Vstartup Threshold vs. Junction

Temperature

TEMPERATURE (°C)

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

ICC1 (mA)

Figure 4. Startup Current Consumption vs.

Junction Temperature

−40 −20 0 20 40 60 80 100 120

12.6

12.5

12.4

12.3

12.2

12.1

12.0

11.9

11.8

11.7

11.6

ICS(min) (mA)

TEMPERATURE (°C)

Figure 5. Minimum Source Current vs.

Junction Temperature

VCC(off) (V)

TEMPERATURE (°C)

Figure 6. Minimum Operating Voltage

Threshold vs. Junction temperature

ICC2 (mA)

TEMPERATURE (°C)

−40 −20 0 20 40 60 80 100 120

1.10

1.05

1.00

0.95

0.90

Figure 7. Steady State Current Consumption

vs. Junction Temperature

ICS(max) (mA)

−40 −20 0 20 40 60 80 100 120

5.780

5.775

5.770

5.765

5.760

5.755

5.750

5.745

5.740

TEMPERATURE (°C)

−40 −20 0 20 40 60 80 100 120

50.0

49.5

49.0

48.5

48.0

47.5

47.0

Figure 8. Maximum Source Current vs.

Junction Temperature

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Figure 9. Comparator Threshold Voltage vs.

Junction Temperature

Vth (mV)

TEMPERATURE (°C)

−40 −20 0 20 40 60 80 100 120

V(offset) (V)

TEMPERATURE (°C)

1.350

1.345

1.340

1.335

1.330

1.325

1.320

Figure 10. Offset Voltage vs. Junction

Temperature

−40 −20 0 20 40 60 80 100 120

RESISTANCE (W)

TEMPERATURE (°C)

Figure 11. Drive Sink and Source Resistance

vs. Junction Temperature

ROH

ROL

ICT (mA)

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

51.0

Figure 12. CT Source Current vs. Junction

Temperature

50.5

50.0

49.5

49.0

48.5

48.0

47.5

47.0

VCT−50mA (V)

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

2.60

Figure 13. CT Pin Voltage vs. Input Voltage

Compensation Current

2.55

2.50

2.45

2.40

2.35

2.30

ICS (mA)

IVC (mA)

0 20 20018016014012040 60 80 100

Figure 14. ICT Dependence on IVC Current

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APPLICATION INFORMATION

The NCL30100 implements a peak current mode control

scheme with a quasi−fixed OFF time. An optional input

feedforward voltage control is provided to enhance

regulation response with widely varying input voltages.

Only a few external components are necessary to implement

the buck converter. The NCL30100 incorporates the

following features:

•Very Low Startup Current: The patented internal supply

block is specially designed to offer a very low current

consumption during startup.

•Negative Current Sensing: By sensing the total current,

this technique does not impact the MOSFET driving

voltage (VGS) during switching. Furthermore, the

programming resistor together with the pin capacitance

forms a residual noise filter which blanks spurious

spikes. This approach also supports a flexible resistor

selection. Finally unlike a positive sensing approach,

there is virtually no power dissipation in the current

sense resistor thus improving efficiency.

•Controller architecture supports high brightness LED

drive current requirements: Selection of the external

n−channel MOSFET can be easily optimized based on

operation voltage, drive current and size giving the

designer flexibility to easily make design tradeoffs.

•Typical $5.5% Current Regulation: The ICS pin offers

$5.5% from 0 to 85°C (+5.5% −9.5% across −40°C to

125°C) accuracy of the current typically, so the LED

peak current is precisely controlled

•No output capacitor is needed: By operating the

controller in continuous conduction mode, it is possible

to eliminate the bulky output filter capacitor.

The following section describes in detail each of the control

blocks

Current Sensing Block

The NCL30100 utilizes a technique called negative

current sensing which is used to set the peak current through

the switch and the inductor. This approach offers several

benefits over traditional positive current sensing.

•Maximum peak voltage across the current sense resistor

is user controlled and can be optimized by changing the

value of the shift resistor.

•The gate drive capability is improved because the

current sense resistor is located out of the gate driver

loop and does not deteriorate the switch on and also

switch off gate drive amplitude.

•Natural leading edge blanking is filter switching noise

at FET turn−in

•The CS pin is not exposed to negative voltage, which

could induce a parasitic substrate current within the IC

and distort the surrounding internal circuitry.

The current sensing circuit is shown in Figure 15.

Figure 15. Primary Current Sensing

Input Voltage

Regulator

RCS

Rshift

Iprimary

GND

IVC

12.5−50 mA

To Latch

VCS

Vshift

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Once the external MOSFET is switched on, the inductor

current starts to flow through the sense resistor RCS. The

current creates a voltage drop VCS on the resistor RCS, which

is negative with respect to GND. Since the comparator

connected to CS pin requires a positive voltage, a voltage

Vshift is developed across the resistor Rshift by a current

source which level−shifts the negative voltage VCS. The

level−shift current is in the range from 12.5 to 50 mA

depending on the optional input voltage compensation loop

control block signal (see more details in the input voltage

compensation section). The peak inductor current is equal

to:

Ipk +

ICS @Rshift *Vth

RCS

(eq. 1)

To achieve the best Ipk precision, higher values of ICS

should be used. The Equation 1 shows the higher drop on

RCS reduces the influence of the Vth tolerance. Vth is the

comparator threshold which is nominally 38 mV.

A typical CS pin voltage waveform for continuous

condition mode is shown in Figure 16.

Figure 16. CS Pin Voltage

Switch

Turn on

Ishift = 50 mA

Ishift = 12.5 mA

Figure 16 also shows the effect of the inductor current

based on the range of control possible via the IVC input.

OFF Time Control

The internal current source, together with an external

capacitor, controls the switch−off time. In addition, the

optional IVC control signal can modulate the off time based

on input line voltage conditions. This block is illustrated in

Figure 17.

Figure 17. OFF Time Control

GND

50 mA

To Latch’s Set Input

VOffset

VOffset to VDD

To Latch’s Output

From Input Voltage

Compensation Block

During the switch−on time, the CT capacitor is kept

discharged by an internal switch. As soon as the latch output

changes to a low state, the Isource is enabled and the voltage

across CT starts to ramp−up until its value reaches the

threshold given by the Voffset. The current injected into IVC

can change this threshold. The IVC operation will be

discussed in the next section.

Figure 18. CT Pin Voltage

toff−min

I1 I2 I3

Voffset

VDD

CT pin

Voltage

Goes Up

Goes Down

IVC

The voltage that can be observed on CT pin is shown in

Figure 18. The bold line shows the minimum IVC current

when the off time is at its minimum. The amount of current

injected into the IVC input can increase the off time by

changing the turn off comparator switching threshold. I1, I2,

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and I3 represent different delays depending on the

magnitude of IVC.

Gate Driver

The Gate Driver consists of a CMOS buffer designed to

directly drive a power MOSFET. It features unbalanced

source and sink capabilities to optimize switch on and off

performance without additional external components. The

power MOSFET is switched off at high drain current, to

minimize its switch off losses the sink capability of the gate

driver is increased for a faster switch off. On the other hand,

the source capability of the driver is reduced to slow−down

the power MOSFET at switch on in order to reduce EMI

generation. Whenever the IC supply voltage is lower than

the under voltage threshold, the Gate Driver is low, pulling

down the gate to ground thus eliminating the need for an

external resistor.

Input Voltage Compensation:

The Input Voltage Compensation block gives the user

optional flexibility to sense the input voltage and modify the

current sense threshold and off time. This function provides

a feed forward mechanism that can be used when the input

voltage of the controller is loosely regulated to improve

output current regulation. If the input voltage is well

regulated, the IVC input can also be used to adjust the offset

of the off time comparator and the current sense control to

achieve the best current regulation accuracy.

An external resistor connected between IVC and the input

supply results in a current being injected into this pin which

has an internal 17 kW resistor connected to a current mirror.

This current information is used to modify Voffset and ICS.

By changing Voffset the off time comparator threshold is

modified and the off time is increased. A small capacitor

should be connected between the IVC pin and ground to

filter out noise generated during switching period. Figure 19

shows the simplified internal schematic:

Figure 19. Input Voltage Compensation, OFF Time

Control

Current

Mirror

1:1

Current

Mirror

1:1

25 kW

VOffset To OFF

Time

Comparator

VCC

17 kW

IVC

Figure 20. IVC Loop Transfer Characteristic

IVC Pin Sink Current

Voffset

VDD

OFF Time Comparator Input

Voltage

The transfer characteristic (output voltage to input

current) of the input voltage compensation loop control

block can be seen in Figure 20. VDD refers to the internal

stabilized supply. If no IVC current is injected, the off time

comparator is set to Voffset.

The value of the current injected into IVC also change Ics.

This is accomplished by changing the voltage drop on Rshift.

The corresponding block diagram of the IVC pin can be seen

in Figure 21.

Figure 21. Input Voltage Compensation Loop – Current Sense Control

Current

Mirror

4:3

To Current Sense Comparator

17 kW

IVC CS

37.5 mA12.5 mA

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The current sense characteristic can be seen in Figure 22.

As illustrated, by varied the IVC current between 0 − 50 mA,

the sourcing current can range from 12.5 to 50 mA.

IVC Pin Sink Current

CS Pin Source Current

50 mA

12.5 mA

50 mA

0 mA100 mA 140 mAmA

Figure 22. Current Sense Regulation Characteristic

Biasing the controller

The NCL30010 Vcc input can range up to 18 V. For

applications that have an input voltage that is greater than

that level, an external resistor should be connected between

Vin and the VCC supply capacitor. The value of the resistor

can be calculated as follows:

R2+

Vin *VCC

ICC2

(eq. 2)

Where:

VCC − Voltage at which IC operates (see spec.)

ICC2 – Current at steady state operation

Vin − Input voltage

The ICC current is composed of two components: The

quiescent current consumption (300 mA) and the switching

current consumption. The driver consumption depends on

the MOSFET selected and the switching frequency. Total

current consumption can be calculated using following

formula:

ICC +300 @10−6)CMOSFET @VCC @fswitching (eq. 3)

In applications where the input voltage Vin is varying

dramatically, a zener can be used to limit the voltage going

into VCC, thus reducing the switching current contribution.

Switching Frequency

The switching frequency varies with the output load and

input voltage. The highest frequency appears at highest

input voltage. Since the peak inductor current is fixed, the

on−time portion of the switching period can be calculated:

ton +L@

Ipk

Vin

)CSdelay (eq. 4)

Where:

L − Inductor inductance

Ipk − Peak current

As seen from the above equation, the turn on time depends

on the input voltage. In the case of a low voltage AC input

where there is ripple due to the time varying input voltage

and input rectifier, natural frequency dithering is produced

to improve the EMI signature of the LED driver.

The turn off time is determined by the charging of the

external capacitor connected to the CT pin. The minimum

toff value can be computed as:

toff +CT@

Voffset

ICT

)CTdelay (eq. 5)

Where:

Voffset − Offset voltage (see parametric table)

ICT − CT pin source current (see parametric table)

Finally, the switching frequency then can be evaluated by:

FSW +1

ton )toff

L@Ipk

Vin )

CT@Voffset

50@10−6)435 @10−9

(eq. 6)

The sum of the nominal CSdelay and CTdelay is

approximately 435 nsec.

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Reverse Buck Operating Description

Figure 23 illustrates a typical application schematic and

Figure 24 displays simplified waveforms illustrate the

converter in steady state operation for critical circuit nodes.

GND

DRV

Figure 23. Simplified Application Schematic

CT IVC

VCC

Vin

Rsense

Rshift

NCL30100

IC1

D1 LED

Imag

Idemag

VCS

ICS

Vsense

ICT

VCT VDRV

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Vcc

VDRV

Ipk

Imag

Imin

Idemag

ILED

50 uA

ICT

VCT

VSense

ICS

VCS

38 mV

Figure 24. Voltage and Current Nodes in the Application Circuit

The current follows the red line in Figure 23 when Q1 is

turned on. The converter operates in continuous conduction

mode therefore the current through the inductor never goes

to zero. When the switch is on, the current creates a negative

voltage drop on the Rsense resistor. This negative voltage can

not be measured directly by the IC so an Rshift resistor is

connected to CS pin. Inside the IC there is a current source

connected to this pin. This current source creates constant

voltage drop on resistor Rsense which shifts the negative

voltage drop presented on Rsense positive. The magnetizing

current Imag increases linearly, the negative voltage on

Rsense increased as well. Thus the voltage on CS pin

approaching zero. On the CS pin there is a comparator with

a reference level of 38 mV. Once the voltage on the CS pin

reaches this reference level, the DRV output is turned off and

current path Imag disappears. Energy stored in the inductor

as a magnetic field keeps current flowing in the same

direction. The current path is now closed via diode D1

(green line). Once the DRV is turned off, the internal current

source starts to charge the CT capacitor and the voltage on

this node increases. Once the CT capacitor voltage reaches

the VCT level, Q1 is turned on and an internal switch

discharges the CT capacitor to be ready for the next

switching cycle.

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Application Design Example:

A typical step down application will be used to illustrate the basic design process based on nominal design parameters:

•Input voltage: Vin − 12 Vac (12 V dc after the bridge)

•Nominal LED current: 700 mA (rms)

•LEDripple: 120 mA (peak−to−peak)

•VLED: 3.2 V

•Freewheel diode Vf: 0.5 V

•Target Switching Frequency: 450 kHz

Dimming using PWM signal 1 kHz with duty cycle 0 – 99%

Figure 25. Example Design Schematic

12 V

NCL30100

IC1

DIMM

0/5 V

Vac

Vac CS

GND

DRV

VCC

IVC

Note this simplified step−by−step design process neglects

any parasitic contribution of the PCB.

First, we need to determine the nominal tON/tOFF ratio:

ton

toff

VLED )Vf

Vin *VLED

+3.2 )0.5

12 *3.2 +3.7

8.8 (eq. 7)

Next the typical duty cycle (DC) will be calculated:

DC +

tON

tON )tOFF

+3.7

3.7 )8.8 +0.296 (eq. 8)

Target switching frequency is set at 450 kHz, now we need

to determine the period:

T+1

fop +1

450 @103+2.222 ms(eq. 9)

Combination the previous equation we can calculate the tON

and tOFF durations:

tON +DC @T+0.296 @2.222 @10−6+658 ns (eq. 10)

tOFF +(1*DC)@T+(1*0.296)@2.222 @10−6

+1.564 ms

Now all the parameters are defined to calculate inductor

value:

V+di @L

dt åL+ǒVIN *VLEDǓ@tON

Iripple (eq. 11)

(12 *3.2)@658 @10−9

0.12 ^48.3 mH

A standard value 47 mH is chosen.

Next the CT capacitor can be calculated, but we need to

first determine the IVC current which can be simply

calculated.

IIVC +V

R)RIVC

+12

1.5 @106)17 @103^7.91 mA

(eq. 12)

The IVC current controls the dependence of the peak

current to the input voltage. If the input voltage is well

regulated, the IVC pin should be grounded. The value for

IVC resistor should be chosen based on graphs below.

Note as well that the IVC can be used to implement analog

dimming since increasing the current into IVC pin will

decrease the Ipeak of the LED).

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Figure 26. Rivc Impact versus Vin for ILED =

700 mA Nominal

100

200

300

400

500

600

700

800

900

1000

7 8 9 101112131415161718

INPUT VOLTAGE (V)

ILED (mA)

100

200

300

400

500

600

7 8 9 10 11 12 13 14 15 16 17 18

INPUT VOLTAGE (V)

Figure 27. Rivc Impact versus Vin for ILED =

350 mA Nominal

ILED (mA)

Rivc = 300k

Rivc = 510k

Rivc = 1 Meg

Rivc = 1.5 Meg

Rivc = 2.2 Meg

Rivc = 3.7 Meg

Rivc = infinity

Rivc = 300k

Rivc = 510k

Rivc = 1 Meg

Rivc = 1.5 Meg

Rivc = 2.2 Meg

Rivc = 3.7 Meg

Rivc = infinity

A value 1.5 MW was used since the input voltage has a

sinusoidal component due to the low voltage AC input and

desires to have a small bulk capacitance, thus compensating

for part of this variation.

The dependence of VCT on IVC current is described by the

following equation:

VCT +−0.097 @X2)24.5 @X)1358.1

976.8 [V](eq. 13)

Using the result from Equation 12 and put it to Equation 13

the VCT threshold will be calculated:

VCT +−0.097 @7.912)24.5 @7.91 )1358.1

976.8

(eq. 14)

^1.58 V

The CT capacitance can be calculated using the equations

above:

I+dv @C

dt åCCT +

ICT @ǒtOFF *CTdelayǓ

VCT (eq. 15)

50 @10−6@ǒ1.654 @10−6*220 @10−9Ǔ

1.58 ^45.8 pF

The intrinsic pin capacitance CT pin (~8 pF) in

conjunction with the dimming transistor (~10 pF) in this

schematic approximately 18 pF so this value must be

subtracted from the calculated value in Equation 15. The

calculated value is not standard, so the nearest value 33 pF

has been selected.

Now we can calculate the IPK of LED. The average value

is set to 700 mA and the target ripple is set at 120 mA, the

IPK equals 760 mA. Rshift has been chosen to be as small a

voltage drop as possible to minimize power dissipation so an

Rshift of 100 mW has been selected.

Before calculation of Rshift we need to know the ICS

current, which affects the offset on Rshift. The ICS value

dependents on the IVC current and for IVC currents between

0 − 50 mA, it can be described by this formula:

ICS +−0.75 @IVC )50 @10−6[mA](eq. 16)

Therefore:

ICS +−0.75 @IVC )50 @10−6(eq. 17)

+−0.75 @7.91 @10−6)50 @10−6^44.07 mA

To calculate Rshift it is necessary to know the Ipk current

through the inductor. From the time that the current sense

comparator detects that the peak current threshold has been

crossed to the time that the external MOSFET switch is

turned off there is a propagation delay. Depending on the

value of the inductor selected (which is based on the target

switching frequency), there is a current error between the

intended peak current and the actual peak current, this is

illustrated in Figure 28.

NCL30100

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Figure 28. A Current Error Between the Intended Peak Current and the Actual Peak Current

Ipeak

Ics

ton toff

ILED ΔiL

(Vin-V

LED

)

-VLED- V

diode

Ipeak

Ics

ton toff

ILED

(Vin-V

LED

)

-VLED- V

diode

-VLED- V

diode

V+di @L

dt åIdelay +V@t

L+8.8 @215 @10−9

47 @10−6(eq. 18)

^0.0402 A

V/L is simply the slew rate through the inductor and td is

the internal propagation delay so the current overshoot from

target is approximately 40 mA as calculated in Equation 18.

All values necessary for Rshift calculation are known, the

Rshift value is described by this formula:

Rshift +

Rsense @ǒIpk *IdelayǓ)Vth

ICS (eq. 19)

+0.1 @(0.76 *0.0402))0.038

44.07 @10−6^2496 W

This value of resistance can be a parallel combination of

2.7 kW and 30 kW.

To understand the operating junction temperature, we

calculate the die power dissipation:

PDIE +VCC @ǒ300 @10−6)CMOSFET @VCC @fswitchingǓ

(eq. 20)

+12 @ǒ300 @10−6)560 @10−12 @12 @450 @103Ǔ

+39.8 mW

Using the PDIE, we can calculate junction temperature:

TempIC +TA)PDIE @RqJA +TA)0.0399 @178

(eq. 21)

+TA)7.1°C

A design spreadsheet to aid in calculating the external

components necessary for a specific set of operating

conditions is available for download at the

ON Semiconductor website.

For a low voltage AC input diode D3 is placed into the Vcc

line. Since Capacitor C3 is charged from a sinusoidal

voltage. If the input voltage approaches zero, the IC is still

supplied from C3. Due to this diode, the IC keeps the LED

driver operating even if the sinusoidal voltage is lower than

VCC(min) until Vin is lower than VLED. The use of this diode

make sense only if a single LED is used and the converter is

supplied by sinusoidal voltage 12 Vac. For two LEDs in

series their forward voltage is almost as high as VCC(min) of

the IC.

Parasitic capacitance and inductance are presented in real

applications which will have an influence on the circuit

operation. They are depending on the PCB design which is

user dependent. The BOM, PCB and some plots are enclosed

for better understanding of the system behavior.

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Figure 29. PCB Design the Circuit Calculated Above.

Only Single Layer PCB is Used for the Application.

Figure 30. The Component Side (Several Transistor

Packages are Possible to Use)

BILL OF MATERIALS FOR THE SINGLE LAYER EVALUATION BOARD (NCL30100ASLDGEVB)

Des-

ignat-

or Qty

Descrip-

tion Value Tol Footprint Manufacturer

Manufacturer

Part Number

Substitution

Allowed Pb−Free

Com-

ments

C1 1 Capacitor 2.2 mF / 25 V 10% 0805 AVX 08053C225KAT2A Yes Yes

C2 1 Capacitor 33 pF 5% 0603 Kemet C0603C330J5GACTU Yes Yes

C3 1 Capacitor 4.7 mF / 25 V 10% 0805 AVX 08053D475KAT2A Yes Yes

C5 1 Capacitor 1 nF 10% 0603 Kemet C0603C104K5RACTU Yes Ye s

D1 1 Surface

Mount

Schottky

Power

Rectifier

MBR130T3G −SOD−123 ON Semiconductor MBR130T3G No Yes

D2 1 Zener

Diode

16 V 5% SOD−123 ON semiconductors MMSZ16T1G No Yes

D3 1 Schottky

Diode

NSR0520V2T1G −SOD−523 ON semiconductors NSR0520V2T1G No Yes

D4,

D5,

D6,

4 Schottky

Diode

NSR0340HT1G −SOD−323 ON semiconductors NSR0340HT1G No Yes

IC1 1 LED

Driver

NCL30100 −TSOP−6ON semiconductors NCL30100SNT1G No Yes

L3 1 Inductors 47 mH10% WE−PD2_M Wurth Electronik 744774147 No Yes

Q1 1 Power

MOSFET

NTGS4141NT1G −TSOP−6ON semiconductors NTGS4141NT1G No Yes

Q2 1 Power

MOSFET

NU −SOT−223 ON semiconductors NTF3055−100T1G No Yes Option

Q2 1 Power

MOSFET

NU −DPAK ON semiconductors NTD23N03RT4G No Yes Option

Q2 1 Power

MOSFET

NU −SOT−363 ON semiconductors NTJS4160NT1G No Yes Option

Q2 1 Power

MOSFET

NU −SOT−23 ON semiconductors NTR4170NT1G No Yes Option

Q3 1 General

Purpose

Transistor

NPN

BC817−16 −SOT−23 ON semiconductors BC817−16LT1G No Yes

NCL30100

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BILL OF MATERIALS FOR THE SINGLE LAYER EVALUATION BOARD (NCL30100ASLDGEVB)

Des-

ignat-

Com-

ments

Pb−Free

Substitution

Allowed

Manufacturer

Part Number

ManufacturerFootprintTolValue

Descrip-

tion

Qty

Q3 1 Power

MOSFET

NU −SOT−23 ON semiconductors NTS4001NT1G No Ye s Option

R1 1 Resistor 1.5 M 1% 0603 Rohm Semiconductor MCR03EZPFX1504 Yes Ye s

R2 1 Resistor 300 R 1% 0603 Rohm Semiconductor MCR03EZPFX3000 Yes Yes

R3 1 Resistor 30 k 1% 0603 Rohm Semiconductor MCR03EZPFX3002 Yes Ye s

R4 1 Resistor 0.1 R 1% 0805 Welwyn LRCS0805−0R1FT5 Yes Yes

R5 1 Resistor 2.7 k 1% 0603 Rohm Semiconductor MCR03EZPFX2701 Yes Yes

R8 1 Resistor 10 k 1% 0603 Rohm Semiconductor MCR03EZPFX1002 Yes Ye s

R9 1 Resistor 5.6 k 1% 0603 Rohm Semiconductor MCR03EZPFX5601 Yes Yes

Figure 31. Completed PCB with Devices

Figure 32. Snapshot of CT Pin Voltage, Driver and

ILED

Figure 33. Voltage Measured on RCS (R4)

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Figure 34. Current Through LED if 50% Dimming

at 1 kHz is Applied

Figure 35. The Dimming Detail at 95%. No Overshoot

in LED Current is Observed

Figures 36 and 37 illustrate leading edge and trailing edge

waveforms from a chopped AC source. For proper dimming

control, the bulk capacitance must be reduced to a relatively

small value to achieve best dimming range. Performance in

real world application is dependent on the characteristics of

the actual dimmer and the electronic transformer used to

generated to chopped AC waveform

Figure 36. Trailing Edge Dimming Figure 37. Leading Edge (Triac) Regulation. Small

Overshoot is Seen on the Leading Edge, this is

Based on the Abrupt Chopping of the Low Voltage

AC Waveform

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Figure 38. ILED and Vin Waveform if No Dimming is Used

Figure 39. Efficiency Measurement for the

Demoboard (Vf = 3.2 Nominal)

7 8 9 10111213141516

INPUT VOLTAGE (V)

EFFICIENCY (%)

DC Voltage Efficiency

(No Bridge Rectifier)

Figure 39 represents the efficiency of the converter

driving a single LED at a nominal current of 690 mA. The

addition of the AC bridge rectifier contributes addition

losses into the circuit and it is recommended to us low

forward voltage schottky rectifiers to minimize power

dissipation in the AC rectification stage.

Figure 40. ILED Current Dependence on Input

DC Voltage (No Bridge Rectifier is Used)

620

630

640

650

660

670

680

690

7 8 9 1011121314151

INPUT VOLTAGE (V)

CURRENT (mA)

LED Current Variation

MR 16 Evaluation Board Information

A specific two sided demo board was designed to fit with

the MR 16 form factor. The schematic is almost the same for

both, but the PWM dimming control circuitry has been

removed. If the same components are used, the operation

frequency will be slightly higher due to the lower pin

capacitance because the dimming transistor contribution is

removed.

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Figure 41. Schematic MR 16 Application

GND

DRV

VCC

IVC

12 V

NCL30100

Figure 42. PCB Top Side MR 16 Application

Figure 43. PCB Top Side Devices Placement Figure 44. PCB Bottom Side MR 16 Application

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Figure 45. PCB Bottom Side Devices Placement

Figure 46. Top Side Photo

Figure 47. Bottom Side Photo

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BILL OF MATERIALS FOR THE MR 16 EVALUATION BOARD (NCL30100ADLMGEVB)

Des-

ignat-

or Qty

Descrip-

tion Value Tol Footprint Manufacturer

Manufacturer

Part Number

Substitution

Allowed Pb−Free

Com-

ments

C1 1 Capacitor 2.2 mF / 25 V 10% 0805 AVX 08053C225KAT2A Yes Yes

C2 1 Capacitor 33 pF 5% 0603 Kemet C0603C330J5GACTU Yes Yes

C3 1 Capacitor 4.7 mF / 25 V 10% 0805 AVX 08053D475KAT2A Yes Yes

C4 1 Capacitor 1 nF 10% 0603 Kemet C0603C104K5RACTU Yes Yes

D1 1 Surface

Mount

Schottky

Power

Rectifier

MBR130T3G −SOD−123 ON Semiconductor MBR130T3G No Yes

D2 1 Zener

Diode

16 V 5% SOD−523 ON Semiconductor MM5Z16VT1G No Ye s

D3,

D4,

D5,

4 Schottky

Diode

NSR0340HT1G −SOD−323 ON Semiconductor NSR0340HT1G No Yes

D7 1 Schottky

Diode

NSR0520V2T1G −SOD−523 ON Semiconductor NSR0520V2T1G No Yes

IC1 1 LED

Driver

NCL30100 −TSOP−6ON Semiconductor NCL30100SNT1G No Yes

L1 1 Inductors 47 mH10% WE−PD2_M Wurth Electronik 744774147 No Yes

Q1 1 Power

MOSFET

NTGS4141NT1G −TSOP−6ON Semiconductor NTGS4141NT1G No Yes

Q1 1 Power

MOSFET

NU −SOT−223 ON Semiconductor NTF3055−100T1G No Yes Option

Q1 1 Power

MOSFET

NU −SOT−363 ON Semiconductor NTJS4160NT1G No Yes Option

Q1 1 Power

MOSFET

NU −SOT−23 ON Semiconductor NTR4170NT1G No Yes Option

R1 1 Resistor 1.5 M 1% 0603 Rohm Semiconductor MCR03EZPFX1504 Yes Yes

R2 1 Resistor 300 R 1% 0603 Rohm Semiconductor MCR03EZPFX3000 Yes Yes

R3 1 Resistor 30 k 1% 0603 Rohm Semiconductor MCR03EZPFX3002 Ye s Ye s

R4 1 Resistor 0.1 R 1% 0805 Welwyn LRCS0805−0R1FT5 Yes Yes

R5 1 Resistor 2.7 k 1% 0603 Rohm Semiconductor MCR03EZPFX2701 Yes Yes

Application Design Example for an Offline (115 Vac) Buck Application:

In addition to traditional DC−DC applications, the NCL30100 can also be used in offline applications, a schematic and PCB

layout are provided to illustrate a typical circuit configuration.

•Input voltage: Vin − 115 Vac

•Nominal LED current: 700 mA (rms)

•LEDripple: 120 mA (peak−to−peak)

•VLED: 3.2 V

•Freewheel diode Vf: 0.5 V

•Target Switching Frequency: 50 kHz

Dimming using PWM signal 1 kHz with duty cycle 0 – 99%

In this application example, there is schematic and PCB only. The design steps are the same as above mentioned.

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Figure 48. Design Example Schematic of 115 Vac Converter

47n

150k

GND

DRV

VCC

IVC

R33

24k

IC1

NCL30100

1N4148

5.6k

MRA4003

10k

5.6k

DIMM

0/5 V

Vac

CX1

2.2n

100u

2.2u

BC817−16L

560p10p

24k

MURA130

1mH

MTD6N20ET

GND

16V

The input voltage in range 85−140 Vac is rectified by

bridge rectifier D1, D3, D4 and D6. To limit current peaks

generated during on time period, capacitor C1 is used. CX1,

C2 and L1 are an EMI filter to protect mains against current

spikes mainly generated by D2 if Q1 is turned on. The

NCL30100 is powered through resistors R1 and R2. The

Vcc voltage is limited by D7. Maximum LED current is set

by resistors R3, R4 and R5. In this case Rsense is 0.33 W to

reach higher accuracy. A small capacitor C3 is used to filter

out spikes which are generated during the turn off of diode

D2. It is recommended to use L2 with low series resistance

since current is flowing through the inductor continuously

and D2 should be selected for low forward voltage drop and

fast reverse recovery time.

Figure 49. Component Side Figure 50. Single Layer PCB

Design for this Application

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Figure 51. ILED and Vin Waveform

Figure 52. ILED at the Peak of Sinusoidal Voltage

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Figure 53. Input Voltage and Input Current

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BILL OF MATERIALS FOR THE NCL30100 115 Vac

Des-

ignat-

or Qty Description Value Tol Footprint Manufacturer

Manufacturer

Part Number

Substitution

Allowed Pb−Free

Com-

ments

C1 1 Capacitor 2.2 mF / 200 V 10% E3.5−8 Koshin KR1 2.2u 200V 8X11.5 Yes Yes

C2 1 Capacitor 47 nF 10% 1206 Yageo CC1206KKX7RABB473 Yes Yes

C3 1 Capacitor 10 pF 5% 0603 Kemet C0603C100J5GACTU Yes Yes

C4 1 Capacitor 560 pF 5% 0603 Kemet C0603C561J5GACTU Ye s Ye s

C5 1 Capacitor 1 mF / 25 V 10% 0805 AVX 08053D105KAT2A Yes Yes

D1,

D3,

D4,

4 Standard

Recovery

Power

Rectifier

MRA4003T3G −SMA ON Semiconductor MRA4003T3G No Yes

D2 1 Ultrafast

Power

Rectifier

MURA130T3G −SMA ON Semiconductor MURA130T3G No Yes

D5 1 Standard

Diode

MMSD4148 −SOD−123 ON Semiconductor MMSD4148T1G No Yes

D7 1 Zener Diode 16 V 5% SOD−123 ON Semiconductor MMSZ16VT1G No Yes

IC1 1 LED Driver NCL30100 −TSOP−6ON Semiconductor NCL30100SNT1G No Yes

L1 1 Inductors 100 mH10% WE−PD4_L Wurth Electronik 7445620 No Ye s

L2 1 Inductors 1 mH 10% WE−PD_XXL Wurth Electronik 7447709102 No Yes

Q1 1 Power

MOSFET

MTD6N20 −DPAK ON Semiconductor MTD6N20ET4G No Yes

Q2 1 General

Purpose

Transistor

NPN

BC817−16 −SOT−23 ON Semiconductor BC817−16LT1G No Yes

Q2 1 Power

MOSFET

NU −SOT−23 ON Semiconductor NTS4001NT1G No Yes Option

R1,

2 Resistor 24 k 1% 0806 Rohm Semiconductor MCR06EZPFX2402 Yes Yes

R3 1 Resistor 150 k 1% 0603 Rohm Semiconductor MCR03EZPFX1503 Yes Yes

R4,

2 Resistor 5.6 k 1% 0603 Rohm Semiconductor MCR03EZPFX5601 Yes Yes

R5 1 Resistor 0.33 R 1% 0805 Welwyn LRCS0805−0R33FT5 Yes Yes

R7 1 Resistor 10 k 1% 0603 Rohm Semiconductor MCR03EZPFX1002 Yes Yes

CX1 1 EMI

Suppression

Capacitor

2.2 nF / 300 V 20% XC10B5 Epcos B32021A3222M289 Yes Yes

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PACKAGE DIMENSIONS

ÉÉÉ

TSOP−6

CASE 318G−02

ISSUE U

456

0.05

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM

LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D

AND E1 ARE DETERMINED AT DATUM H.

5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

DIM

MIN NOM MAX

MILLIMETERS

0.90 1.00 1.10

A1 0.01 0.06 0.10

b0.25 0.38 0.50

c0.10 0.18 0.26

D2.90 3.00 3.10

E2.50 2.75 3.00

e0.85 0.95 1.05

L0.20 0.40 0.60

0.25 BSC

−

0°10°

1.30 1.50 1.70

RECOMMENDED

NOTE 5

SEATING

PLANE

GAUGE

PLANE

DETAIL Z

0.60

3.20 0.95

0.95

PITCH

DIMENSIONS: MILLIMETERS

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

NCL30100/D

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