CYIV-53001-1.5
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Cyclone IV Device Handbook,
Volume 3
November 2011
Subscribe
ISO
9001:2008
Registered
1. Cyclone IV Device Datasheet
This chapter describes the electrical and switching characteristics for CycloneIV
devices. Electrical characteristics include operating conditions and power
consumption. Switching characteristics include transceiver specifications, core, and
periphery performance. This chapter also describes I/O timing, including
programmable I/O element (IOE) delay and programmable output buffer delay.
This chapter includes the following sections:
■“Operating Conditions” on page 1–1
■“Power Consumption” on page 1–15
■“Switching Characteristics” on page 1–16
■“I/O Timing” on page 1–38
■“Glossary” on page 1–38
Operating Conditions
When Cyclone IV devices are implemented in a system, they are rated according to a
set of defined parameters. To maintain the highest possible performance and
reliability of Cyclone IV devices, you must consider the operating requirements
described in this chapter.
Cyclone IV devices are offered in commercial, industrial, extended industrial and,
automotive grades. Cyclone IV E devices offer –6 (fastest), –7, –8, –8L, and –9L speed
grades for commercial devices, –8L speed grades for industrial devices, and –7 speed
grade for extended industrial and automotive devices. Cyclone IV GX devices offer
–6 (fastest), –7, and –8 speed grades for commercial devices and –7 speed grade for
industrial devices.
fFor more information about the supported speed grades for respective Cyclone IV
devices, refer to the Cyclone IV FPGA Device Family Overview chapter.
1Cyclone IV E devices are offered in core voltages of 1.0 and 1.2 V. Cyclone IV E
devices with a core voltage of 1.0 V have an ‘L’ prefix attached to the speed grade.
In this chapter, a prefix associated with the operating temperature range is attached to
the speed grades; commercial with a “C” prefix, industrial with an “I” prefix, and
automotive with an “A” prefix. Therefore, commercial devices are indicated as C6, C7,
C8, C8L, or C9L per respective speed grade. Industrial devices are indicated as I7, I8,
or I8L. Automotive devices are indicated as A7.
November 2011
CYIV-53001-1.5
1–2 Chapter 1: Cyclone IV Device Datasheet
Operating Conditions
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
1Cyclone IV E industrial devices I7 are offered with extended operating temperature
range.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Cyclone IV
devices. The values are based on experiments conducted with the device and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied at these conditions. Table 1–1 lists the absolute
maximum ratings for Cyclone IV devices.
cConditions beyond those listed in Table 1–1 cause permanent damage to the device.
Additionally, device operation at the absolute maximum ratings for extended periods
of time have adverse effects on the device.
Maximum Allowed Overshoot or Undershoot Voltage
During transitions, input signals may overshoot to the voltage shown in Table 1–2 and
undershoot to –2.0 V for a magnitude of currents less than 100 mA and for periods
shorter than 20 ns. Table 1–2 lists the maximum allowed input overshoot voltage and
the duration of the overshoot voltage as a percentage over the lifetime of the device.
The maximum allowed overshoot duration is specified as a percentage of high-time
over the lifetime of the device.
Table 1–1. Absolute Maximum Ratings for Cyclone IV Devices (1) —Preliminary
Symbol Parameter Min Max Unit
VCCINT
Core voltage, PCI Express (PCIe) hard IP
block, and transceiver physical coding sublayer
(PCS) power supply
–0.5 1.8 V
VCCA Phase-locked loop (PLL) analog power supply –0.5 3.75 V
VCCD_PLL PLL digital power supply –0.5 1.8 V
VCCIO I/O banks power supply –0.5 3.9 V
VCC_CLKIN Differential clock input pins power supply –0.5 3.9 V
VCCH_GXB Transceiver output buffer power supply –0.5 2.625 V
VCCA_GXB
Transceiver physical medium attachment (PMA)
and auxiliary power supply –0.5 2.625 V
VCCL_GXB Transceiver PMA and auxiliary power supply –0.5 1.8 V
VIDC input voltage –0.5 3.95 V
IOUT DC output current, per pin –25 40 mA
TSTG Storage temperature –65 150 °C
TJOperating junction temperature –40 125 °C
Note to Table 1–1:
(1) Supply voltage specifications apply to voltage readings taken at the device pins with respect to ground, not at the
power supply.
Chapter 1: Cyclone IV Device Datasheet 1–3
Operating Conditions
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
1A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to
4.3 V can only be at 4.3 V for 65% over the lifetime of the device; for a device lifetime
of 10 years, this amounts to 65/10ths of a year.
Figure 1–1 shows the methodology to determine the overshoot duration. The
overshoot voltage is shown in red and is present on the input pin of the Cyclone IV
device at over 4.3 V but below 4.4 V. From Table 1–2, for an overshoot of 4.3 V, the
percentage of high time for the overshoot can be as high as 65% over a 10-year period.
Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period
assumes that the device is always turned on with 100% I/O toggle rate and 50% duty
cycle signal. For lower I/O toggle rates and situations in which the device is in an idle
state, lifetimes are increased.
Table 1–2. Maximum Allowed Overshoot During Transitions over a 10-Year Time Frame for
Cyclone IV Devices
Symbol Parameter Condition (V) Overshoot Duration as % of High Time Unit
Vi
AC Input
Voltage
VI = 4.20 100 %
VI = 4.25 98 %
VI = 4.30 65 %
VI = 4.35 43 %
VI = 4.40 29 %
VI = 4.45 20 %
VI = 4.50 13 %
VI = 4.55 9 %
VI = 4.60 6 %
Figure 1–1. Cyclone IV Devices Overshoot Duration
3.3 V
4.3 V
4.4 V
T
DT
1–4 Chapter 1: Cyclone IV Device Datasheet
Operating Conditions
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
Recommended Operating Conditions
This section lists the functional operation limits for AC and DC parameters for
Cyclone IV devices. Table 1–3 and Table 1–4 list the steady-state voltage and current
values expected from Cyclone IV E and Cyclone IV GX devices. All supplies must be
strictly monotonic without plateaus.
Table 1–3. Recommended Operating Conditions for Cyclone IV E Devices (1), (2) (Part 1 of 2)
Symbol Parameter Conditions Min Typ Max Unit
VCCINT (3)
Supply voltage for internal logic,
1.2-V operation — 1.15 1.2 1.25 V
Supply voltage for internal logic,
1.0-V operation — 0.97 1.0 1.03 V
VCCIO (3), (4)
Supply voltage for output buffers,
3.3-V operation — 3.135 3.3 3.465 V
Supply voltage for output buffers,
3.0-V operation — 2.85 3 3.15 V
Supply voltage for output buffers,
2.5-V operation — 2.375 2.5 2.625 V
Supply voltage for output buffers,
1.8-V operation — 1.71 1.8 1.89 V
Supply voltage for output buffers,
1.5-V operation — 1.425 1.5 1.575 V
Supply voltage for output buffers,
1.2-V operation — 1.14 1.2 1.26 V
VCCA (3) Supply (analog) voltage for PLL
regulator — 2.375 2.5 2.625 V
VCCD_PLL (3)
Supply (digital) voltage for PLL,
1.2-V operation — 1.15 1.2 1.25 V
Supply (digital) voltage for PLL,
1.0-V operation — 0.97 1.0 1.03 V
VIInput voltage — –0.5 — 3.6 V
VOOutput voltage — 0 — VCCIO V
TJOperating junction temperature
For commercial use 0 — 85 °C
For industrial use –40 — 100 °C
For extended temperature (5) –40 — 125 °C
For automotive use –40 — 125 °C
tRAMP Power supply ramp time
Standard power-on reset
(POR) (6) 50 µs — 50 ms —
Fast POR (7) 50 µs — 3 ms —
Chapter 1: Cyclone IV Device Datasheet 1–5
Operating Conditions
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
IDiode
Magnitude of DC current across
PCI-clamp diode when enable ———10mA
Notes to Table 1–3:
(1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades.
(2) VCCIO for all I/O banks must be powered up during device operation. All
VCCA
pins must be powered to 2.5 V (even when PLLs are not used)
and must be powered up and powered down at the same time.
(3) VCC must rise monotonically.
(4) VCCIO powers all input buffers.
(5) The I7 devices support extended operating junction temperature up to 125°C (usual range is –40°C to 100°C). When using I7 devices at the
extended junction temperature ranging from –40°C to 125°C, select C8 as the target device when designing in the Quartus® II software. The I7
devices meet all C8 timing specifications when I7 devices operate beyond 100°C and up to 125°C.
(6) The POR time for Standard POR ranges between 50 and 200 ms. Each individual power supply must reach the recommended operating range
within 50 ms.
(7) The POR time for Fast POR ranges between 3 and 9 ms. Each individual power supply must reach the recommended operating range within
3ms.
Table 1–3. Recommended Operating Conditions for Cyclone IV E Devices (1), (2) (Part 2 of 2)
Symbol Parameter Conditions Min Typ Max Unit
Table 1–4. Recommended Operating Conditions for Cyclone IV GX Devices (Part 1 of 2)—Preliminary
Symbol Parameter Conditions Min Typ Max Unit
VCCINT (3) Core voltage, PCIe hard IP block, and
transceiver PCS power supply — 1.16 1.2 1.24 V
VCCA (1),(3) PLL analog power supply — 2.375 2.5 2.625 V
VCCD_PLL (2) PLL digital power supply — 1.16 1.2 1.24 V
VCCIO (3),(4)
I/O banks power supply for 3.3-V
operation — 3.135 3.3 3.465 V
I/O banks power supply for 3.0-V
operation — 2.85 3 3.15 V
I/O banks power supply for 2.5-V
operation — 2.375 2.5 2.625 V
I/O banks power supply for 1.8-V
operation — 1.71 1.8 1.89 V
I/O banks power supply for 1.5-V
operation — 1.425 1.5 1.575 V
I/O banks power supply for 1.2-V
operation — 1.14 1.2 1.26 V
VCC_CLKIN
(3),(5),(6)
Differential clock input pins power
supply for 3.3-V operation — 3.135 3.3 3.465 V
Differential clock input pins power
supply for 3.0-V operation — 2.85 3 3.15 V
Differential clock input pins power
supply for 2.5-V operation — 2.375 2.5 2.625 V
Differential clock input pins power
supply for 1.8-V operation — 1.71 1.8 1.89 V
Differential clock input pins power
supply for 1.5-V operation — 1.425 1.5 1.575 V
Differential clock input pins power
supply for 1.2-V operation — 1.14 1.2 1.26 V
1–6 Chapter 1: Cyclone IV Device Datasheet
Operating Conditions
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
ESD Performance
This section lists the electrostatic discharge (ESD) voltages using the human body
model (HBM) and charged device model (CDM) for Cyclone IV devices general
purpose I/Os (GPIOs) and high-speed serial interface (HSSI) I/Os. Table 1–5 lists the
ESD for Cyclone IV devices GPIOs and HSSI I/Os.
VCCH_GXB Transceiver output buffer power supply — 2.375 2.5 2.625 V
VCCA_GXB
Transceiver PMA and auxiliary power
supply — 2.375 2.5 2.625 V
VCCL_GXB
Transceiver PMA and auxiliary power
supply — 1.16 1.2 1.24 V
VIDC input voltage — –0.5 — 3.6 V
VODC output voltage — 0 — VCCIO V
TJOperating junction temperature For commercial use 0 — 85 °C
For industrial use –40 — 100 °C
tRAMP Power supply ramp time
Standard power-on reset
(POR) (7) 50 µs — 50 ms —
Fast POR (8) 50 µs — 3 ms —
IDiode
Magnitude of DC current across
PCI-clamp diode when enabled — ——10mA
Notes to Table 1–4:
(1) All
VCCA
pins must be powered to 2.5 V (even when PLLs are not used) and must be powered up and powered down at the same time.
(2) You must connect VCCD_PLL to VCCINT through a decoupling capacitor and ferrite bead.
(3) Power supplies must rise monotonically.
(4) VCCIO for all I/O banks must be powered up during device operation. Configurations pins are powered up by VCCIO of I/O Banks 3, 8, and 9 where
I/O Banks 3 and 9 only support VCCIO of 1.5, 1.8, 2.5, 3.0, and 3.3 V. For fast passive parallel (FPP) configuration mode, the VCCIO level of I/O
Bank 8 must be powered up to 1.5, 1.8, 2.5, 3.0, and 3.3 V.
(5) You must set VCC_CLKIN to 2.5 V if you use
CLKIN
as a high-speed serial interface (HSSI)
refclk
or as a
DIFFCLK
input.
(6) The
CLKIN
pins in I/O Banks 3B and 8B can support single-ended I/O standard when the pins are used to clock left PLLs in non-transceiver
applications.
(7) The POR time for Standard POR ranges between 50 and 200 ms. VCCINT, VCCA, and VCCIO of I/O Banks 3, 8, and 9 must reach the recommended
operating range within 50 ms.
(8) The POR time for Fast POR ranges between 3 and 9 ms. VCCINT
, VCCA, and VCCIO of I/O Banks 3, 8, and 9 must reach the recommended operating
range within 3 ms.
Table 1–4. Recommended Operating Conditions for Cyclone IV GX Devices (Part 2 of 2)—Preliminary
Symbol Parameter Conditions Min Typ Max Unit
Table 1–5. ESD for Cyclone IV Devices GPIOs and HSSI I/Os
Symbol Parameter Passing Voltage Unit
VESDHBM
ESD voltage using the HBM (GPIOs) (1) ± 2000 V
ESD using the HBM (HSSI I/Os) (2) ± 1000 V
VESDCDM
ESD using the CDM (GPIOs) ± 500 V
ESD using the CDM (HSSI I/Os) (2) ± 250 V
Notes to Table 1–5:
(1) The passing voltage for EP4CGX15 and EP4CGX30 row I/Os is ±1000V.
(2) This value is applicable only to Cyclone IV GX devices.
Chapter 1: Cyclone IV Device Datasheet 1–7
Operating Conditions
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
DC Characteristics
This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT)
tolerance, and bus hold specifications for Cyclone IV devices.
Supply Current
The device supply current requirement is the minimum current drawn from the
power supply pins that can be used as a reference for power size planning. Use the
Excel-based early power estimator (EPE) to get the supply current estimates for your
design because these currents vary greatly with the resources used. Table 1–6 lists the
I/O pin leakage current for Cyclone IV devices.
Bus Hold
The bus hold retains the last valid logic state after the source driving it either enters
the high impedance state or is removed. Each I/O pin has an option to enable bus
hold in user mode. Bus hold is always disabled in configuration mode.
Table 1–7 lists bus hold specifications for Cyclone IV devices.
Table 1–6. I/O Pin Leakage Current for Cyclone IV Devices (1), (2)
Symbol Parameter Conditions Device Min Typ Max Unit
IIInput pin leakage current VI = 0 V to VCCIOMAX — –10 — 10 A
IOZ
Tristated I/O pin leakage
current VO = 0 V to VCCIOMAX — –10 — 10 A
Notes to Table 1–6:
(1) This value is specified for normal device operation. The value varies during device power-up. This applies for all VCCIO settings (3.3, 3.0, 2.5,
1.8, 1.5, and 1.2 V).
(2) The 10 A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be observed when the diode is on.
Table 1–7. Bus Hold Parameter for Cyclone IV Devices (Part 1 of 2) (1)—Preliminary
Parameter Condition
VCCIO (V)
Unit1.2 1.5 1.8 2.5 3.0 3.3
Min Max Min Max Min Max Min Max Min Max Min Max
Bus hold
low,
sustaining
current
VIN > VIL
(maximum) 8 — 12 — 30—50—70—70—A
Bus hold
high,
sustaining
current
VIN < VIL
(minimum) –8 — –12 — –30 — –50 — –70 — –70 — A
Bus hold
low,
overdrive
current
0 V < VIN < VCCIO — 125 — 175 — 200 — 300 — 500 — 500 A
Bus hold
high,
overdrive
current
0 V < VIN < VCCIO — –125 — –175 — –200 — –300 — –500 — –500 A
1–8 Chapter 1: Cyclone IV Device Datasheet
Operating Conditions
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
OCT Specifications
Table 1–8 lists the variation of OCT without calibration across process, temperature,
and voltage (PVT).
OCT calibration is automatically performed at device power-up for OCT-enabled
I/Os.
Table 1–9 lists the OCT calibration accuracy at device power-up.
Bus hold trip
point — 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V
Note to Table 1–7:
(1) Bus hold trip points are based on the calculated input voltages from the JEDEC standard.
Table 1–7. Bus Hold Parameter for Cyclone IV Devices (Part 2 of 2) (1)—Preliminary
Parameter Condition
VCCIO (V)
Unit1.2 1.5 1.8 2.5 3.0 3.3
Min Max Min Max Min Max Min Max Min Max Min Max
Table 1–8. Series OCT Without Calibration Specifications for Cyclone IV Devices—Preliminary
Description VCCIO (V)
Resistance Tolerance
Unit
Commercial Maximum
Industrial, Extended
industrial, and
Automotive Maximum
Series OCT without
calibration
3.0 ±30 ±40 %
2.5 ±30 ±40 %
1.8 ±40 ±50 %
1.5 ±50 ±50 %
1.2 ±50 ±50 %
Table 1–9. Series OCT with Calibration at Device Power-Up Specifications for Cyclone IV Devices
—Preliminary
Description VCCIO (V)
Calibration Accuracy
Unit
Commercial Maximum
Industrial, Extended
industrial, and
Automotive Maximum
Series OCT with
calibration at device
power-up
3.0 ±10 ±10 %
2.5 ±10 ±10 %
1.8 ±10 ±10 %
1.5 ±10 ±10 %
1.2 ±10 ±10 %
Chapter 1: Cyclone IV Device Datasheet 1–9
Operating Conditions
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
The OCT resistance may vary with the variation of temperature and voltage after
calibration at device power-up. Use Table 1–10 and Equation 1–1 to determine the
final OCT resistance considering the variations after calibration at device power-up.
Table 1–10 lists the change percentage of the OCT resistance with voltage and
temperature.
Table 1–10. OCT Variation After Calibration at Device Power-Up for Cyclone IV Devices—
Preliminary
Nominal Voltage dR/dT (%/°C) dR/dV (%/mV)
3.0 0.262 –0.026
2.5 0.234 –0.039
1.8 0.219 –0.086
1.5 0.199 –0.136
1.2 0.161 –0.288
Equation 1–1. Final OCT Resistance (1), (2), (3), (4), (5), (6)
RV = (V2 – V1) × 1000 × dR/dV ––––– (7)
RT = (T2 – T1) × dR/dT ––––– (8)
For Rx < 0; MFx = 1/ (|Rx|/100 + 1) ––––– (9)
For Rx > 0; MFx = Rx/100 + 1 ––––– (10)
MF = MFV × MFT ––––– (11)
Rfinal = Rinitial × MF ––––– (12)
Notes to Equation 1–1:
(1) T2 is the final temperature.
(2) T1 is the initial temperature.
(3) MF is multiplication factor.
(4) Rfinal is final resistance.
(5) Rinitial is initial resistance.
(6) Subscript x refers to both V and T
.
(7) RV is a variation of resistance with voltage.
(8) RT is a variation of resistance with temperature.
(9) dR/dT is the change percentage of resistance with temperature after calibration at device power-up.
(10) dR/dV is the change percentage of resistance with voltage after calibration at device power-up.
(11) V2 is final voltage.
(12) V1 is the initial voltage.
1–10 Chapter 1: Cyclone IV Device Datasheet
Operating Conditions
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
Example 1–1 shows how to calculate the change of 50-I/O impedance from 25°C at
3.0 V to 85°C at 3.15 V.
Pin Capacitance
Table 1–11 lists the pin capacitance for Cyclone IV devices.
Example 1–1. Impedance Change
RV = (3.15 – 3) × 1000 × –0.026 = –3.83
RT = (85 – 25) × 0.262 = 15.72
Because RV is negative,
MFV = 1 / (3.83/100 + 1) = 0.963
Because RT is positive,
MFT = 15.72/100 + 1 = 1.157
MF = 0.963 × 1.157 = 1.114
Rfinal = 50 × 1.114 = 55.71
Table 1–11. Pin Capacitance for Cyclone IV Devices —Preliminary
Symbol Parameter
Typical –
Quad Flat
Pack
(QFP)
Typical –
Quad Flat
No Leads
(QFN)
Typical –
Fineline
BGA
(FBGA)
Unit
CIOTB Input capacitance on top and bottom I/O pins 7 7 6 pF
CIOLR Input capacitance on right I/O pins 7 7 5 pF
CLVDSLR Input capacitance on right I/O pins with dedicated LVDS output 8 8 7 pF
CVREFLR
(1)
Input capacitance on right dual-purpose
VREF
pin when used as
VREF or user I/O pin 21 21 21 pF
CVREFTB
(1)
Input capacitance on top and bottom dual-purpose
VREF
pin when
used as VREF or user I/O pin 23 (2) 23 23 pF
CCLKTB Input capacitance on top and bottom dedicated clock input pins 7 7 6 pF
CCLKLR Input capacitance on right dedicated clock input pins 6 6 5 pF
Notes to Table 1–11:
(1) When you use the
VREF
pin as a regular input or output, you can expect a reduced performance of toggle rate and tCO because of higher pin
capacitance.
(2) CVREFTB for the EP4CE22 device is 30 pF.
Chapter 1: Cyclone IV Device Datasheet 1–11
Operating Conditions
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
Internal Weak Pull-Up and Weak Pull-Down Resistor
Table 1–12 lists the weak pull-up and pull-down resistor values for Cyclone IV
devices.
Hot-Socketing
Table 1–13 lists the hot-socketing specifications for Cyclone IV devices.
1During hot-socketing, the I/O pin capacitance is less than 15 pF and the clock pin
capacitance is less than 20 pF.
Table 1–12. Internal Weak Pull-Up and Weak Pull-Down Resistor Values for Cyclone IV Devices (1) —Preliminary
Symbol Parameter Conditions Min Typ Max Unit
R_PU
Value of the I/O pin pull-up resistor
before and during configuration, as
well as user mode if you enable the
programmable pull-up resistor option
VCCIO = 3.3 V ± 5% (2), (3) 72541k
VCCIO = 3.0 V ± 5% (2), (3) 72847k
VCCIO = 2.5 V ± 5% (2), (3) 83561k
VCCIO = 1.8 V ± 5% (2), (3) 10 57 108 k
VCCIO = 1.5 V ± 5% (2), (3) 13 82 163 k
VCCIO = 1.2 V ± 5% (2), (3) 19 143 351 k
R_PD
Value of the I/O pin pull-down resistor
before and during configuration
VCCIO = 3.3 V ± 5% (4) 61930k
VCCIO = 3.0 V ± 5% (4) 62236k
VCCIO = 2.5 V ± 5% (4) 62543k
VCCIO = 1.8 V ± 5% (4) 73571k
VCCIO = 1.5 V ± 5% (4) 8 50 112 k
Notes to Table 1–12:
(1) All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins. The weak pull-down feature is only available
for JTAG
TCK
.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(3) R_PU = (VCCIO –V
I)/IR_PU
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = VCC + 5% – 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = 0 V;
Maximum condition: 100°C; VCCIO = VCC – 5%, VI = 0 V; in which VI refers to the input voltage at the I/O pin.
(4) R_PD = VI/IR_PD
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = VCC –5%;
Maximum condition: 100°C; VCCIO = VCC – 5%, VI = VCC – 5%; in which VI refers to the input voltage at the I/O pin.
Table 1–13. Hot-Socketing Specifications for Cyclone IV Devices —Preliminary
Symbol Parameter Maximum
IIOPIN(DC) DC current per I/O pin 300 A
IIOPIN(AC) AC current per I/O pin 8 mA (1)
IXCVRTX(DC) DC current per transceiver
TX
pin 100 mA
IXCVRRX(DC) DC current per transceiver
RX
pin 50 mA
Note to Table 1–13:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
1–12 Chapter 1: Cyclone IV Device Datasheet
Operating Conditions
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
Schmitt Trigger Input
Cyclone IV devices support Schmitt trigger input on the
TDI
,
TMS
,
TCK
,
nSTATUS
,
nCONFIG
,
nCE
,
CONF_DONE
, and
DCLK
pins. A Schmitt trigger feature introduces
hysteresis to the input signal for improved noise immunity, especially for signals with
slow edge rate. Table 1–14 lists the hysteresis specifications across the supported
VCCIO range for Schmitt trigger inputs in Cyclone IV devices.
I/O Standard Specifications
The following tables list input voltage sensitivities (VIH and VIL), output voltage (VOH
and VOL), and current drive characteristics (IOH and IOL), for various I/O standards
supported by Cyclone IV devices. Table 1–15 through Table 1–20 provide the I/O
standard specifications for Cyclone IV devices.
Table 1–14. Hysteresis Specifications for Schmitt Trigger Input in Cyclone IV Devices—
Preliminary
Symbol Parameter Conditions (V) Minimum Unit
VSCHMITT
Hysteresis for Schmitt trigger
input
VCCIO = 3.3 200 mV
VCCIO = 2.5 200 mV
VCCIO = 1.8 140 mV
VCCIO = 1.5 110 mV
Table 1–15. Single-Ended I/O Standard Specifications for Cyclone IV Devices (1), (2) —Preliminary
I/O Standard
VCCIO (V) VIL (V) VIH (V) VOL (V) VOH (V) IOL
(mA)
IOH
(mA)
Min Typ Max Min Max Min Max Max Min
3.3-V LVTTL (3) 3.135 3.3 3.465 — 0.8 1.7 3.6 0.45 2.4 4 –4
3.3-V LVCMOS (3) 3.135 3.3 3.465 — 0.8 1.7 3.6 0.2 VCCIO – 0.2 2 –2
3.0-V LVTTL (3) 2.85 3.0 3.15 –0.3 0.8 1.7 VCCIO + 0.3 0.45 2.4 4 –4
3.0-V LVCMOS (3) 2.85 3.0 3.15 –0.3 0.8 1.7 VCCIO + 0.3 0.2 VCCIO – 0.2 0.1 –0.1
2.5 V (3) 2.375 2.5 2.625 –0.3 0.7 1.7 VCCIO + 0.3 0.4 2.0 1 –1
1.8 V 1.71 1.8 1.89 –0.3 0.35 x
VCCIO
0.65 x
VCCIO
2.25 0.45 VCCIO –
0.45 2–2
1.5 V 1.425 1.5 1.575 –0.3 0.35 x
VCCIO
0.65 x
VCCIO
VCCIO + 0.3 0.25 x
VCCIO
0.75 x
VCCIO
2–2
1.2 V 1.14 1.2 1.26 –0.3 0.35 x
VCCIO
0.65 x
VCCIO
VCCIO + 0.3 0.25 x
VCCIO
0.75 x
VCCIO
2–2
3.0-V PCI 2.85 3.0 3.15 — 0.3 x
VCCIO
0.5 x
VCCIO
VCCIO + 0.3 0.1 x VCCIO 0.9 x VCCIO 1.5 –0.5
3.0-V PCI-X 2.85 3.0 3.15 — 0.35 x
VCCIO
0.5 x
VCCIO
VCCIO + 0.3 0.1 x VCCIO 0.9 x VCCIO 1.5 –0.5
Notes to Table 1–15:
(1) For voltage-referenced receiver input waveform and explanation of terms used in Table 1–15, refer to “Glossary” on page 1–38.
(2) AC load CL = 10 pF
(3) For more information about interfacing Cyclone IV devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III
and Cyclone IV Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
Chapter 1: Cyclone IV Device Datasheet 1–13
Operating Conditions
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
Table 1–16. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Cyclone IV Devices (1)
—Preliminary
I/O
Standard
VCCIO (V) VREF (V) VTT (V) (2)
Min Typ Max Min Typ Max Min Typ Max
SSTL-2
Class I, II 2.375 2.5 2.625 1.19 1.25 1.31 VREF –
0.04 VREF
VREF +
0.04
SSTL-18
Class I, II 1.7 1.8 1.9 0.833 0.9 0.969 VREF –
0.04 VREF
VREF +
0.04
HSTL-18
Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 0.85 0.9 0.95
HSTL-15
Class I, II 1.425 1.5 1.575 0.71 0.75 0.79 0.71 0.75 0.79
HSTL-12
Class I, II 1.14 1.2 1.26 0.48 x VCCIO (3) 0.5 x VCCIO (3) 0.52 x VCCIO (3)
—0.5 x
VCCIO
—
0.47 x VCCIO (4) 0.5 x VCCIO (4) 0.53 x VCCIO (4)
Notes to Table 1–16:
(1) For an explanation of terms used in Table 1–16, refer to “Glossary” on page 1–38.
(2) VTT of the transmitting device must track VREF of the receiving device.
(3) Value shown refers to DC input reference voltage, VREF(DC).
(4) Value shown refers to AC input reference voltage, VREF(AC).
Table 1–17. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Cyclone IV Devices—Preliminary
I/O
Standard
VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL
(mA)
IOH
(mA)
Min Max Min Max Min Max Min Max Max Min
SSTL-2
Class I —VREF –
0.18
VREF +
0.18 ——
VREF –
0.35
VREF +
0.35 —VTT –
0.57
VTT +
0.57 8.1 –8.1
SSTL-2
Class II —VREF –
0.18
VREF +
0.18 ——
VREF –
0.35
VREF +
0.35 —VTT –
0.76
VTT +
0.76 16.4 –16.4
SSTL-18
Class I —VREF –
0.125
VREF +
0.125 ——
VREF –
0.25
VREF +
0.25 —VTT –
0.475
VTT +
0.475 6.7 –6.7
SSTL-18
Class II —VREF –
0.125
VREF +
0.125 ——
VREF –
0.25
VREF +
0.25 —0.28
VCCIO –
0.28 13.4 –13.4
HSTL-18
Class I —VREF –
0.1
VREF +
0.1 ——
VREF –
0.2
VREF +
0.2 —0.4
VCCIO –
0.4 8–8
HSTL-18
Class II —VREF –
0.1
VREF +
0.1 ——
VREF –
0.2
VREF +
0.2 —0.4
VCCIO –
0.4 16 –16
HSTL-15
Class I —VREF –
0.1
VREF +
0.1 ——
VREF –
0.2
VREF +
0.2 —0.4
VCCIO –
0.4 8–8
HSTL-15
Class II —VREF –
0.1
VREF +
0.1 ——
VREF –
0.2
VREF +
0.2 —0.4
VCCIO –
0.4 16 –16
HSTL-12
Class I –0.15 VREF –
0.08
VREF +
0.08 VCCIO + 0.15 –0.24 VREF –
0.15
VREF +
0.15
VCCIO +
0.24
0.25 ×
VCCIO
0.75 ×
VCCIO
8–8
HSTL-12
Class II –0.15 VREF –
0.08
VREF +
0.08 VCCIO + 0.15 –0.24 VREF –
0.15
VREF +
0.15
VCCIO +
0.24
0.25 ×
VCCIO
0.75 ×
VCCIO
14 –14
1–14 Chapter 1: Cyclone IV Device Datasheet
Operating Conditions
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
fFor more information about receiver input and transmitter output waveforms, and for
other differential I/O standards, refer to the I/O Features in Cyclone IV Devices chapter.
Table 1–18. Differential SSTL I/O Standard Specifications for Cyclone IV Devices (1)—Preliminary
I/O Standard
VCCIO (V) VSwing(DC) (V) VX(AC) (V) VSwing(AC)
(V) VOX(AC) (V)
Min Typ Max Min Max Min Typ Max Min Max Min Typ Max
SSTL-2
Class I, II 2.375 2.5 2.625 0.36 VCCIO VCCIO/2 – 0.2 — VCCIO/2
+ 0.2 0.7 VCCI
O
VCCIO/2 –
0.125 —VCCIO/2
+ 0.125
SSTL-18
Class I, II 1.7 1.8 1.90 0.25 VCCIO
VCCIO/2 –
0.175 —VCCIO/2
+ 0.175 0.5 VCCI
O
VCCIO/2 –
0.125 —VCCIO/2
+ 0.125
Note to Table 1–18:
(1) Differential SSTL requires a VREF input.
Table 1–19. Differential HSTL I/O Standard Specifications for Cyclone IV Devices (1)—Preliminary
I/O Standard
VCCIO (V) VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC) (V)
Min Typ Max Min Max Min Typ Max Min Typ Max Mi
nMax
HSTL-18
Class I, II 1.71 1.8 1.89 0.2 — 0.85 — 0.95 0.85 — 0.95 0.4 —
HSTL-15
Class I, II 1.425 1.5 1.575 0.2 — 0.71 — 0.79 0.71 — 0.79 0.4 —
HSTL-12
Class I, II 1.14 1.2 1.26 0.16 VCCIO 0.48 x VCCIO —0.52 x
VCCIO
0.48 x
VCCIO
—0.52 x
VCCIO
0.3 0.48 x
VCCIO
Note to Table 1–19:
(1) Differential HSTL requires a VREF input.
Table 1–20. Differential I/O Standard Specifications for Cyclone IV Devices (1) (Part 1 of 2)—Preliminary
I/O Standard
VCCIO (V) VID (mV) VIcM (V) (2) VOD (mV) (3) VOS (V) (3)
Min Typ Max Min Max Min Condition Max Min Typ Max Min Typ Max
LVPECL
(Row I/Os)
(6)
2.375 2.5 2.625 100 —
0.05 DMAX500 Mbps 1.80
——— — — —0.55 500 Mbps D
MAX
700 Mbps 1.80
1.05 DMAX > 700 Mbps 1.55
LVPECL
(Column
I/Os) (6)
2.375 2.5 2.625 100 —
0.05 DMAX 500 Mbps 1.80
——— — — —0.55 500 Mbps DMAX
700 Mbps 1.80
1.05 DMAX > 700 Mbps 1.55
LVDS (Row
I/Os) 2.375 2.5 2.625 100 —
0.05 DMAX 500 Mbps 1.80
247 — 600 1.125 1.25 1.375 0.55 500 Mbps DMAX
700 Mbps 1.80
1.05 DMAX > 700 Mbps 1.55
Chapter 1: Cyclone IV Device Datasheet 1–15
Power Consumption
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
Power Consumption
Use the following methods to estimate power for a design:
■the Excel-based EPE
■the QuartusII PowerPlay power analyzer feature
The interactive Excel-based EPE is used prior to designing the device to get a
magnitude estimate of the device power. The Quartus II PowerPlay power analyzer
provides better quality estimates based on the specifics of the design after
place-and-route is complete. The PowerPlay power analyzer can apply a combination
of user-entered, simulation-derived, and estimated signal activities that, combined
with detailed circuit models, can yield very accurate power estimates.
LVDS
(Column
I/Os)
2.375 2.5 2.625 100 —
0.05 DMAX 500 Mbps 1.80
247 — 600 1.125 1.25 1.3750.55 500 Mbps DMAX
700 Mbps 1.80
1.05 DMAX > 700 Mbps 1.55
BLVDS (Row
I/Os) (4) 2.375 2.5 2.625 100 — — — — — — — — — —
BLVDS
(Column
I/Os) (4)
2.375 2.5 2.625 100 — — — — — — — — — —
mini-LVDS
(Row I/Os)
(5)
2.375 2.5 2.625 — — — — — 300 — 600 1.0 1.2 1.4
mini-LVDS
(Column
I/Os) (5)
2.375 2.5 2.625 — — — — — 300 — 600 1.0 1.2 1.4
RSDS® (Row
I/Os) (5) 2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.5
RSDS
(Column
I/Os) (5)
2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.5
PPDS (Row
I/Os) (5) 2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.4
PPDS
(Column
I/Os) (5)
2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.4
Notes to Table 1–20:
(1) For an explanation of terms used in Table 1–20, refer to “Glossary” on page 1–38.
(2) VIN range: 0 V VIN 1.85 V.
(3) RL range: 90 R
L 110 .
(4) There are no fixed VIN, VOD, and VOS specifications for BLVDS. They depend on the system topology.
(5) The Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins.
(6) The LVPECL I/O standard is only supported on dedicated clock input pins. This I/O standard is not supported for output pins.
Table 1–20. Differential I/O Standard Specifications for Cyclone IV Devices (1) (Part 2 of 2)—Preliminary
I/O Standard
VCCIO (V) VID (mV) VIcM (V) (2) VOD (mV) (3) VOS (V) (3)
Min Typ Max Min Max Min Condition Max Min Typ Max Min Typ Max
1–16 Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
fFor more information about power estimation tools, refer to the Early Power Estimator
User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II
Handbook.
Switching Characteristics
This section provides performance characteristics of Cyclone IV core and periphery
blocks for commercial grade devices.
These characteristics can be designated as Preliminary or Final.
■Preliminary characteristics are created using simulation results, process data, and
other known parameters. The upper-right hand corner of these tables show the
designation as “Preliminary”.
■Final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon
process, voltage, and junction temperature conditions. There are no designations
on finalized tables.
Chapter 1: Cyclone IV Device Datasheet 1–17
Switching Characteristics
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
Transceiver Performance Specifications
Table 1–21 lists the Cyclone IV GX transceiver specifications.
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 1 of 4)—Preliminary
Symbol/
Description Conditions
C6 C7, I7 C8
Unit
Min Typ Max Min Typ Max Min Typ Max
Reference Clock
Supported I/O
Standards 1.2 V PCML, 1.5 V PCML, 3.3 V PCML, Differential LVPECL, LVDS, HCSL
Input frequency
from
REFCLK
input
pins
— 50 — 156.25 50 — 156.25 50 — 156.25 MHz
Spread-spectrum
modulating clock
frequency
Physical interface
for PCI Express
(PIPE) mode
30 — 33 30 — 33 30 — 33 kHz
Spread-spectrum
downspread PIPE mode — 0 to
–0.5% ——
0 to
–0.5% ——
0 to
–0.5% ——
VICM (AC coupled) 1100 ± 5% 1100 ± 5% 1100 ± 5% mV
VICM (DC coupled)
HCSL I/O
standard for PCIe
reference clock
250 — 550 250 — 550 250 — 550 mV
Transmitter REFCLK
Phase Noise (1) Frequency offset
= 1MHz – 8MHZ
—— –123 — — –123 — — –123 dBc/Hz
Transmitter REFCLK
Total Jitter (1) — — 42.3 — — 42.3 — — 42.3 ps
Rref ——
2000
± 1% ——
2000
± 1% ——
2000
± 1% —
Transceiver Clock
cal_blk_clk
clock
frequency — 10 — 125 10 — 125 10 — 125 MHz
fixedclk
clock
frequency
PCIe Receiver
Detect — 125 — — 125 — — 125 — MHz
reconfig_clk
clock frequency
Dynamic
reconfiguration
clock frequency
2.5/
37.5
(2)
—50
2.5/
37.5
(2)
—50
2.5/
37.5
(2)
—50MHz
Delta time between
reconfig_clk
———2——2——2ms
Transceiver block
minimum
power-down pulse
width
——1——1——1—µs
Receiver
Supported I/O
Standards
1.4 V PCML,
1.5 V PCML,
2.5 V PCML,
LVPECL, LVDS
1–18 Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
Data rate (F324 and
smaller package) — 600 — 2500 600 — 2500 600 — 2500 Mbps
Data rate (F484 and
larger package) — 600 — 3125 600 — 3125 600 — 2500 Mbps
Absolute VMAX for a
receiver pin (3) — — — 1.6 — — 1.6 — — 1.6 V
Operational VMAX for
a receiver pin — — — 1.5 — — 1.5 — — 1.5 V
Absolute VMIN for a
receiver pin —–0.4 — — –0.4 — — –0.4 — — V
Peak-to-peak
differential input
voltage VID (diff p-p)
VICM = 0.82 V
setting, Data Rate
= 600 Mbps to
3.125 Gbps
0.1 — 2.7 0.1 — 2.7 0.1 — 2.7 V
VICM VICM = 0.82 V
setting —820 ±
10% ——
820 ±
10% ——
820 ±
10% —mV
Differential on-chip
termination resistors
100 setting — 100 — — 100 — — 100 —
150 setting — 150 — — 150 — — 150 —
Differential and
common mode
return loss
PIPE, Serial
Rapid I/O SR,
SATA, CPRI LV,
SDI, XAUI
Compliant —
Programmable ppm
detector (4) —± 62.5, 100, 125, 200,
250, 300 ppm
Clock data recovery
(CDR) ppm
tolerance (without
spread-spectrum
clocking enabled)
———
±300 (5),
±350
(6),(7)
——
±300
(5),
±350
(6),(7)
——
±300
(5),
±350
(6),(7)
ppm
CDR ppm tolerance
(with synchronous
spread-spectrum
clocking enabled) (8)
———
350 to
–5350
(7),(9)
——
350 to
–5350
(7),(9)
——
350 to
–5350
(7),(9)
ppm
Run length — — 80 — — 80 — — 80 — UI
Programmable
equalization
No Equalization — — 1.5 — — 1.5 — — 1.5 dB
Medium Low — — 4.5 — — 4.5 — — 4.5 dB
Medium High — — 5.5 — — 5.5 — — 5.5 dB
High — — 7 — — 7 — — 7 dB
Signal detect/loss
threshold PIPE mode 65 — 175 65 — 175 65 — 175 mV
tLTR (10) — —— 75 —— 75—— 75 µs
tLTR-LTD_Manual (11) — 15— — 15— —15— — µs
tLTD (12) — 0 100 4000 0 100 4000 0 100 4000 ns
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 2 of 4)—Preliminary
Symbol/
Description Conditions
C6 C7, I7 C8
Unit
Min Typ Max Min Typ Max Min Typ Max
Chapter 1: Cyclone IV Device Datasheet 1–19
Switching Characteristics
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
tLTD_Manual (13) — — — 4000 — — 4000 — — 4000 ns
tLTD_Auto (14) — — — 4000 — — 4000 — — 4000 ns
Receiver buffer and
CDR offset
cancellation time
(per channel)
— — — 17000 — — 17000 — — 17000
recon
fig_c
lk
cycles
Programmable DC
gain
DC Gain Setting =
0—0 — —0 ——0 —dB
DC Gain Setting =
1—3 — —3 ——3 —dB
DC Gain Setting =
2—6 — —6 ——6 —dB
Transmitter
Supported I/O
Standards 1.5 V PCML
Data rate (F324 and
smaller package) — 600 — 2500 600 — 2500 600 — 2500 Mbps
Data rate (F484 and
larger package) — 600 — 3125 600 — 3125 600 — 2500 Mbps
VOCM 0.65 V setting — 650 — — 650 — — 650 — mV
Differential on-chip
termination resistors
100 setting — 100 — — 100 — — 100 —
150 setting — 150 — — 150 — — 150 —
Differential and
common mode
return loss
PIPE, CPRI LV,
Serial Rapid I/O
SR, SDI, XAUI,
SATA
Compliant —
Rise time — 50 — 200 50 — 200 50 — 200 ps
Fall time — 50 — 200 50 — 200 50 — 200 ps
Intra-differential pair
skew — — — 15 — — 15 — — 15 ps
Intra-transceiver
block skew — — — 120 — — 120 — — 120 ps
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 3 of 4)—Preliminary
Symbol/
Description Conditions
C6 C7, I7 C8
Unit
Min Typ Max Min Typ Max Min Typ Max
1–20 Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
PLD-Transceiver Interface
Interface speed
(F324 and smaller
package)
— 25 — 125 25 — 125 25 — 125 MHz
Interface speed
(F484 and larger
package)
— 25 — 156.25 25 — 156.25 25 — 156.25 MHz
Digital reset pulse
width — Minimum is 2 parallel clock cycles
Notes to Table 1–21:
(1) This specification is valid for transmitter output jitter specification with a maximum total jitter value of 112 ps, typically for 3.125 Gbps SRIO and XAUI
protocols.
(2) The minimum
reconfig_clk
frequency is 2.5 MHz if the transceiver channel is configured in Transmitter Only mode. The minimum
reconfig_clk
frequency
is 37.5 MHz if the transceiver channel is configured in Receiver Only or Receiver and Transmitter mode.
(3) The device cannot tolerate prolonged operation at this absolute maximum.
(4) The rate matcher supports only up to ±300 parts per million (ppm).
(5) Supported for the N148, F169, and F324 device packages only.
(6) Supported for the F484, F672, and F896 device packages only. Pending device characterization.
(7) To support CDR ppm tolerance greater than ±300 ppm, implement ppm detector in user logic and configure CDR to Manual Lock Mode.
(8) Asynchronous spread-spectrum clocking is not supported.
(9) For the EP4CGX30 (F484 package only), EP4CGX50, and EP4CGX75 devices, the CDR ppl tolerance is ±200 ppm.
(10) Time taken until
pll_locked
goes high after
pll_powerdown
deasserts.
(11) Time that the CDR must be kept in lock-to-reference mode after
rx_analogreset
deasserts and before
rx_locktodata
is asserted in manual mode.
(12) Time taken to recover valid data after the
rx_locktodata
signal is asserted in manual mode (Figure 1–2), or after
rx_freqlocked
signal goes high in
automatic mode (Figure 1–3).
(13) Time taken to recover valid data after the
rx_locktodata
signal is asserted in manual mode.
(14) Time taken to recover valid data after the
rx_freqlocked
signal goes high in automatic mode.
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 4 of 4)—Preliminary
Symbol/
Description Conditions
C6 C7, I7 C8
Unit
Min Typ Max Min Typ Max Min Typ Max
Chapter 1: Cyclone IV Device Datasheet 1–21
Switching Characteristics
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
Figure 1–2 shows the lock time parameters in manual mode.
1LTD = lock-to-data. LTR = lock-to-reference.
Figure 1–3 shows the lock time parameters in automatic mode.
Figure 1–2. Lock Time Parameters for Manual Mode
rx _analogreset
rx _ digitalreset
Reset Signals
Output Status Signals
rx _ locktorefclk
2
3
4
CDR Control Signals
rx _ locktodata
3
busy
1
Two parallel clock cycles
LTD_Manual (2)
t
LTR_LTD_Manual (1)
t
Figure 1–3. Lock Time Parameters for Automatic Mode
Reset Signals
rx _ analogreset
2
Output Status Signals
rx _ freqlocked
3
rx _ digitalreset
4
busy
1
Two parallel clock cycles
LTD_Auto (1)
t
1–22 Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
Figure 1–4 shows the differential receiver input waveform.
Figure 1–5 shows the transmitter output waveform.
Table 1–22 lists the typical VOD for Tx term that equals 100 ..
Figure 1–4. Receiver Input Waveform
Single-Ended Waveform
Differential Waveform VID (diff peak-peak) = 2 x VID (single-ended)
Positive Channel (p)
Negative Channel (n)
Ground
V
ID
V
ID
V
ID
p − n = 0 V
V
CM
Figure 1–5. Transmitter Output Waveform—Preliminary
Single-Ended Waveform
Differential Waveform VOD (diff peak-peak) = 2 x VOD (single-ended)
Positive Channel (p)
Negative Channel (n)
Ground
V
OD
V
OD
V
OD
p − n = 0 V
V
CM
Table 1–22. Typical VOD Setting, Tx Term = 100 —Preliminary
Symbol
VOD Setting (mV)
1234
(1) 56
VOD Typical (mV) 400 600 800 900 1000 1200
Note to Table 1–22:
(1) This setting is required for compliance with the PCIe protocol.
Chapter 1: Cyclone IV Device Datasheet 1–23
Switching Characteristics
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
Table 1–23 lists the Cyclone IV GX transceiver block AC specifications.
Core Performance Specifications
The following sections describe the clock tree specifications, PLLs, embedded
multiplier, memory block, and configuration specifications for Cyclone IV Devices.
Clock Tree Specifications
Table 1–24 lists the clock tree specifications for Cyclone IV devices.
Table 1–23. Transceiver Block AC Specification for Cyclone IV GX Devices (1), (2) —Preliminary
Symbol/
Description Conditions
C6 C7, I7 C8
Unit
Min Typ Max Min Typ Max Min Typ Max
PCIe Transmit Jitter Generation (3)
Total jitter at 2.5 Gbps
(Gen1) Compliance pattern — — 0.25 — — 0.25 — — 0.25 UI
PCIe Receiver Jitter Tolerance (3)
Total jitter at 2.5 Gbps
(Gen1) Compliance pattern > 0.6 > 0.6 > 0.6 UI
GIGE Transmit Jitter Generation (4)
Deterministic jitter
(peak-to-peak) Pattern = CRPAT ——0.14——0.14——0.14UI
Total jitter (peak-to-peak) Pattern = CRPAT — — 0.279 — — 0.279 — — 0.279 UI
GIGE Receiver Jitter Tolerance (4)
Deterministic jitter
tolerance (peak-to-peak) Pattern = CJPAT > 0.4 > 0.4 > 0.4 UI
Combined deterministic
and random jitter
tolerance (peak-to-peak)
Pattern = CJPAT > 0.66 > 0.66 > 0.66 UI
Notes to Table 1–23:
(1) Dedicated
refclk
pins were used to drive the input reference clocks.
(2) The jitter numbers specified are valid for the stated conditions only.
(3) The jitter numbers for PIPE are compliant to the PCIe Base Specification 2.0.
(4) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
Table 1–24. Clock Tree Performance for Cyclone IV Devices (Part 1 of 2)—Preliminary
Device
Performance
Unit
C6 C7 C8 C8L (1) C9L (1) I7 I8L (1) A7
EP4CE6 500 437.5 402 362 265 437.5 362 402 MHz
EP4CE10 500 437.5 402 362 265 437.5 362 402 MHz
EP4CE15 500 437.5 402 362 265 437.5 362 402 MHz
EP4CE22 500 437.5 402 362 265 437.5 362 402 MHz
EP4CE30 500 437.5 402 362 265 437.5 362 402 MHz
EP4CE40 500 437.5 402 362 265 437.5 362 402 MHz
1–24 Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
PLL Specifications
Table 1–25 lists the PLL specifications for Cyclone IV devices when operating in the
commercial junction temperature range (0°C to 85°C), the industrial junction
temperature range (–40°C to 100°C), the extended industrial junction temperature
range (–40°C to 125°C), and the automotive junction temperature range (–40°C to
125°C). For more information about the PLL block, refer to “Glossary” on page 1–38.
EP4CE55 500 437.5 402 362 265 437.5 362 — MHz
EP4CE75 500 437.5 402 362 265 437.5 362 — MHz
EP4CE115 — 437.5 402 362 265 437.5 362 — MHz
EP4CGX15 500 437.5 402 — — 437.5 — — MHz
EP4CGX22 500 437.5 402 — — 437.5 — — MHz
EP4CGX30 500 437.5 402 — — 437.5 — — MHz
EP4CGX50 500 437.5 402 — — 437.5 — — MHz
EP4CGX75 500 437.5 402 — — 437.5 — — MHz
EP4CGX110 500 437.5 402 — — 437.5 — — MHz
EP4CGX150 500 437.5 402 — — 437.5 — — MHz
Note to Table 1–24:
(1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades.
Table 1–24. Clock Tree Performance for Cyclone IV Devices (Part 2 of 2)—Preliminary
Device
Performance
Unit
C6 C7 C8 C8L (1) C9L (1) I7 I8L (1) A7
Table 1–25. PLL Specifications for Cyclone IV Devices (1), (2) (Part 1 of 2)—Preliminary
Symbol Parameter Min Typ Max Unit
fIN (3)
Input clock frequency (–6, –7, –8 speed grades) 5 — 472.5 MHz
Input clock frequency (–8L speed grade) 5 — 362 MHz
Input clock frequency (–9L speed grade) 5 — 265 MHz
fINPFD PFD input frequency 5 — 325 MHz
fVCO (4) PLL internal VCO operating range 600 — 1300 MHz
fINDUTY Input clock duty cycle 40 — 60 %
tINJITTER_CCJ (5)
Input clock cycle-to-cycle jitter
FREF 100 MHz — — 0.15 UI
FREF < 100 MHz — — ±750 ps
fOUT_EXT (external clock
output) (3) PLL output frequency — — 472.5 MHz
fOUT (to global clock)
PLL output frequency (–6 speed grade) — — 472.5 MHz
PLL output frequency (–7 speed grade) — — 450 MHz
PLL output frequency (–8 speed grade) — — 402.5 MHz
PLL output frequency (–8L speed grade) — — 362 MHz
PLL output frequency (–9L speed grade) — — 265 MHz
tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 %
tLOCK Time required to lock from end of device configuration — — 1 ms
Chapter 1: Cyclone IV Device Datasheet 1–25
Switching Characteristics
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
tDLOCK
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset
is deasserted)
—— 1 ms
tOUTJITTER_PERIOD_DEDCLK (6)
Dedicated clock output period jitter
FOUT 100 MHz — — 300 ps
FOUT < 100 MHz — — 30 mUI
tOUTJITTER_CCJ_DEDCLK (6)
Dedicated clock output cycle-to-cycle jitter
FOUT 100 MHz — — 300 ps
FOUT < 100 MHz — — 30 mUI
tOUTJITTER_PERIOD_IO (6)
Regular I/O period jitter
FOUT 100 MHz — — 650 ps
FOUT < 100 MHz — — 75 mUI
tOUTJITTER_CCJ_IO (6)
Regular I/O cycle-to-cycle jitter
FOUT 100 MHz — — 650 ps
FOUT < 100 MHz — — 75 mUI
tPLL_PSERR Accuracy of PLL phase shift — — ±50 ps
tARESET Minimum pulse width on
areset
signal. 10 — — ns
tCONFIGPLL Time required to reconfigure scan chains for PLLs — 3.5 (7) —
SCANCLK
cycles
fSCANCLK
scanclk
frequency — — 100 MHz
tCASC_OUTJITTER_PERIOD_DEDCLK
(8),(9)
Period jitter for dedicated clock output in cascaded
PLLs (FOUT 100 MHz) — — 425 ps
Period jitter for dedicated clock output in cascaded
PLLs (FOUT 100 MHz) — — 42.5 mUI
Notes to Table 1–25:
(1) This table is applicable for general purpose PLLs and multipurpose PLLs.
(2) You must connect VCCD_PLL to VCCINT through the decoupling capacitor and ferrite bead.
(3) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(4) The VCO frequency reported by the Quartus II software in the PLL Summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 200 ps.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL when an input jitter of 30 ps is applied.
(7) With 100-MHz
scanclk
frequency.
(8) The cascaded PLLs specification is applicable only with the following conditions:
■Upstream PLL—0.59 MHz Upstream PLL bandwidth < 1 MHz
■Downstream PLL—Downstream PLL bandwidth > 2 MHz
(9) PLL cascading is not supported for transceiver applications.
Table 1–25. PLL Specifications for Cyclone IV Devices (1), (2) (Part 2 of 2)—Preliminary
Symbol Parameter Min Typ Max Unit
1–26 Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
Embedded Multiplier Specifications
Table 1–26 lists the embedded multiplier specifications for Cyclone IV devices.
Memory Block Specifications
Table 1–27 lists the M9K memory block specifications for Cyclone IV devices.
Configuration and JTAG Specifications
Table 1–28 lists the configuration mode specifications for Cyclone IV devices.
Table 1–26. Embedded Multiplier Specifications for Cyclone IV Devices —Preliminary
Mode
Resources Used Performance
Unit
Number of Multipliers C6 C7, I7, A7 C8 C8L, I8L C9L
9 × 9-bit multiplier 1 340 300 260 240 175 MHz
18 × 18-bit multiplier 1 287 250 200 185 135 MHz
Table 1–27. Memory Block Performance Specifications for Cyclone IV Devices —Preliminary
Memory Mode
Resources Used Performance
Unit
LEs M9K
Memory C6 C7, I7, A7 C8 C8L, I8L C9L
M9K Block
FIFO 256 × 36 47 1 315 274 238 200 157 MHz
Single-port 256 × 36 0 1 315 274 238 200 157 MHz
Simple dual-port 256 × 36 CLK 0 1 315 274 238 200 157 MHz
True dual port 512 × 18 single CLK 0 1 315 274 238 200 157 MHz
Table 1–28. Passive Configuration Mode Specifications for Cyclone IV Devices (1)
Programming Mode VCCINT Voltage Level (V) DCLK fMAX Unit
Passive Serial (PS) 1.0 (3) 66 MHz
1.2 133 MHz
Fast Passive Parallel (FPP) (2) 1.0 (3) 66 MHz
1.2 (4) 100 MHz
Notes to Table 1–28:
(1) For more information about PS and FPP configuration timing parameters, refer to the Configuration and Remote
System Upgrades in Cyclone IV Devices chapter.
(2) FPP configuration mode supports all Cyclone IV E devices (except for E144 package devices) and EP4CGX50,
EP4CGX75, EP4CGX110, and EP4CGX150 only.
(3) VCCINT = 1.0 V is only supported for Cyclone IV E 1.0 V core voltage devices.
(4) Cyclone IV E devices support 1.2 V VCCINT. Cyclone IV E 1.2 V core voltage devices support 133 MHz
DCLK
fMAX for
EP4CE6, EP4CE10, EP4CE15, EP4CE22, EP4CE30, and EP4CE40 only.
Chapter 1: Cyclone IV Device Datasheet 1–27
Switching Characteristics
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
Table 1–29 lists the active configuration mode specifications for Cyclone IV devices.
Table 1–30 lists the JTAG timing parameters and values for Cyclone IV devices.
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the high-speed I/O
interface, external memory interface, and the PCI/PCI-X bus interface. I/Os using the
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speeds. I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-,
1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency
with a 10 pF load.
Table 1–29. Active Configuration Mode Specifications for Cyclone IV Devices—Preliminary
Programming Mode DCLK Range Unit
Active Parallel (AP) (1) 20 to 40 MHz
Active Serial (AS) 20 to 40 MHz
Note to Table 1–29:
(1) AP configuration mode is only supported for Cyclone IV E devices.
Table 1–30. JTAG Timing Parameters for Cyclone IV Devices (1) —Preliminary
Symbol Parameter Min Max Unit
tJCP TCK clock period 40 — ns
tJCH TCK clock high time 19 — ns
tJCL TCK clock low time 19 — ns
tJPSU_TDI JTAG port setup time for TDI 1 — ns
tJPSU_TMS JTAG port setup time for TMS 3 — ns
tJPH JTAG port hold time 10 — ns
tJPCO JTAG port clock to output (2),(3) —15ns
tJPZX JTAG port high impedance to valid output (2),(3) —15ns
tJPXZ JTAG port valid output to high impedance (2),(3) —15ns
tJSSU Capture register setup time 5 — ns
tJSH Capture register hold time 10 — ns
tJSCO Update register clock to output — 25 ns
tJSZX Update register high impedance to valid output — 25 ns
tJSXZ Update register valid output to high impedance — 25 ns
Notes to Table 1–30:
(1) For more information about JTAG waveforms, refer to “JTAG Waveform” in “Glossary” on page 1–38.
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V
LVTTL/LVCMOS and 1.5-V LVCMOS, the output time specification is 16 ns.
(3) For EP4CGX22, EP4CGX30 (F324 and smaller package), EP4CGX110, and EP4CGX150 devices, the output time
specification for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins is 16 ns. For 1.8-V LVTTL/LVCMOS
and 1.5-V LVCMOS, the output time specification is 18 ns.
1–28 Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
fFor more information about the supported maximum clock rate, device and pin
planning, IP implementation, and device termination, refer to Section III: System
Performance Specifications of the External Memory Interfaces Handbook.
1Actual achievable frequency depends on design- and system-specific factors. Perform
HSPICE/IBIS simulations based on your specific design and system setup to
determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Table 1–31 through Table 1–36 list the high-speed I/O timing for Cyclone IV devices.
For definitions of high-speed timing specifications, refer to “Glossary” on page 1–38.
Table 1–31. RSDS Transmitter Timing Specifications for Cyclone IV Devices (1), (2), (4) (Part 1 of 2)—Preliminary
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
fHSCLK
(input clock
frequency)
×10 10 — 180 10 — 155.5 10 — 155.5 10 — 155.5 10 — 132.5 MHz
×8 10 — 180 10 — 155.5 10 — 155.5 10 — 155.5 10 — 132.5 MHz
×7 10 — 180 10 — 155.5 10 — 155.5 10 — 155.5 10 — 132.5 MHz
×4 10 — 180 10 — 155.5 10 — 155.5 10 — 155.5 10 — 132.5 MHz
×2 10 — 180 10 — 155.5 10 — 155.5 10 — 155.5 10 — 132.5 MHz
×1 10 — 360 10 — 311 10 — 311 10 — 311 10 — 265 MHz
Device
operation in
Mbps
×10 100 — 360 100 — 311 100 — 311 100 — 311 100 — 265 Mbps
×8 80 — 360 80 — 311 80 — 311 80 — 311 80 — 265 Mbps
×7 70 — 360 70 — 311 70 — 311 70 — 311 70 — 265 Mbps
×4 40 — 360 40 — 311 40 — 311 40 — 311 40 — 265 Mbps
×2 20 — 360 20 — 311 20 — 311 20 — 311 20 — 265 Mbps
×1 10 — 360 10 — 311 10 — 311 10 — 311 10 — 265 Mbps
tDUTY — 45 — 55 45 — 55 45 — 55 45 — 55 45 — 55 %
Transmitter
channel-to-
channel skew
(TCCS)
— — — 200 — — 200 — — 200 — — 200 — — 200 ps
Output jitter
(peak to peak) — — — 500 — — 500 — — 550 — — 600 — — 700 ps
tRISE
20 – 80%,
CLOAD =
5pF
— 500 — — 500 — — 500 — — 500 — — 500 — ps
tFALL
20 – 80%,
CLOAD =
5pF
— 500 — — 500 — — 500 — — 500 — — 500 — ps
Chapter 1: Cyclone IV Device Datasheet 1–29
Switching Characteristics
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
tLOCK (3) — ——1——1—— 1——1——1ms
Notes to Table 1–31:
(1) Applicable for true RSDS and emulated RSDS_E_3R transmitter.
(2) Cyclone IV E devices—true RSDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated RSDS transmitter is supported at the
output pin of all I/O Banks.
Cyclone IV GX devices—true RSDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated RSDS transmitter is supported at the output
pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(3) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7
speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–31. RSDS Transmitter Timing Specifications for Cyclone IV Devices (1), (2), (4) (Part 2 of 2)—Preliminary
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Table 1–32. Emulated RSDS_E_1R Transmitter Timing Specifications for Cyclone IV Devices (1), (3) (Part 1 of 2)
—Preliminary
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
fHSCLK (input
clock
frequency)
×10 10 — 85 10 — 85 10 — 85 10 — 85 10 — 72.5 MHz
×8 10 — 85 10 — 85 10 — 85 10 — 85 10 — 72.5 MHz
×7 10 — 85 10 — 85 10 — 85 10 — 85 10 — 72.5 MHz
×4 10 — 85 10 — 85 10 — 85 10 — 85 10 — 72.5 MHz
×2 10 — 85 10 — 85 10 — 85 10 — 85 10 — 72.5 MHz
×1 10 — 170 10 — 170 10 — 170 10 — 170 10 — 145 MHz
Device
operation in
Mbps
×10 100 — 170 100 — 170 100 — 170 100 — 170 100 — 145 Mbps
×8 80 — 170 80 — 170 80 — 170 80 — 170 80 — 145 Mbps
×7 70 — 170 70 — 170 70 — 170 70 — 170 70 — 145 Mbps
×4 40 — 170 40 — 170 40 — 170 40 — 170 40 — 145 Mbps
×2 20 — 170 20 — 170 20 — 170 20 — 170 20 — 145 Mbps
×1 10 — 170 10 — 170 10 — 170 10 — 170 10 — 145 Mbps
tDUTY — 45 — 55 45 — 55 45 — 55 45 — 55 45 — 55 %
TCCS — — — 200 — — 200 — — 200 — — 200 — — 200 ps
Output jitter
(peak to peak) — — — 500 — — 500 — — 550 — — 600 — — 700 ps
tRISE
20 – 80%,
CLOAD =
5pF
— 500 — — 500 — — 500 — — 500 — — 500 — ps
tFALL
20 – 80%,
CLOAD =
5pF
— 500 — — 500 — — 500 — — 500 — — 500 — ps
1–30 Chapter 1: Cyclone IV Device Datasheet
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Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
tLOCK (2) — ——1——1——1——1—— 1 ms
Notes to Table 1–32:
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O Banks of Cyclone IV E devices and I/O Banks 3, 4, 5, 6, 7, 8, and 9 of Cyclone IV GX
devices.
(2) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and
A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–32. Emulated RSDS_E_1R Transmitter Timing Specifications for Cyclone IV Devices (1), (3) (Part 2 of 2)
—Preliminary
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Table 1–33. Mini-LVDS Transmitter Timing Specifications for Cyclone IV Devices (1), (2), (4) (Part 1 of 2)—Preliminary
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
fHSCLK (input
clock
frequency)
×10 10 — 200 10 — 155.5 10 — 155.5 10 — 155.5 10 — 132.5 MHz
×8 10 — 200 10 — 155.5 10 — 155.5 10 — 155.5 10 — 132.5 MHz
×7 10 — 200 10 — 155.5 10 — 155.5 10 — 155.5 10 — 132.5 MHz
×4 10 — 200 10 — 155.5 10 — 155.5 10 — 155.5 10 — 132.5 MHz
×2 10 — 200 10 — 155.5 10 — 155.5 10 — 155.5 10 — 132.5 MHz
×1 10 — 400 10 — 311 10 — 311 10 — 311 10 — 265 MHz
Device
operation in
Mbps
×10 100 — 400 100 — 311 100 — 311 100 — 311 100 — 265 Mbps
×8 80 — 400 80 — 311 80 — 311 80 — 311 80 — 265 Mbps
×7 70 — 400 70 — 311 70 — 311 70 — 311 70 — 265 Mbps
×4 40 — 400 40 — 311 40 — 311 40 — 311 40 — 265 Mbps
×2 20 — 400 20 — 311 20 — 311 20 — 311 20 — 265 Mbps
×1 10 — 400 10 — 311 10 — 311 10 — 311 10 — 265 Mbps
tDUTY — 45 — 55 45 — 55 45 — 55 45 — 55 45 — 55 %
TCCS — — — 200 — — 200 — — 200 — — 200 — — 200 ps
Output jitter
(peak to peak) — — — 500 — — 500 — — 550 — — 600 — — 700 ps
tRISE
20 – 80%,
CLOAD =
5pF
— 500 — — 500 — — 500 — — 500 — — 500 — ps
tFALL
20 – 80%,
CLOAD =
5pF
— 500 — — 500 — — 500 — — 500 — — 500 — ps
Chapter 1: Cyclone IV Device Datasheet 1–31
Switching Characteristics
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
tLOCK (3) — ——1—— 1 —— 1 —— 1 —— 1 ms
Notes to Table 1–33:
(1) Applicable for true and emulated mini-LVDS transmitter.
(2) Cyclone IV E—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated mini-LVDS transmitter is supported at
the output pin of all I/O banks.
Cyclone IV GX—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated mini-LVDS transmitter is supported at the
output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(3) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and
A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–33. Mini-LVDS Transmitter Timing Specifications for Cyclone IV Devices (1), (2), (4) (Part 2 of 2)—Preliminary
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Table 1–34. True LVDS Transmitter Timing Specifications for Cyclone IV Devices (1), (3) —Preliminary
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Max Min Max Min Max Min Max Min Max
fHSCLK (input
clock
frequency)
×10 10 420 10 370 10 320 10 320 10 250 MHz
×8 10 420 10 370 10 320 10 320 10 250 MHz
×7 10 420 10 370 10 320 10 320 10 250 MHz
×4 10 420 10 370 10 320 10 320 10 250 MHz
×2 10 420 10 370 10 320 10 320 10 250 MHz
×1 10 420 10 402.5 10 402.5 10 362 10 265 MHz
HSIODR
×10 100 840 100 740 100 640 100 640 100 500 Mbps
×8 80 840 80 740 80 640 80 640 80 500 Mbps
×7 70 840 70 740 70 640 70 640 70 500 Mbps
×4 40 840 40 740 40 640 40 640 40 500 Mbps
×2 20 840 20 740 20 640 20 640 20 500 Mbps
×1 10 420 10 402.5 10 402.5 10 362 10 265 Mbps
tDUTY —45554555455545554555%
TCCS — — 200 — 200 — 200 — 200 — 200 ps
Output jitter
(peak to peak) — — 500 — 500 — 550 — 600 — 700 ps
tLOCK (2) ——1—1—1—1—1ms
Notes to Table 1–34:
(1) Cyclone IV E—true LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6.
Cyclone IV GX—true LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6.
(2) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
1–32 Chapter 1: Cyclone IV Device Datasheet
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Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
Table 1–35. Emulated LVDS Transmitter Timing Specifications for Cyclone IV Devices (1), (3) —Preliminary
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Max Min Max Min Max Min Max Min Max
fHSCLK (input
clock
frequency)
×10 10 320 10 320 10 275 10 275 10 250 MHz
×8 10 320 10 320 10 275 10 275 10 250 MHz
×7 10 320 10 320 10 275 10 275 10 250 MHz
×4 10 320 10 320 10 275 10 275 10 250 MHz
×2 10 320 10 320 10 275 10 275 10 250 MHz
×1 10 402.5 10 402.5 10 402.5 10 362 10 265 MHz
HSIODR
×10 100 640 100 640 100 550 100 550 100 500 Mbps
×8 80 640 80 640 80 550 80 550 80 500 Mbps
×7 70 640 70 640 70 550 70 550 70 500 Mbps
×4 40 640 40 640 40 550 40 550 40 500 Mbps
×2 20 640 20 640 20 550 20 550 20 500 Mbps
×1 10 402.5 10 402.5 10 402.5 10 362 10 265 Mbps
tDUTY — 455545554555455545 55%
TCCS — — 200 — 200 — 200 — 200 — 200 ps
Output jitter
(peak to peak) — — 500 — 500 — 550 — 600 — 700 ps
tLOCK (2) ——1—1—1—1— 1ms
Notes to Table 1–35:
(1) Cyclone IV E—emulated LVDS transmitter is supported at the output pin of all I/O Banks.
Cyclone IV GX—emulated LVDS transmitter is supported at the output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(2) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–36. LVDS Receiver Timing Specifications for Cyclone IV Devices (1), (3) (Part 1 of 2)—Preliminary
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Max Min Max Min Max Min Max Min Max
fHSCLK (input
clock
frequency)
×10 10 437.5 10 370 10 320 10 320 10 250 MHz
×8 10 437.5 10 370 10 320 10 320 10 250 MHz
×7 10 437.5 10 370 10 320 10 320 10 250 MHz
×4 10 437.5 10 370 10 320 10 320 10 250 MHz
×2 10 437.5 10 370 10 320 10 320 10 250 MHz
×1 10 437.5 10 402.5 10 402.5 10 362 10 265 MHz
HSIODR
×10 100 875 100 740 100 640 100 640 100 500 Mbps
×8 80 875 80 740 80 640 80 640 80 500 Mbps
×7 70 875 70 740 70 640 70 640 70 500 Mbps
×4 40 875 40 740 40 640 40 640 40 500 Mbps
×2 20 875 20 740 20 640 20 640 20 500 Mbps
×1 10 437.5 10 402.5 10 402.5 10 362 10 265 Mbps
Chapter 1: Cyclone IV Device Datasheet 1–33
Switching Characteristics
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
External Memory Interface Specifications
The external memory interfaces for Cyclone IV devices are auto-calibrating and easy
to implement.
fFor more information about the supported maximum clock rate, device and pin
planning, IP implementation, and device termination, refer to Section III: System
Performance Specifications of the External Memory Interface Handbook.
Table 1–37 lists the memory output clock jitter specifications for Cyclone IV devices.
SW — — 400 — 400 — 400 — 550 — 640 ps
Input jitter
tolerance — — 500 — 500 — 550 — 600 — 700 ps
tLOCK (2) ——1—1—1—1—1ms
Notes to Table 1–36:
(1) Cyclone IV E—LVDS receiver is supported at all I/O Banks.
Cyclone IV GX—LVDS receiver is supported at I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(2) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–36. LVDS Receiver Timing Specifications for Cyclone IV Devices (1), (3) (Part 2 of 2)—Preliminary
Symbol Modes
C6 C7, I7 C8, A7 C8L, I8L C9L
Unit
Min Max Min Max Min Max Min Max Min Max
Table 1–37. Memory Output Clock Jitter Specifications for Cyclone IV Devices (1),(2) —
Preliminary
Parameter Symbol Min Max Unit
Clock period jitter tJIT(per) –125 125 ps
Cycle-to-cycle period jitter tJIT(cc) –200 200 ps
Duty cycle jitter tJIT(duty) –150 150 ps
Notes to Table 1–37:
(1) Memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2
standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL
output routed on a global clock (GCLK) network.
1–34 Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
Duty Cycle Distortion Specifications
Table 1–38 lists the worst case duty cycle distortion for Cyclone IV devices.
OCT Calibration Timing Specification
Table 1–39 lists the duration of calibration for series OCT with calibration at device
power-up for Cyclone IV devices.
IOE Programmable Delay
Table 1–40 and Table 1–41 list the IOE programmable delay for Cyclone IV E 1.0 V
core voltage devices.
Table 1–38. Duty Cycle Distortion on Cyclone IV Devices I/O Pins (1), (2), (3)—Preliminary
Symbol
C6 C7, I7 C8, I8L, A7 C9L
Unit
Min Max Min Max Min Max Min Max
Output Duty Cycle 4555455545554555 %
Notes to Table 1–38:
(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and IOE driving the dedicated and general
purpose I/O pins.
(2) Cyclone IV devices meet the specified duty cycle distortion at the maximum output toggle rate for each combination of I/O standard and current
strength.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–39. Timing Specification for Series OCT with Calibration at Device Power-Up for
Cyclone IV Devices (1)—Preliminary
Symbol Description Maximum Units
tOCTCAL
Duration of series OCT with
calibration at device power-up 20 µs
Note to Table 1–39:
(1) OCT calibration takes place after device configuration and before entering user mode.
Table 1–40. IOE Programmable Delay on Column Pins for Cyclone IV E 1.0 V Core Voltage Devices (1), (2)
(Part 1 of 2)—Preliminary
Parameter Paths Affected
Number
of
Setting
Min
Offset
Max Offset
UnitFast Corner Slow Corner
C8L I8L C8L C9L I8L
Input delay from pin to
internal cells
Pad to I/O
dataout to core 7 0 2.054 1.924 3.387 4.017 3.411 ns
Input delay from pin to
input register
Pad to I/O input
register 8 0 2.010 1.875 3.341 4.252 3.367 ns
Delay from output register
to output pin
I/O output
register to pad 2 0 0.641 0.631 1.111 1.377 1.124 ns
Chapter 1: Cyclone IV Device Datasheet 1–35
Switching Characteristics
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
Table 1–42 and Table 1–43 list the IOE programmable delay for Cyclone IV E 1.2 V
core voltage devices.
Input delay from
dual-purpose clock pin to
fan-out destinations
Pad to global
clock network 12 0 0.971 0.931 1.684 2.298 1.684 ns
Notes to Table 1–40:
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Table 1–40. IOE Programmable Delay on Column Pins for Cyclone IV E 1.0 V Core Voltage Devices (1), (2)
(Part 2 of 2)—Preliminary
Parameter Paths Affected
Number
of
Setting
Min
Offset
Max Offset
UnitFast Corner Slow Corner
C8L I8L C8L C9L I8L
Table 1–41. IOE Programmable Delay on Row Pins for Cyclone IV E 1.0 V Core Voltage Devices (1), (2)—Preliminary
Parameter Paths Affected
Number
of
Setting
Min
Offset
Max Offset
UnitFast Corner Slow Corner
C8L I8L C8L C9L I8L
Input delay from pin to
internal cells
Pad to I/O
dataout to core 7 0 2.057 1.921 3.389 4.146 3.412 ns
Input delay from pin to
input register
Pad to I/O input
register 8 0 2.059 1.919 3.420 4.374 3.441 ns
Delay from output register
to output pin
I/O output
register to pad 2 0 0.670 0.623 1.160 1.420 1.168 ns
Input delay from
dual-purpose clock pin to
fan-out destinations
Pad to global
clock network 12 0 0.960 0.919 1.656 2.258 1.656 ns
Notes to Table 1–41:
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Table 1–42. IOE Programmable Delay on Column Pins for Cyclone IV E 1.2 V Core Voltage Devices (1),(2) (Part 1 of 2)—
Preliminary
Parameter Paths
Affected
Number
of
Setting
Min
Offset
Max Offset
UnitFast Corner Slow Corner
C6 I7 A7 C6 C7 C8 I7 A7
Input delay from pin to
internal cells
Pad to I/O
dataout to
core
7 0 1.314 1.211 1.211 2.177 2.340 2.433 2.388 2.508 ns
Input delay from pin to
input register
Pad to I/O
input register 8 0 1.307 1.203 1.203 2.19 2.387 2.540 2.430 2.545 ns
Delay from output
register to output pin
I/O output
register to
pad
2 0 0.437 0.402 0.402 0.747 0.820 0.880 0.834 0.873 ns
1–36 Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
Table 1–44 and Table 1–45 list the IOE programmable delay for Cyclone IV GX
devices.
Input delay from
dual-purpose clock pin
to fan-out destinations
Pad to global
clock
network
12 0 0.693 0.665 0.665 1.200 1.379 1.532 1.393 1.441 ns
Notes to Table 1–42:
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Table 1–42. IOE Programmable Delay on Column Pins for Cyclone IV E 1.2 V Core Voltage Devices (1),(2) (Part 2 of 2)—
Preliminary
Parameter Paths
Affected
Number
of
Setting
Min
Offset
Max Offset
UnitFast Corner Slow Corner
C6 I7 A7 C6 C7 C8 I7 A7
Table 1–43. IOE Programmable Delay on Row Pins for Cyclone IV E 1.2 V Core Voltage Devices (1),(2)—Preliminary
Parameter Paths
Affected
Number
of
Setting
Min
Offset
Max Offset
UnitFast Corner Slow Corner
C6 I7 A7 C6 C7 C8 I7 A7
Input delay from pin to
internal cells
Pad to I/O
dataout to
core
7 0 1.314 1.209 1.209 2.201 2.386 2.510 2.429 2.548 ns
Input delay from pin to
input register
Pad to I/O
input register 8 0 1.312 1.207 1.207 2.202 2.402 2.558 2.447 2.557 ns
Delay from output
register to output pin
I/O output
register to
pad
2 0 0.458 0.419 0.419 0.783 0.861 0.924 0.875 0.915 ns
Input delay from
dual-purpose clock pin
to fan-out destinations
Pad to global
clock
network
12 0 0.686 0.657 0.657 1.185 1.360 1.506 1.376 1.422 ns
Notes to Table 1–43:
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Table 1–44. IOE Programmable Delay on Column Pins for Cyclone IV GX Devices (1), (2) (Part 1 of 2)—Preliminary
Parameter Paths
Affected
Number
of
Settings
Min
Offset
Max Offset
UnitFast Corner Slow Corner
C6 I7 C6 C7 C8 I7
Input delay from pin to
internal cells
Pad to I/O
dataout to
core
7 0 1.313 1.209 2.184 2.336 2.451 2.387 ns
Input delay from pin to
input register
Pad to I/O
input register 8 0 1.312 1.208 2.200 2.399 2.554 2.446 ns
Chapter 1: Cyclone IV Device Datasheet 1–37
Switching Characteristics
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
Delay from output
register to output pin
I/O output
register to
pad
2 0 0.438 0.404 0.751 0.825 0.886 0.839 ns
Input delay from
dual-purpose clock pin
to fan-out destinations
Pad to global
clock
network
12 0 0.713 0.682 1.228 1.41 1.566 1.424 ns
Notes to Table 1–44:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Table 1–44. IOE Programmable Delay on Column Pins for Cyclone IV GX Devices (1), (2) (Part 2 of 2)—Preliminary
Parameter Paths
Affected
Number
of
Settings
Min
Offset
Max Offset
UnitFast Corner Slow Corner
C6 I7 C6 C7 C8 I7
Table 1–45. IOE Programmable Delay on Row Pins for Cyclone IV GX Devices (1), (2) —Preliminary
Parameter Paths
Affected
Number
of
Settings
Min
Offset
Max Offset
UnitFast Corner Slow Corner
C6 I7 C6 C7 C8 I7
Input delay from pin to
internal cells
Pad to I/O
dataout to
core
7 0 1.314 1.210 2.209 2.398 2.526 2.443 ns
Input delay from pin to
input register
Pad to I/O
input register 8 0 1.313 1.208 2.205 2.406 2.563 2.450 ns
Delay from output
register to output pin
I/O output
register to
pad
2 0 0.461 0.421 0.789 0.869 0.933 0.884 ns
Input delay from
dual-purpose clock pin
to fan-out destinations
Pad to global
clock network 12 0 0.712 0.682 1.225 1.407 1.562 1.421 ns
Notes to Table 1–45:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software
1–38 Chapter 1: Cyclone IV Device Datasheet
I/O Timing
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
I/O Timing
Use the following methods to determine I/O timing:
■the Excel-based I/O Timing
■the Quartus II timing analyzer
The Excel-based I/O timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
fThe Excel-based I/O Timing spreadsheet is downloadable from Cyclone IV Devices
Literature website.
Glossary
Table 1–46 lists the glossary for this chapter.
Table 1–46. Glossary (Part 1 of 5)
Letter Term Definitions
A——
B——
C——
D——
E——
FfHSCLK High-speed I/O block: High-speed receiver/transmitter input and output clock frequency.
GGCLK Input pin directly to Global Clock network.
GCLK PLL Input pin to Global Clock network through the PLL.
HHSIODR High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
I
Input Waveforms
for the SSTL
Differential I/O
Standard
VIL
VREF
VIH
VSWING
Chapter 1: Cyclone IV Device Datasheet 1–39
Glossary
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
JJTAG Waveform
K——
L——
M——
N——
O——
PPLL Block
The following highlights the PLL specification parameters:
Q——
Table 1–46. Glossary (Part 2 of 5)
Letter Term Definitions
TDO
TCK
tJPZX tJPCO
tJSCO tJSXZ
tJPH
tJSH
tJPXZ
tJCP
tJPSU_TMS
t JCL
tJCH
TDI
TMS
Signal
to be
Captured
Signal
to be
Driven
tJPSU_TDI
tJSZX
tJSSU
Core Clock
Phase tap
Reconfigurable in User Mode
Key
CLK
N
M
PFD VCOCP LF
CLKOUT Pins
GCLK
fINPFD
fIN
fVCO fOUT
fOUT _EXT
Switchover
Counters
C0..C4
1–40 Chapter 1: Cyclone IV Device Datasheet
Glossary
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
R
RLReceiver differential input discrete resistor (external to Cyclone IV devices).
Receiver Input
Waveform
Receiver input waveform for LVDS and LVPECL differential standards:
Receiver input
skew margin
(RSKM)
High-speed I/O block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
S
Single-ended
voltage-
referenced I/O
Standard
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
SW (Sampling
Window)
High-speed I/O block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
Table 1–46. Glossary (Part 3 of 5)
Letter Term Definitions
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = VIH
Negative Channel (n) = VIL
Ground
VID
VID
0 V
VCM
p - n
VID
V
IH(AC)
V
IH(DC)
V
REF
V
IL(DC)
V
IL(AC)
V
OH
V
OL
V
CCIO
V
SS
Chapter 1: Cyclone IV Device Datasheet 1–41
Glossary
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
T
tCHigh-speed receiver and transmitter input and output clock period.
Channel-to-
channel-skew
(TCCS)
High-speed I/O block: The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the TCCS measurement.
tcin Delay from the clock pad to the I/O input register.
tCO Delay from the clock pad to the I/O output.
tcout Delay from the clock pad to the I/O output register.
tDUTY High-speed I/O block: Duty cycle on high-speed transmitter output clock.
tFALL Signal high-to-low transition time (80–20%).
tHInput register hold time.
Timing Unit
Interval (TUI)
High-speed I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
tINJITTER Period jitter on the PLL clock input.
tOUTJITTER_DEDCLK Period jitter on the dedicated clock output driven by a PLL.
tOUTJITTER_IO Period jitter on the general purpose I/O driven by a PLL.
tpllcin Delay from the PLL inclk pad to the I/O input register.
tpllcout Delay from the PLL inclk pad to the I/O output register.
Transmitter
Output
Waveform
Transmitter output waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O
Standards:
tRISE Signal low-to-high transition time (20–80%).
tSU Input register setup time.
U——
Table 1–46. Glossary (Part 4 of 5)
Letter Term Definitions
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = VOH
Negative Channel (n) = VOL
Ground
VOD
VOD
VOD
0 V
Vos
p - n
1–42 Chapter 1: Cyclone IV Device Datasheet
Glossary
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
V
VCM(DC) DC common mode input voltage.
VDIF(AC) AC differential input voltage: The minimum AC input differential voltage required for switching.
VDIF(DC) DC differential input voltage: The minimum DC input differential voltage required for switching.
VICM Input common mode voltage: The common mode of the differential signal at the receiver.
VID
Input differential voltage swing: The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VIH
Voltage input high: The minimum positive voltage applied to the input that is accepted by the
device as a logic high.
VIH(AC) High-level AC input voltage.
VIH(DC) High-level DC input voltage.
VIL
Voltage input low: The maximum positive voltage applied to the input that is accepted by the
device as a logic low.
VIL (AC) Low-level AC input voltage.
VIL (DC) Low-level DC input voltage.
VIN DC input voltage.
VOCM Output common mode voltage: The common mode of the differential signal at the transmitter.
VOD
Output differential voltage swing: The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter. VOD = VOH – VOL.
VOH
Voltage output high: The maximum positive voltage from an output that the device considers is
accepted as the minimum positive high level.
VOL
Voltage output low: The maximum positive voltage from an output that the device considers is
accepted as the maximum positive low level.
VOS Output offset voltage: VOS = (VOH + VOL) / 2.
VOX (AC)
AC differential output cross point voltage: the voltage at which the differential output signals
must cross.
VREF Reference voltage for the SSTL and HSTL I/O standards.
VREF (AC)
AC input reference voltage for the SSTL and HSTL I/O standards. VREF(AC) = VREF(DC) + noise. The
peak-to-peak AC noise on VREF must not exceed 2% of VREF(DC).
VREF (DC) DC input reference voltage for the SSTL and HSTL I/O standards.
VSWING (AC)
AC differential input voltage: AC input differential voltage required for switching. For the SSTL
differential I/O standard, refer to Input Waveforms.
VSWING (DC)
DC differential input voltage: DC input differential voltage required for switching. For the SSTL
differential I/O standard, refer to Input Waveforms.
VTT Termination voltage for the SSTL and HSTL I/O standards.
VX (AC)
AC differential input cross point voltage: The voltage at which the differential input signals must
cross.
W——
X——
Y——
Z——
Table 1–46. Glossary (Part 5 of 5)
Letter Term Definitions
Chapter 1: Cyclone IV Device Datasheet 1–43
Document Revision History
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 3
Document Revision History
Table 1–47 lists the revision history for this chapter.
Table 1–47. Document Revision History
Date Version Changes
November 2011 1.5
■Updated “Maximum Allowed Overshoot or Undershoot Voltage”, “Operating
Conditions”, and “PLL Specifications” sections.
■Updated Table 1–2, Table 1–3, Table 1–4, Table 1–5, Table 1–8, Table 1–9,
Table 1–15, Table 1–18, Table 1–19, and Table 1–21.
■Updated Figure 1–1.
December 2010 1.4
■Updated for the Quartus II software version 10.1 release.
■Updated Table 1–21 and Table 1–25.
■Minor text edits.
July 2010 1.3
Updated for the Quartus II software version 10.0 release:
■Updated Table 1–3, Table 1–4, Table 1–21, Table 1–25, Table 1–28, Table 1–30,
Table 1–40, Table 1–41, Table 1–42, Table 1–43, Table 1–44, and Table 1–45.
■Updated Figure 1–2 and Figure 1–3.
■Removed SW Requirement and TCCS for Cyclone IV Devices tables.
■Minor text edits.
March 2010 1.2
Updated to include automotive devices:
■Updated the “Operating Conditions” and “PLL Specifications” sections.
■Updated Table 1–1, Table 1–8, Table 1–9, Table 1–21, Table 1–26, Table 1–27,
Table 1–31, Table 1–32, Table 1–33, Table 1–34, Table 1–35, Table 1–36,
Table 1–37, Table 1–38, Table 1–40, Table 1–42, and Table 1–43.
■Added Table 1–5 to include ESD for Cyclone IV devices GPIOs and HSSI I/Os.
■Added Table 1–44 and Table 1–45 to include IOE programmable delay for
Cyclone IV E 1.2 V core voltage devices.
■Minor text edits.
February 2010 1.1
■Updated Table 1–3 through Table 1–44 to include information for Cyclone IV E
devices and Cyclone IV GX devices for Quartus II software version 9.1 SP1 release.
■Minor text edits.
November 2009 1.0 Initial release.
1–44 Chapter 1: Cyclone IV Device Datasheet
Document Revision History
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 3
