Features
•
Four Short-circuit-protected High-side Drivers with a Maximum Current Capability of
50 mA Each
•
Four Short-circuit-protected Low-side Drivers with a Maximum Current Capability of
50 mA Each
•
ON Resistance High Side Ron < 10Ω Versus Total Temperature Range
•
ON Resistance Low Side Ron < 7Ω Versus Total Temperature Range
•
Short-circuit Detection of Each Driver Stage
•
Disabling of Driver Stages in the Case of Short-circuit and
Overtemperature Detection
•
Independent Control of Each Driver Stage via an 8-bit Shift Register
•
Status Output Reports Short-circuit Condition
•
Status Output Reports when All Loads Are Switched Off
•
Timing of Status Output Reset Signalizes Failure Mode
•
Temperature Protection in Conjunction with Short-circuit Detection
1. Description
The U6820BM is a driver interface in BCDMOS technology with 8 independent driver
stages having a maximum current capability of 50 mA each. Its partitioning into 4
high-side and 4 low-side driver stages allows an easy connection of either 4 half-
bridges or 2 H-bridges on the pc board. The U6820BM communicates with a micro-
controller via an 8-bit serial interface. Integrated protection against short circuit and
overtemperature give added value. EMI protection and 2-kV ESD protection together
with automotive qualification referring to conducted interference (ISO/TR 7637/1)
make this IC ideal for both automotive and industrial applications.
Figure 1-1. Block Diagram
VCC
STATUS
CLK
DI
CS
HS4 HS3 HS2 HS1
Thermal protection
698 1
Control
logic
16
3
Power-on reset
VCC
VCC
2
7
1015
5
VCC
VCC
4
14
11
13
12
LS1LS2LS3LS4
GNDCC
HH
3
SS
4S
2S
1
L
S
3
L
S
4
L
S
2
L
S
1
Input Register
HH
Current
limiter Current
limiter
Current
limiter
Current
limiter
Current
limiter Current
limiter Current
limiter
Current
limiter
GND S
VS
Dual Quad
BCDMOS
Driver IC
U6820BM
Rev. 4527B–BCD–09/05
2
4527B–BCD–09/05
U6820BM
2. Pin Configuration
Figure 2-1. Pinning SO16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VS
GNDCC
GNDS
VCC
LS2
HS2
HS1
LS1
STATUS
DI
CLK
CS
LS3
HS3
HS4
LS4
Table 2-1. Pin Description
Pin Symbol Function
1 HS1 Output high side 1
2LS1Output low side 1
3 VS Supply voltage 6V to 18V
4 GNDCC Digital ground
5 GNDS Power ground
6 VCC Supply voltage 5V (external)
7LS2Output low side 2
8 HS2 Output high side 2
9 HS3 Output high side 3
10 LS3 Output low side 3
11 CS Set supply status (chip select)
12 CLK Clock line for 8-bit control shift register
13 DI Data line for 8-bit control shift register
14 STATUS Status output (H = fault, diagnostic “H” if all driver stages are switched off)
15 LS4 Output low side 4
16 HS4 Output high side 4
3
4527B–BCD–09/05
U6820BM
3. Description of the Control Interface to the Microcontroller
The serial-parallel interface basically includes an 8-bit shift register (SR), an 8-bit command reg-
ister (CR) and a 4-bit counter.
The data input takes place with commands at pins DI (data input), CS (chip select) and CLK
(clock). With a falling edge at CLK, the information at DI is transferred into the SR. The first infor-
mation written into the SR is the least significant bit (LSB). The pin STATUS is used for
diagnostic purposes and reports any fault condition to the microcontroller.
The input CS in accordance with the CR controls the serial interface. A high level at CS disables
the SR. With a falling edge at CS, the SR is enabled. The CR control allows only the first 8 bits to
be transferred into the SR, and further clocks at CLK are ineffective. If a rising edge occurs at
CS after 8 clocks precisely, the information from the SR is transferred into the CR. If the number
of clock cycles during the low phase of CS was less or more than eight transitions, no transfer
will take place. A new command switches the output stages on or off immediately.
Each output stage is controlled by one specific bit of the CR. Low level means “supply off” or
inactive, and high level means “supply on” or active. If all 8 bits are at a low level, the output
stages will be set into standby mode.
If one of the output stages detects a short circuit and additionally overtemperature condition, the
corresponding control bit in the CR is set to low. This reset has priority over an external com-
mand to CR, thus, this does not affect the 1st control bit. The priority protects the IC against
overtemperature by activating the temperature shut down immediately.
4. The STATUS Output
The STATUS output is at low level during normal operation. If one or more output stages detect
short circuit or if overtemperature is indicated, the STATUS output changes to high level
(OR-connection).
For diagnostic purposes (self test of the status output), the status output can also be brought into
high level during standby mode.
4.1 Timing of the Status Output Reset Signalizes the Failure Mode
The use of different reset conditions at the STATUS output simplifies the failure analysis during
normal operation, and is also beneficial during testing.
The storage content can be used for STATUS output. It is indicated and latched immediately
with the rising edge of CS at STATUS output if less than 8 clocks were received during the low
phase of CS. The reset is initiated by the falling edge of the 8th clock (bit 7) of the next data
input.
Also, the appearance of more than 8 clocks is latched and indicated at STATUS by the rising
edge of the 9th clock. The reset is initiated by the falling edge of the 2nd clock (bit 1) of the next
data input.
The detection of overtemperature is latched internally. It is reset by the falling edge of the 4th
clock (bit 3) of a data transfer if overtemperature is no longer present.
4
4527B–BCD–09/05
U6820BM
4.2 Power-on Reset
After switching on the supply voltage, all data latches are reset and the outputs are switched off.
The typical power-on reset threshold is VCC = 3.7V. The outputs are activated after the first data
transfer.
4.3 Short-circuit Protection
The current of the output stages is limited by an active feedback control. Short circuit at one out-
put stage sets the diagnostic pin 14 (STATUS) to high. In case of both conditions, short circuit at
one of the outputs and temperature detection, the affected output is switched off selectively. It
will be activated again after the first new data transfer.
4.4 Inductance Protection
Clamping diodes and FETs are integrated to protect the IC against too high or too low voltages
at the outputs. They prevent the IC from latch up and parasitic currents which may exceed
power dissipation.
4.5 Temperature Protection
The IC is protected by an overtemperature detection. As soon as the junction temperature
Tj = 155°C typically is exceeded, the diagnostic pin 14 (STATUS) is set “high”. General overtem-
perature detection along with short-circuit condition at a specific output result in temperature
shut down at that specific output. After temperature shut down, the data input register has to be
set again with a hysteresis of typically ∆T = 15K (Tj = 140°C).
4.6 ESD Protection
All output stages are protected against electrostatic discharge up to 5 kV (HBM) with external
components (see Figure 8-1), all other pins are protected up to 2 kV (HBM).
Table 4-1. Timing of the STATUS Output
Shift Register Command Register Condition Low-side Switch High-side Switch Status
LS1 LS2 LS3 LS4 HS1 HS2 HS3 HS4 Set Reset
0000000000000000 All out = OK off off off off off off off off H New CS
1111111111111111 All on = OK on on on on on on on on L
0000000100000001 E.g. one on = OK off off off off off off off on L
0111111101111111 Short at LS3 off on on on on on on on H No short
1111111111101111 Temp & short at HS4 on on on off on on on on H New CS4
1100001100000000 V
VCC < 3.7 V = P-ON off off off off off off off off H P-ON, CS
11100011xxxxxxxx CS with less 8 CLK x x x x x x x x H New CS 8
00011100xxxxxxxx CS with more 8 CLK x x x x x x x x H New CS 2
5
4527B–BCD–09/05
U6820BM
Figure 4-1. Data Transfer Timing Diagram
Table 4-2. AC Characteristics for Testing
Specification Conditions Minimum Maximum Unit
tr (rise) 10% to 90% VCC on CLK, DI and CS 10 ns
tf (fall) 10% to 90% VCC on CLK, DI and CS 10 ns
tCLKP 1/2 VCC 250 ns
tCLKH 1/2 VCC 100 ns
tCLKL 1/2 VCC 100 ns
tCLKCS 1/2 VCC 150 ns
tCSCLK 1/2 VCC 100 ns
tDICLK 1/2 VCC 80 ns
tDIH/L 1/2 VCC 100 ns
tCLKCSH 1/2 VCC 100 ns
tCS 1/2 VCC 250 ns
t
CSCLK
t
CLKP
t
CLKH
t
CLKL
t
DICLK
t
DIH/L
t
CLKCS
50%
50%
50%
t
CLKCSH
tCS
CLK
DI
CS
90 %
10%
t
r
90 %
t
f
LSB MSB
6
4527B–BCD–09/05
U6820BM
Figure 4-2. Block Diagram of the Control Interface
CL
DIN
EN
Q7
H4
Q6
H3
Q5
H2
Q4
H1
Q3
L4
Q2
L3
Q1
L2
Q0
L1
Shift register SR
P-ON-Reset
Th-protection
DI
CS
CLK
R
CL NQ
D
DFF
Q
CL
R NQ
D
DFF
Q
LS1_ON
ISC_LS1
ISC_LS2
ISC_LS3
ISC_LS4
ISC_HS1
ISC_HS2
ISC_HS4
LS2_ON
LS3_ON
LS4_ON
HS1_ON
HS2_ON
HS3_ON
HS4_ON
ISC_HS3
STATUS
STD_BY
R
CL NQ
D Q
DFF
Serial-Parallel Interface
CLK
12
13
11
14
R
CL NQ
D
DFF
Q
norm = 0
norm = 0
Load CR
LSB
h if 8
h if 4
h if 2
All norm = 0
CL
R
D Q
DFF
NQ
POR norm=0
8CLK
Q1
2
Q2
4
Q3
8
CL
R
EN
Q0
1
Counter
NR NQ
CL
DIN
NR NQ
DIN
NR NQ
DIN
NR NQ
DIN
NR NQ
DIN
NR NQ
DIN
NR NQ
DIN
NR NQ
DIN
Command register BR
7
4527B–BCD–09/05
U6820BM
5. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters Pin Symbol Minimum Maximum Unit
Supply voltage 3 VVS –0.3 +40 V
Logic supply voltage 6 VVCC –0.3 +7 V
Logic input voltage 11, 12 13 CS, CLK, DI –0.3 VVCC + 0.5 V
Logic output voltage 14 STATUS –0.3 VVCC + 0.3 V
Input current 3I
VS 0.2 mA
6I
VCC 5mA
Output current
(internally limited) 1-2, 8-11, 15-16 I1H-4H and I1L-4L 30 65 mA
Junction temperature range Tj–40 +150 °C
Storage temperature range Tstg –55 +150 °C
6. Thermal Resistance
Parameters Symbol Value Unit
Junction ambient RthJA 110 K/W
Junction case RthJC 26 K/W
7. Operating Range
Parameters Pin Symbol Value Unit
Supply voltage 3 VVS 6 to 18 V
Logic supply voltage 6 VVCC 4.5 to 5.5 V
Logic input voltage low 11, 12, 13 CS, CLK, DI –0.2 to (0.2 × VVCC)V
Logic input voltage high 11, 12, 13 CS, CLK, DI (0.7 × VVCC) to (VVCC + 0.3) V
Logic output voltage (1 mA load) 14 STATUS 0.5 to (VVCC – 1) V
Clock frequency fCLK 5MHz
Junction temperature range Tj–40 to +150 °C
8
4527B–BCD–09/05
U6820BM
8. Electrical Characteristics
7V < VVS < 40V; 4.5V < VVCC > 5.5V; –40°C < Tj < 150°C; unless otherwise specified
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit
Type
*
1 Current Consumption
1.1 Supply current VS No external load 3 IVS 0.2 mA A
1.2 Supply current VCC No external load 6 IVCC 5mAA
1.3 Power-on reset threshold 6 VCC POR 3.43.74.0VA
1.4 Power-on reset delay time After switching on VCC 6T
d POR 60 95 130 µs D
2 Thermal Shutdown
2.1 Thermal shutdown set t j PW set 140 155 165 °C A
2.2 Thermal shutdown reset t j PW reset 130 135 155 °C A
2.3 Thermal hysteresis Dt 20 K A
3 Output Specifications (1L - 4L, 1H - 4H)
3.1 On-resistance low Iout = 26 mA,
Tj = 125°C
2, 7,
10, 15 RDSONLOW 347ΩA
3.2 On-resistance high Iout = 26 mA,
Tj = 125°C
1, 8,
9, 16 RDSONHIGH 46.2510ΩA
3.3 Output leakage current
lowside VLSIDE 1-4 = 17.5V 2, 7,
10, 15 ILOWSIDE 5µAA
3.4 Output leakage current
highside VHSIDE 1-4 = 0.5V 1, 8,
9, 16 IHIGHSIDE –5 µA A
3.5 Output leakage steepness
1-2,
7-10,
15-16
dVOUT/ dt 50 200 400 mV/µs D
3.6 Over current limitation
highside
1, 8,
9, 16 IHIGHSIDE 27 45 95 mA A
3.7 Over current limitation
lowside
2, 7,
10, 15 ILOWSIDE 27 45 80 mA A
4 Serial Interface – Inputs: CS, CLK and DATA
4.1 Input voltage low level
threshold 11-13 VILOW 0.2×
VVCC VA
4.2 Input voltage high level
threshold 11-13 VIHIGH 0.7×
VVCC VA
4.3 Hysteresis of input voltage 11-13 ∆Vi300 mV A
4.4 Pull-down current
(internal pull-up
resistor:
30 kΩ to 140 kΩ)
11-13 Ii300 µA A
5 Serial Interface – Output: STATUS
5.1 Output voltage low level I = 1 mA VOLOW 0.5 V A
5.2 Output voltage high level I = 1 mA VOHIGH VVCC – 1 VVCC VA
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
9
4527B–BCD–09/05
U6820BM
Figure 8-1. Application Circuit
Note: It is strongly recommended to connect the blocking capacitors at VS and VCC as close as possible to the power supply and GND
pins. Recommended value for VS is less than 100 µF electrolytic in parallel with 100 nF ceramic. Value for electrolytic capacitor
depends on external loads, noise and surge immunity efforts. Recommended value for VCC is 33 µF electrolytic in parallel with
100 nF ceramic. The 4-Ω resistors connected to the pins HS1 - HS4 support the protection in case of a short circuit of these pins
to VBatt.
LS2LS3LS4
STATUS
R * R * R *R *
R * = ca. 4 Ohm (I Lim for inv. supply)
µC
4.7nF
Typical application with
4 Hall-ICs for rotational speed detection
27k
27k
27k
4.7nF
4.7nF
4.7nF 4.7nF
100
4.7nF
100
4.7nF
100
4.7nF
100
33µF
V
BATT
100nF
V
CC
100nF
5 V
12 V
27k
Sensor
control
+
47µF
+
V
CC
CLK
DI
CS
HS4 HS3 HS2 HS1
Thermal protection
U6820BM
698 1
Control
logic
16
3
Power-on reset
V
CC
V
CC
27
1015
5
V
CC
V
CC
4
14
11
13
12
LS1
GND
CC
HH
3
SS
4S
2S
1
L
S
3
L
S
4
L
S
2
L
S
1
Input register
HH
Current
limiter
Current
limiter
Current
limiter
Current
limiter
Current
limiter
Current
limiter
Current
limiter
Current
limiter
GND
S
V
S
RR
LR
RF
LF
10
4527B–BCD–09/05
U6820BM
10. Package Information
11. Revision History
9. Ordering Information
Extended Type Number Package Remarks
U6820BM-MFPG3Y SO16 Taped and reeled, Pb-free
technical drawings
according to DIN
specifications
Package SO16
Dimensions in mm
10.0
9.85
8.89
0.4
1.27
1.4
0.25
0.10
5.2
4.8
3.7
3.8
6.15
5.85
0.2
16 9
18
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No. History
4527B-BCD-09/05
• Put datasheet in a new template
• Pb-free logo on page 1 added
• New heading rows on Table “Absolute Maximum Ratings” on page 7 added
• Table “Ordering Information” on page 10 changed
Printed on recycled paper.
4527B–BCD–09/05
© Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are® and others, are registered
trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
Atmel Corporation Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Literature Requests
www.atmel.com/literature
