32-Bit TC1736 32-Bit Single-Chip Microcontroller Data Sheet V1.1 2009-08 Microcontrollers Edition 2009-08 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 32-Bit TC1736 32-Bit Single-Chip Microcontroller Data Sheet V1.1 2009-08 Microcontrollers TC1736 TC1736 Data Sheet Revision History: V1.1, 2009-08 Previous Version: V1.0 Page Subjects (major changes since last revision) Page 5-95 IDD for 40 MHz variant and the test condition is updated. Page 5-115 The thermal resistance values are updated, the method used for the specified thermal resistances is included. Page 5-116 The package name is corrected. Previous Version: V0.2 Page 2-25 Text which describes the endurance of PFlash and DFlash is enhanced. Page 3-56 Input spike-filter info is added to PORST. Page 3-56 A footnote is added to VDDMF . Page 5-82 The spike-filters parameters are included, tSF1, tSF2. Page 5-85 The maximum limit for IOZ1 is updated. Page 5-93 The temperature sensor measurement time parameter is added. Page 5-95 IDD for 40 MHz variant is added. Page 5-101 The condition for HWCFG is deleted from hold time from PORST rising edge. Page 5-102 The power, pad, reset timing figure is updated. Page 5-103 The notes under the PLL sections are updated. Trademarks TriCore(R) is a trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V1.1, 2009-08 TC1736 Table of Contents Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.2 2.2.1 2.2.2 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.4.1 2.4.4.2 2.4.4.3 2.4.4.4 2.4.5 2.4.6 2.4.6.1 2.4.6.2 2.4.6.3 2.4.6.4 2.4.6.5 2.4.7 2.4.8 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.6.1 2.5.7 2.5.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Related Documentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reserved, Undefined, and Unimplemented Terminology . . . . . . . . . . . . 9 Register Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 System Architecture of the TC1736 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 System Features of the TC1736 device . . . . . . . . . . . . . . . . . . . . . . . . 15 High-Performance 32-Bit TriCore CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 On-Chip System Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Flexible Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 General Purpose I/O Ports and Peripheral I/O Lines . . . . . . . . . . . . . . . 23 Program Memory Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Overlay RAM and Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Emulation Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Tuning Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Program and Data Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Data Access Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 TC1736 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 On-Chip Peripheral Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous/Synchronous Serial Interfaces . . . . . . . . . . . . . . . . . . . . 32 High-Speed Synchronous Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . 34 Micro Second Channel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MultiCAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Micro Link Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 General Purpose Timer Array (GPTAv5) . . . . . . . . . . . . . . . . . . . . . . . . 43 Functionality of GPTA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Analog-to-Digital Converter (ADC0, ADC1) . . . . . . . . . . . . . . . . . . . . . . 46 Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . . . 47 Data Sheet 1 V1.1, 2009-08 TC1736 Table of Contents 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Time Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibration Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tool Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Test Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FAR Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 51 51 52 52 53 53 3 3.1 3.1.1 3.1.2 3.2 3.2.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TC1736 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 54 54 55 56 73 4 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.8.1 5.3.8.2 5.3.8.3 5.4 5.4.1 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 77 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Analog to Digital Converters (ADC0/ADC1) . . . . . . . . . . . . . . . . . . . . . 85 Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . . . 90 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . 112 SSC Master / Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Data Sheet 2 V1.1, 2009-08 TC1736 Table of Contents 5.4.2 5.4.3 5.4.4 Data Sheet Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3 V1.1, 2009-08 TC1736 Summary of Features 1 * * * * * * * * * Summary of Features High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline - Superior real-time performance - Strong bit handling - Fully integrated DSP capabilities - Single precision Floating Point Unit (FPU) - Up to 80 MHz operation at full temperature range Multiple on-chip memories - Up to 36 Kbyte Data Memory (LDRAM) - 8 Kbyte Code Scratchpad Memory (SPRAM) - Up to 1 Mbyte Program Flash Memory (PFlash) - 32 Kbyte Data Flash Memory (DFlash, represents 8Kbyte EEPROM) - Instruction Cache: up to 8Kbyte (ICACHE, configurable) - 4 Kbyte Overlay Memory (OVRAM) - 16 Kbyte BootROM (BROM) 8-Channel DMA Controller Sophisticated interrupt system with 255 hardware priority arbitration levels serviced by CPU High performing on-chip bus structure - 64-bit Local Memory Buses between CPU, Flash and Data Memory - 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units - One bus bridges (LFI Bridge) Versatile On-chip Peripheral Units - Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection - Two High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction - One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices - One High-Speed Micro Link interface (MLI) for serial inter-processor communication - One MultiCAN Module with 2CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer - One General Purpose Timer Array Modules (GPTA) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management 24 analog input lines for ADC - 2 independent kernels (ADC0, ADC1) - Analog supply voltage range from 3.3 V to 5 V (single supply) - Performance for 12 bit resolution (@fADCI = 10 MHz) 2 different FADC input channels Extreme fast conversion, 21 cycles of fFADC clock (262.5 ns @ fFADC = 80 MHz) Data Sheet 4 V1.1, 2009-08 TC1736 Summary of Features * * * * * * * * * * * - 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) 70 digital general purpose I/O lines (GPIO), 4 input lines Digital I/O ports with 3.3 V capability On-chip debug support for OCDS Level 1 (CPU, DMA, On Chip Bus) Dedicated Emulation Device chip available (TC1736ED) - multi-core debugging, real time tracing, and calibration - four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface Power Management System Clock Generation Unit with PLL Core supply voltage of 1.5 V I/O voltage of 3.3 V Full automotive temperature range: -40 to +125C Package variants: PG-LQFP-144-10 Data Sheet 5 V1.1, 2009-08 TC1736 Summary of Features Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: * * The derivative itself, i.e. its function set, the temperature range, and the supply voltage The package and the type of delivery. For the available ordering codes for the TC1736 please refer to the "Product Catalog Microcontrollers", which summarizes all available microcontroller variants. This document describes the derivatives of the device.The Table 1 enumerates these derivatives and summarizes the differences. Table 1 TC1736 Derivative Synopsis Derivative Ambient PFlash Temperature Range LDRAM CPU frequency SAK-TC1736-128F80HL TA = -40oC to +125oC 1 Mbyte 36 Kbyte 80 MHz SAK-TC1736-96F40HL TA = -40oC to +125oC 768 Kbyte 32 Kbyte 40 MHz Data Sheet 6 V1.1, 2009-08 TC1736 Introduction 2 Introduction The TC1736 32-Bit Single-Chip Microcontroller is a cost-optimized version of the TC1767 32-Bit Single-Chip Microcontroller with less pin count and less functionalities. In comparison to the TC1767, the TC1736 provides: * * * * * * * Less memories in general No PCP Reduced functionality of the GPTA with less I/Os Two CAN nodes only Less analog inputs Reduced CPU clock frequency No LVDS capability for MSC0 output lines The TC1736 Emulation Device is implemented as a TC1767 emulation device in a QFP144 package variant. 2.1 About this Document This document is designed to be read primarily by design engineers and software engineers who need a detailed description of the interactions of the TC1736 functional units, registers, instructions, and exceptions. This TC1736 Data Sheet describes the features of the TC1736 with respect to the TriCore Architecture. Where the TC1736 directly implements TriCore architectural functions, this manual simply refers to those functions as features of the TC1736. In all cases where this manual describes a TC1736 feature without referring to the TriCore Architecture, this means that the TC1736 is a direct implementation of the TriCore Architecture. Where the TC1736 implements a subset of TriCore architectural features, this manual describes the TC1736 implementation, and then describes how it differs from the TriCore Architecture. The differences between the TC1736 and the TriCore Architecture are documented in the section for each subject. 2.1.1 Related Documentations A complete description of the TriCore architecture is found in the document entitled "TriCore Architecture Manual". The architecture of the TC1736 is described separately this way because of the configurable nature of the TriCore specification: Different versions of the architecture may contain a different mix of systems components. The TriCore architecture, however, remains constant across all derivative designs in order to maintain compatibility. This Data Sheets together with the "TriCore Architecture Manual" are required to understand the complete functionalities of the TC1736 microcontroller . Data Sheet 7 V1.1, 2009-08 TC1736 Introduction 2.1.2 Text Conventions This document uses the following text conventions for named components of the TC1736: * * * * * * * Functional units of the TC1736 are given in plain UPPER CASE. For example: "The SSC supports full-duplex and half-duplex synchronous communication". Pins using negative logic are indicated by an overline. For example: "The external reset pin, ESR0, has dual-functionality.". Bit fields and bits in registers are in general referenced as "Module_Register name.Bit field" or "Module_Register name.Bit". For example: "The Current CPU Priority Number bit field CPU_ICR.CCPN is cleared". Most of the register names contain a module name prefix, separated by an underscore character "_" from the actual register name (for example, "ASC0_CON", where "ASC0" is the module name prefix, and "CON" is the kernel register name). In chapters describing the kernels of the peripheral modules, the registers are mainly referenced with their kernel register names. The peripheral module implementation sections mainly refer to the actual register names with module prefixes. Variables used to describe sets of processing units or registers appear in mixed upper and lower cases. For example, register name "MSGCFGn" refers to multiple "MSGCFG" registers with variable n. The boundary of the variables are always given where the register expression is first used (for example, "n = 0-31"), and may be repeated when necessary. The default radix is decimal. Hexadecimal constants are suffixed with a subscript letter "H", as in 100H. Binary constants are suffixed with a subscript letter "B", as in: 111B. When the extent of register fields, groups register bits, or groups of pins are collectively named in the body of the document, they are represented as "NAME[A:B]", which defines a range for the named group from B to A. Individual bits, signals, or pins are given as "NAME[C]" where the range of the variable C is given in the text. For example: CFG[2:0] and SRPN[0]. Units are abbreviated as follows: - MHz = Megahertz - s = Microseconds - kBaud, kbit = 1000 characters/bits per second - MBaud, Mbit = 1,000,000 characters/bits per second - Kbyte, KB = 1024 bytes of memory - Mbyte, MB = 1048576 bytes of memory In general, the k prefix scales a unit by 1000 whereas the K prefix scales a unit by 1024. Hence, the Kbyte unit scales the expression preceding it by 1024. The kBaud unit scales the expression preceding it by 1000. The M prefix scales by 1,000,000 or 1048576, and scales by .000001. For example, 1 Kbyte is 1024 bytes, 1 Mbyte is 1024 x 1024 bytes, 1 kBaud/kbit are 1000 characters/bits Data Sheet Intro, V1.1 8 V1.1, 2009-08 TC1736 Introduction * per second, 1 MBaud/Mbit are 1000000 characters/bits per second, and 1 MHz is 1,000,000 Hz. Data format quantities are defined as follows: - Byte = 8-bit quantity - Half-word = 16-bit quantity - Word = 32-bit quantity - Double-word = 64-bit quantity 2.1.3 Reserved, Undefined, and Unimplemented Terminology In tables where register bit fields are defined, the following conventions are used to indicate undefined and unimplemented function. Furthermore, types of bits and bit fields are defined using the abbreviations as shown in Table 2-1. Table 2-1 Bit Function Terminology Function of Bits Description Unimplemented, Reserved Register bit fields named 0 indicate unimplemented functions with the following behavior. * Reading these bit fields returns 0. * These bit fields should be written with 0 if the bit field is defined as r or rh. * These bit fields have to be written with 0 if the bit field is defined as rw. These bit fields are reserved. The detailed description of these bit fields can be found in the register descriptions. rw The bit or bit field can be read and written. rwh As rw, but bit or bit field can be also set or reset by hardware. r The bit or bit field can only be read (read-only). w The bit or bit field can only be written (write-only). A read to this register will always give a default value back. rh This bit or bit field can be modified by hardware (read-hardware, typical example: status flags). A read of this bit or bit field give the actual status of this bit or bit field back. Writing to this bit or bit field has no effect to the setting of this bit or bit field. Data Sheet 9 V1.1, 2009-08 TC1736 Introduction Table 2-1 Bit Function Terminology (cont'd) Function of Bits Description s Bits with this attribute are "sticky" in one direction. If their reset value is once overwritten by software, they can be switched again into their reset state only by a reset operation. Software cannot switch this type of bit into its reset state by writing the register. This attribute can be combined to "rws" or "rwhs". f Bits with this attribute are readable only when they are accessed by an instruction fetch. Normal data read operations will return other values. 2.1.4 Register Access Modes Read and write access to registers and memory locations are sometimes restricted. In memory and register access tables, the terms as defined in Table 2-2 are used. Table 2-2 Access Terms Symbol Description U Access Mode: Access permitted in User Mode 0 or 1. Reset Value: Value or bit is not changed by a reset operation. SV Access permitted in Supervisor Mode. R Read-only register. 32 Only 32-bit word accesses are permitted to this register/address range. E Endinit-protected register/address. PW Password-protected register/address. NC No change, indicated register is not changed. BE Indicates that an access to this address range generates a Bus Error. nBE Indicates that no Bus Error is generated when accessing this address range, even though it is either an access to an undefined address or the access does not follow the given rules. nE Indicates that no Error is generated when accessing this address or address range, even though the access is to an undefined address or address range. True for CPU accesses (MTCR/MFCR) to undefined addresses in the CSFR range. Data Sheet Intro, V1.1 10 V1.1, 2009-08 TC1736 Introduction 2.1.5 Abbreviations and Acronyms The following acronyms and terms are used in this document: ADC Analog-to-Digital Converter AGPR Address General Purpose Register ALU Arithmetic and Logic Unit ASC Asynchronous/Synchronous Serial Controller BCU Bus Control Unit BROM Boot ROM & Test ROM CAN Controller Area Network CISC Complex Instruction Set Computing CPS CPU Slave Interface CPU Central Processing Unit CSA Context Save Area CSFR Core Special Function Register DAP Device Access Port DAS Device Access Server DFLASH Data Flash Memory DGPR Data General Purpose Register DMA Direct Memory Access DMI Data Memory Interface ERU External Request Unit EMI Electro-Magnetic Interference FADC Fast Analog-to-Digital Converter FAM Flash Array Module FCS Flash Command State Machine FIM Flash Interface and Control Module FPI Flexible Peripheral Interconnect (Bus) FPU Floating Point Unit GPIO General Purpose Input/Output GPR General Purpose Register GPTA General Purpose Timer Array Data Sheet 11 V1.1, 2009-08 TC1736 Introduction ICACHE Instruction Cache I/O Input / Output JTAG Joint Test Action Group = IEEE1149.1 LBCU Local Memory Bus Control Unit LDRAM Local Data RAM LFI Local Memory-to-FPI Bus Interface LMB Local Memory Bus LTC Local Timer Cell MLI Micro Link Interface MMU Memory Management Unit MSB Most Significant Bit MSC Micro Second Channel NC Non-Connected NMI Non-Maskable Interrupt OCDS On-Chip Debug Support OVRAM Overlay Memory PMU Program Memory Unit PLL Phase Locked Loop PFLASH Program Flash Memory PMI Program Memory Interface PMU Program Memory Unit RAM Random Access Memory RISC Reduced Instruction Set Computing SBCU System Peripheral Bus Control Unit SCU System Control Unit SFR Special Function Register SPB System Peripheral Bus SPRAM Scratch-Pad RAM SRAM Static Data Memory SRN Service Request Node SSC Synchronous Serial Controller Data Sheet Intro, V1.1 12 V1.1, 2009-08 TC1736 Introduction STM System Timer WDT Watchdog Timer 2.2 System Architecture of the TC1736 The TC1736 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications: * * * Reduced Instruction Set Computing (RISC) processor architecture Digital Signal Processing (DSP) operations and addressing modes On-chip memories and peripherals DSP operations and addressing modes provide the computational power necessary to efficiently analyze complex real-world signals. The RISC load/store architecture provides high computational bandwidth with low system cost. On-chip memory and peripherals are designed to support even the most demanding high-bandwidth real-time embedded control-systems tasks. Additional High-level features of the TC1736 include: * * * * * * * * Program Memory Unit - instruction memory and instruction cache Serial communication interfaces - flexible synchronous and asynchronous modes DMA Controller - DMA operations and interrupt servicing General-purpose timers High-performance on-chip buses On-chip debugging and emulation facilities Flexible interconnections to external components Flexible power-management System Features * * Maximum CPU clock frequency: 80 MHz Maximum System Peripheral Bus frequency: 80 MHz The TC1736 is a high-performance microcontroller with TriCore CPU, program and data memories, buses, bus arbitration, an interrupt controller, a DMA controller and several on-chip peripherals. The TC1736 is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price/performance, real-time responsiveness, computational power, data bandwidth, and power consumption are key design elements. The TC1736 offers several versatile on-chip peripheral units such as serial controllers, timer units, and Analog-to-Digital converters. Within the TC1736, all these peripheral units are connected to the TriCore CPU/system via the System Peripheral Bus (SPB) and the Local Memory Bus (LMB). Several I/O lines on the TC1736 ports are reserved for these peripheral units to communicate with the external world. Data Sheet 13 V1.1, 2009-08 TC1736 Introduction 2.2.1 Block Diagram Figure 2-1 shows the block diagram of the TC1736. FPU PMI DMI TM TriCore CPU 8 KB SPRAM/ ICACHE Up to 36 KB LDRAM (configurable ) CPS Local Memory Bus (LMB) Abbreviations: ICACHE: Instruction Cache SPRAM: Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash LBCU PMU DMA 8 Channel Up to 1 MB PFLASH 32 KB DFLASH 16 KB BROM 4 KB OVRAM LFI Bridge GPTA GPTA0 ASC0 SSC0 Ports STM OCDS SSC1 SBCU SCU MLI0 PLL ASC1 System Peripheral Bus (SPB) MultiCAN (2 Nodes) MSC0 ADC0 ADC1 FADC (3.3-5V) (3.3-5V) (3.3V) 16 4 Analog Inputs Figure 2-1 Data Sheet Intro, V1.1 4 TC 1736_BlockDiag TC1736 Block Diagram 14 V1.1, 2009-08 TC1736 Introduction 2.2.2 System Features of the TC1736 device The TC1736 has the following features: Packages * PG-LQFP-144-10 package, 0.5 mm pitch Clock Frequencies * * Maximum CPU clock frequency: 80 MHz Maximum SPB clock frequency: 80 MHz Data Sheet 15 V1.1, 2009-08 TC1736 Introduction 2.3 High-Performance 32-Bit TriCore CPU TriCore (TC1.3.1) Architectural Highlights * * * * * * * * * * * * * Unified RISC MCU/DSP 32-bit architecture with 4 Gbytes unified data, program, and input/output address space Fast automatic context-switching Multiply-accumulate unit Floating point unit Saturating integer arithmetic High-performance on-chip peripheral bus (FPI Bus) Register based design with multiple variable register banks Bit handling Packed data operations Zero overhead loop Precise exceptions Flexible power management High-Efficiency TriCore Instruction Set * * * * * 16/32-bit instructions for reduced code size Data types include: Boolean, array of bits, character, signed and unsigned integer, integer with saturation, signed fraction, double-word integers, and IEEE-754 singleprecision floating point Data formats include: Bit, 8-bit byte, 16-bit half-word, 32-bit word, and 64-bit doubleword data formats Powerful instruction set Flexible and efficient addressing mode for high code density Integrated CPU related On-Chip Memories * * * 8 KB instruction memory - configurable as SPRAM and ICACHE in 4 KB granularity Up to 36 KB data memory (LDRAM) On-chip SRAMs with parity error detection Data Sheet Intro, V1.1 16 V1.1, 2009-08 TC1736 Introduction 2.4 On-Chip System Units The TC1736 32-Bit Single-Chip Microcontroller offers several versatile on-chip system peripheral units such as DMA controller, embedded Flash module, interrupt system and ports. 2.4.1 Flexible Interrupt System The TC1736 includes a programmable interrupt system with the following features: Features * * * * * Fast interrupt response Hardware arbitration Programmable service request nodes (SRNs) Flexible interrupt-prioritizing scheme with 255 interrupt priority levels per SRN to choose from Each SRN is mapped to the CPU interrupt system 2.4.2 Direct Memory Access Controller The TC1736 includes a fast and flexible DMA controller with 8 independent DMA channels (one DMA engine). Features * * * * * independent DMA channels - Up to 16 selectable request inputs per DMA channel - 2-level programmable priority of DMA channels within the DMA Sub-Block - Software and hardware DMA request - Hardware requests by selected on-chip peripherals and external inputs 3-level programmable priority of the DMA Sub-Block at the on-chip bus interfaces Buffer capability for move actions on the buses (at least 1 move per bus is buffered) Individually programmable operation modes for each DMA channel - Single Mode: stops and disables DMA channel after a predefined number of DMA transfers - Continuous Mode: DMA channel remains enabled after a predefined number of DMA transfers; DMA transaction can be repeated - Programmable address modification - Two shadow register modes (with or without automatic re-set and direct write access). Full 32-bit addressing capability of each DMA channel - 4 Gbyte address range - Data block move supports > 32 Kbyte per DMA transaction - Circular buffer addressing mode with flexible circular buffer sizes Data Sheet 17 V1.1, 2009-08 TC1736 Introduction * * * * * Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit Register set for each DMA channel - Source and destination address register - Channel control and status register - Transfer count register Flexible interrupt generation (the service request node logic for the MLI channel is also implemented in the DMA module) DMA module is working on FPI frequency, LMB interface on LMB frequency. Dependant on the target/destination address, Read/write requests from the Move Engine are directed to the FPI, LMB, MLI or to the the Cerberus. Data Sheet Intro, V1.1 18 V1.1, 2009-08 TC1736 Introduction 2.4.3 System Timer The TC1736's STM is designed for global system timing applications requiring both high precision and long range. Features * * * * * * * * Free-running 56-bit counter All 56 bits can be read synchronously Different 32-bit portions of the 56-bit counter can be read synchronously Flexible interrupt generation based on compare match with partial STM content Driven by maximum 80 MHz (= fSYS, default after reset = fSYS/2) Counting starts automatically after a reset operation STM registers are reset by an application reset if bit ARSTDIS.STMDIS is cleared. If bit ARSTDIS.STMDIS is set, the STM registers are not reset.1). STM can be halted in debug/suspend mode Special STM register semantics provide synchronous views of the entire 56-bit counter, or 32-bit subsets at different levels of resolution. The maximum clock period is 256 x fSTM. At fSTM = 80 MHz, for example, the STM counts 28.56 years before overflowing. Thus, it is capable of continuously timing the entire expected product life time of a system without overflowing. The STM can be optionally disabled for power-saving purposes, or suspended for debugging purposes via its clock control register. In suspend mode of the TC1736 (initiated by writing an appropriate value to STM_CLC register), the STM clock is stopped but all registers are still readable. Due to the 56-bit width of the STM, it is not possible to read its entire content with one instruction. It needs to be read with two load instructions. Since the timer would continue to count between the two load operations, there is a chance that the two values read are not consistent (due to possible overflow from the low part of the timer to the high part between the two read operations). To enable a synchronous and consistent reading of the STM content, a capture register (STM_CAP) is implemented. It latches the content of the high part of the STM each time when one of the registers STM_TIM0 to STM_TIM5 is read. Thus, STM_CAP holds the upper value of the timer at exactly the same time when the lower part is read. The second read operation would then read the content of the STM_CAP to get the complete timer value. The STM can also be read in sections from seven registers, STM_TIM0 through STM_TIM6, that select increasingly higher-order 32-bit ranges of the STM. These can be viewed as individual 32-bit timers, each with a different resolution and timing range. The content of the 56-bit System Timer can be compared against the content of two compare values stored in the STM_CMP0 and STM_CMP1 registers. Service requests 1) "STM registers" means all registers except STM_CLC, STM_SRC0, and STM_SRC1. Data Sheet 19 V1.1, 2009-08 TC1736 Introduction can be generated on a compare match of the STM with the STM_CMP0 or STM_CMP1 registers. Figure 2-2 provides an overview on the STM module. It shows the options for reading parts of STM content. STM Module 31 23 to DMA etc. 15 7 31 Interrupt Control Clock Control 23 STM_CMP1 STM IR0 55 STM IR1 0 Compare Register 0 STM_CMP0 47 15 7 0 Compare Register 1 39 31 23 15 7 0 56-bit System Timer Enable / Disable 00H STM_CAP fSTM 00H STM_TIM6 STM_TIM5 Address Decoder STM_TIM4 STM_TIM3 PORST STM_TIM2 STM_TIM1 STM_TIM0 MCB06185_mod Figure 2-2 Data Sheet Intro, V1.1 General Block Diagram of the STM Module Registers 20 V1.1, 2009-08 TC1736 Introduction 2.4.4 System Control Unit The following SCU introduction gives an overview about the TC1736 System Control Unit (SCU). 2.4.4.1 Clock Generation Unit The Clock Generation Unit (CGU) allows a very flexible clock generation for the TC1736. During user program execution the frequency can be programmed for an optimal ratio between performance and power consumption. 2.4.4.2 Features of the Watchdog Timer The main features of the WDT are summarized here. * * * * * * * * * 16-bit Watchdog counter Selectable input frequency: fFPI/256 or fFPI/16384 16-bit user-definable reload value for normal Watchdog operation, fixed reload value for Time-Out and Prewarning Modes Incorporation of the ENDINIT bit and monitoring of its modifications Sophisticated Password Access mechanism with fixed and user-definable password fields Access Error Detection: Invalid password (during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation Overflow Error Detection: An overflow of the counter triggers the Watchdog reset generation Watchdog function can be disabled; access protection and ENDINIT monitor function remain enabled Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system malfunction is assumed and the TC1736 is held in reset until a system / class 0 reset occurs. 2.4.4.3 Reset Operation The following reset request triggers are available: * * * * * * 1 External power-on hardware reset request trigger; PORST, (cold reset) 2 External System Request reset triggers; ESR0 and ESR1 (warm reset) Watchdog Timer (WDT) reset request trigger, (warm reset) Software reset (SW), (warm reset) Debug (OCDS) reset request trigger, (warm reset) JTAG reset (special reset) Data Sheet 21 V1.1, 2009-08 TC1736 Introduction There are two basic types of reset request triggers: * * Trigger sources that do not depend on a clock, such as the PORST. This trigger force the device into an asynchronous reset assertion independently of any clock. The activation of an asynchronous reset is asynchronous to the system clock, whereas its de-assertion is synchronized. Trigger sources that need a clock in order to be asserted, such as the input signals ESR0 and ESR1, the WDT trigger, the parity trigger, or the SW trigger. 2.4.4.4 External Interface The SCU provides interface pads for system purpose. Various functions are covered by these pins. Due to the different tasks some of the pads can not be shared with other functions but most of them can be shared with other functions. The following functions are covered by the SCU controlled pads: * * * * * Reset request triggers Reset indication Trap request triggers Interrupt request triggers Non SCU module triggers The first three points are covered by the ESR pads and the last two points by the ERU pads. Data Sheet Intro, V1.1 22 V1.1, 2009-08 TC1736 Introduction 2.4.5 General Purpose I/O Ports and Peripheral I/O Lines The TC1736 includes a flexible Ports structure with the following features: Features * * * * * * * 70 digital General-Purpose Input/Output (GPIO) port lines Input/output functionality individually programmable for each port line Programmable input characteristics (pull-up, pull-down, no pull device) Programmable output driver strength for EMI minimization (weak, medium, strong) Programmable output characteristics (push-pull, open drain) Programmable alternate output functions Output lines of each port can be updated port-wise or set/reset/toggled bit-wise 2.4.6 Program Memory Unit (PMU) The devices of the AudoF family contain at least one Program Memory Unit. This is named "PMU0". Some devices contain additional PMUs which are named "PMU1", ... In the TC1736, the PMU0 contains the following submodules: * * * * * The Flash command and fetch control interface for Program Flash and Data Flash. The Overlay RAM interface with Online Data Acquisition (OLDA) support. The Boot ROM interface. The Emulation Memory interface. The Local Memory Bus LMB slave interface. Following memories are controlled by and belong to the PMU0: * * * * 1 Mbyte of Program Flash memory (PFlash) 32 Kbyte of Data Flash memory (DFlash, represents 8 Kbyte EEPROM) 16 Kbyte of Boot ROM (BROM) 4 Kbyte Overlay RAM (OVRAM) Data Sheet 23 V1.1, 2009-08 TC1736 Introduction The following figure shows the block diagram of the PMU0: To/From Local Memory Bus 64 LMB Interface Slave PMU0 Overlay RAM Interface PMU Control 64 64 64 ROM Control 64 OVRAM 64 Flash Interface Module 64 BROM DFLASH Emulation Memory Interface PFLASH Emulation Memory (ED chip only ) Figure 2-3 2.4.6.1 PMU0_BasicBlockDiag_generic PMU0 Basic Block Diagram Boot ROM The internal 16 Kbyte Boot ROM (BROM) is divided into two parts, used for: * * firmware (Boot ROM), and factory test routines (Test ROM). The different sections of the firmware in Boot ROM provide startup and boot operations after reset. The TestROM is reserved for special routines, which are used for testing, stressing and qualification of the component. 2.4.6.2 Overlay RAM and Data Acquisition The overlay memory OVRAM is provided in the PMU especially for redirection of data accesses to program memory to the OVRAM by using the data overlay function. The data overlay functionality itself is controlled in the DMI module. Data Sheet Intro, V1.1 24 V1.1, 2009-08 TC1736 Introduction For online data acquisition (OLDA) of application or calibration data a virtual 32 KB memory range is provided which can be accessed without error reporting. Accesses to this OLDA range can also be redirected to an overlay memory. 2.4.6.3 Emulation Memory Interface In TC1736 Emulation Device, an Emulation Memory (EMEM) is provided, which can fully be used for calibration via program memory or OLDA overlay. The Emulation Memory interface shown in Figure 2-3 is a 64-bit wide memory interface that controls the CPUaccesses to the Emulation Memory in the TC1736 Emulation Device. In the TC1736 production device, the EMEM interface is always disabled. 2.4.6.4 Tuning Protection Tuning protection is required by the user to absolutely protect control data (e.g. for engine control), serial number and user software, stored in the Flash, from being manipulated, and to safely detect changed or disturbed data. For the internal Flash, these protection requirements are excellently fulfilled in the TC1736 with * * * Flash read and write protection with user-specific protection levels, and with dedicated HW and firmware, supporting the internal Flash read protection, and with the Alternate Boot Mode. Special tuning protection support is provided for external Flash, which must also be protected. 2.4.6.5 Program and Data Flash The embedded Flash modules of PMU0 includes 1 Mbyte of Flash memory for code or constant data (called Program Flash) and additionally 32 Kbyte of Flash memory used for emulation of EEPROM data (called Data Flash). The Program Flash is realized as one independent Flash bank, whereas the Data Flash is built of two Flash banks, allowing the following combinations of concurrent Flash operations: * * * Read code or data from Program Flash, while one bank of Data Flash is busy with a program or erase operation. Read data from one bank of Data Flash, while the other bank of Data Flash is busy with a program or erase operation. Program one bank of Data Flash while erasing the other bank of Data Flash, read from Program Flash. Both, the Program Flash and the Data Flash, provide error correction of single-bit errors within a 64-bit read double-word, resulting in an extremely low failure rate. Read accesses to Program Flash are executed in 256-bit width, to Data Flash in 64-bit width (both plus ECC). Single-cycle burst transfers of up to 4 double-words and sequential prefetching with control of prefetch hit are supported for Program Flash. Data Sheet 25 V1.1, 2009-08 TC1736 Introduction The minimum programming width is the page, including 256 bytes in Program Flash and 128 bytes in Data Flash. Concurrent programming and erasing in Data Flash is performed using an automatic erase suspend and resume function. A basic block diagram of the Flash Module is shown in the following figure. Control Redundancy Control FSI Control Flash Command State Machine FCS Voltage Control SFRs FSRAM Microcode Address Addr Bus 64 64 Write Bus Page Write Buffers 256 byte and 128 byte WR_DATA Program Flash 8 ECC Block PF-Read Buffer ECC Code 8 64 Read Bus 64 256+32 bit and DF-Read Buffer Bank 0 Data Flash Bank 1 Bank 0 Bank 1 64+8 bit RD_DATA Flash Interface&Control Module FIM PMU Flash Array Module FAM Flash FSI & Array Flash_BasicBlockDiagram_generic.vsd Figure 2-4 Basic Block Diagram of Flash Module All Flash operations are controlled simply by transferring command sequences to the Flash which are based on JEDEC standard. This user interface of the embedded Flash is very comfortable, because all operations are controlled with high level commands, such as "Erase Sector". State transitions, such as termination of command execution, or errors are reported to the user by maskable interrupts. Command sequences are normally written to Flash by the CPU, but may also be issued by the DMA controller (or OCDS). The Flash also features an advanced read/write protection architecture, including a read protection for the whole Flash array (optionally without Data Flash) and separate write protection for all sectors (only Program Flash). Write protected sectors can be made reprogrammable (enabled with passwords), or they can be locked for ever (ROM function). Each sector can be assigned to up to three different users for write protection. The different users are organized hierarchically. Program Flash Features and Functions * * * 1 Mbyte on-chip Program Flash in PMU0. Any use for instruction code or constant data. 256 bit read interface (burst transfer operation). Data Sheet Intro, V1.1 26 V1.1, 2009-08 TC1736 Introduction * * * * * * * * * * * * * * * * * * * * * Dynamic correction of single-bit errors during read access. Transfer rate in burst mode: One 64-bit double-word per clock cycle. Sector architecture: - Eight 16 Kbyte, one 128 Kbyte and three 256 Kbyte sectors. - Each sector separately erasable. - Each sector lockable for protection against erase and program (write protection). One additional configuration sector (not accessible to the user). Optional read protection for whole Flash, with sophisticated read access supervision. Combined with whole Flash write protection -- thus supporting protection against Trojan horse programs. Sector specific write protection with support of re-programmability or locked forever. Comfortable password checking for temporary disable of write or read protection. User controlled configuration blocks (UCB) in configuration sector for keywords and for sector-specific lock bits (one block for every user; up to three users). Pad supply voltage (VDDP) also used for program and erase (no VPP pin). Efficient 256 byte page program operation. All Flash operations controlled by CPU per command sequences (unlock sequences) for protection against unintended operation. End-of-busy as well as error reporting with interrupt and bus error trap. Write state machine for automatic program and erase, including verification of operation quality. Support of margin check. Delivery in erased state (read all zeros). Global and sector status information. Overlay support with SRAM for calibration applications. Configurable wait state selection for different CPU frequencies. Endurance = 1000; minimum 1000 program/erase cycles per physical sector; reduced endurance of 100 per 16 KB sector. Operating lifetime (incl. Retention): 20 years with endurance=1000. For further operating conditions see data sheet section "Flash Memory Parameters". Data Flash Features and Functions * * * * * * * 32 Kbyte on-chip Flash, configured in two independent Flash banks of equal size. 64 bit read interface. Erase/program one bank while data read access from the other bank. Programming one bank while erasing the other bank using an automatic suspend/resume function. Dynamic correction of single-bit errors during read access. Sector architecture: - Two sectors of equal size. - Each sector separately erasable. 128 byte pages to be written in one step. Data Sheet 27 V1.1, 2009-08 TC1736 Introduction * * * * * * * Operational control per command sequences (unlock sequences, same as those of Program Flash) for protection against unintended operation. End-of-busy as well as error reporting with interrupt and bus error trap. Write state machine for automatic program and erase. Margin check for detection of problematic Flash bits. Endurance = 30000 (can be device dependent); i.e. 30000 program/erase cycles per sector are allowed, with a retention of min. 5 years. Dedicated DFlash status information. Other characteristics: Same as Program Flash. Data Sheet Intro, V1.1 28 V1.1, 2009-08 TC1736 Introduction 2.4.7 Data Access Overlay The data overlay functionality provides the capability to redirect data accesses by the TriCore to program memory (internal Program Flash or external memory) to the Overlay SRAM in the PMU, or to the Emulation Memory in Emulation Device ED. This functionality makes it possible, for example, to modify the application's test and calibration parameters (which are typically stored in the program memory) during run time of a program. Note that read and write data accesses from/to program memory are redirected. Attention: As the address translation is implemented in the DMI, it is only effective for data accesses by the TriCore. Instruction fetches by the TriCore or accesses by any other master (including the debug interface) are not affected! Summary of Features and Functions * * * * * * * * 16 overlay ranges ("blocks") configurable for Program Flash and external memory Support of 4 Kbyte embedded Overlay SRAM (OVRAM) in PMU Support of up to 256 Kbyte overlay/calibration memory in Emulation Device (EMEM) Support of Online Data Acquisition into range of up to 32 KB and of its overlay Support of different overlay memory selections for every enabled overlay block Sizes of overlay blocks selectable from 16 byte to 2 Kbyte for redirection to OVRAM Sizes of overlay blocks selectable from 1 Kbyte to 128 Kbyte for redirection to EMEM All configured overlay ranges can be enabled with only one register write access Data Sheet 29 V1.1, 2009-08 TC1736 Introduction 2.4.8 TC1736 Development Support Overview about the TC1736 development environment: Complete Development Support A variety of software and hardware development tools for the 32-bit microcontroller TC1736 are available from experienced international tool suppliers. The development environment for the Infineon 32-bit microcontroller includes the following tools: * * * * Embedded Development Environment for TriCore Products The TC1736 On-chip Debug Support (OCDS) provides a JTAG port for communication between external hardware and the system The System Timer (STM) with high-precision, long-range timing capabilities The TC1736 includes a power management system, a watchdog timer as well as reset logic Data Sheet Intro, V1.1 30 V1.1, 2009-08 TC1736 Introduction 2.5 On-Chip Peripheral Units The TC1736 micro controller offers several versatile on-chip peripheral units such as serial controllers, timer units, and Analog-to-Digital converters. Several I/O lines on the TC1736 ports are reserved for these peripheral units to communicate with the external world. On-Chip Peripheral Units * * * * * * * * Two Asynchronous/Synchronous Serial Channels (ASC0, ASC1) with baud rate generator, parity, framing and overrun error detection Two Synchronous Serial Channels (SSC0, SSC1) with programmable data length and shift direction One Micro Second Bus Interface (MSC0) for serial communication One CAN Module with two CAN nodes (MultiCAN) for high-efficiency data handling via FIFO buffering and gateway data transfer One Micro Link Serial Bus Interfaces (MLI0) for serial multiprocessor communication One General Purpose Timer Array (GPTA0) with a powerful set of digital signal filtering and timer functionality to accomplish autonomous and complex Input/Output management Two Analog-to-Digital Converter Units (ADC0, ADC1) with 8-bit, 10-bit, or 12-bit resolution. One fast Analog-to-Digital Converter Unit (FADC) Data Sheet 31 V1.1, 2009-08 TC1736 Introduction 2.5.1 Asynchronous/Synchronous Serial Interfaces The TC1736 includes two Asynchronous/Synchronous Serial Interfaces, ASC0 and ASC1. Both ASC modules have the same functionality. Figure 2-5 shows a global view of the Asynchronous/Synchronous Serial Interface (ASC). Clock Control fASC RXD Address Decoder Interrupt Control ASC Module (Kernel) TXD RXD Port Control TXD EIR TBIR TIR RIR To DMA MCB05762_mod Figure 2-5 General Block Diagram of the ASC Interface The ASC provides serial communication between the microcontrollers, microprocessors, or external peripherals. TC1736 and other The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock that is generated by the ASC internally. In Asynchronous Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC with a separate serial clock signal, which can be accurately adjusted by a prescaler implemented as fractional divider. Data Sheet Intro, V1.1 32 V1.1, 2009-08 TC1736 Introduction Features * * * * * Full-duplex asynchronous operating modes - 8-bit or 9-bit data frames, LSB first - Parity-bit generation/checking - One or two stop bits - Baud rate from 5.0 Mbit/s to 1.19 bit/s (@ 80 MHz module clock) - Multiprocessor mode for automatic address/data byte detection - Loop-back capability Half-duplex 8-bit synchronous operating mode - Baud rate from 10.0 Mbit/s to 813.8 bit/s (@ 80 MHz module clock) Double-buffered transmitter/receiver Interrupt generation - On a transmit buffer empty condition - On a transmit last bit of a frame condition - On a receive buffer full condition - On an error condition (frame, parity, overrun error) Implementation features - Connections to DMA Controller - Connections of receiver input to GPTA (LTC) for baud rate detection and LIN break signal measuring Data Sheet 33 V1.1, 2009-08 TC1736 Introduction 2.5.2 High-Speed Synchronous Serial Interfaces The TC1736 includes two High-Speed Synchronous Serial Interfaces, SSC0 and SSC1. Both SSC modules have the same functionality. Figure 2-6 shows a global view of the Synchronous Serial interface (SSC). fSSC Clock Control Master fCLC Slave Address Decoder RIR Interrupt Control TIR EIR DMA Requests SSC Module (Kernel) Slave Master Slave Master MRSTA MRSTB MTSR MTSR MTSRA MTSRB MRST SCLKA SCLKB SCLK MRST Port Control SLSI[7:1] SLSO[7:0] SLSOANDO[7:0] SLSOANDI[7:0] SCLK SLSI[7:1] SLSO[7:0] SLSOANDO[7:0] Enable M/S Select MCB06058_mod Figure 2-6 General Block Diagram of the SSC Interface The SSC supports full-duplex and half-duplex serial synchronous communication up to 40 Mbit/s (@ 80 MHz module clock, Master Mode). The serial clock signal can be generated by the SSC itself (Master Mode) or can be received from an external master (Slave Mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data are double-buffered. A shift clock generator provides the SSC with a separate serial clock signal. One slave select input is available for slave mode operation. Eight programmable slave select outputs (chip selects) are supported in Master Mode. Data Sheet Intro, V1.1 34 V1.1, 2009-08 TC1736 Introduction Features * * * * * * * Master and Slave Mode operation - Full-duplex or half-duplex operation - Automatic pad control possible Flexible data format - Programmable number of data bits: 2 to 16 bits - Programmable shift direction: LSB or MSB shift first - Programmable clock polarity: Idle low or idle high state for the shift clock - Programmable clock/data phase: Data shift with leading or trailing edge of the shift clock Baud rate generation - Master Mode: 40.0 Mbit/s to 610.36 bit/s (@ 80 MHz module clock) - Slave Mode: 20 Mbit/s to 610.36 bit/s (@ 80 MHz module clock) Interrupt generation - On a transmitter empty condition - On a receiver full condition - On an error condition (receive, phase, baud rate, transmit error) Flexible SSC pin configuration Seven slave select inputs SLSI[7:1] in Slave Mode Eight programmable slave select outputs SLSO in Master Mode - Automatic SLSO generation with programmable timing - Programmable active level and enable control - Combinable with SLSO output signals from other SSC modules Data Sheet 35 V1.1, 2009-08 TC1736 Introduction 2.5.3 Micro Second Channel Interface The Micro Second Channel (MSC) interface provides serial communication links typically used to connect power switches or other peripheral devices. The serial communication link includes a fast synchronous downstream channel and a slow asynchronous upstream channel. Figure 2-7 shows a global view of the interface signals of the MSC interface. fMSC Clock Control fCLC FCLP FCLN Interrupt SR[3:0] Control 4 MSC Module (Kernel) SOP Downstream Channel Address Decoder SON EN0 EN1 EN2 To DMA ALTINH[15:0] 16 Upstream Channel ALTINL[15:0] EN3 16 8 SDI[7:0] EMGSTOPMSC MCB06059 Figure 2-7 General Block Diagram of the MSC Interface The downstream and upstream channels of the MSC module communicate with the external world via nine I/O lines. Eight output lines are required for the serial communication of the downstream channel (clock, data, and enable signals). One out of eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The source of the serial data to be transmitted by the downstream channel can be MSC register contents or data that is provided on the ALTINL/ALTINH input lines. These input lines are typically connected with other on-chip peripheral units (for example with a timer unit such as the GPTA). An emergency stop input signal makes it possible to set bits of the serial data stream to dedicated values in an emergency case. Clock control, address decoding, and interrupt service request control are managed outside the MSC module kernel. Service request outputs are able to trigger an interrupt or a DMA request. Data Sheet Intro, V1.1 36 V1.1, 2009-08 TC1736 Introduction Features * * * Fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses High-speed synchronous serial transmission on downstream channel - Serial output clock frequency: fFCL = fMSC/2 (fMSCmax = 80 MHz) - Fractional clock divider for precise frequency control of serial clock fMSC - Command, data, and passive frame types - Start of serial frame: Software-controlled, timer-controlled, or free-running - Programmable upstream data frame length (16 or 12 bits) - Transmission with or without SEL bit - Flexible chip select generation indicates status during serial frame transmission - Emergency stop without CPU intervention Low-speed asynchronous serial reception on upstream channel - Baud rate: fMSC divided by 4, 8, 16, 32, 64, 128, or 256 (fMSCmax = 80 MHz) - Standard asynchronous serial frames - Parity error checker - 8-to-1 input multiplexer for SDI lines - Built-in spike filter on SDI lines Data Sheet 37 V1.1, 2009-08 TC1736 Introduction 2.5.4 MultiCAN Controller The MultiCAN module provides two independent CAN nodes, representing two serial communication interfaces. The number of available message objects 64. MultiCAN Module Kernel fCAN Clock Control Address Decoder Interrupt Control fCLC Message Object Buffer 64 Objects Linked List Control CAN Node 1 TXDC1 CAN Node 0 TXDC0 RXDC1 Port Control RXDC0 CAN Control MCA06060_N2 Figure 2-8 Overview of the MultiCAN Module The MultiCAN module contains two independently operating CAN nodes with Full-CAN functionality that are able to exchange Data and Remote Frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. All two CAN nodes share a common set of message objects. Each message object can be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the CAN nodes or to set up a FIFO buffer. The message objects are organized in double-chained linked lists, where each CAN node has its own list of message objects. A CAN node stores frames only into message objects that are allocated to the message object list of the CAN node, and it transmits only messages belonging to this message object list. A powerful, command-driven list controller performs all message object list operations. The bit timings for the CAN nodes are derived from the module timer clock (fCAN) and are programmable up to a data rate of 1 Mbit/s. External bus transceivers are connected to a CAN node via a pair of receive and transmit pins. Data Sheet Intro, V1.1 38 V1.1, 2009-08 TC1736 Introduction Features * * * * * * * * * * * Compliant with ISO 11898 CAN functionality according to CAN specification V2.0 B active Dedicated control registers for each CAN node Data transfer rates up to 1 Mbit/s Flexible and powerful message transfer control and error handling capabilities Advanced CAN bus bit timing analysis and baud rate detection for each CAN node via a frame counter Full-CAN functionality: A set of 64 message objects can be individually - Allocated (assigned) to any CAN node - Configured as transmit or receive object - Setup to handle frames with 11-bit or 29-bit identifier - Identified by a timestamp via a frame counter - Configured to remote monitoring mode Advanced Acceptance Filtering - Each message object provides an individual acceptance mask to filter incoming frames. - A message object can be configured to accept standard or extended frames or to accept both standard and extended frames. - Message objects can be grouped into four priority classes for transmission and reception. - The selection of the message to be transmitted first can be based on frame identifier, IDE bit and RTR bit according to CAN arbitration rules, or on its order in the list. Advanced message object functionality - Message objects can be combined to build FIFO message buffers of arbitrary size, limited only by the total number of message objects. - Message objects can be linked to form a gateway that automatically transfers frames between 2 different CAN buses. A single gateway can link any two CAN nodes. An arbitrary number of gateways can be defined. Advanced data management - The message objects are organized in double-chained lists. - List reorganizations can be performed at any time, even during full operation of the CAN nodes. - A powerful, command-driven list controller manages the organization of the list structure and ensures consistency of the list. - Message FIFOs are based on the list structure and can easily be scaled in size during CAN operation. - Static allocation commands offer compatibility with MultiCAN applications that are not list-based. Advanced interrupt handling Data Sheet 39 V1.1, 2009-08 TC1736 Introduction - Up to 16 interrupt output lines are available. Interrupt requests can be routed individually to one of the 16 interrupt output lines. - Message post-processing notifications can be combined flexibly into a dedicated register field of 256 notification bits. Data Sheet Intro, V1.1 40 V1.1, 2009-08 TC1736 Introduction 2.5.5 Micro Link Interface This TC1736 contains one Micro Link Interface, MLI0. The Micro Link Interface (MLI) is a fast synchronous serial interface to exchange data between microcontrollers or other devices, such as stand-alone peripheral components. Figure 2-9 shows how two microcontrollers are typically connected together via their MLI interfaces. Controller 1 Controller 2 CPU CPU Peripheral A Peripheral B Peripheral C Peripheral D Memory MLI MLI Memory System Bus System Bus MCA06061 Figure 2-9 Typical Micro Link Interface Connection Features * * * * * * * * * * Synchronous serial communication between an MLI transmitter and an MLI receiver Different system clock speeds supported in MLI transmitter and MLI receiver due to full handshake protocol (4 lines between a transmitter and a receiver) Fully transparent read/write access supported (= remote programming) Complete address range of target device available Specific frame protocol to transfer commands, addresses and data Error detection by parity bit 32-bit, 16-bit, or 8-bit data transfers supported Programmable baud rates - MLI transmitter baud rate: max. fMLI/2 (= 40 Mbit/s @ 80 MHz module clock) - MLI receiver baud rate: max. fMLI Address range protection scheme to block unauthorized accesses Multiple receiving devices supported Data Sheet 41 V1.1, 2009-08 TC1736 Introduction Figure 2-10 shows a general block diagram of the MLI module. TREADY[D:A] 4 TVALID[D:A] fSYS Fract. Divider MLI Transmitter I/O Control 4 TDATA TCLK TR[3:0] fMLI Port Control MLI Module BRKOUT RCLK[D:A] 4 RREADY[D:A] 4 SR[7:0] Move Engine MLI Receiver I/O Control RVALID[D:A] 4 RDATA[D:A] 4 MCB06062_mod Figure 2-10 General Block Diagram of the MLI Modules The MLI transmitter and MLI receiver communicate with other MLI receivers and MLI transmitters via a four-line serial connection each. Several I/O lines of these connections are available outside the MLI module kernel as a four-line output or input vector with index numbering A, B, C and D. The MLI module internal I/O control blocks define which signal of a vector is actually taken into account and also allow polarity inversions (to adapt to different physical interconnection means). Data Sheet Intro, V1.1 42 V1.1, 2009-08 TC1736 Introduction 2.5.6 General Purpose Timer Array (GPTAv5) The TC1736 contains the General Purpose Timer Array (GPTA0). Figure 2-11 shows a global view of the GPTA module. The GPTA provides a set of timer, compare, and capture functionalities that can be flexibly combined to form signal measurement and signal generation units. They are optimized for tasks typical of engine, gearbox, and electrical motor control applications, but can also be used to generate simple and complex signal waveforms required for other industrial applications. GPTA0 Clock Generation Unit FPC0 FPC1 DCM0 PDL0 DCM1 FPC2 FPC3 FPC4 DCM2 DIGITAL PLL PDL1 DCM3 FPC5 GT0 C lo ck Bu s fGPTA Clock Distribution Unit Signal Generation Unit GT1 GTC00 GTC01 GTC02 GTC03 LTC00 LTC01 LTC02 LTC03 Global Timer Cell Array Local Timer Cell Array GTC30 GTC31 LTC62 LTC63 I/O Line Sharing Unit Interrupt Sharing Unit MCB05910_TC1767 Figure 2-11 General Block Diagram of the GPTA Module in the TC1736 Data Sheet 43 V1.1, 2009-08 TC1736 Introduction 2.5.6.1 Functionality of GPTA0 The General Purpose Timer Array (GPTA0) provides a set of hardware modules required for high-speed digital signal processing: * * * * * * * * Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. Phase Discrimination Logic units (PDL) decode the direction information output by a rotation tracking system. Duty Cycle Measurement Cells (DCM) provide pulse-width measurement capabilities. A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA module clock ticks during an input signal's period. Global Timer units (GT) driven by various clock sources are implemented to operate as a time base for the associated Global Timer Cells. Global Timer Cells (GTC) can be programmed to capture the contents of a Global Timer on an external or internal event. A GTC may also be used to control an external port pin depending on the result of an internal compare operation. GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform. Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be logically tied together to drive a common external port pin with a complex signal waveform. LTCs - enabled in Timer Mode or Capture Mode - can be clocked or triggered by various external or internal events. On-chip Trigger and Gating Signals (OTGS) can be configured to provide trigger or gating signals to integrated peripherals. Input lines can be shared by an LTC and a GTC to trigger their programmed operation simultaneously. The following list summarizes the specific features of the GPTA units. Clock Generation Unit * * Filter and Prescaler Cell (FPC) - Six independent units - Three basic operating modes: Prescaler, Delayed Debounce Filter, Immediate Debounce Filter - Selectable input sources: Port lines, GPTA module clock, FPC output of preceding FPC cell - Selectable input clocks: GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or uncompensated PLL clock. - fGPTA/2 maximum input signal frequency in Filter Modes Phase Discriminator Logic (PDL) - Two independent units - Two operating modes (2- and 3- sensor signals) Data Sheet Intro, V1.1 44 V1.1, 2009-08 TC1736 Introduction * * * - fGPTA/4 maximum input signal frequency in 2-sensor Mode, fGPTA/6 maximum input signal frequency in 3-sensor Mode Duty Cycle Measurement (DCM) - Four independent units - 0 - 100% margin and time-out handling - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Digital Phase Locked Loop (PLL) - One unit - Arbitrary multiplication factor between 1 and 65535 - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Clock Distribution Unit (CDU) - One unit - Provides nine clock output signals: fGPTA, divided fGPTA clocks, FPC1/FPC4 outputs, DCM clock, LTC prescaler clock Signal Generation Unit * * * Global Timers (GT) - Two independent units - Two operating modes (Free-Running Timer and Reload Timer) - 24-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Global Timer Cell (GTC) - 32 units related to the Global Timers - Two operating modes (Capture, Compare and Capture after Compare) - 24-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Local Timer Cell (LTC) - 64 independent units - Three basic operating modes (Timer, Capture and Compare) for 63 units - Special compare modes for one unit - 16-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Interrupt Sharing Unit * 111 interrupt sources, generating up to 38 service requests Data Sheet 45 V1.1, 2009-08 TC1736 Introduction On-chip Trigger Unit * 16 on-chip trigger signals I/O Sharing Unit * Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and MSC interface 2.5.7 Analog-to-Digital Converter (ADC0, ADC1) The analog to digital converter module (ADC) allows the conversion of analog input values into discrete digital values based on the successive approximation method. The module contains 2 independent kernels (ADC0, ADC1) that can operate autonomously or can be synchronized to each other. An ADC kernel is a unit used to convert an analog input signal (done by an analog part) and provides means for triggering conversions, data handling and storage (done by a digital part). analog part kernel 0 ... analog inputs AD converter data (result) handling conversion control request control analog part kernel 1 ... analog inputs digital part kernel 0 digital part kernel 1 AD converter data (result) handling conversion control request control bus interface ADC_2_kernels Figure 2-12 ADC Module with two ADC Kernels Features of the Analog Part of each ADC Kernel * * Input voltage range from 0V to analog supply voltage Analog supply voltage range from 3.3 V to 5 V (single supply) (5 V nominal supply voltage, performance degradation accepted for lower voltages) Data Sheet Intro, V1.1 46 V1.1, 2009-08 TC1736 Introduction * * * * * * Input multiplexer width of 16 possible analog input channels (not all of them are necessarily available on pins) VAREF and 1 alternative reference input at channel 0 Programmable sample time (in periods of fADCI) Wide range of accepted analog clock frequencies fADCI Multiplexer test mode (channel 7 input can be connected to ground via a resistor for test purposes during run time by specific control bit) Power saving mechanisms Features of the Digital Part of each ADC Kernel * * * * * * * * * * * * Independent result registers (16 independent registers) 5 conversion request sources (e.g. for external events, auto-scan, programmable sequence, etc.) Synchronization of the ADC kernels for concurrent conversion starts Control an external analog multiplexer, respecting the additional set up time Programmable sampling times for different channels Possibility to cancel running conversions on demand with automatic restart Flexible interrupt generation (possibility of DMA support) Limit checking to reduce interrupt load Programmable data reduction filter by adding conversion results Support of conversion data FIFO Support of suspend and power down modes Individually programmable reference selection for each channel (with exception of dedicated channels always referring to VAREF 2.5.8 Fast Analog to Digital Converter (FADC) General Features * * * * * * * * * * * * Extreme fast conversion, 21 cycles of fFADC clock (262.5 ns @ fFADC = 80 MHz) 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) Successive approximation conversion method Two differential input channels with impedance control overlaid with ADC1 inputs Each differential input channel can also be used as single-ended input Offset and gain calibration support for each channel Programmable gain of 1, 2, 4, or 8 for each channel Free-running (Channel Timers) or triggered conversion modes Trigger and gating control for external signals Built-in Channel Timers for internal triggering Channel timer request periods independently selectable for each channel Selectable, programmable digital anti-aliasing and data reduction filter block with four independent filter units Data Sheet 47 V1.1, 2009-08 TC1736 Introduction VFAREF VDDAF VDDMF VDDIF VFAGND VSSAF VSSMF Interrupt Control DMA TS[H:A] GS[H:A] fFADC Data Reduction Unit fCLC SRx A/D Control A/D Converter Stage SRx Channel Trigger Control Input Structure Clock Control FAIN2P FAIN2N FAIN3P FAIN3N input channel 2 input channel 3 Channel Timers MCB06065_m2 Figure 2-13 Block Diagram of the FADC Module with 2 Input Channels Data Sheet Intro, V1.1 48 V1.1, 2009-08 TC1736 Introduction As shown in Figure 2-13, the main FADC functional blocks are: * * * * * * An Input Structure containing the differential inputs and impedance control. An A/D Converter Stage responsible for the analog-to-digital conversion including an input multiplexer to select between the channel amplifiers A Data Reduction Unit containing programmable anti-aliasing and data reduction filters A Channel Trigger Control block determining the trigger and gating conditions for the FADC channels A Channel Timer for each channel to independently trigger the conversions An A/D Control block responsible for the overall FADC functionality FADC Power Supply and References The FADC module is supplied by the following power supply and reference voltage lines: * * * * VDDMF / VSSMF: FADC Analog Channel Amplifier Power Supply (3.3 V) VDDIF / VSSMF: FADC Analog Input Stage Power Supply (3.3 - 5 V), the VDDIF supply does not appear as supply pin, because it is internally connected to the VDDM supply of the ADC that is sharing the FADC input pins. VDDAF / VSSAF: FADC Analog Part Power Supply (1.5 V), to be fed in externally VFAREF / VFAGND: FADC Reference Voltage (3.3 V max.) and FADC Reference Ground Input Structure The input structure of the FADC in the TC1736 contains: * * * A differential analog input stage for each input channel to select the input impedance (differential or single-ended measurement) and to decouple the FADC input signal from the pins. Input channels 2 and 3 are overlaid with ADC1 input signals (AN28, AN29, AN30, AN31). A channel amplifier for each input channel with a settling time (about 5s) when changing the characteristics of an input stage (changing between unused, differential, single-ended N, or single-ended P mode). Data Sheet 49 V1.1, 2009-08 TC1736 Introduction FAIN2P FAIN2N Analog Input Stages Rp Channel Amplifier Stages VDDMF Rn VSSMF FAIN3P Rp FAIN3N Rn VDDMF Converter Stage A/D conversion Control control gain CHNR VSSMF VDDIF A/D VSSMF VDDAF VSSAF MCA06432_m2n Figure 2-14 FADC Input Structure in TC1736 Data Sheet Intro, V1.1 50 V1.1, 2009-08 TC1736 Introduction 2.6 On-Chip Debug Support (OCDS) The TC1736 contains resources for different kinds of "debugging", covering needs from software development to real-time-tuning. These resources are either embedded in specific modules (e.g. breakpoint logic of the TriCore) or part of a central peripheral (known as CERBERUS). 2.6.1 On-Chip Debug Support The classic software debug approach (start/stop, single-stepping) is supported by several features labelled "OCDS Level 1": * * * * * * * * * * * * * * Run/stop and single-step execution for TriCore. Means to request all kinds of reset without usage of sideband pins. Halt-after-Reset for repeatable debug sessions. Different Boot modes to use application software not yet programmed to the Flash. A total of four hardware breakpoints for the TriCore based on instruction address, data address or combination of both. Unlimited number of software breakpoints (DEBUG instruction) for TriCore. Debug event generated by access to a specific address via the system peripheral bus. Tool access to all SFRs and internal memories independent of the Core. Two central Break Switches to collect debug events from all modules (TriCore, DMA, BCU, break input pins) and distribute them selectively to breakable modules (TriCore, break output pins). Central Suspend Switch to suspend parts of the system (TriCore, Peripherals) instead if breaking them as reaction to a debug event. Dedicated interrupt resources to handle debug events inside TriCore (breakpoint trap, software interrupt) and Cerberus, e.g. for implementing Monitor programs. Access to all OCDS Level 1 resources also for TriCore for debug tools integrated into the application code. Triggered Transfer of data in response to a debug event; if target is programmed to be a device interface simple variable tracing can be done. In depth performance analysis and profiling support given by the Emulation Device through MCDS Event Counters driven by a variety of trigger signals (e.g. cache hit, wait state, interrupt accepted). 2.6.2 Real Time Trace For detailed tracing of the system's behavior a pin-compatible Emulation Device will be available.1) 1) The OCDS L2 interface of AudoNG is not available. Data Sheet 51 V1.1, 2009-08 TC1736 Introduction 2.6.3 Calibration Support Two main use cases are catered for by resources in addition the OCDS Level 1 infrastructure: Overlay of non-volatile on-chip memory and non-intrusive signaling: * * * * * * * * 4 KB SRAM for Overlay. Can be split into up to 16 blocks which can overlay independent regions of on-chip Data Flash. Changing the configuration is triggered by a single SFR access to maintain consistency. Overlay configuration switch does not require the TriCore to be stopped or suspended. Invalidation of the Data Cache (maintaining write-back data) can be done concurrently with the same SFR. 256 KB additional Overlay RAM on Emulation Device, shared with the trace functionality. A dedicated trigger SFR with 32 independent status bits is provided to centrally post requests from application code to the host computer. The host is notified automatically when the trigger SFR is updated by the TriCore. No polling via a system bus is required. 2.6.4 Tool Interfaces Three options exist for the communication channel between Tools (e.g. Debugger, Calibration Tool) and TC1736: * * * * * * * * Two wire DAP (Device Access Port) protocol for long connections or noisy environments. Four (or five) wire JTAG (IEEE 1149.1) for standardized manufacturing tests. CAN (plus software linked into the application code) for low bandwidth deeply embedded purposes. DAP and JTAG are clocked by the tool. Bit clock up to 40 MHz for JTAG, up to 80 MHz for DAP. Hot attach (i.e. physical disconnect/reconnect of the host connection without reset of the TC1736) for all interfaces. Infineon standard DAS (Device Access Server) implementation for seamless, transparent tool access over any supported interface. Lock mechanism to prevent unauthorized tool access to critical application code. Data Sheet Intro, V1.1 52 V1.1, 2009-08 TC1736 Introduction 2.6.5 Self-Test Support Some manufacturing tests can be invoked by the application (e.g. after power-on) if needed: * Hardware-accelerated checksum calculation (e.g. for Flash content). 2.6.6 FAR Support To efficiently locate and identify faults after integration of a TC1736 into a system special functions are available: * * Boundary Scan (IEEE 1149.1) via JTAG and DAP. SSCM (Single Scan Chain Mode1)) for structural scan testing of the chip itself. 1) This function requires access to some device pins (e.g. TESTMODE) in addition to those needed for OCDS. Data Sheet 53 V1.1, 2009-08 TC1736 Pinning 3 Pinning 3.1 TC1736 Pinning Figure 3-1 shows the TC1736 logic symbol. 3.1.1 Logic Symbol General Control OCDS / JTAG Control Analog Inputs Analog Power Supply Digital Circuitry Power Supply PORST TESTMODE ESR0 ESR1 Data Sheet 12 8 TRST TCK/DAP0 TDI/BRKIN/ BRKOUT TDO/DAP2/ BRKIN/ BRKOUT TMS / DAP1 AN[x:0] VD D M VSSM V D D MF V SSMF V D D AF V AR EF0 VAGN D 0 VFAR EF V FAGN D VD D FL3 VD D VD D P VSS Figure 3-1 Alternate Functions 14 16 2 16 24 TC1736 8 9 2 Port 0 GPTA0, SCU Port 3 GPTA0, SCU, SSC1, OCDS GPTA0, SSC1, MLI 0, MSC0 GPTA0, ASC0/1, SSC0/1, SCU, CAN Port 4 GPTA0, SCU Port 5 GPTA0, SSC0/1, MLI 0 Port 9 GPTA0 XTAL1 XTAL2 V D D OSC V D D OSC3 V SSOSC Oscillator Port 1 Port 2 9 TC 1736_LogSym_144 TC1736 Logic Symbol 54 V1.1, 2009-08 TC1736 Pinning 3.1.2 Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PG-LQFP-144-10 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P3.4/MTSR0/OUT88 P3.7/SLSO02/SLSO12/SLSI01/OUT89 P3.3/MRST0/OUT87 P3.2/SCLK0/OUT86 P3.8/SLSO06/TXD1/OUT90 P3.6/SLSO01/SLSO11/SLSOANDO1 P3.5/SLSO00/SLSO10/SLSOANDO0 VSS VDDP VDD ESR0 PORST ESR1 P1.1/IN17/OUT17/OUT73 TESTMODE P1.15/BRKIN/BRKOUT P1.0/IN16/OUT16/OUT72/BRKIN/BRKOUT TCK/DAP0 TRST TDO/DAP2/BRKIN/BRKOUT TMS/DAP1 TDI/BRKIN/BRKOUT P1.4/IN20/OUT20/OUT76/EMGSTOP VDDOSC3 VDDOSC VSSOSC XTAL2 XTAL1 VSS VDDP VDD P1.11/IN27/OUT27/IN51/OUT51/SCLK1B P1.10/IN26/OUT26/IN50/OUT50/SLSO17 P1.9/IN25/OUT25/IN49/OUT49/MRST1B P1.8/IN24/OUT24/IN48/OUT48/MTSR1B P4.3/IN31/IN55/OUT31/OUT55/EXTCLK0 AN19 AN16 AN15 AN14 VAGND0 VAREF0 VSSM VDDM AN13 AN12 AN11 AN10 AN9 AN8 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VDD VDDP VSS TCLK0/OUT32/IN32/P2.0 TREADY0A/SLSO13/SLSO03/OUT33/IN33/P2.1 TVALID0/OUT34/IN34/P2.2 TDATA0/OUT35/IN35/P2.3 RCLK0A/OUT36/IN36/P2.4 RREADY0A/OUT37/IN37/P2.5 RVALID0A/OUT38/IN38/P2.6 RDATA0A/OUT39/IN39/P2.7 VSS VDDP VDD EXTCLK1/OUT54/OUT30/IN54/IN30/P4.2 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 OUT40/IN40/P5.0 OUT41/IN41/P5.1 OUT42/IN42/P5.2 OUT43/IN43/P5.3 OUT80/P9.0 OUT81/P9.1 OUT44/IN44/P5.4 OUT45/IN45/P5.5 OUT46/IN46/P5.6 OUT47/IN47/P5.7 TCLK0/P5.15 VDD VDDP VSS RDATA0B/P5.8 RVALID0B/P5.9 RREADY0B/P5.10 RCLK0B/P5.11 SLSO07/TDATA0/P5.12 SLSO16/TVALID0B/P5.13 TREADY0B/P5.14 VDDP 1) VDD VSS VDDAF VDDMF VSSMF VFAREF VFAGND AN31 AN30 AN29 AN28 AN7 AN25 AN23 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 P0.15/IN15/OUT15/OUT71/REQ5 P0.14/IN14/OUT14/OUT70/REQ4 P0.7/IN7/OUT7/OUT63/REQ3/HWCFG7 P0.6/IN6/OUT6/OUT62/REQ2/HWCFG6 VSS VDDP VDD P0.13/IN13/OUT13/OUT69 P0.12/IN12/OUT12/OUT68 P0.5/IN5/OUT5/OUT61/HWCFG5 P0.4/IN4/OUT4/OUT60/HWCFG4 P2.13/SLSI11/SDI0 P2.8/SLSO04/SLSO14/EN00 P2.12/MTSR1A/SOP0B P2.11/SCLK1A/FCLP0B P2.10/MRST1A P2.9/SLSO05/SLSO15/EN01 VSS VDDP VDD P0.3/IN3/OUT3/OUT59/HWCFG3 P0.2/IN2/OUT2/OUT58/HWCFG2 P0.1/IN1/OUT1/OUT57/HWCFG1 P0.0/IN0/OUT0/OUT56/HWCFG0 P3.11/REQ1/OUT93 P3.12/RXDCAN0/RXD0B/OUT94 P3.13/TXDCAN0/TXD0/OUT95 VDDFL3 VSS VDDP P3.9/RXD1A/OUT91 P3.10/REQ0/OUT92 P3.0/RXD0A/OUT84 P3.1/TXD0/OUT85 P3.14/RXDCAN1/RXD1B/OUT96 P3.15/TXDCAN1/TXD1B/OUT97 Figure 3-2 shows the pin configuration of the TC1736 package PG-LQFP-144-10. 1) This pin is used as standby power supply in emulation device. TC1736 Pinning Figure 3-2 Data Sheet Pin Configuration of PG-LQFP-144-10 Package (top view) 55 V1.1, 2009-08 TC1736 Pinning 3.2 Pin Definitions and Functions Table 3-1 Pin Pin Definitions and Functions (PG-LQFP-144-10 Package)1) Symbol Ctrl. Type Function P0.0 I/O0 IN0 I A1/ PU HWCFG0 I Hardware Configuration Input 0 OUT0 O1 GPTA0 Output 0F OUT56 O2 GPTA0 Output 56 Reserved O3 - P0.1 I/O0 IN1 I HWCFG1 I Hardware Configuration Input 1 OUT1 O1 GPTA0 Output 1 OUT57 O2 GPTA0 Output 57 Reserved O3 - P0.2 I/O0 IN2 I HWCFG2 I Hardware Configuration Input 2 OUT2 O1 GPTA0 Output 2 OUT58 O2 GPTA0 Output 58 Reserved O3 - P0.3 I/O0 IN3 I HWCFG3 I Hardware Configuration Input 3 OUT3 O1 GPTA0 Output 3 OUT59 O2 GPTA0 Output 59 Reserved O3 - Port 0 121 122 123 124 Data Sheet A1/ PU A1/ PU A1/ PU Port 0 General Purpose I/O Line 0 GPTA0 Input 0 Port 0 General Purpose I/O Line 1 GPTA0 Input 1 Port 0 General Purpose I/O Line 2 GPTA0 Input 2 Port 0 General Purpose I/O Line 3 GPTA0 Input 3 56 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 134 P0.4 I/O0 IN4 I A1/ PU HWCFG4 I Hardware Configuration Input 4 OUT4 O1 GPTA0 Output 4 OUT60 O2 GPTA0 Output 60 Reserved O3 - P0.5 I/O0 IN5 I HWCFG5 I Hardware Configuration Input 5 OUT5 O1 GPTA0 Output 5 OUT61 O2 GPTA0 Output 61 Reserved O3 - P0.6 I/O0 IN6 I HWCFG6 I Hardware Configuration Input 6 REQ2 I External Request Input 2 OUT6 O1 GPTA0 Output 6 OUT62 O2 GPTA0 Output 62 Reserved O3 - P0.7 I/O0 IN7 I HWCFG7 I Hardware Configuration Input 7 REQ3 I External Request Input 3 OUT7 O1 GPTA0 Output 7 OUT63 O2 GPTA0 Output 63 Reserved O3 - 135 141 142 Data Sheet A1/ PU A1/ PU A1/ PU Port 0 General Purpose I/O Line 4 GPTA0 Input 4 Port 0 General Purpose I/O Line 5 GPTA0 Input 5 Port 0 General Purpose I/O Line 6 GPTA0 Input 6 Port 0 General Purpose I/O Line 7 GPTA0 Input 7 57 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 136 P0.12 I/O0 IN12 I A1/ PU OUT12 O1 GPTA0 Output 12 OUT68 O2 GPTA0 Output 68 Reserved O3 - P0.13 I/O0 IN13 I OUT13 O1 GPTA0 Output 13 OUT69 O2 GPTA0 Output 69 Reserved O3 - P0.14 I/O0 IN14 I REQ4 I External Request Input 4 OUT14 O1 GPTA0 Output 14 OUT70 O2 GPTA0 Output 70 Reserved O3 - P0.15 I/O0 IN15 I REQ5 I External Request Input 5 OUT15 O1 GPTA0 Output 15 OUT71 O2 GPTA0 Output 71 Reserved O3 - P1.0 I/O0 IN16 I BRKIN I OCDS Break Input OUT16 O1 GPTA0 Output 16 OUT72 O2 GPTA0 Output 72 Reserved O3 - BRKOUT O OCDS Break Output (controlled by OCDS module) 137 143 144 A1/ PU A1/ PU A1/ PU Port 0 General Purpose I/O Line 12 GPTA0 Input 12 Port 0 General Purpose I/O Line 13 GPTA0 Input 13 Port 0 General Purpose I/O Line 14 GPTA0 Input 14 Port 0 General Purpose I/O Line 15 GPTA0 Input 15 Port 1 92 Data Sheet A2/ PU Port 1 General Purpose I/O Line 0 GPTA0 Input 16 58 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 95 P1.1 I/O0 IN17 I A1/ PU OUT17 O1 GPTA0 Output 17 OUT73 O2 GPTA0 Output 73 Reserved O3 - P1.4 I/O0 IN20 I EMGSTOP I Emergency Stop Input OUT20 O1 GPTA0 Output 20 OUT76 O2 GPTA0 Output 76 Reserved O3 - P1.8 I/O0 IN24 I IN48 I GPTA0 Input 48 MTSR1B I SSC1 Slave Receive Input B (Slave Mode) OUT24 O1 GPTA0 Output 24 OUT48 O2 GPTA0 Output 48 MTSR1B O3 SSC1 Master Transmit Output B (Master Mode) P1.9 I/O0 IN25 I IN49 I GPTA0 Input 49 MRST1B I SSC1 Master Receive Input B (Master Mode) OUT25 O1 GPTA0 Output 25 OUT49 O2 GPTA0 Output 49 MRST1B O3 SSC1 Slave Transmit Output B (Slave Mode) 86 74 75 Data Sheet A1/ PU A2/ PU A2/ PU Port 1 General Purpose I/O Line 1 GPTA0 Input 17 Port 1 General Purpose I/O Line 4 GPTA0 Input 20 Port 1 General Purpose I/O Line 8 GPTA0 Input 24 Port 1 General Purpose I/O Line 9 GPTA0 Input 25 59 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 76 P1.10 I/O0 IN26 I A2/ PU IN50 I GPTA0 Input 50 OUT26 O1 GPTA0 Output 26 OUT50 O2 GPTA0 Output 50 SLSO17 O3 SSC1 Slave Select Output 7 P1.11 I/O0 IN27 I IN51 I GPTA0 Input 51 SCLK1B I SSC1 Clock Input B OUT27 O1 GPTA0 Output 27 OUT51 O2 GPTA0 Output 51 SCLK1B O3 SSC1 Clock Output B P1.15 I/O0 BRKIN I Reserved O1 - Reserved O2 - Reserved O3 - BRKOUT O OCDS Break Output (controlled by OCDS module) P2.0 I/O0 IN32 I OUT32 O1 GPTA0 Output 32 TCLK0 O2 MLI0 Transmitter Clock Output 0 Reserved O3 - 77 93 A2/ PU A2/ PU Port 1 General Purpose I/O Line 10 GPTA0 Input 26 Port 1 General Purpose I/O Line 11 GPTA0 Input 27 Port 1 General Purpose I/O Line 15 OCDS Break Input Port 2 61 Data Sheet A2/ PU Port 2 General Purpose I/O Line 0 GPTA0 Input 32 60 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 62 P2.1 I/O0 IN33 I A2/ PU TREADY0A I MLI0 Transmitter Ready Input A OUT33 O1 GPTA0 Output 33 SLSO03 O2 SSC0 Slave Select Output Line 3 SLSO13 O3 SSC1 Slave Select Output Line 3 P2.2 I/O0 IN34 I OUT34 O1 GPTA0 Output 34 TVALID0 O2 MLI0 Transmitter Valid Output Reserved O3 - P2.3 I/O0 IN35 I OUT35 O1 GPTA0 Output 35 TDATA0 O2 MLI0 Transmitter Data Output Reserved O3 - P2.4 I/O0 IN36 I RCLK0A I MLI Receiver Clock Input A OUT36 O1 GPTA0 Output 36 OUT36 O2 GPTA0 Output 36 Reserved O3 - P2.5 I/O0 IN37 I OUT37 O1 GPTA0 Output 37 RREADY0A O2 MLI0 Receiver Ready Output A Reserved O3 - 63 64 65 66 Data Sheet A2/ PU A2/ PU A2/ PU A2/ PU Port 2 General Purpose I/O Line 1 GPTA0 Input 33 Port 2 General Purpose I/O Line 2 GPTA0 Input 34 Port 2 General Purpose I/O Line 3 GPTA0 Input 35 Port 2 General Purpose I/O Line 4 GPTA0 Input 36 Port 2 General Purpose I/O Line 5 GPTA0 Input 37 61 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 67 P2.6 I/O0 IN38 I A2/ PU RVALID0A I MLI Receiver Valid Input A OUT38 O1 GPTA0 Output 38 OUT38 O2 GPTA0 Output 38 Reserved O3 - P2.7 I/O0 IN39 I RDATA0A I MLI Receiver Data Input A OUT39 O1 GPTA0 Output 39 OUT39 O2 GPTA0 Output 39 Reserved O3 - P2.8 I/O0 SLSO04 O1 SLSO14 O2 SSC1 Slave Select Output 4 EN00 O3 MSC0 Enable Output 0 P2.9 I/O0 SLSO05 O1 SLSO15 O2 SSC1 Slave Select Output 5 EN01 O3 MSC0 Enable Output 1 P2.10 I/O0 MRST1A I MRST1A O1 SSC1 Slave Transmit Output Reserved O2 - Reserved O3 - P2.11 I/O0 SCLK1A I SCLK1A O1 SSC1 Clock Output A Reserved O2 - FCLP0B O3 MSC0 Clock Output Positive B 68 132 128 129 130 Data Sheet A2/ PU A2/ PU A2/ PU A2/ PU A2/ PU Port 2 General Purpose I/O Line 6 GPTA0 Input 38 Port 2 General Purpose I/O Line 7 GPTA0 Input 39 Port 2 General Purpose I/O Line 8 SSC0 Slave Select Output 4 Port 2 General Purpose I/O Line 9 SSC0 Slave Select Output 5 Port 2 General Purpose I/O Line 10 SSC1 Master Receive Input A Port 2 General Purpose I/O Line 11 SSC1 Clock Input A 62 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 131 P2.12 I/O0 MTSR1A I A2/ PU MTSR1A O1 SSC1 Master Transmit Output A Reserved O2 - SOP0B O3 MSC0 Serial Data Output Positive B P2.13 I/O0 SLSI11 I SDI0 I MSC0 Serial Data Input Reserved O1 - Reserved O2 - Reserved O3 - P3.0 I/O0 RXD0A I RXD0A O1 ASC0 Clock Output (Synch. Mode) RXD0A O2 ASC0 Clock Output (Synch. Mode) OUT84 O3 GPTA0 Output 84 P3.1 I/O0 TXD0 O1 TXD0 O2 ASC0 Transmitter Output OUT85 O3 GPTA0 Output 85 P3.2 I/O0 SCLK0 I SCLK0 O1 SSC0 Clock Output (Master Mode) SCLK0 O2 SSC0 Clock Output (Master Mode) OUT86 O3 GPTA0 Output 86 133 A1/ PU Port 2 General Purpose I/O Line 12 SSC1 Slave Receive Input A Port 2 General Purpose I/O Line 13 SSC1 Slave Select Input 1 Port 3 112 111 105 Data Sheet A1/ PU A1/ PU A2/ PU Port 3 General Purpose I/O Line 0 ASC0 Receiver Input A (Async. & Sync. Mode) Port 3 General Purpose I/O Line 1 ASC0 Transmitter Output Port 3 General Purpose I/O Line 2 SSC0 Clock Input (Slave Mode) 63 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 106 P3.3 I/O0 MRST0 I A2/ PU MRST0 O1 SSC0 Slave Transmit Output (Slave Mode) MRST0 O2 SSC0 Slave Transmit Output (Slave Mode) OUT87 O3 GPTA0 Output 87 P3.4 I/O0 MTSR0 I MTSR0 O1 SSC0 Master Transmit Output (Master Mode) MTSR0 O2 SSC0 Master Transmit Output (Master Mode) OUT88 O3 GPTA0 Output 88 P3.5 I/O0 SLSO00 O1 SLSO10 O2 108 102 A2/ PU A2/ PU P3.6 I/O0 SLSO01 O1 SLSO11 O2 104 Port 3 General Purpose I/O Line 4 SSC0 Slave Receive Input (Slave Mode) Port 3 General Purpose I/O Line 5 SSC0 Slave Select Output 0 SSC0 AND SSC1 Slave Select Output 0 A2/ PU Port 3 General Purpose I/O Line 6 SSC0 Slave Select Output 1 SSC1 Slave Select Output 1 SLSOANDO1 O3 107 SSC0 Master Receive Input (Master Mode) SSC1 Slave Select Output 0 SLSOANDO0 O3 103 Port 3 General Purpose I/O Line 3 SSC0 AND SSC1 Slave Select Output 1 P3.7 I/O0 SLSI01 I SLSO02 O1 SSC0 Slave Select Output 2 SLSO12 O2 SSC1 Slave Select Output 2 OUT89 O3 GPTA0 Output 89 P3.8 I/O0 SLSO06 O1 TXD1 O2 ASC1 Transmitter Output OUT90 O3 GPTA0 Output 90 Data Sheet A2/ PU A2/ PU Port 3 General Purpose I/O Line 7 SSC0 Slave Select Input 1 Port 3 General Purpose I/O Line 8 SSC0 Slave Select Output 6 64 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 114 P3.9 I/O0 RXD1A I A1/ PU RXD1A O1 ASC1 Receiver Output A (Synchronous Mode) RXD1A O2 ASC1 Receiver Output A (Synchronous Mode) OUT91 O3 GPTA0 Output 91 P3.10 I/O0 REQ0 I Reserved O1 - Reserved O2 - OUT92 O3 GPTA0 Output 92 P3.11 I/O0 REQ1 I Reserved O1 - Reserved O2 - OUT93 O3 GPTA0 Output 93 P3.12 I/O0 RXDCAN0 I RXD0B I ASC0 Receiver Input B RXD0B O1 ASC0 Receiver Output B (Synchronous Mode) RXD0B O2 ASC0 Receiver Output B (Synchronous Mode) OUT94 O3 GPTA0 Output 94 P3.13 I/O0 TXDCAN0 O1 TXD0 O2 ASC0 Transmitter Output OUT95 O3 GPTA0 Output 95 113 120 119 118 Data Sheet A1/ PU A1/ PU A1/ PU A2/ PU Port 3 General Purpose I/O Line 9 ASC1 Receiver Input A Port 3 General Purpose I/O Line 10 External Request Input 0 Port 3 General Purpose I/O Line 11 External Request Input 1 Port 3 General Purpose I/O Line 12 CAN Node 0 Receiver Input Port 3 General Purpose I/O Line 13 CAN Node 0 Transmitter Output 65 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 110 P3.14 I/O0 RXDCAN1 I A1/ PU RXD1B I ASC1 Receiver Input B RXD1B O1 ASC1 Receiver Output B (Synchronous Mode) RXD1B O2 ASC1 Receiver Output B (Synchronous Mode) OUT96 O3 GPTA0 Output 96 P3.15 I/O0 TXDCAN1 O1 TXD1 O2 ASC1 Transmitter Output OUT97 O3 GPTA0 Output 97 P4.2 I/O0 IN30 I IN54 I GPTA0 Input 54 OUT30 O1 GPTA0 Output 30 OUT54 O2 GPTA0 Output 54 EXTCLK1 O3 External Clock 1 Output P4.3 I/O0 IN31 I IN55 I GPTA0 Input 55 OUT31 O1 GPTA0 Output 31 OUT55 O2 GPTA0 Output 55 EXTCLK0 O3 External Clock 0 Output 109 A2/ PU Port 3 General Purpose I/O Line 14 CAN Node 1 Receiver Input Port 3 General Purpose I/O Line 15 CAN Node 1 Transmitter Output Port 4 72 73 Data Sheet A2/ PU A2/ PU Port 4 General Purpose I/O Line 2 GPTA0 Input 30 Port 4 General Purpose I/O Line 3 GPTA0 Input 31 66 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Symbol Ctrl. Type Function P5.0 I/O0 IN40 I A1/ PU OUT40 O1 GPTA0 Output 40 Reserved O2 - Reserved O3 - P5.1 I/O0 IN41 I OUT41 O1 GPTA0 Output 41 Reserved O2 - Reserved O3 - P5.2 I/O0 IN42 I OUT42 O1 GPTA0 Output 42 Reserved O2 - Reserved O3 - P5.3 I/O0 IN43 I OUT43 O1 GPTA0 Output 43 Reserved O2 - Reserved O3 - P5.4 I/O0 IN44 I OUT44 O1 GPTA0 Output 44 Reserved O2 - Reserved O3 - Port 5 1 2 3 4 7 Data Sheet A1/ PU A1/ PU A1/ PU A1/ PU Port 5 General Purpose I/O Line 0 GPTA0 Input 40 Port 5 General Purpose I/O Line 1 GPTA0 Input 41 Port 5 General Purpose I/O Line 2 GPTA0 Input 42 Port 5 General Purpose I/O Line 3 GPTA0 Input 43 Port 5 General Purpose I/O Line 4 GPTA0 Input 44 67 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 8 P5.5 I/O0 IN45 I A1/ PU OUT45 O1 GPTA0 Output 45 Reserved O2 - Reserved O3 - P5.6 I/O0 IN46 I OUT46 O1 GPTA0 Output 46 Reserved O2 - Reserved O3 - P5.7 I/O0 IN47 I OUT47 O1 GPTA0 Output 47 Reserved O2 - Reserved O3 - P5.8 I/O0 RDATA0B I Reserved O1 - Reserved O2 - Reserved O3 - P5.9 I/O0 RVALID0B I Reserved O1 - Reserved O2 - Reserved O3 - P5.10 I/O0 RREADY0B O1 Reserved O2 - Reserved O3 - 9 10 15 16 17 Data Sheet A1/ PU A1/ PU A2/ PU A2/ PU A2/ PU Port 5 General Purpose I/O Line 5 GPTA0 Input 45 Port 5 General Purpose I/O Line 6 GPTA0 Input 46 Port 5 General Purpose I/O Line 7 GPTA0 Input 47 Port 5 General Purpose I/O Line 8 MLI0 Receiver Data Input B Port 5 General Purpose I/O Line 9 MLI0 Receiver Data Valid Input B Port 5 General Purpose I/O Line 10 MLI0 Receiver Ready Input B 68 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 18 P5.11 I/O0 RCLK0B I A2/ PU Reserved O1 - Reserved O2 - Reserved O3 - P5.12 I/O0 TDATA0 O1 MLI0 Transmitter Data Output SLSO07 O2 SSC0 Slave Select Output 7 Reserved O3 - P5.13 I/O0 TVALID0B O1 SLSO16 O2 SSC1 Slave Select Output 6 Reserved O3 - P5.14 I/O0 TREADY0B I Reserved O1 - Reserved O2 - Reserved O3 - P5.15 I/O0 TCLK0 O1 Reserved O2 - Reserved O3 - P9.0 I/O0 Reserved O1 OUT80 O2 GPTA0 Output 80 Reserved O3 - 19 20 21 11 A2 A2/ PU A2/ PU A2/ PU Port 5 General Purpose I/O Line 11 MLI0 Receiver Clock Input B Port 5 General Purpose I/O Line 12 Port 5 General Purpose I/O Line 13 MLI0 Transmitter Valid Input B Port 5 General Purpose I/O Line 14 MLI0 Transmitter Ready Input B Port 5 General Purpose I/O Line 15 MLI0 Transmitter Clock Output Port 9 5 Data Sheet A1/ PU Port 9 General Purpose I/O Line 0 - 69 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 6 P9.1 I/O0 Reserved O1 A2/ PU OUT81 O2 GPTA0 Output 81 Reserved O3 - Port 9 General Purpose I/O Line 1 - Analog Input Port 57 AN0 I D Analog Input 0 56 AN1 I D Analog Input 1 55 AN2 I D Analog Input 2 54 AN3 I D Analog Input 3 53 AN4 I D Analog Input 4 52 AN5 I D Analog Input 5 51 AN6 I D Analog Input 6 34 AN7 I D Analog Input 7 50 AN8 I D Analog Input 8 49 AN9 I D Analog Input 9 48 AN10 I D Analog Input 10 47 AN11 I D Analog Input 11 46 AN12 I D Analog Input 12 45 AN13 I D Analog Input 13 40 AN14 I D Analog Input 14 39 AN15 I D Analog Input 15 38 AN16 I D Analog Input 16 37 AN19 I D Analog Input 19 36 AN23 I D Analog Input 23 35 AN25 I D Analog Input 25 33 AN28 I D Analog Input 28 32 AN29 I D Analog Input 29 31 AN30 I D Analog Input 30 30 AN31 I D Analog Input 31 44 VDDM - - ADC Analog Part Power Supply (3.3V - 5V) Data Sheet 70 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 43 VSSM VAREF0 VAGND0 VDDMF VDDAF VSSMF VSSAF VFAREF VFAGND VDD - - ADC Analog Part Ground - - ADC Reference Voltage - - ADC Reference Ground - - FADC Analog Part Power Supply (3.3V)2) - - FADC Analog Part Logic Power Supply (1.5V) - - FADC Analog Part Ground - - FADC Analog Part Ground - - FADC Reference Voltage - - FADC Reference Ground - - Digital Core Power Supply (1.5V) 13, VDDP 22, 59, 70, 79, 100, 115, 126, 139 - - Port Power Supply (3.3V) 14, VSS 24, 60, 69, 80, 101, 116, 127, 140 - - Digital Ground - - Main Oscillator and PLL Power Supply (1.5V) 42 41 26 25 27 28 29 12, 23,3) 58, 71, 78, 99, 125, 138 84 VDDOSC Data Sheet 71 V1.1, 2009-08 TC1736 Pinning Table 3-1 Pin Definitions and Functions (PG-LQFP-144-10 Package)1) (cont'd) Pin Symbol Ctrl. Type Function 85 - - Main Oscillator Power Supply (3.3V) - - Main Oscillator and PLL Ground 117 VDDOSC3 VSSOSC VDDFL3 - - Power Supply for Flash (3.3V) 81 XTAL1 I - Main Oscillator Input 82 XTAL2 O - Main Oscillator Output 87 TDI/BRKIN/ BRKOUT I/O A2/ PU JTAG Serial Data Input / OCDS Break Input / OCDS Break Output (controlled by OCDS module) 88 TMS/DAP1 I/O A2/ PD JTAG State Machine Control Input / Device Access Port Line 1 89 TDO/DAP2/ BRKIN/ BRKOUT I/O A2/ PU JTAG Serial Data Output / Device Access Port Line 2 / OCDS Break Input / OCDS Break Output (controlled by OCDS module) 90 TRST I A1/ PD JTAG Reset Input 91 TCK/DAP0 I A1/ PD JTAG Clock Input / Device Access Port Line 0 94 TESTMODE I PU Test Mode Select Input 96 ESR1 I/O A2/ PD External System Request Reset Input 1 97 PORST I PD Power On Reset Input (input pad with input spike-filter) 98 ESR0 I/O A2/ PD External System Request Reset Input 0 83 1) TC1736ED : PG-LQFP-144-10 2) This pin is also connected to the analog power supply for comparator of the ADC module. 3) For the emulation device (ED), this pin is bonded to VDDSB (ED Stand By RAM supply). In the non ED device, this pin is bonded to a VDD pad. Legend for Table 3-1 Column "Ctrl.": I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB) Data Sheet 72 V1.1, 2009-08 TC1736 Pinning O = Output O0 = Output with IOCR bit field selection PCx = 1X00B O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2) O3 = Output with IOCR bit field selection PCx = 1X11(ALT3) Column "Type": A1 = Pad class A1 (LVTTL) A2 = Pad class A2 (LVTTL) D = Pad class D (ADC) PU = with pull-up device connected during reset (PORST = 0) PD = with pull-down device connected during reset (PORST = 0) TR = tri-state during reset (PORST = 0) 3.2.1 Reset Behavior of the Pins Table 3-2 describes the pull-up/pull-down behavior of the System I/O pins during poweron reset. Table 3-2 List of Pull-up/Pull-down PORST Reset Behavior of the Pins Pins PORST = 0 PORST = 1 All GPIOs,TDI, TESTMODE Pull-up PORST, TRST, TCK, TMS Pull-down ESR0 The open-drain driver is Pull-up2) used to drive low.1) ESR1 Pull-down3) TDO Pull-up High-impedance 1) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details. 2) See the SCU_IOCR register description. 3) see the SCU_IOCR register description. Data Sheet 73 V1.1, 2009-08 TC1736 Identification Registers 4 Identification Registers The Identification Registers uniquely identify a module or the whole device. Table 4-1 TC1736 Identification Registers Short Name Value Address Stepping ADC0_ID 0058 C000H F010 1008H - ADC1_ID 0058 C000H F010 1408H - ASC0_ID 0000 4402H F000 0A08H - ASC1_ID 0000 4402H F000 0B08H - CAN_ID 002B C061H F000 4008H - CBS_JDPID 0000 6350H F000 0408H - CBS_JTAGID 1015 B083H F000 0464H - CPS_ID 0015 C007H F7E0 FF08H - CPU_ID 000A C006H F7E1 FE18H - DMA_ID 001A C004H F000 3C08H - DMI_ID 0008 C005H F87F FC08H - FADC_ID 0027 C003H F010 0408H - FLASH0_ID 0056 C001H F800 2008H - FPU_ID 0054 C003H F7E1 A020H - GPTA0_ID 0029 C005H F000 1808H - LBCU_ID 000F C005H F87F FE08H - LFI_ID 000C C006H F87F FF08H - MCHK_ID 001B C001H F010 C208H - MLI0_ID 0025 C007H F010 C008H - MSC0_ID 0028 C003H F000 0808H - PMI_ID 000B C005H F87F FD08H - PMU0_ID 0050 C001H F800 0508H - SBCU_ID 0000 6A0CH F000 0108H - SCU_CHIPID 0000 9201H F000 0640H - SCU_ID 0052 C001H F000 0508H - SCU_MANID 0000 1820H F000 0644H - SCU_RTID 0000 0000H F000 0648H AA-step Data Sheet 74 V1.1, 2009-08 TC1736 Identification Registers Table 4-1 TC1736 Identification Registers (cont'd) Short Name Value Address Stepping SSC0_ID 0000 4511H F010 0108H - SSC1_ID 0000 4511H F010 0208H - STM_ID 0000 C006H F000 0208H - Data Sheet 75 V1.1, 2009-08 TC1736 Electrical Parameters 5 Electrical Parameters 5.1 General Parameters 5.1.1 Parameter Interpretation The parameters listed in this section partly represent the characteristics of the TC1736 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column "Symbol": * * CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1736 and must be regarded for a system design. SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1736 designed in. Data Sheet 76 V1.1, 2009-08 TC1736 Electrical Parameters 5.1.2 Pad Driver and Pad Classes Summary This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the Section 18.2.1. Table 2 Pad Driver and Pad Classes Overview Leakage1) Termination Class Power Type Supply Sub Class Speed Load Grade A LVTTL I/O, LVTTL outputs A1 (e.g. GPIO) 6 MHz 100 pF 500 nA A2 (e.g. serial I/Os) 40 MHz 50 pF 6 A Series termination recommended ADC - - - - see Table 18-7 DE 3.3 V 5V No 1) Values are for TJmax = 150 C. Data Sheet 77 V1.1, 2009-08 TC1736 Electrical Parameters 5.1.3 Absolute Maximum Ratings Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > related VDD or VIN < VSS) the voltage on the related VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Table 3 Absolute Maximum Rating Parameters Parameter Symbol Values Min. Typ. Max. TA Storage temperature TST TJ Junction temperature Voltage at 1.5 V power supply VDD pins with respect to VSS1) Voltage at 3.3 V power supply VDDP pins with respect to VSS2) Voltage at 5 V power supply VDDM pins with respect to VSS Voltage on any Class A input VIN Ambient temperature Unit Note / Test Con dition SR -40 - 125 C Under bias SR -65 - 150 C - SR -40 - 150 C Under bias - - 2.25 V - SR - - 3.75 V - SR - - 5.5 V - VDDP + 0.5 V Whatever is lower SR SR -0.5 - pin and dedicated input pins with respect to VSS or max. 3.7 Voltage on any Class D analog input pin with respect to VAGND VAIN VAREFx Voltage on any Class D analog input pin with respect to VSSAF, if the FADC is switched through to the pin. VAINF VFAREF -0.5 - VDDM + 0.5 V - -0.5 - VDDM + 0.5 V - SR SR 1) Applicable for VDD, VDDOSC, VDDPLL, and VDDAF. 2) Applicable for VDDP, VDDFL3, and VDDMF. Data Sheet 78 V1.1, 2009-08 TC1736 Electrical Parameters 5.1.4 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1736. All parameters specified in the following table refer to these operating conditions, unless otherwise noted. Table 4 Operating Condition Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 1.42 - 1.582) V - 3.13 - 3.473) V For Class A pins (3.3 V 5%) 3.13 - 3.473) V - 3.13 - 3.473) V FADC 1.42 - 1.58 2) V FADC 4.75 - 5.25 V For Class DE pins, ADC SR 0 - - V - SR - -40 +125 C - - - - - See separate specification Page 18-12, Page 18-17 -1 - 3 mA 4) Sum of overload current |IOV| at class D pins - - 10 mA per single ADC Overload coupling KOVAP 5) factor for analog inputs K - - 5x10-5 0 < IOV < 3 mA - - 5x10-4 -1 mA < IOV < 0 Digital supply voltage1) VDD SR VDDOSC SR VDDP SR VDDOSC3 SR VDDFL3 SR Analog supply voltages VDDMF SR VDDAF SR VDDM SR Digital ground voltage Ambient temperature under bias VSS TA Analog supply voltages - Overload current at class D pins IOV OVAN CPU & LMB Bus Frequency fCPU SR - - 80 40 MHz Derivative dependent FPI Bus Frequency fSYS ISC SR - - 80 MHz 6) - +5 mA 6) Short circuit current Data Sheet SR -5 79 V1.1, 2009-08 TC1736 Electrical Parameters Table 4 Operating Condition Parameters Parameter Symbol Values Absolute sum of short circuit currents of a pin group (see Table 5) |ISC_PG| Inactive device pin current IID Absolute sum of short circuit currents of the device |ISC_D| External load capacitance CL Min. Typ. Max. Unit Note / Test Condition - - 20 mA See note - 1 mA All power supply voltages VDDx = 0 - - 100 mA See note4) - - - pF Depending on pin class. See DC characteristics SR SR -1 SR SR 1) Digital supply voltages applied to the TC1736 must be static regulated voltages which allow a typical voltage swing of 5%. 2) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 3) Voltage overshoot up to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 4) See additional document "TC1767 Pin Reliability in Overload" for definition of overload current on digital pins. 5) The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to the resulting leakage current (IleakTOT) into an adjacent pin: IleakTOT = kA x |IOV| + IOZ1. Thus under overload conditions an additional error leakage voltage (VAEL) will be induced onto an adjacent analog input pin due to the resistance of the analog input source (RAIN). That means VAEL = RAIN x |IleakTOT|. The definition of adjacent pins is related to their order on the silicon. The Injected leakage current always flows in the opposite direction from the causing overload current. Therefore, the total leakage current must be calculated as an algebraic sum of the both component leakage currents (the own leakage current IOZ1 and the optional injected leakage current). 6) Applicable for digital outputs. Data Sheet 80 V1.1, 2009-08 TC1736 Electrical Parameters Table 5 Pin Groups for Overload/Short-Circuit Current Sum Parameter Group Pins 1 P5.[14:8] 2 P2.[7:0] 3 P4.[3:2]; P1.[11:8] 4 P1.4; TDI/BRKIN/BRKOUT; TMS/DAP1; TDO/DAP2/BRKIN/BRKOUT; TRST, TCK/DAP0; P1.[1:0]; P1.15; TESTMODE; ESR0; PORST; ESR1 5 P3.[10:0]; P3.[15:14] 6 P3.[13:11]; P0.[3:0] 7 P2.[13:8]; P0.[5:4]; P0.[13:12] 8 P0.[7:6]; P0.[15:14]; P5.[7:0]; P5.15; P9.[1:0] Data Sheet 81 V1.1, 2009-08 TC1736 Electrical Parameters 5.2 DC Parameters 5.2.1 Input/Output Pins Table 6 Input/Output DC-Characteristics (Operating Conditions apply) Parameter Symbol Values Min. Typ. Max. 10 - Unit Note / Test Condition General Parameters Pull-up current1) |IPUH| 100 A CC |IPDL| Pull-down current1) Pin capacitance (Digital I/O) class A1/A2/Input pads. 10 - 150 A CC 1) CIO VIN < VIHAmin; VIN >VILAmax; class A1/A2/Input pads. - - 10 pF f = 1 MHz TA = 25 C CC Input only Pads (VDDP = 3.13 to 3.47 V = 3.3 V 5%) Input low voltage VILI -0.3 - 0.36 x V - - VDDP VDDP+ V Whatever is lower SR 0.62 x Input high voltage VIHI SR VDDP Ratio VIL/VIH CC 0.58 Input high voltage VIHJ 0.64 x TRST, TCK SR VDDP 0.1 x 0.3 or max. 3.6 - - - - - VDDP+ V Whatever is lower 0.3 or max. 3.6 - - V 4) - - 3000 6000 nA ((VDDP/2)-1) < VIN < ((VDDP/2)+1) Otherwise Spike filter always tSF1 - blocked pulse CC duration - 10 ns Input hysteresis HYSI CC VDDP Input leakage current2) Data Sheet IOZI CC 82 V1.1, 2009-08 TC1736 Electrical Parameters Table 6 Input/Output DC-Characteristics (cont'd)(Operating Conditions apply) Parameter Spike filter passthrough pulse duration Symbol tSF2 Values Min. Typ. Max. 100 - - Unit Note / Test Condition ns CC Class A Pads (VDDP = 3.13 to 3.47 V = 3.3V 5%) Output low voltage VOLA 2)3) Output high voltage2) 3) - - 0.4 V CC VOHA IOL = 2 mA for medium and strong driver mode, IOL = 500 A for weak driver mode 2.4 - - V CC IOH = -2 mA for medium and strong driver mode, IOH = -500 A for weak driver mode VDDP - - - V 0.4 IOH = -1.4 mA for medium and strong driver mode, IOH = -400 A for weak driver mode - 0.36 x V - Input high voltage VIHA1 0.62 x Class A1 pins SR VDDP - VDDP VDDP+ V Whatever is lower Ratio VIL/VIH - - - - Input high voltage VIHA2 0.60 x Class A2 pins SR VDDP - VDDP+ 0.3 or max. 3.6 V Whatever is lower Ratio VIL/VIH CC 0.60 - - - - Input hysteresis HYSA 0.1 x CC VDDP - - V 4) Input leakage current Class A2 pins IOZA2 - 3000 nA ((VDDP/2)-1) < VIN < ((VDDP/2)+1) Otherwise2) Input low voltage Class A1/2 pins Data Sheet VILA -0.3 SR SR 0.58 - 0.3 or max. 3.6 6000 83 V1.1, 2009-08 TC1736 Electrical Parameters Table 6 Input/Output DC-Characteristics (cont'd)(Operating Conditions apply) Parameter Input leakage current Class A1 pins Symbol IOZA1 Values Unit Note / Test Condition Min. Typ. Max. - - 500 nA 0 V <VIN < VDDP - - - - - CC Class D Pads See ADC Characteristics 1) Not subject to production test, verified by design / characterization. 2) Only one of these parameters is tested, the other is verified by design characterization 3) Maximum resistance of the driver RDSON, defined for P_MOS / N_MOS transistor separately: 25 / 20 for strong driver mode, IOH / L < 2 mA, 200 / 150 for medium driver mode, IOH / L < 400 uA, 600 / 400 for weak driver mode, IOH / L < 100 uA, verified by design / characterization. 4) Function verified by design, value verified by design characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. Data Sheet 84 V1.1, 2009-08 TC1736 Electrical Parameters 5.2.2 Analog to Digital Converters (ADC0/ADC1) All ADC parameters are optimized for and valid in the range of VDDM = 5V 5%. Table 7 ADC Characteristics (Operating Conditions apply) Parameter Symbol Values Min. Analog supply voltage Analog ground voltage Unit Note / Test Condition Typ. Max. 5 5.25 V - 3.13 3.3 3.471) V - VDD SR 1.42 1.5 1.582) V Power supply for ADC digital part, internal supply VSSM SR -0.1 - 0.1 V - V - VAREF - V - VDDM SR 4.75 Analog reference VAREFx SR VAGNDx+1 voltage14) V VDDM VDDM+ 0.05 1)3)4) Analog reference VAGNDx SR VSSMx ground14) 0.05V 1V SR VAGNDx - VAREFx V - Analog reference VAREFxVDDM/2 5)14) voltage range VAGNDx SR - VDDM + V 0.05 - Analog input voltage range VAIN 0 fADC SR 1 fADCI CC 0.5 - 80 MHz - - 10 MHz - tS CC 2 - 257 TADCI - Total unadjusted TUE6) CC - error5) - 4 LSB 12-bit conversion, without noise7)8) - - 2 LSB 10-bit conversion8) - - 1 LSB 8-bit conversion8) - 1.5 3.0 LSB 12-bit conversion without noise8)10) - 1.5 3.0 LSB 12-bit conversion without noise8)10) - 0.5 3.5 LSB 12-bit conversion without noise8)10) Converter Clock Internal ADC clocks Sample time DNL error9) 5) EADNL CC INL error9)5) EAINL CC 9)5) Gain error EAGAIN CC Data Sheet 85 V1.1, 2009-08 TC1736 Electrical Parameters Table 7 ADC Characteristics (cont'd) (Operating Conditions apply) Parameter Symbol 9)5) Offset error EAOFF Values Unit Note / Test Condition Min. Typ. Max. - 1.0 4.0 LSB 12-bit conversion without noise8)10) -300 - 100 nA (0% VDDM) < VIN < (3% VDDM) -100 - 200 nA (3% VDDM) < VIN < (97% VDDM) -100 - 300 nA (97% VDDM) < VIN < (100% VDDM) CC Input leakage IOZ1 CC current at analog inputs of ADC0/1 11) 12) 13) Input leakage current at VAREF0/1, per module IOZ2 CC - - 1.5 A 0 V < VAREF < VDDM, no conversion running Input current at VAREF0/114), per module IAREF CC - 35 75 A rms 0 V < VAREF < Total capacitance of the voltage reference inputs16)14) CAREFTOT Switched capacitance at the positive reference voltage input14) CAREFSW Resistance of the reference voltage input path16) RAREF Total capacitance of the analog inputs16) CAINTOT Data Sheet VDDM15) - 20 40 pF 8) - 15 30 pF 8)17) - 500 1000 500 Ohm increased for AN[1:0] used as reference input8) - 25 30 pF 6)8) CC CC CC CC 86 V1.1, 2009-08 TC1736 Electrical Parameters Table 7 ADC Characteristics (cont'd) (Operating Conditions apply) Parameter Switched capacitance at the analog voltage inputs Symbol CAINSW Unit Note / Test Condition Min. Typ. Max. - 7 20 pF 8)18) 700 1500 8) 550 90019) Test feature available only for AIN7 8) 20) 15 rms 30 peak mA Test feature available only for AIN78) CC ON resistance of RAIN the transmission gates in the analog voltage path ON resistance for the ADC test (pull-down for AIN7) Values CC - RAIN7T CC 180 Current through IAIN7T resistance for the ADC test (pulldown for AIN7) CC - 1) Voltage overshoot up to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 2) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 3) A running conversion may become inexact in case of violating the normal operating conditions (voltage overshoot). VAREF increases or the VDDM decreases, so that the reference voltage VAREF = (VDDM + 0.05 V to VDDM + 0.07 V), then the accuracy of the ADC decreases by 4 LSB12. 5) If a reduced reference voltage in a range of VDDM/2 to VDDM is used, then the ADC converter errors increase. 4) If If the reference voltage is reduced with the factor k (k<1), then TUE, DNL, INL Gain and Offset errors increase with the factor 1/k. If a reduced reference voltage in a range of 1 V to VDDM/2 is used, then there are additional decrease in the ADC speed and accuracy. 6) TUE is tested at VAREF = 5.0 V, VAGND = 0 V and VDDM = 5.0 V 7) ADC module capability. 8) Not subject to production test, verified by design / characterization. 9) The sum of DNL/INL/Gain/Offset errors does not exceed the related TUE total unadjusted error. 10) For 10-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with factor 0.25. For 8-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with 0.0625. 11) The leakage current definition is a continuous function, as shown in Figure 18-3. The numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function. Data Sheet 87 V1.1, 2009-08 TC1736 Electrical Parameters 12) Only one of these parameters is tested, the other is verified by design characterization. 13) The leakage current decreases typically 30% for junction temperature decrease of 10oC. 14) Applies to AINx, when used as auxiliary reference inputs. 15) IAREF_MAX is valid for the minimum specified conversion time. The current flowing during an ADC conversion with a duration of up to tC = 25s can be calculated with the formula IAREF_MAX = QCONV/tC. Every conversion needs a total charge of QCONV = 150pC from VAREF. All ADC conversions with a duration longer than tC = 25s consume an IAREF_MAX = 6A. 16) For the definition of the parameters see also Figure 18-2. 17) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this smaller capacitances are successively switched to the reference voltage. 18) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before the sampling moment. Because of the parasitic elements the voltage measured at AINx deviates from VAREF/2, and is typically 1.35V. 19) RAIN7T = 1400 Ohm maximum and 830 Ohm typical in the VDDM = 3.3V 5% range. 20) The DC current at the pin is limited to 3 mA for the operational lifetime. clock generation ADC kernel interrupts, etc. fADC divider for fADCI analog clock f ADCI registers analog part divider for f ADCD digital clock fADCD arbiter ADC_clocking Figure 1 Data Sheet ADC0/ADC1 Clock Circuit 88 V1.1, 2009-08 TC1736 Electrical Parameters Table 8 Conversion Time (Operating Conditions apply) Parameter Symbol Value Unit Note CC 2 x TADC + (4 + STC + n) x TADCI s tC Conversion time with post-calibration 2 x TADC + (2 + STC + n) x TADCI Conversion time without post-calibration REXT VAIN = n = 8, 10, 12 for n - bit conversion TADC = 1 / fADC TADCI = 1 / fADCI Analog Input Circuitry RAIN, On ANx CEXT CAINSW CAINTOT - CAINSW VAGNDx RAIN7T Reference Voltage Input Circuitry RAREF, On VAREFx VAREF CAREFTOT - CAREFSW CAREFSW VAGNDx Analog_InpRefDiag Figure 2 ADC0/ADC1 Input Circuits Io z 1 300nA 200nA 100nA -1 0 0 n A V IN [ V D D M % ] 3% 97% 100% -3 0 0 n A A D C L e a k a g e 1 0 .v s d Figure 3 Data Sheet ADC0/ADC1Analog Inputs Leakage 89 V1.1, 2009-08 TC1736 Electrical Parameters 5.2.3 Fast Analog to Digital Converter (FADC) All parameters apply to FADC used in differential mode, which is the default and the intended mode of operation, and which takes advantage of many error cancelation effects inherent to differential measurements in general. Table 9 FADC Characteristics (Operating Conditions apply) Parameter Symbol Values Min. DNL error INL error Gradient error9) Unit Note / Test Condition Typ. Max. - 1 LSB 9) - 4 LSB 9) - 5 % Without calibration gain 1, 2, 4 - - 6 % Without calibration gain 8 - - 203) mV With calibration1) CC - - 903) mV Without calibration - - 60 mV - - 3.474) V - - 1.585) V - - 0.1 V - - 3.474)6) V Nominal 3.3 V EFDNL CC - EFINL CC - - EFGRAD CC Offset error9)1) EFOFF2) Reference error of internal VFAREF/2 EFREF Analog supply voltages VDDMF SR 3.13 VDDAF SR 1.42 -0.1 VSSAF Analog ground voltage CC SR Analog reference voltage VFAREF Analog reference ground VFAGND 3.13 SR VSSAF + V 0.05 V - VDDMF V - - 10 mA - - 10 mA 7) - 120 A rms Independent of conversion Input leakage current IFOZ2 - 8) at VFAREF CC - 500 nA 0 V < VIN < VDDMF - Input leakage current IFOZ3 CC at VFAGND8) - 8 A 0 V < VIN < VDDMF Analog input voltage VAINF range Analog supply currents Input current at VFAREF Data Sheet VSSAF - - SR 0.05 V VFAGND - SR IDDMF SR - IDDAF SR - - IFAREF CC 90 V1.1, 2009-08 TC1736 Electrical Parameters Table 9 FADC Characteristics (Operating Conditions apply) (cont'd) Parameter Symbol Values Min. Conversion time tC_FADC CC - Unit Note / Test Condition CLK of For 10-bit conv. Typ. Max. - 21 fFADC Converter clock Input resistance of the analog voltage path (Rn, Rp) fFADC SR 10 100 RFAIN - 80 MHz - - 200 k 9) 2 - - MHz - CC - - 5 s - CC Channel amplifier cutoff frequency9) fCOFF Settling time of a channel amplifier (after changing channel amplifier input)9) tSET CC 1) Calibration should be performed at each power-up. In case of continuous operation, calibration should be performed minimum once per week, or on regular basis in order to compensate for temperature changes. 2) The offset error voltage drifts over the whole temperature range maximum 6 LSB. 3) Applies when the gain of the channel equals one. For the other gain settings, the offset error increases; it must be multiplied with the applied gain. 4) Voltage overshoots up to 4 V are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 5) Voltage overshoots up to 1.7 V are permissible, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 6) A running conversion may become inexact in case of violating the normal operating conditions (voltage overshoots). 7) Current peaks of up to 40 mA with a duration of max. 2 ns may occur 8) This value applies in power-down mode. 9) Not subject to production test, verified by design / characterization. The calibration procedure should run after each power-up, when all power supply voltages and the reference voltage have stabilized. Data Sheet 91 V1.1, 2009-08 TC1736 Electrical Parameters FADC Analog Input Stage RN FAINxN VFAREF /2 = VFAGND + + RP FAINxP - FADC Reference Voltage Input Circuitry VFAREF IFAREF VFAREF VFAGND FADC_InpRefDiag Figure 4 Data Sheet FADC Input Circuits 92 V1.1, 2009-08 TC1736 Electrical Parameters 5.2.4 Table 10 Oscillator Pins Oscillator Pins Characteristics (Operating Conditions apply) Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. Frequency range fOSC CC 8 - 25 MHz External Crystal Mode selected Input low voltage at XTAL11) VILX SR -0.2 - 0.3 x V - Input high voltage at XTAL11) VIHX SR 0.7 x - VDDOSC3 IIX1 CC - - VDDOSC3 VDDOSC3 V - Input current at XTAL1 + 0.2 25 A 0 V < VIN < VDDOSC3 1) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3 x VDDOSC3 is sufficient. Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Refer to the limits specified by the crystal supplier. 5.2.5 Table 11 Temperature Sensor Temperature Sensor Characteristics (Operating Conditions apply) Parameter Symbol Temperature sensor range TSR SR Values Unit Note / Test Condition Min. Typ. Max. -40 150 C Junction temperature Temperature sensor measurement time tTSMT SR - - 100 s - Start-up time after reset tTSST SR TTSA CC - - 10 s - - - 6 C Calibrated Sensor accuracy Data Sheet 93 V1.1, 2009-08 TC1736 Electrical Parameters The following formula calculates the temperature measured by the DTS in [oC] from the RESULT bitfield of the DTSSTAT register. (1) DTSSTAT RESULT - 619 Tj = -----------------------------------------------------------------2, 28 Data Sheet 94 V1.1, 2009-08 TC1736 Electrical Parameters 5.2.6 Power Supply Current The default test conditions (differences explicitly specified) are: VDD = 1.58 V, VDDP = 3.47 V, Tj=150oC. All other operating conditions apply. Table 12 Power Supply Currents, Maximum Power Consumption Parameter Symbol Values Min. Typ. Max. Core active mode supply current 1) 2) IDD Unit Note / Test Condition CC - - 250 mA - - 150 mA Realistic core active mode supply current 3)4) fCPU=80 MHz fCPU/fSYS = 1:1 VDD = 1.53 V, TJ = 150oC FADC 3.3 V analog supply current IDDMF CC - - 10 mA - FADC 1.5 V analog supply current IDDAF CC - - 10 mA - 4) Flash memory 3.3 V supply current IDDFL3R CC - - 60 mA continuously reading the Flash memory 5) IDDFL3E CC - - 61 mA Flash memory erase-verify6) - - 3 mA - 4) - - 10 mA - 4) - - 14 mA - 4) 7) - - 34 mA IDDP including Data Flash programming current 4) 8) CC - 2 3 mA ADC0 / 1 800 mW worst case TA = 125oC, PD x RJA < 25oC Oscillator 1.5 V supply Oscillator 3.3 V supply Pad currents,sum of VDDP 3.3 V supplies ADC 5 V power supply Maximum Average Power Dissipation1) IDDOSC CC IDDOSC3 CC IDDP CC IDDP_FP CC IDDM PD SR - 1) Infineon Power Loop: CPU running, all peripherals active. The power consumption of each custom application will most probably be lower than this value, but must be evaluated separately. 2) The IDD maximum value is 190 mA at fCPU = 40 MHz, constant TJ = 150oC, for the Infineon Max Power Loop. The dependency in this range is, at constant junction temperature, linear. fCPU/fSYS = 1:1 mode. 3) The IDD maximum value is 110 mA at fCPU = 40 MHz, constant TJ = 150oC, for the Realistic Pattern. The dependency in this range is, at constant junction temperature, linear. fCPU/fSYS = 1:1 mode. Data Sheet 95 V1.1, 2009-08 TC1736 Electrical Parameters 4) Not tested in production separately, verified by design / characterization. 5) This value assumes worst case of reading flash line with all cells erased. In case of 50% cells written with "1" and 50% cells written with "0", the maximum current drops down to 53 mA. 6) Relevant for the power supply dimensioning, not for thermal considerations. In case of erase of Data Flash, internal flash array loading effects may generate transient current spikes of up to 15 mA for maximum 5 ms. 7) No GPIO activity 8) This value is relevant for the power supply dimensioning not for thermal considerations. The currents caused by the GPIO activity depend on the particular application and should be added separately. Data Sheet 96 V1.1, 2009-08 TC1736 Electrical Parameters 5.3 AC Parameters All AC parameters are defined with the temperature compensation disabled. That means, keeping the pads constantly at maximum strength. 5.3.1 Testing Waveforms VD D P 90% 90% 10% 10% VSS tR tF rise_fall_vddp.vsd Figure 5 Rise/Fall Time Parameters VD D P VD D P / 2 Test Points VD D P / 2 VSS mct04881_vddp.vsd Figure 6 Testing Waveform, Output Delay VLoad+ 0.1 V VLoad- 0.1 V Timing Reference Points VOH - 0.1 V VOL - 0.1 V MCT04880_new Figure 7 Data Sheet Testing Waveform, Output High Impedance 97 V1.1, 2009-08 TC1736 Electrical Parameters 5.3.2 Output Rise/Fall Times Table 13 Output Rise/Fall Times (Operating Conditions apply) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Class A1 Pads Rise/fall times1) tRA1, tFA1 - - 50 ns 140 18000 150 550 65000 Regular (medium) driver, 50 pF Regular (medium) driver, 150 pF Regular (medium) driver, 20 nF Weak driver, 20 pF Weak driver, 150 pF Weak driver, 20 000 pF - 3.7 ns 7.5 7 18 50 140 18000 150 550 65000 Strong driver, sharp edge, 50 pF Strong driver, sharp edge, 100pF Strong driver, med. edge, 50 pF Strong driver, soft edge, 50 pF Medium driver, 50 pF Medium driver, 150 pF Medium driver, 20 000 pF Weak driver, 20 pF Weak driver, 150 pF Weak driver, 20 000 pF Class A2 Pads Rise/fall times 1) tRA2, tFA2 - 1) Not all parameters are subject to production test, but verified by design/characterization and test correlation. Data Sheet 98 V1.1, 2009-08 TC1736 Electrical Parameters 5.3.3 Power Sequencing V +-5% 5V VAREF +-5% 3.3V +-5% 1.5V -12% 0.5V -12% 0.5V 0.5V t VDDP PORST power down power fail t Power-Up 8.vsd Figure 8 5 V / 3.3 V / 1.5 V Power-Up/Down Sequence The following list of rules applies to the power-up/down sequence: All ground pins VSS must be externally connected to one single star point in the system. Regarding the DC current component, all ground pins are internally directly connected. 1. At any moment, each power supply must be higher than any lower_power_supply - 0.5 V, or: VDD5 > VDD3.3 - 0.5 V; VDD5 > VDD1.5 - 0.5 V;VDD3.3 > VDD1.5 - 0.5 V, see Figure 18-8. 2. During power-up and power-down, the voltage difference between the power supply pins of the same voltage (3.3 V, 1.5 V, and 5 V) with different names (for example VDDP, VDDFL3 ...), that are internaly connected via diodes must be lower than 100 mV. On the other hand, all power supply pins with the same name (for example all VDDP ), are internaly directly connected. It is recommended that the power pins of the same voltage are driven by a single power supply. * Data Sheet 99 V1.1, 2009-08 TC1736 Electrical Parameters 3. The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.5, and VAREF powersupplies and the oscillator have reached stable operation, within the normal operating conditions. 4. At normal power down the PORST signal should be activated within the normal operating range, and then the power supplies may be switched off. Care must be taken that all Flash write or delete sequences have been completed. 5. At power fail the PORST signal must be activated at latest when any 3.3 V or 1.5 V power supply voltage falls 12% below the nominal level. The same limit of 3.3 V-12% applies to the 5 V power supply too. If, under these conditions, the PORST is activated during a Flash write, only the memory row that was the target of the write at the moment of the power loss will contain unreliable content. In order to ensure clean power-down behavior, the PORST signal should be activated as close as possible to the normal operating voltage range. 6. In case of a power-loss at any power-supply, all power supplies must be powereddown, conforming at the same time to the rules number 2 and 4. 7. Although not necessary, it is additionally recommended that all power supplies are powered-up/down together in a controlled way, as tight to each other as possible. 8. Aditionally, regarding the ADC reference voltage VAREF: - VAREF must power-up at the same time or later than VDDM, and - VAREF must power-down eather earlier or at latest to satisfy the condition VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF filter capacitance through the ESD diodes through the VDDM power supply. In case of discharging the reference capacitance through the ESD diodes, the current must be lower than 5 mA. Data Sheet 100 V1.1, 2009-08 TC1736 Electrical Parameters 5.3.4 Table 14 Power, Pad and Reset Timing Power, Pad and Reset Timing Parameters Parameter Symbol Values Min. Min. VDDP voltage to ensure defined pad states1) VDDPPA CC 0.6 Typ. Max. Unit Note / Test Condition - - V - Oscillator start-up time2) tOSCS CC - - 10 ms - Minimum PORST active tPOA time after power supplies are stable at operating levels SR 10 - - ms - ESR0 pulse width tHD CC program - mable3)5) - fSYS - PORST rise time tPOR tPOS SR - - 50 ms - SR 0 - - ns - Hold time from PORST rising edge tPOH SR 100 - - ns TESTMODE TRST Setup time to ESR0 rising edge tHDS SR 0 - - ns - Hold time from ESR0 rising edge tHDH SR 16 x 1/fSYS5) - - ns HWCFG Ports inactive after PORST reset active6)7) tPIP CC - - 150 ns - Ports inactive after ESR0 reset active (and for all logic) tPI CC - - 8x ns 1/fSYS - Power on Reset Boot Time8) tBP CC - - 2.5 ms - Application Reset Boot Time9) tB CC 150 - 960 s 1.7 ms fCPU=80MHz fCPU=40MHz Setup time to PORST rising edge4) 1) This parameter is valid under assumption that PORST signal is constantly at low level during the powerup/power-down of the VDDP. Data Sheet 101 V1.1, 2009-08 TC1736 Electrical Parameters 2) tOSCS is defined from the moment when VDDOSC3 = 3.13 V until the oscillations reach an amplitude at XTAL1 of 0,3 x VDDOSC3. This parameter is verified by device characterization. The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystal suppliers. 3) Any ESR0 activation is internally prolonged to SCU_RSTCNTCON.RELSA FPI bus clock (fFPI) cycles. 4) Applicable for input pins TESTMODE and TRST pins. 5) fFPI = fCPU / 2 6) Not subject to production test, verified by design / characterization. 7) This parameter includes the delay of the analog spike filter in the PORST pad. 8) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first user instruction has entered the CPU and its processing starts. 9) The duration of the boot time is defined between the following events: 1. Hardware reset: the falling edge of a short ESR0 pulse and the moment when the first user instruction has entered the CPU and its processing starts, if the ESR0 pulse is shorter than SCU_RSTCNTCON.RELSA x TFPI. If the ESR0 pulse is longer than SCU_RSTCNTCON.RELSA x TFPI, only the time beyond it should be added to the boot time (ESR0 falling edge to first user instruction). 2. Software reset: the moment of starting the software reset and the moment when the first user instruction has entered the CPU and its processing starts VD D P -12% V D D PPA V D D PPA VDDP VDD VD D -12% tPOA tPOA PORST tPOH TRST TESTMODE tPOH t hd t hd ESR0 tHDH tHDH tHDH HWCFG t PIP tPI t PIP tPI Pads tPI tPI t PIP tPI Pad-state undefined Tri-state or pull device active reset_beh2 As programmed Figure 9 Data Sheet Power, Pad and Reset Timing 102 V1.1, 2009-08 TC1736 Electrical Parameters 5.3.5 Phase Locked Loop (PLL) Note: All PLL characteristics defined on this and the next page are not subject to production test, but verified by design characterization. Table 15 PLL Parameters (Operating Conditions apply) Parameter Symbol |Dm| VCO frequency range fVCO VCO input frequency range fREF fPLLBASE PLL base frequency1) PLL lock-in time tL Accumulated jitter Values Min. Typ. Max. Unit Note / Test Con dition - - 7 ns 400 - 800 MHz - 8 - 16 MHz - 50 200 320 MHz - - - 200 s - - 1) The CPU base frequency with which the application software starts after PORST is calculated by dividing the limit values by 16 (this is the K2 factor after reset). Phase Locked Loop Operation When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMBBus clock fLMB) is constantly adjusted to the selected frequency. The PLL is constantly adjusting its output frequency to correspond to the input frequency (from crystal or clock source), resulting in an accumulated jitter that is limited. This means that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle. This is especially important for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in [ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the number m of consecutive fLMB clock periods. for ( K2 100 ) ( m ( f LMB [ MHz ] ) 2 ) and ( 1 - 0, 01 x K2 ) x ( m - 1 ) 740 - + 5 x ---------------------------------------------------------------- + 0, 01 x K2 D m [ ns ] = ------------------------------------------- 0, 5 x f LMB [ MHz ] - 1 K2 x f LMB [ MHz ] else Data Sheet 740 -+5 D m [ ns ] = -------------------------------------------K2 x f LMB [ MHz ] 103 (2) (3) V1.1, 2009-08 TC1736 Electrical Parameters With rising number m of clock cycles the maximum jitter increases linearly up to a value of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock frequency fLMB results in a higher absolute maximum jitter value. Figure 18-10 gives the jitter curves for several K2 / fLMB combinations. 10.0 Dm ns fLMB = 40 MHz (K2 = 10) fLMB = 40 MHz (K2 = 20) 8.0 7.0 6.0 4.0 fLMB = 80 MHz (K2 = 6) fLMB = 80 MHz (K2 = 10) 2.0 1.0 0.0 0 20 40 60 Dm = Max. jitter m = Number of consecutive fLMB periods K2 = K2-divider of PLL Figure 10 80 100 120 oo m TC1736_PLL_JITT Approximated Maximum Accumulated PLL Jitter for Typical LMBBus Clock Frequencies fLMB Note: The specified PLL jitter values are valid if the capacitive load per output pin does not exceed CL = 20 pF with the maximum driver and sharp edge. In case of applications with many pins with high loads, driver strengths and toggle rates the specified jitter values could be exceeded. Note: The maximum peak-to-peak noise on the pad supply voltage, measured between VDDOSC3 at pin 85 and VSSOSC at pin 83, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. The maximum peak-to peak noise on the pad supply votage, measured between VDDOSC at pin 84 and VSSOSC at pin 83, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. Data Sheet 104 V1.1, 2009-08 TC1736 Electrical Parameters These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Data Sheet 105 V1.1, 2009-08 TC1736 Electrical Parameters 5.3.6 JTAG Interface Timing The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 16 JTAG Interface Timing Parameters (Operating Conditions apply) Parameter Min. Typ. Max. Unit Note / Test Condition t1 SR t2 SR t3 SR t4 SR t5 SR t6 SR 25 - - ns - 12 - - ns - 10 - - ns - - - 4 ns - - - 4 ns - 6 - - ns - t7 SR 6 - - ns - TDO valid after TCK falling t8 CC edge1) (propagation delay) t CC 8 - - 13 ns CL = 50 pF - - 3 ns CL = 20 pF TDO hold after TCK falling t18 CC edge1) 2 - - ns TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time TDI/TMS setup to TCK rising edge TDI/TMS hold after TCK rising edge Symbol Values TDO high imped. to valid from TCK falling edge1)2) t9 CC - - 14 ns CL = 50 pF TDO valid to high imped. from TCK falling edge1) t10 CC - - 13.5 ns CL = 50 pF 1) The falling edge on TCK is used to generate the TDO timing. 2) The setup time for TDO is given implicitly by the TCK cycle time. Data Sheet 106 V1.1, 2009-08 TC1736 Electrical Parameters t1 0.9 VD D P 0.5 VD D P t5 t2 0.1 VD D P t4 t3 MC_ JTAG_ TCK Figure 11 Test Clock Timing (TCK) TCK t6 t7 t6 t7 TMS TDI t9 t8 t1 0 TDO t18 MC_JTAG Figure 12 Data Sheet JTAG Timing 107 V1.1, 2009-08 TC1736 Electrical Parameters 5.3.7 DAP Interface Timing The following parameters are applicable for communication through the DAP debug interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 17 DAP Interface Timing Parameters (Operating Conditions apply) Parameter Symbol t11 SR t12 SR t13 SR t14 SR t15 SR t16 SR DAP0 clock period DAP0 high time DAP0 low time DAP0 clock rise time DAP0 clock fall time DAP1 setup to DAP0 rising edge Values Min. Typ. Max. Unit Note / Test Condition 12.5 - - ns - 4 - - ns - 4 - - ns - - - 2 ns - - - 2 ns - 6 - - ns - DAP1 hold after DAP0 rising edge t17 SR 6 - - ns - DAP1 valid per DAP0 clock period1) t19 SR 8 - - ns 80 MHz, CL = 20 pF t19 SR 10 - - ns 40 MHz, CL = 50 pF 1) The Host has to find a suitable sampling point by analyzing the sync telegram response. t11 0.9 VD D P 0.5 VD D P t1 5 t1 2 t14 0.1 VD D P t1 3 MC_DAP0 Figure 13 Data Sheet Test Clock Timing (DAP0) 108 V1.1, 2009-08 TC1736 Electrical Parameters DAP0 t1 6 t1 7 DAP1 MC_ DAP1_RX Figure 14 DAP Timing Host to Device t1 1 DAP1 t1 9 MC_ DAP1_TX Figure 15 Data Sheet DAP Timing Device to Host 109 V1.1, 2009-08 TC1736 Electrical Parameters 5.3.8 Peripheral Timings Note: Peripheral timing parameters are not subject to production test. They are verified by design / characterization. 5.3.8.1 Micro Link Interface (MLI) Timing MLI Transmitter Timing t13 t14 t10 t12 TCLKx t11 t15 t15 TDATAx TVALIDx t16 t17 TREADYx MLI Receiver Timing t23 t24 t20 t22 RCLKx t21 t25 t26 RDATAx RVALIDx t27 t27 RREADYx MLI_Tmg_2.vsd Figure 16 MLI Interface Timing Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx. Data Sheet 110 V1.1, 2009-08 TC1736 Electrical Parameters Table 18 MLI Transmitter/Receiver Timing (Operating Conditions apply), CL = 50 pF Parameter Symbol Values Min. Typ. Max. Unit Note / Test Co ndition - - ns MLI Transmitter Timing TCLK clock period TCLK high time TCLK low time TCLK rise time TCLK fall time TDATA/TVALID output delay time t10 t11 t12 t13 t14 t15 CC 2 x TMLI 1) 0.45 x t10 0.5 x t10 0.55 x t10 ns 2)3) CC 0.45 x t10 0.5 x t10 0.55 x t10 ns 2)3) CC - 4) ns - CC - - 4) ns - CC -3 - 4.4 ns - CC - TREADY setup time to TCLK rising edge t16 SR 18 - - ns - TREADY hold time from TCLK rising edge t17 SR 0 - - ns - t20 t21 t22 t23 t24 t25 SR 1 x TMLI - - ns 1) SR - 0.5 x t20 - ns 5)6) SR - 0.5 x t20 - ns 5)6) SR - - 4 ns 7) SR - - 4 ns 7) SR 4.2 - - ns - RDATA/RVALID hold time t26 from RCLK rising edge SR 2.2 - - ns - RREADY output delay time t27 CC 0 - 16 ns - MLI Receiver Timing RCLK clock period RCLK high time RCLK low time RCLK rise time RCLK fall time RDATA/RVALID setup time to RCLK falling edge 1) TMLImin. = TSYS = 1/fSYS. When fSYS = 80 MHz, t10 = 25 ns and t20 = 12.5 ns. 2) The following formula is valid: t11 + t12 = t10 3) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be regarded additionally to t11/t12. 4) For high-speed MLI interface, strong driver sharp edge selection (class A2 pad) is recommended for TCLK. 5) The following formula is valid: t21 + t22 = t20 6) The min. and max. value of is parameter can be adjusted by considering the other receiver timing parameters. Data Sheet 111 V1.1, 2009-08 TC1736 Electrical Parameters 7) The RCLK max. input rise/fall times are best case parameters for fSYS = 80 MHz. For reduction of EMI, slower input signal rise/fall times can be used for longer RCLK clock periods. 5.3.8.2 Micro Second Channel (MSC) Interface Timing Table 19 MSC Interface Timing (Operating Conditions apply), CL = 50 pF Parameter Symbol Values Min. FCLP clock period1)2) SOP/ENx outputs delay from FCLP rising edge SDI bit time SDI rise time SDI fall time Typ. Unit Note / Test Con dition Max. t40 t45 CC 2 x TMSC3) - - ns - CC -10 10 ns - t46 t48 t49 CC 8 x TMSC - ns - SR 100 ns - SR 100 ns - 1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times. 2) FCLP signal high and low can be minimum 1 x TMSC. 3) TMSCmin = TSYS = 1/fSYS. When fSYS = 80 MHz, t40 = 25 ns t40 0.9 VDDP 0.1 VDDP FCLP t45 t45 SOP EN t48 t49 0.9 VDDP 0.1 VDDP SDI t46 t46 MSC_Tmg_1.vsd Figure 17 MSC Interface Timing Note: Sample the data at SOP with the falling edge of FCLP in the target device. Data Sheet 112 V1.1, 2009-08 TC1736 Electrical Parameters 5.3.8.3 Table 20 SSC Master / Slave Mode Timing SSC Master/Slave Mode Timing (Operating Conditions apply), CL = 50 pF Parameter Symbol Values Min. Typ. Max. Unit Note / Test Con dition Master Mode Timing t50 t51 CC 2 x TSSC - - ns 1)2)3) CC 0 - 8 ns - MRST setup to SCLK falling edge t52 SR 13 - - ns 3) MRST hold from SCLK falling edge t53 SR 0 - - ns 3) t54 SR 4 x TSSC t55/t54 SR 45 t56 SR TSSC + 5 - - ns 1)3) - 55 % - - - ns 3)4) MTSR hold from SCLK latching edge t57 SR TSSC + 5 - - ns 3)4) SLSI setup to first SCLK latching edge t58 SR TSSC + 5 - - ns 3) SLSI hold from last SCLK latching edge t59 SR 7 - - ns - MRST delay from SCLK shift edge t60 CC 0 - 15 ns - SLSI to valid data on MRST t61 CC - - 10 ns - SCLK clock period MTSR/SLSOx delay from SCLK rising edge Slave Mode Timing SCLK clock period SCLK duty cycle MTSR setup to SCLK latching edge 1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times. 2) SCLK signal high and low times can be minimum 1 x TSSC. 3) TSSCmin = TSYS = 1/fSYS. When fSYS = 80 MHz, t50 = 25 ns. 4) Fractional divider switched off, SSC internal baud rate generation used. Data Sheet 113 V1.1, 2009-08 TC1736 Electrical Parameters t50 SCLK1)2) t51 t51 MTSR1) t52 t53 Data valid MRST1) t51 SLSOx2) 1) This timing is based on the following setup: CON.PH = CON.PO = 0. 2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK high pulse is in the first one of a transmission. SSC_TmgMM Figure 18 SSC Master Mode Timing t54 First latching SCLK edge First shift SCLK edge SCLK1) t55 t56 Last latching SCLK edge t55 t56 t57 Data valid MTSR1) t57 Data valid t60 t60 MRST1) t61 SLSI t59 t58 1) This timing is based on the following setup: CON.PH = CON.PO = 0. SSC_TmgSM Figure 19 Data Sheet SSC Slave Mode Timing 114 V1.1, 2009-08 TC1736 Electrical Parameters 5.4 Package and Reliability 5.4.1 Package Parameters Table 21 Thermal Parameters (Operating Conditions apply) Device Package RJCT1) RJCB1) RJLeads1) Unit TC1736 PG-LQFP-144-10 8.0 7.5 34.0 Note K/W 1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ = TA + RTJA x PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances. Thermal resistances as measured by the `cold plate method' (MIL SPEC-883 Method 1012.1). Data Sheet 115 V1.1, 2009-08 TC1736 Electrical Parameters 0.5 H 7 MAX. +0.08 0.12 -0.03 1.6 MAX. Package Outline 0.10.05 1.4 0.05 5.4.2 0.6 0.15 0.22 0.05 2) 0.08 C 17.5 0.08 M A-B D C 144x 22 20 0.2 A-B D 144x 1) 0.2 A-B D H 4x 22 B 20 A 1) D 144 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Does not include dambar protrusion of 0.08 max. per side Figure 20 GPP09243 PG-LQFP-144-10, Plastic Thin Quad Flat Package You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Data Sheet 116 V1.1, 2009-08 TC1736 Electrical Parameters 5.4.3 Flash Memory Parameters The data retention time of the TC1736's Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table 22 Flash Parameters Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. Program Flash Retention Time, Physical Sector1)2) tRET CC 20 - - years Max. 1000 erase/program cycles Program Flash Retention Time Logical Sector1)2) tRETL CC 20 - - years Max. 100 erase/program cycles Data Flash Endurance per 16 KB Sector NE - - cycles Max. data retention time 5 years Data Flash Endurance, NE8 CC 120000 - EEPROM Emulation (4 x 8 KB) - cycles Max. data retention time 5 years CC 30 000 tPR CC - - 5 ms - Program Flash Erase tERP CC - Time per 256-KB Sector - 5 s fCPU = 80 MHz Data Flash Erase Time tERD CC - for 2 x 16-KB Sector - 1.25 s fCPU = 80 MHz tWU CC - - 4000/fCPU s +180 Programming Time per Page3) Wake-up time - 1) Storage and inactive time included. 2) At average weighted junction temperature Tj = 100oC, or the retention time at average weighted temperature of Tj = 110oC is minimum 10 years, or the retention time at average weighted temperature of Tj = 150oC is minimum 0.7 years. 3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The reprogramming takes additional 5 ms. Data Sheet 117 V1.1, 2009-08 TC1736 Electrical Parameters 5.4.4 Table 23 Quality Declarations Quality Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 24000 hours -2) 3) ESD susceptibility VHBM according to Human Body Model (HBM) - - 2000 V Conforming to JESD22-A114-B ESD susceptibility VCDM according to Charged Device Model (CDM) - - 500 V Conforming to JESD22-C101-C Moisture Sensitivity Level - - 3 - Conforming to Jedec J-STD-020C for 240C Operation Lifetime1) tOP MSL 1) This lifetime refers only to the time when the device is powered on. 2) For worst-case temperature profile equivalent to: 2000 hours at Tj = 150oC 16000 hours at Tj = 125oC 6000 hours at Tj = 110oC 3) This 30000 hours worst-case temperature profile is also covered: 300 hours at Tj = 150oC 1000 hours at Tj = 140oC 1700 hours at Tj = 130oC 24000 hours at Tj = 120oC 3000 hours at Tj = 110oC Data Sheet 118 V1.1, 2009-08 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG