6
SCDCT2512PCB Rev A
48 17 DB10 Bidirectional parallel data bus bit 10.
49 19 DB12 Bidirectional parallel data bus bit 12.
50 21 DB14 Bidirectional parallel data bus bit 14.
51 23 VL+5 Volt input power supply connection for RTU digital logic section.
52 25 GND Power supply return for RTU digital logic section.
53 27 ADDRD Input of the 2nd MSB of the assigned terminal address.
54 29 ADDRB Input of the 2nd LSB of the assigned terminal address.
55 31 ADDRP Input of address parity bit. The combination of assigned terminal address and ADDRP
must be odd parity for the RT to work.
56 33 TXDATAOUT B HIGH, output to the primary side of the coupling transformer that connects to the B
channel of the 1553 bus.
57 35 VEEB-12 / -15 Volt input power supply connection for the B channel transceiver. (See note 7).
58 37 VLB +5 Volt input power supply connection for the B channel transceiver.
59 39 RXDATAIN B Input from the LOW side of primary side of the coupling transformer that connects to the
B channel of the 1553 bus.
60 80 A2 Multiplexed address line output. When INCMD is LOW, or A5 through A9 are all zeroes
or all ones (mode command), it represents the latched output of the 3rd MSB in the word
count field of the command word. When INCMD is HIGH and A5 through A9 are not all
zeroes or all ones, it represents the 3rd MSB of the current word counter. (See note 1).
61 78 A0 Multiplexed address line output. When INCMD is LOW, or A5 through A9 are all zeroes
or all ones (mode command), it represents the latched output of the LSB in the word
count field of the command. When INCMD is HIGH and A5 through A9 are not all
zeroes or all ones, it represents the LSB of the current word counter. (See note 1).
62 76 DTACK Data transfer acknowledge - Active LOW output signal during data transfers to or from
the subsystem indicating the RTU has received the DTGRT in response to DTREQ and is
presently doing the transfer. Can be connected directly pins 67 on Plug-In Pkg or pin 66
on Flat Pkg (BUF ENA) for control of 3-state data buffers; and to 3-state address buffer
control lines, if they are used.
63 74 A4 Multiplexed address line output. When INCMD is LOW or A5 through A9 are all zeroes
or all ones (mode command), it represents the latched output of the MSB in the word
count field of the command word. When INCMD is HIGH and A5 through A9 are not all
zeroes or all ones, it represents the MSB of the current word counter. (See note 1).
64 72 R/W Read/Write - Output signal that controls the direction of the internal data bus buffers.
Normally, the signal is LOW and the buffers drive the data bus. When data is needed from
the subsystem, it goes HIGH to turn the buffers around and the RT now appears as an
input. The signal is HIGH only when DTREQ is active (LOW).
65 70 GBR Good block received - LOW level output pulse (500 ns) used to flag the subsystem that a
valid, legal, non-mode receive command with the correct number of data words has been
received without a message error and successfully transferred to the subsystem. (See
note 4).
66 68 12 MHz 12 MHz clock input - Input for the master clock used to run RTU circuits.
67 66 BUF ENA
Buffer enable - Input used to enable or 3-state the internal data bus buffers when they are
driving the bus. When LOW, the data bus buffers are enabled. Could be connected to
DTACK, (pin 62, Plug-In Pkg), (pin 76, Flat Pkg) if RT is sharing the same data bus as
the subsystem. (See note 5).
68 64 RESET Input resets entire RT when LOW.
TERMINAL CONNECTIONS AND PIN FUNCTIONS (con’t)
Plug-In
Pkg
Flat
Pkg Function Description