CY7C344-25JCT - CYPRESS SEMICONDUCTOR

32-Macrocell MAX® EPLD

CY7C344

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Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-03006 Rev. *B Revised June 6, 2005

Features

• High-performance, high-density replacement for TTL,

74HC, and custom logic

• 32 macrocells, 64 expander product terms in one LAB

• 8 dedicated inputs, 16 I/O pins

• 0.8-micron double-metal CMOS EPROM technology

• 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC

package

Functional Description

Available in a 28-pin, 300-mil DIP or windowed J-leaded

ceramic chip carrier (HLCC), the CY7C344 represents the

densest EPLD of this size. Eight dedicated inputs and 16

bidirectional I/O pins communicate to one logic array block. In

the CY7C344 LAB there are 32 macrocells and 64 expander

product terms. When an I/O macrocell is used as an input, two

expanders are used to create an input path. Even if all of the

I/O pins are driven by macrocell registers, there are still 16

“buried” registers available. All inputs, macrocells, and I/O pins

are interconnected within the LAB.

The speed and density of the CY7C344 makes it a natural for

all types of applications. With just this one device, the designer

can implement complex state machines, registered logic, and

combinatorial “glue” logic, without using multiple chips. This

architectural flexibility allows the CY7C344 to replace

multichip TTL solutions, whether they are synchronous,

asynchronous, combinatorial, or all three.

Selection Guide

7C344-15 7C344-20 7C344-25 Unit

Maximum Access Time 15 20 25 ns

Maximum Operating Current Commercial 200 200 200 mA

Military 220 220

Industrial 220 220 220

Maximum Standby Current Commercial 150 150 150 mA

Military 170 170

Industrial 170 170 170

Note:

1. Numbers in () refer to J-leaded packages.

Logic Block Diagram

MACROCELL 2

MACROCELL 4

MACROCELL 6

MACROCELL 8

MACROCELL 10

MACROCELL 12

MACROCELL 14

MACROCELL 16

MACROCELL 18

MACROCELL 20

MACROCELL 22

MACROCELL 24

MACROCELL 26

MACROCELL 28

MACROCELL 30

MACROCELL 32

MACROCELL 1

MACROCELL 3

MACROCELL 5

MACROCELL 7

MACROCELL 9

MACROCELL 11

MACROCELL 13

MACROCELL 15

MACROCELL 17

MACROCELL 19

MACROCELL 21

MACROCELL 23

MACROCELL 25

MACROCELL 27

MACROCELL 29

MACROCELL 31

INPUT

15(22)

15(23)

27(6)

28(7)

INPUT 1(8)

INPUT/CLK 2(9)

INPUT 13(20)

INPUT 14(21)

I/O 3(10)

I/O 4(11)

I/O 5(12)

I/O 6(13)

I/O 9(16)

I/O 10(17)

I/O 11(18)

I/O 12(19)

I/O 17(24)

I/O 18(25)

I/O 19(26)

I/O 20(27)

I/O 23(2)

I/O 24(3)

I/O 25(4)

I/O 26(5)

64 EXPANDER PRODUCT TERM ARRAY 32

Pin Configurations

Top View

HLCC

11 12 13 14 1516 1718

432 28 2726

I/O

INPUT

I/O

INPUT

INPUT/CLK

I/O

GND

I/O

INPUT

I/O

GND

I/O

INPUT

Top View

CerDIP

INPUT/CLK

I/O

VCC

GND

I/O

INPUT

I/O

VCC

GND

I/O

INPUT

[1]

CY7C344

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Document #: 38-03006 Rev. *B Page 2 of 15

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied...................................................0°C to +70°C

Maximum Junction Temperature (Under Bias).............150°C

Supply Voltage to Ground Potential ............... –2.0V to +7.0V

Maximum Power Dissipation...................................1500 mW

DC VCC or GND Current ............................................500 mA

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ............................. >2001V

DC Output Current, per Pin ......................–25 mA to +25 mA

DC Input Voltage[2] .........................................–3.0V to +7.0V

DC Program Voltage................................................... +13.0V

Operating Range

Range

Ambient

Temperature VCC

Commercial 0°C to +70°C5V ±5%

Industrial –40°C to +85°C5V ±10%

Military –55°C to +125°C (Case) 5V ±10%

Electrical Characteristics Over the Operating Range[3]

Parameter Description Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 8 mA 0.45 V

VIH Input HIGH Level 2.2 VCC+0.3 V

VIL Input LOW Level –0.3 0.8 V

IIX Input Current GND ≤ VIN ≤ VCC –10 +10 µA

IOZ Output Leakage Current VO = VCC or GND –40 +40 µA

IOS Output Short Circuit Current VCC = Max., VOUT = 0.5V[4, 5] –30 –90 mA

ICC1 Power Supply

Current (Standby)

VI = VCC or GND (No

Load)

Commercial 150 mA

Military/Industrial 170 mA

ICC2 Power Supply Current VI = VCC or GND (No

Load) f = 1.0 MHz[4,6] Commercial 200 mA

Military/Industrial 220 mA

tRRecommended Input Rise Time 100 ns

tFRecommended Input Fall Time 100 ns

Capacitance

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance VIN = 2V, f = 1.0 MHz 10 pF

COUT Output Capacitance VOUT = 2.0V, f = 1.0 MHz 10 pF

AC Test Loads and Waveforms[7]

Notes:

2. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns.

3. Typical values are for TA = 25°C and VCC = 5V.

4. Guaranteed by design but not 100% tested.

5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid

test problems caused by tester ground degradation.

6. Measured with device programmed as a 16-bit counter.

7. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external timing

parameters are measured referenced to external pins of the device.

3.0V

OUTPUT

R1 464Ω

250Ω

50 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

≤ 6 ns ≤ 6 ns

OUTPUT

R1 464Ω

250Ω

(a) (b)

OUTPUT 1.75V

Equivalent to: THÉVENIN EQUIVALENT (commercial/military)

ALL INPUT PULSES

5pF

tRtF

163Ω

CY7C344

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Document #: 38-03006 Rev. *B Page 3 of 15

Timing Delays

Timing delays within the CY7C344 may be easily determined

using Warp®, Warp Professional™, or Warp Enterprise™

software. The CY7C344 has fixed internal delays, allowing the

user to determine the worst case timing delays for any design.

Design Recommendations

Operation of the devices described herein with conditions

above those listed under “Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other

conditions above those indicated in the operational sections of

this data sheet is not implied. Exposure to absolute maximum

ratings conditions for extended periods of time may affect

device reliability. The CY7C344 contains circuitry to protect

device pins from high-static voltages or electric fields; however,

normal precautions should be taken to avoid applying any

voltage higher than maximum rated voltages.

For proper operation, input and output pins must be

constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused

inputs must always be tied to an appropriate logic level (either VCC or

GND). Each set of VCC and GND pins must be connected together

directly at the device. Power supply decoupling capacitors of at least

0.2 µF must be connected between VCC and GND. For the most

effective decoupling, each VCC pin should be separately decoupled.

Timing Considerations

Unless otherwise stated, propagation delays do not include

expanders. When using expanders, add the maximum

expander delay tEXP to the overall delay.

When calculating synchronous frequencies, use tS1 if all inputs

are on the input pins. tS2 should be used if data is applied at an I/O

pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting frequency

in the data-path mode unless 1/(tWH + tWL) is less than 1/tS2.

When expander logic is used in the data path, add the appro-

priate maximum expander delay, tEXP to tS1. Determine which of

1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The

lowest of these frequencies is the maximum data-path frequency for

the synchronous configuration.

When calculating external asynchronous frequencies, use

tAS1 if all inputs are on dedicated input pins. If any data is applied to

an I/O pin, tAS2 must be used as the required set-up time. If (tAS2 +

tAH) is greater than tACO1, 1/(tAS2 + tAH) becomes the limiting

frequency in the data-path mode unless 1/(tAWH + tAWL) is less than

1/(tAS2 + tAH).

When expander logic is used in the data path, add the appro-

priate maximum expander delay, tEXP to tAS1. Determine which

of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency.

The lowest of these frequencies is the maximum data-path frequency

for the asynchronous configuration.

The parameter tOH indicates the system compatibility of this device

when driving other synchronous logic with positive input hold times,

which is controlled by the same synchronous clock. If tOH is greater

than the minimum required input hold time of the subsequent

synchronous logic, then the devices are guaranteed to function

properly with a common synchronous clock under worst-case

environmental and supply voltage conditions.

The parameter tAOH indicates the system compatibility of this

device when driving subsequent registered logic with a positive hold

time and using the same clock as the CY7C344. In general, if tAOH

is greater than the minimum required input hold time of the subse-

quent logic (synchronous or asynchronous), then the devices are

guaranteed to function properly under worst-case environmental and

supply voltage conditions, provided the clock signal source is the

same. This also applies if expander logic is used in the clock signal

path of the driving device, but not for the driven device. This is due to

the expander logic in the second device’s clock signal path adding an

additional delay (tEXP), causing the output data from the preceding

device to change prior to the arrival of the clock signal at the following

device’s register.

Figure 1. CY7C344 Timing Model

LOGIC ARRAY

CONTROLDELAY

tLAC

EXPANDER

DELAY

tEXP

CLOCK

DELAY

tIC

tRD

tCOMB

tLATCH

INPUT

DELAY

tIN

OUTPUT

DELAY

tOD

tXZ

tZX

LOGIC ARRAY

DELAY

tLAD

FEEDBACK

DELAY

tFD

OUTPUT

INPUT

SYSTEM CLOCK DELAYtICS

tRH

tRSU

tPRE

tCLR

I/O

I/O DELAY

tIO

I/O

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Document #: 38-03006 Rev. *B Page 4 of 15

External Synchronous Switching Characteristics Over Operating Range [7]

Parameter Description

7C344-15 7C344-20 7C344-25

UnitMin. Max. Min. Max. Min. Max.

tPD1 Dedicated Input to Combinatorial Output Delay[8] Com’l/Ind 15 20 25 ns

Mil 15 20 25

tPD2 I/O Input to Combinatorial Output Delay[9] Com’l/Ind 15 20 25 ns

Mil 15 20 25

tPD3 Dedicated Input to Combinatorial Output Delay

with Expander Delay[10] Com’l/Ind 30 30 40 ns

Mil 30 30 40

tPD4 I/O Input to Combinatorial Output Delay with

Expander Delay[4, 11] Com’l/Ind 30 30 40 ns

Mil 30 30 40

tEA Input to Output Enable Delay[4] Com’l/Ind 20 20 25 ns

Mil 20 20 25

tER Input to Output Disable Delay[4] Com’l/Ind 20 20 25 ns

Mil 20 20 25

tCO1 Synchronous Clock Input to Output Delay Com’l/Ind 10 12 15 ns

Mil 10 12 15

tCO2 Synchronous Clock to Local Feedback to

Combinatorial Output[4, 12] Com’l/Ind 20 22 29 ns

Mil 20 22 29

tSDedicated Input or Feedback Set-Up Time to

Synchronous Clock Input Com’l/Ind 10 12 15 ns

Mil 10 12 15

tHInput Hold Time from Synchronous Clock Input[7] Com’l/Ind 0 0 0 ns

Mil 0 0 0

tWH Synchronous Clock Input HIGH Time[4] Com’l/Ind 6 7 8 ns

Mil 6 7 8

tWL Synchronous Clock Input LOW Time[4] Com’l/Ind 6 7 8 ns

Mil 6 7 8

tRW Asynchronous Clear Width[4] Com’l/Ind 20 20 25 ns

Mil 20 20 25

tRR Asynchronous Clear Recovery Time[4] Com’l/Ind 20 20 25 ns

Mil 20 20 25

tRO Asynchronous Clear to Registered Output

Delay[4] Com’l/Ind 15 20 25 ns

Mil 15 20 25

tPW Asynchronous Preset Width[4] Com’l /Ind 20 20 25 ns

Mil 20 20 25

tPR Asynchronous Preset Recovery Time[4] Com’l /Ind 20 20 25 ns

Mil 20 20 25

Notes:

8. This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander

terms are used to form the logic function.

9. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to

form the logic function.

10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes

expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter

is tested periodically by sampling production material.

11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used to

form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by

sampling production material.

12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output for

which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the register

is synchronously clocked. This parameter is tested periodically by sampling production material.

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Document #: 38-03006 Rev. *B Page 5 of 15

tPO Asynchronous Preset to Registered Output

Delay[4] Com’l /Ind 15 20 25 ns

Mil 15 20 25

tCF Synchronous Clock to Local Feedback Input[4, 13] Com’l /Ind 4 4 7 ns

Mil 4 4 7

tPExternal Synchronous Clock Period (1/fMAX3)[4] Com’l/Ind 13 14 16 ns

Mil 13 14 16

fMAX1 External Maximum Frequency(1/(tCO1 + tS))[4, 14] Com’l/Ind 50.0 41.6 33.3 MHz

Mil 50.0 41.6 33.3

fMAX2 Maximum Frequency with Internal Only

Feedback (1/(tCF + tS))[4, 15] Com’l/Ind 71.4 62.5 45.4 MHz

Mil 71.4 62.5 45.4

fMAX3 Data Path Maximum Frequency, least of

1/(tWL + tWH), 1/(tS + tH), or (1/tCO1)[4, 16] Com’l/Ind 83.3 71.4 62.5 MHz

Mil 83.3 71.4 62.5

fMAX4 Maximum Register Toggle Frequency

1/(tWL + tWH)[4, 17] Com’l/Ind 83.3 71.4 62.5 MHz

Mil 83.3 71.4 62.5

tOH Output Data Stable Time from Synchronous

Clock Input[4, 18] Com’l/Ind 3 3 3 ns

Mil 3 3 3

Notes:

13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, tS, is the minimum internal

period for an internal state machine configuration. This parameter is tested periodically by sampling production material.

14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only feedback can operate.

15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states must

also control external points, this frequency can still be observed as long as it is less than 1/tCO1. This specification assumes no expander logic is used. This parameter

is tested periodically by sampling production material.

16. This frequency indicates the maximum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that no

expander logic is used.

17. This specification indicates the guaranteed maximum frequency in synchronous mode, at which an individual output or buried register can be cycled by a clock

signal applied to either a dedicated input pin or an I/O pin.

18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.

External Synchronous Switching Characteristics Over Operating Range (continued)[7]

Parameter Description

7C344-15 7C344-20 7C344-25

UnitMin. Max. Min. Max. Min. Max.

CY7C344

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Document #: 38-03006 Rev. *B Page 6 of 15

External Asynchronous Switching Characteristics Over Operating Range[7]

7C344-15 7C344-20 7C344-25

Parameter Description Min. Max. Min. Max. Min. Max. Unit

tACO1 Asynchronous Clock Input to Output Delay Com’l/Ind 15 20 25 ns

Mil 15 20 25

tACO2 Asynchronous Clock Input to Local Feedback to

Combinatorial Output[19] Com’l/Ind 30 30 37 ns

Mil 30 30 37

tAS Dedicated Input or Feedback Set-Up Time to

Asynchronous Clock Input Com’l/Ind 7 9 12 ns

Mil 7 9 12

tAH Input Hold Time from Asynchronous Clock Input Com’l/Ind 7 9 12 ns

Mil 7 9 12

tAWH Asynchronous Clock Input HIGH Time[4, 20] Com’l/Ind 679ns

Mil 679

tAWL Asynchronous Clock Input LOW Time[4] Com’l/Ind 7 9 11 ns

Mil 7 9 11

tACF Asynchronous Clock to Local Feedback Input[4, 21] Com’l/Ind 18 18 21 ns

Mil 18 18 21

tAP External Asynchronous Clock Period (1/fMAX4)[4] Com’l/Ind 13 16 20 ns

Mil 13 16 20

fMAXA1 External Maximum Frequency in Asynchronous

Mode 1/(tACO1 + tAS)[4, 22] Com’l/Ind 45.4 34.4 27 MHz

Mil 45.4 34.4 27

fMAXA2 Maximum Internal Asynchronous Frequency

1/(tACF + tAS) or 1/(tAWH + tAWL)[4, 23] Com’l/Ind 40 37 30.3 MHz

Mil 40 37 30.3

fMAXA3 Data Path Maximum Frequency in Asynchronous

Mode[4, 24] Com’l/Ind 66.6 50 40 MHz

Mil 66.6 50 40

fMAXA4 Maximum Asynchronous Register Toggle

Frequency 1/(tAWH + tAWL)[4, 25] Com’l/Ind 76.9 62.5 50 MHz

Mil 76.9 62.5 50

tAOH Output Data Stable Time from Asynchronous Clock

Input[4, 26] Com’l/Ind 15 15 15 ns

Mil 15 15 15

Notes:

19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the registered output signal to a combinatorial

output for which the registered output signal is used as an input. Assumes no expanders are used in logic of combinatorial output or the asynchronous clock

input. This parameter is tested periodically by sampling production material.

20. This parameter is measured with a positive-edge-triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped. If a

given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL.

21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronously clocked register. This delay plus the

asynchronous register set-up time, tAS, is the minimum internal period for an asynchronously clocked state machine configuration. This delay assumes no expander logic in

the asynchronous clock path. This parameter is tested periodically by sampling production material.

22. This parameter indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can

operate. It is assumed that no expander logic is employed in the clock signal path or data path.

23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. If

register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. This specification assumes

no expander logic is utilized. This parameter is tested periodically by sampling production material.

24. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode.

This frequency is least of 1/(tAWH + tAWL), 1/(tAS + tAH), or 1/tACO1. It also indicates the maximum frequency at which the device may operate in the asynchronously clocked

data-path mode. Assumes no expander logic is used.

25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode

by a clock signal applied to an external dedicated input or an I/O pin.

26. This parameter indicates the minimum time that the previous register output data is maintained on the output pin after an asynchronous register clock input to

an external dedicated input or I/O pin.

CY7C344

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Document #: 38-03006 Rev. *B Page 7 of 15

Typical Internal Switching Characteristics Over Operating Range[7]

7C344-15 7C344-20 7C344-25

Parameter Description Min. Max. Min. Max. Min. Max. Unit

tIN Dedicated Input Pad and Buffer Delay Com’l/Ind 4 5 7 ns

Mil 4 5 7

tIO I/O Input Pad and Buffer Delay Com’l/Ind 4 5 7 ns

Mil 4 5 7

tEXP Expander Array Delay Com’l/Ind 810 15 ns

Mil 810 15

tLAD Logic Array Data Delay Com’l/Ind 7 9 10 ns

Mil 7 9 10

tLAC Logic Array Control Delay Com’l/Ind 5 7 7 ns

Mil 5 7 7

tOD Output Buffer and Pad Delay Com’l/Ind 4 5 5 ns

Mil 4 5 5

tZX Output Buffer Enable Delay[27] Com’l/Ind 7 8 11 ns

Mil 7 8 11

tXZ Output Buffer Disable Delay Com’l/Ind 7 8 11 ns

Mil 7 8 11

tRSU Register Set-Up Time Relative to Clock Signal

at Register Com’l/Ind 5 5 8 ns

Mil 5 5 8

tRH Register Hold Time Relative to Clock Signal at

Com’l/Ind 7 9 12 ns

Mil 7 9 12

tLATCH Flow-Through Latch Delay Com’l/Ind 1 1 3 ns

Mil 1 1 3

tRD Register Delay Com’l/Ind 1 1 1 ns

Mil 1 1 1

tCOMB Transparent Mode Delay[28] Com’l/Ind 1 1 3 ns

Mil 1 1 3

tCH Clock HIGH Time Com’l/Ind 6 7 8 ns

Mil 6 7 8

tCL Clock LOW Time Com’l/Ind 6 7 8 ns

Mil 6 7 8

tIC Asynchronous Clock Logic Delay Com’l/Ind 7 8 10 ns

Mil 7 8 10

tICS Synchronous Clock Delay Com’l/Ind 1 2 3 ns

Mil 1 2 3

tFD Feedback Delay Com’l/Ind 1 1 1 ns

Mil 1 1 1

tPRE Asynchronous Register Preset Time Com’l/Ind 5 6 9 ns

Mil 5 6 9

Notes:

27. Sample tested only for an output change of 500 mV.

28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial

operation.

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Document #: 38-03006 Rev. *B Page 8 of 15

tCLR Asynchronous Register Clear Time Com’l/Ind 5 6 9 ns

Mil 5 6 9

tPCW Asynchronous Preset and Clear Pulse Width Com’l/Ind 5 5 7 ns

Mil 5 5 7

tPCR Asynchronous Preset and Clear Recovery Time Com’l/Ind 5 5 7 ns

Mil 5 5 7

Typical Internal Switching Characteristics Over Operating Range[7] (continued)

7C344-15 7C344-20 7C344-25

Parameter Description Min. Max. Min. Max. Min. Max. Unit

Switching Waveforms

External Combinatorial

tPD1/tPD2

tER

tEA

VALID OUTPUT

DEDICATED INPUT/

I/O INPUT

COMBINATORIAL

OUTPUT

COMBINATORIAL OR

REGISTERED OUTPUT

HIGH-IMPEDANCE

THREE-STATE

HIGH-IMPEDANCE

THREE-STATE

External Synchronous

tStWH tWL

tRR/tPR

tRW/tPW

tOH

tCO1

tRO/tPO

tCO2

DEDICATED INPUTS OR

REGISTERED FEEDBACK

SYNCHRONOUS

CLOCK

ASYNCHRONOUS

CLEAR/PRESET

REGISTERED

OUTPUTS

COMBINATORIAL OUTPUT FROM

REGISTERED FEEDBACK [12]

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Document #: 38-03006 Rev. *B Page 9 of 15

Switching Waveforms (continued)

tACO1

External Asynchronous

tAH

tAS tAWH tAWL

tRR/tPR

tRW/tPW

tAOH

tRO/tPO

tACO2

ASYNCHRONOUS

CLOCK INPUT

ASYNCHRONOUS REGISTERED

OUTPUTS

DEDICATED INPUTS OR

REGISTERED FEEDBACK

ASYNCHRONOUS

CLEAR/PRESET

COMBINATORIAL OUTPUT FROM

ASYNCH. REGISTERED

FEEDBACK[19]

Internal Combinatorial

tIN

tIO

tPIA

tEXP

tLAC,t

LAD

INPUT PIN

EXPANDER

I/O PIN

LOGIC ARRAY

ARRAY DELAY

OUTPUT

LOGIC ARRAY

INPUT

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Document #: 38-03006 Rev. *B Page 10 of 15

Switching Waveforms (continued)

Internal Asynchronous

tIO

tAWH tAWL tF

tIN

tIC

tRSU tRH

tRD,tLATCH tFD tCLR,tPRE tFD

CLOCK PIN

LOGIC ARRAY

CLOCK FROM

DATA FROM

CLOCK INTO

LOGIC ARRAY

TO ANOTHER LAB

tPIA

TO LOCAL LAB

LOGIC ARRAY

Internal Synchronous (Input Path)

tCH tCL

tIN tICS

tRSU tRH

SYSTEM CLOCK PIN

SYSTEM CLOCK

AT REGISTER

DATA FROM

LOGIC ARRAY

Internal Synchronous (Output Path)

tXZ tZX

tOD

HIGH Z

CLOCK FROM

LOGIC ARRAY

DATA FROM

OUTPUT PIN

tRD

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Document #: 38-03006 Rev. *B Page 11 of 15

MILITARY SPECIFICATIONS

Group A Subgroup Testing

Ordering Information

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

15 CY7C344-15HC/HI H64 28-Lead Windowed Leaded Chip Carrier Commercial/Industrial

CY7C344-15JC/JI J64 28-Lead Plastic Leaded Chip Carrier

CY7C344-15PC/PI P21 28-Lead (300-Mil) Molded DIP

CY7C344-15WC/WI W22 28-Lead Windowed CerDIP

20 CY7C344-20HC/HI H64 28-Lead Windowed Leaded Chip Carrier Commercial/Industrial

CY7C344-20JC/JI J64 28-Lead Plastic Leaded Chip Carrier

CY7C344-20PC/PI P21 28-Lead (300-Mil) Molded DIP

CY7C344-20WC/WI W22 28-Lead Windowed CerDIP

CY7C344-20HMB H64 28-Lead Windowed Leaded Chip Carrier Military

CY7C344-20WMB W22 28-Lead Windowed CerDIP

25 CY7C344-25HC/HI H64 28-Lead Windowed Leaded Chip Carrier Commercial/Industrial

CY7C344-25JC/JI J64 28-Lead Plastic Leaded Chip Carrier

CY7C344-25PC/PI P21 28-Lead (300-Mil) Molded DIP

CY7C344-25WC/WI W22 28-Lead Windowed CerDIP

CY7C344-25HMB H64 28-Lead Windowed Leaded Chip Carrier Military

CY7C344-25WMB W22 28-Lead Windowed CerDIP

DC Characteristics

Parameter Subgroups

VOH 1, 2, 3

VOL 1, 2, 3

VIH 1, 2, 3

VIL 1, 2, 3

IIX 1, 2, 3

IOZ 1, 2, 3

ICC1 1, 2, 3

Switching Characteristics

Parameter Subgroups

tPD1 7, 8, 9, 10, 11

tPD2 7, 8, 9, 10, 11

tPD3 7, 8, 9, 10, 11

tCO1 7, 8, 9, 10, 11

tS7, 8, 9, 10, 11

tH7, 8, 9, 10, 11

tACO1 7, 8, 9, 10, 11

tAS 7, 8, 9, 10, 11

tAH 7, 8, 9, 10, 11

CY7C344

USE ULTRA37000TM FOR

ALL NEW DESIGNS

Document #: 38-03006 Rev. *B Page 12 of 15

Package Diagrams

28-Pin Windowed Leaded Chip Carrier H64

51-80077-**

CY7C344

USE ULTRA37000TM FOR

ALL NEW DESIGNS

Document #: 38-03006 Rev. *B Page 13 of 15

Package Diagrams (continued)

28-Lead Plastic Leaded Chip Carrier J64

51-85001-*A

DIMENSIONS IN INCHES [MM] MIN.

MAX.

SEATING PLANE

0.260[6.60]

0.295[7.49]

0.090[2.28]

0.110[2.79]

0.055[1.39]

0.065[1.65]

0.015[0.38]

0.020[0.50]

0.015[0.38]

0.060[1.52]

0.120[3.05]

0.140[3.55]

0.009[0.23]

0.012[0.30]

0.310[7.87]

0.385[9.78]

0.290[7.36]

0.325[8.25]

0.030[0.76]

0.080[2.03]

0.115[2.92]

0.160[4.06]

0.140[3.55]

0.190[4.82]

1.345[34.16]

1.385[35.18]

3° MIN.

114

15 28

REFERENCE JEDEC MO-095

LEAD END OPTION

SEE LEAD END OPTION

(LEAD #1, 14, 15 & 28)

PACKAGE WEIGHT: 2.15 gms

28-Lead (300-Mil) PDIP P21

51-85014-*D

CY7C344

USE ULTRA37000TM FOR

ALL NEW DESIGNS

Document #: 38-03006 Rev. *B Page 14 of 15

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

MAX and Warp are registered trademarks and Ultra37000, Warp Professional and Warp Enterprise are trademarks of Cypress

Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective

holders.

Package Diagrams (continued)

28-Lead (300-Mil) Windowed CerDIP W22

MIL-STD-1835 D-15 Config. A

51-80087-**

CY7C344

USE ULTRA37000TM FOR

ALL NEW DESIGNS

Document #: 38-03006 Rev. *B Page 15 of 15

Document History Page

Document Title: CY7C344 32-Macrocell MAX® EPLD

Document Number: 38-03006

REV. ECN NO. Issue Date

Orig. of

Change Description of Change

** 106271 04/19/01 SZV Change from Spec number: 38-00127 to 38-03006

*A 213375 See ECN FSG Added note to title page: “Use Ultra37000 For All New Designs”

*B 373715 See ECN PCX Corrected header information