DESCRIPTION
The APS12450 three-wire planar Hall-effect sensor integrated
circuits (ICs) were developed in accordance with ISO 26262:2011
as a hardware safety element out of context with ASIL B
capability (pending assessment) for use in automotive safety-
related systems when integrated and used in the manner
prescribed in the applicable safety manual and datasheet. The
enhanced three-wire interface provides interconnect open/
short diagnostics and a fault state to communicate diagnostic
information while maintaining compatibility with legacy
three-wire systems. The continuous background diagnostics
are transparent to the host system and results in a reduced
fault tolerant time.
The APS12450 product options include magnetic switchpoints,
temperature coefficient, and output polarity. The response can
be matched to SmCo, NdFeB, or low-cost ferrite magnets. For
situations where a functionally equivalent three-wire switch
device is preferred, refer to the APS11450.
APS12450-DS, Rev. 1
MCO-0000562
FEATURES AND BENEFITS
• Functional safety
□Developed in accordance with ISO 26262:2011 to meet
ASIL B requirements (pending assessment)
□Integrated background diagnostics for:
○Signal path
○Regulator
○Hall plate and bias
○Overtemperature detection
○Nonvolatile memory
□Defined fault state
• Multiple product options
□Magnetic polarity, switchpoints, and hysteresis
□Temperature coefficient
□Output polarity
• Reduces module bill-of-materials (BOM) and assembly cost
□ASIL B sensor can replace redundant sensors
□Integrated overvoltage clamp and reverse-battery diode
Three-Wire Hall-Effect Latch with Advanced Diagnostics
Functional Block Diagram
APS12450
PACKAGES
Not to scale
3-pin SOT23-W (LH) 3-pin ultramini SIP (UA)
VC
C
GND
H
ALL
A
MP
.
D
YNAMIC
O
FFSET
C
ANCELLATION
R
EGULATOR
Low-Pass
Filter
To All Subcircuits
S
AMPLE
, H
OLD
&
A
VERAGING
S
YSTEM
D
IAGNOSTICS
C
LOCK
L
OGIC
O
UTPUT
C
ONTROL
Schmitt Output
(Internal)
VOUT
April 23, 2019
TYPICAL APPLICATIONS
• Automotive and industrial safety systems
• Seat/window motors
• Sun roof/convertible top/tailgate/liftgate actuation
• Brake and clutch by wire actuators
• Engine management actuators
• Electric power steering (EPS)
• Transmission shift actuator
2
-
Continued on the next page…
Continued on the next page…
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
RoHS
COMPLIANT
FEATURES AND BENEFITS (continued)
• Automotive-grade ruggedness and fault tolerance
□Extended AEC-Q100 Grade 0 qualification
○Operation to 175°C junction temperature
□3 to 30 V operating voltage range
□±8 kV HBM ESD
□Overtemperature indication
APS12450 sensors are engineered to operate in the harshest
environments with minimal external components. They are qualified
beyond the requirements of AEC-Q100 Grade 0 and will survive
extended operation at 175°C junction temperature.
These monolithic ICs include on-chip reverse-battery protection,
overvoltage protection (e.g., 40 V load dump), ESD protection,
overtemperature detection, and an internal voltage regulator for
operation directly from an automotive battery bus. These integrated
features reduce the end-product bill-of-materials (BOM) and
assembly cost.
Package options include industry-standard surface-mount SOT (LH)
and through-hole SIP (UA) packages. Both packages are RoHS-
compliant and lead (Pb) free with 100% matte-tin-plated leadframes.
DESCRIPTION (continued)
SELECTION GUIDE [1]
Part Number Package Packing Output Polarity
(B > BOP)
Temperature
Coefficient
Magnetic
Operate Point,
BOP (typ)
APS12450LLHALX-0SLA 3-pin SOT23W surface mount 13-in. reel, 10,000 pieces/reel
Low 0%/°C 22 GAPS12450LLHALT-0SLA 3-pin SOT23W surface mount 7-in. reel, 3000 pieces/reel
APS12450LUAA-0SLA 3-pin SIP through-hole bulk, 500 pieces/bag
APS12450LLHALX-1SLA 3-pin SOT23W surface mount 13-in. reel, 10,000 pieces/reel
Low 0%/°C 50 GAPS12450LLHALT-1SLA 3-pin SOT23W surface mount 7-in. reel, 3000 pieces/reel
APS12450LUAA-1SLA 3-pin SIP through-hole bulk, 500 pieces/bag
APS12450LLHALX-3SLA 3-pin SOT23W surface mount 13-in. reel, 10,000 pieces/reel
Low 0%/°C 150 GAPS12450LLHALT-3SLA 3-pin SOT23W surface mount 7-in. reel, 3000 pieces/reel
APS12450LUAA-3SLA 3-pin SIP through-hole bulk, 500 pieces/bag
[1] Contact Allegro MicroSystems for options not listed in the selection guide.
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Notes Rating Unit
Supply Voltage [2] VCC 35 V
Reverse Supply Voltage VRCC –30 V
Forward Output Voltage VOUT 30 V
Reverse Output Voltage VROUT –0.3 V
Output Current Sink IOUT(SINK) VCC to VOUT 12 mA
Maximum Junction Temperature TJ(MAX)
165 °C
For 500 hours 175 °C
Storage Temperature Tstg –65 to 170 °C
[2] This rating does not apply to extremely short voltage transients such as load dump and/or ESD. Those events have individual ratings
specific to the respective transient voltage event. Contact your local field applications engineer for information on EMC test results.
L
Opera�ng Mode
S
– Unipolar South Sensing
N – Unipolar North Sensing
Allegro Iden�fier (Device Family)
APS – Digital Posi�on Sensor
Ambient Opera�ng Temperature Range
L – -40°C to +150°C
Instruc�ons (Packing)
LT – 7-in. reel, 3,000 pieces/reel (LH Only)
LX – 13-in. reel, 10,000 pieces/reel (LH Only)
TN – 13-in. reel, 4,000 pieces/reel (UA Only)
(no op�on code) – bulk, 500 pieces/bag (UA only)
Package Designa�on
LHA
– 3-pin SOT23W Surface Mount
UAA – 3-pin SIP Through-Hole
Complete Part
Number Format
Device Switch Threshold Magnitude
0 – 22 G BOP, -22 G BRP (typ.)
1 – 50 G BOP, -50 G BRP (typ.)
3 – 150 G BOP, -150 G BRP (typ.)
Output Polarity for B > BOP
H – High (Output Off)
L – Low (Output On)
-
L L H A S0 L
Configura�on Op�ons
T
APS12450
Allegro Device Number
12450 – ASIL B Hall-effect Latch
C
Temperature Coefficient
A – Flat
B – -0.035 %/°C
C – -0.12 %/°C
D – -0.2 %/°C
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
1
2
3
GND
VCC
VOUT
1
3
2
VCC
GND
VOUT
LH Package, 3-Pin SOT23W Pinout UA Package, 3-Pin SIP Pinout
Terminal List Table
Name Pin Number Function
LH UA
VCC 1 1 Supply voltage
VOUT 2 3 Output
GND 3 2 Ground
PINOUT DIAGRAMS AND TERMINAL LIST
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
OPERATING CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max),
unless otherwise specified
Characteristics Symbol Test Conditions Min. Typ. [1] Max. Unit
SUPPLY AND STARTUP
Supply Voltage [2] VCC Operating, TJ < 165°C 3.0 – 30 V
Supply Current ICC – – 4.5 mA
Power-On Time [3] ton
VCC > VCC(min), B < BRP(min) – 10 G,
B > BOP(max) + 10 G – – 150 µs
Power-On State POS t < ton(max) VOUT(FAULT) –
Output Rise Time tRISE See Applications Circuit, Figure 9;
VPU = VCC, RPU = 3 kΩ, COUT = 1 nF, IOUT < 12 mA
2 4 15 µs
Output Fall Time tFALL 2 4 15 µs
Output On Voltage VOUT(LOW) Output ratiometric to VPU;
VPU = VCC, τ < 3 µs [5], IOUT < 12 mA
10 20 30 %
Output Off Voltage VOUT(HIGH) 70 80 90 %
Output Off Voltage Overshoot [4] VOUT(HIGH)OVER
Overshoot percentage relative to VPU (see Figure 8);
VPU = VCC, τ < 3 µs [5], IOUT < 12 mA – 2 – %
tVOUT(H)OVER Duration of output voltage overshoot (VOUT(HIGH)OVER) – – 5 µs
ON-BOARD PROTECTION
Fault Reaction Time tDIAG – 25 60 µs
Diagnostics Fault Retry Time [6] tDIAGF – 2 – ms
Fault Mode Output Voltage
(Fault State) VOUT(FAULT) VPU = VCC, τ < 3 µs, IOUT < 12 mA > VOUT(HIGH)
MAX
VPU – V
Overtemperature Shutdown TSD Temperature increasing – 205 – °C
Overtemperature Hysteresis TJHYS – 25 – °C
[1] Typical data is at TA = 25°C and VCC = 12 V and is for design information only.
[2] VCC represents the voltage between the VCC pin and the GND pin.
[3] Power-On Time (tON) is measured from VCC = VCC(min) to 50% of the output transition from VPU to final value. Adding a bypass capacitor will
increase Power-On Time.
[4] The overshoot specification pertains only to conditions where the overshoot is greater than the VOUT(HIGH)MAX specification.
[5] τ is the time constant of the RC circuit; τ = RPU × COUT.
[6] The diagnostics fault retry repeats continuously until a fault condition is no longer observed. See Diagnostics Mode Operation section for details.
TRANSIENT PROTECTION CHARACTERISTICS: Valid for TA = 25°C and CBYP = 0.1 µF, unless otherwise specified
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
PROTECTION
Forward Supply Zener
Clamp Voltage VZICC(max) + 3 mA 35 – – V
Reverse Supply Zener
Clamp Voltage VRCC ICC = –1 mA – – –30 V
Reverse Supply Current IRCC VRCC = –30 V – – –5 mA
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
MAGNETIC CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max),
unless otherwise specified
Characteristics Symbol Test Conditions Min. Typ. [1] Max. Unit [2]
Sensitivity Temperature
Coefficient TCSENS
Relative to sensitivity
at 25°C
(A) Flat – 0 – %/°C
(B) SmCo – –0.035 – %/°C
(C) NdFeB – –0.12 – %/°C
(D) Ferrite – –0.2 – %/°C
Analog Signal Bandwidth f(-3dB) – 10 – kHz
Operate Point BOP
APS12450–0SxA 5 22 40 G
APS12450–1SxA 15 50 90 G
APS12450–3SxA 100 150 180 G
Release Point BRP
APS12450–0SxA –40 –22 –5 G
APS12450–1SxA –90 –50 –15 G
APS12450–3SxA –180 –150 –100 G
Hysteresis BHYS
APS12450–0SxA 10 45 80 G
APS12450–1SxA 30 100 180 G
APS12450–3SxA 200 300 360 G
Symmetry BSYM BOP + BRP -30 – 30 G
Jitter [3] – BOP = 22 G, B = 100 GPK-PK, 1000 Hz – 0.25 – %
[1] Typical data is at TA = 25°C and VCC = 12 V, unless otherwise noted; for design information only.
[2] 1 G (gauss) = 0.1 mT (millitesla).
[3] Output edge repeatability as a percentage of the period.
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions* Value Unit
Package Thermal Resistance RθJA
Package LH, on 1-layer PCB based on JEDEC standard 228 °C/W
Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side 110 °C/W
Package UA, on 1-layer PCB with copper limited to solder pads 165 °C/W
*Additional thermal information available on the Allegro website.
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE DATA
0
0.5
1
1.5
2
2.5
3
3.5
4
-50 -20 10 40 70 100 130 160
Diag Fault Retry Time, t
DIAGF
(ms )
Ambi ent Temperatur e, T
A
(°C)
tDIAGF vs. TA
3
30
VCC (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
0 5 10 15 20 25 30 35
Diag Fault Retry Time, t
DIAGF
(ms )
Supply Voltage, V
CC
(V)
tDIAGF vs. VCC
-40
25
150
TA(°C)
90
92
94
96
98
100
102
0 5 10 15 20 25 30 35
Output Vol tage, V
OU T( FAULT)
(%)
Supply Voltage, V
CC
(V)
VOUT(FAULT) vs. VCC
-40
25
150
TA(°C)
90
92
94
96
98
100
102
-50 -20 10 40 70 100 130 160
Output Vol tage, V
OU T( FAULT)
(%)
Ambi ent Temperatur e, T
A
(°C)
VOUT(FAULT) vs. TA
3
30
VCC (V)
70
72
74
76
78
80
82
84
86
88
90
-50 -20 10 40 70 100 130 160
Output Vol tage, V
OUT(HIGH)
(%)
Ambi ent Temperatur e, T
A
(°C)
VOUT(HIGH) vs. TA
3
30
VCC (V)
70
72
74
76
78
80
82
84
86
88
90
0 5 10 15 20 25 30 35
Output Vol tage, V
OUT(HIGH)
(%)
Supply Voltage, V
CC
(V)
VOUT(HIGH) vs. VCC
-40
25
150
TA(°C)
10
12
14
16
18
20
22
24
26
28
30
-50 -20 10 40 70 100 130 160
Output Vol tage, V
OUT(LOW)
(%)
Ambi ent Temperatur e, T
A
(°C)
VOUT(LOW) vs. TA
3
30
VCC (V)
10
12
14
16
18
20
22
24
26
28
30
0 5 10 15 20 25 30 35
Output Vol tage, V
OUT(LOW)
(%)
Supply Voltage, V
CC
(V)
VOUT(LOW) vs. VCC
-40
25
150
TA(°C)
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE DATA (continued)
VCC (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 5 10 15 20 25 30 35
Supply Current, I
CC
(mA)
Supply Voltage, V
CC
(V)
ICC vs. VCC
-40
25
150
TA(°C)
0
15
30
45
60
75
90
105
120
135
150
-50 -20 10 40 70 100 130 160
Power-on Ti me, t
on
(µs)
Ambi ent Temperatur e, T
A
(°C)
ton vs. TA
0
2.5
5
7.5
10
12.5
15
-50 -20 10 40 70 100 130 160
Rise & Fall Time, t
RISE
& t
FALL
(µs)
Ambi ent Temperatur e, T
A
(°C)
tRISE & tFALL vs. TA
Fal l
Ris e
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE DATA
APS12450–0SxA
VCC (V)
5
10
15
20
25
30
35
40
0 5 10 15 20 25 30 35
Magnetic Flux Density, B
OP
(G)
Supply Voltage, V
CC
(V)
BOP(0S_A) vs. VCC
-40
25
150
TA(°C)
VCC (V)
-40
-35
-30
-25
-20
-15
-10
-5
0 5 10 15 20 25 30 35
Magnetic Flux Density, B
RP
(G)
Supply Voltage, V
CC
(V)
BRP(0S_A) vs. VCC
-40
25
150
TA(°C)
VCC (V)
10
20
30
40
50
60
70
80
0 5 10 15 20 25 30 35
Magnetic Flux Density, B
HYS
(G)
Supply Voltage, V
CC
(V)
BHYS(0S_A) vs. VCC
-40
25
150
TA(°C)
VCC (V)
-25
-20
-15
-10
-5
0
5
10
15
20
25
0 5 10 15 20 25 30 35
Magnetic Flux Density, B
SYM
(G)
Supply Voltage, V
CC
(V)
BSYM(0S_A) vs. VCC
-40
25
150
TA(°C)
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
10
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE DATA
APS12450–1SxA
VCC (V)
15
22.5
30
37.5
45
52.5
60
67.5
75
82.5
90
0 5 10 15 20 25 30 35
Magnetic Flux Density, B
OP
(G)
Supply Voltage, V
CC
(V)
BOP(1S_A) vs. VCC
-40
25
150
TA(°C)
VCC (V)
-90
-82.5
-75
-67.5
-60
-52.5
-45
-37.5
-30
-22.5
-15
0 5 10 15 20 25 30 35
Magnetic Flux Density, B
RP
(G)
Supply Voltage, V
CC
(V)
BRP(1S_A) vs. VCC
-40
25
150
TA(°C)
VCC (V)
30
55
80
105
130
155
180
0 5 10 15 20 25 30 35
Magnetic Flux Density, B
HYS
(G)
Supply Voltage, V
CC
(V)
BHYS(1S_A) vs. VCC
-40
25
150
TA(°C)
VCC (V)
-25
-20
-15
-10
-5
0
5
10
15
20
25
0 5 10 15 20 25 30 35
Magnetic Flux Density, B
SYM
(G)
Supply Voltage, V
CC
(V)
BSYM(1S_A) vs. VCC
-40
25
150
TA(°C)
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
11
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARACTERISTIC PERFORMANCE DATA
APS12450–3SxA
VCC (V)
100
110
120
130
140
150
160
170
180
0 5 10 15 20 25 30 35
Magnetic Flux Density, B
OP
(G)
Supply Voltage, V
CC
(V)
BOP(3S_A) vs. VCC
-40
25
150
TA(°C)
VCC (V)
-180
-170
-160
-150
-140
-130
-120
-110
-100
0 5 10 15 20 25 30 35
Magnetic Flux Density, B
RP
(G)
Supply Voltage, V
CC
(V)
BRP(3S_A) vs. VCC
-40
25
150
TA(°C)
VCC (V)
200
220
240
260
280
300
320
340
360
0 5 10 15 20 25 30 35
Magnetic Flux Density, B
HYS
(G)
Supply Voltage, V
CC
(V)
BHYS(3S_A) vs. VCC
-40
25
150
TA(°C)
VCC (V)
-25
-20
-15
-10
-5
0
5
10
15
20
25
0 5 10 15 20 25 30 35
Magnetic Flux Density, B
SYM
(G)
Supply Voltage, V
CC
(V)
BSYM(3S_A) vs. VCC
-40
25
150
TA(°C)
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
12
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FUNCTIONAL DESCRIPTION
Operation
The output of these devices switches when a magnetic field perpen-
dicular to the Hall-effect sensor exceeds the operate point threshold
(BOP). When the magnetic field is reduced below the release point
(BRP), the device output switches to the alternate state. The output
state (polarity) and magnetic field polarity depends on the selected
device options. The device is a latch, therefore BOP and BRP will be
in opposite magnetic field polarities.
The difference between operate (BOP) and release (BRP) points is
the hysteresis (BHYS). Hysteresis allows clean switching of the
output even in the presence of external mechanical vibration and
electrical noise. The hysteresis is set to double the programmed
operating point.
Figure 1 shows the output switching behavior relative to increas-
ing and decreasing magnetic field. On the horizontal axis, the
B+ direction indicates increasing south polarity magnetic field
strength. Figure 2 shows the sensing orientation of the magnetic
field, relative to the device package.
Note that this device latches; that is, a south pole of sufficient
strength towards the branded face of the device turns the device
on, and the device remains on with removal of the south pole.
Figure 1 shows the potential unipolar and omnipolar options and
output polarity options of the APS12450 that can be configured.
The direction of the applied magnetic field is perpendicular to the
branded face of the APS12450 (see Figure 2).
Figure 1: Hall latch magnetic and output polarity options
B- indicates increasing north polarity magnetic eld strength, and
B+ indicates increasing south polarity magnetic eld strength.
Switch to Low
Switch to High
B
HYS
B
RPS
B
OPS
B+
Inverted Polarity
V
OUT(LOW)
V
OUT(HIGH)
V+
V
OUT
(north) (south)
B– 0
Standard Polarity
Switch to High
Switch to Low
B
RPS
B
OPS
B
HYS
V+
B- 0
V
OUT(LOW)
V
OUT(HIGH)
V
OUT
B+
(north) (south)
Figure 2: Magnetic Sensing Orientations
APS12450 LH (Panel A), APS12450 UA (Panel B)
Z
XY
Z
XY
Z
XY
A B
C
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
13
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FUNCTIONAL SAFETY
The APS12450 was developed in accordance with ISO 26262:2011
as a hardware safety element out of context with ASIL B capability
(pending assessment) for use in automotive safety-related systems
when integrated and used in the manner prescribed in the appli-
cable safety manual and datasheet.
Diagnostics Mode Operation
The APS12450 features a proprietary diagnostics routine that
meets ASIL B safety requirements (pending assessment). This
internal diagnostics routine continuously runs in the background,
monitoring all key subsystems of the IC. These subsystems are
shown in Table 1 and Figure 3. The diagnostic scheme runs at
high speed and provides minimal impact on device performance.
Signal path diagnostics are injected and measured in less than
2μs,whileallotherdiagnosticsarerunninginrealtimeinthe
background. The Hall element biasing circuit and voltage regula-
torarecheckedforvalidoperation,andthedigitalandnon‐vola-
tile memory blocks are checked for valid device configuration.
The signal path monitoring system verifies two internal state
transitions (BOP and BRP within limits) under normal operation.
In cases when these output transitions do not occur, or if another
internal fault is detected, the output will go to the fault state (see
“Three-Wire Diagnostic Output” section).
In the event of an internal fault, the device will continuously run
the diagnostics routine every 2 ms (tDIAGF). The periodic recov-
ery attempt sequence allows the device to continually check for
the presence of a fault and return to normal operation if the fault
condition clears.
In the case where the fault is no longer present, the output will
resume normal operation. However, if the fault is persistent, the
device will not exit fault mode and the output voltage will con-
tinue to be VOUT(FAULT).
When a system rating higher than ASIL B is required, additional
external safety measures may be employed (e.g., sensor redun-
dancy and rationality checks, etc.). Refer to the device safety
manual for additional details about the diagnostics.
Figure 3: Diagnostics Coverage Block Diagram
VC
C
GND
H
ALL
A
MP
.
D
YNAMIC
O
FFSET
C
ANCELLATION
R
EGULATOR
Low-Pass
Filter
To All Subcircuits
S
AMPLE
, H
OLD
&
A
VERAGING
S
YSTEM
D
IAGNOSTICS
C
LOCK
L
OGIC
O
UTPUT
C
ONTROL
Schmitt Output
(Internal)
VOUT
12
3
4
5
6
Table 1: Diagnostics Coverage
Feature Coverage
1 Hall plate Connectivity and biasing of Hall plate
2 Signal path Signal path and Schmitt trigger
3 Voltage regulator Regulator voltage for normal operation
4 Digital subsystem Digital subsystem and non-volatile memory
5 Entire system Overtemperature and redundancies for single point failures
6 Output Output verified through valid regulations states (external monitor)
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
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Power-On Behavior
During Power-on, the output voltage is in the fault state
(VOUT(FAULT)), which is the pull-up voltage (VPU), until the
device is ready to respond appropriately to the input magnetic
field (t > tON). If the device powers-on with the field within the
hysteresis band, the output will switch from VOUT(FAULT) to the
off state (VOUT(HIGH)) with standard output polarity as shown in
Figure 4. For inverted output polarity operation, the output will
switch from VOUT(FAULT) to VOUT(LOW) (not shown).
Temperature Coefficient and Magnet Selection
The APS12450 allows the user to select the magnetic temperature
coefficient to compensate for drifts of SmCo, NdFeB, and ferrite
magnets over temperature, as indicated in the Magnetic Char-
acteristics specifications table. This compensation improves the
magnetic system performance over the entire temperature range.
For example, the magnetic field strength from NdFeB decreases
as the temperature increases from 25°C to 150°C. This lower
magnetic field strength means that a lower switching threshold
is required to maintain switching at the same distance from the
magnet to the sensor. Correspondingly, higher switching thresh-
olds are required at cold temperatures, as low as –40°C, due to
the higher magnetic field strength from the NdFeB magnet. The
APS12450 compensates the switching thresholds over tempera-
ture as described above. It is recommended that system design-
ers evaluate their magnetic circuit over the expected operating
temperature range to ensure the magnetic switching requirements
are met.
A sample calculation is provided in the “Applications Informa-
tion” section.
Figure 4: Power-On Sequence
t
t
V
V
CC(MIN )
t
ON
0
Output Undefined for V
CC
< V
CC(MIN )
POS
V
OUT(LOW )
V
OUT(FAULT )
V
OUTPUT
SUPPLY VOLTAGE
V
OUT(HIGH)
B > B
OP
B < B
RP
B
RP
< B < B
OP
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
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Three-Wire Diagnostic Output
Three-wire diagnostic output enables the user to identify various
fault conditions external to the IC, in addition to the internal fault
detection. The output low (VOUT(LOW)) and high (VOUT(HIGH))
states are ratiometric to the pull-up voltage, with low and high
states being 20% and 80% respectively. For example, a VCC and
VPULL-UP of 5 V, the output state levels will be 1.0 V and 4.0 V
±0.5V.TheoutputRCtimeconstant(τ)mustbelessthan3µs
(e.g., RPU=3kΩandCOUT = 1 nF), and VPU must be equal to
VCC (recommend pulling up VOUT directly to VCC).
Under normal operation (Figure 5), the output switches between
the VOUT(LOW) (20%) and VOUT(HIGH) (80%) states.
Figure 5: The APS12450 diagnostic output under normal operation (no fault detected)
VCC
VOUT
GND
R
PULL-UP
C
OUT
C
BYPASS
Normal
Operation
V
OUT(HIGH )
(80%)
V
OUT(LOW)
(20%)
GND
V
OUT(FAULT )
(V
PU
)
With various opens and shorts on any of the IC pins, the output
will no longer be controlled by the IC. The output itself may
continue to switch, depending on the external connectivity fault;
however, the output level(s) observed will deviate from the 20%
and 80% (of VPU) output levels.
If an internal fault is detected via diagnostics monitoring, the
output will be set to the fault state, VOUT(FAULT), which is equal
to the pull-up voltage, VPU.
Any output voltage levels outside of the valid VOUT(HIGH) and
VOUT(LOW) ranges indicates a fault as shown in Figure 6. The
observed voltage on VOUT relative to potential fault conditions
are summarized in Table 2.
The output relative to the fault condition is summarized in Table 2
below.
Table 2: Fault Conditions and Resulting Output
Level
Fault Output Level
No Fault 20% or 80% of VPU,
respectively
Short, VCC-VOUT VCC
Short, VOUT-GND GND
Short, VCC-GND VPU
Open, VCC VPU
Open, VOUT VPU
Open, GND VPU
Internal Fault VPU
Note: VOUT(FAULT) ≤ VPULL-UP and VPULL-UP = VCC.
Figure 6: APS12450 valid (normal) and
fault condition output levels
Fault State
External Fault
External Fault
V
OUT(HIGH)
(max)
V
OUT(HIGH)
(min)
V
OUT(LOW)
(max)
V
OUT(LOW)
(min)
+ V
0
Range for valid V
OUT(LOW)
Range for valid V
OUT(HIGH)
90% V
PU
70% V
PU
30% V
PU
10% V
PU
V
PU
= V
CC V
OUT(FAULT )
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
16
Allegro MicroSystems
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Output Overshoot
When the output switches from VOUT(LOW) to VOUT(HIGH),
depending upon the RC circuit, a small overshoot can occur
(VOUT(H)OVER). VOUT(H)OVER is specified as a percentage of
VPULL-UP (and/or VCC, which need to be the same). Therefore
withanRCTimeConstant(τ)of3µs(seethe“Applications
Information” section), a nominal overshoot of 2% is possible.
With VPULL-UP at 5.0 V, the output may overshoot by 0.1 V, for
lessthan5µs(tVOUT(H)OVER). Figure 7 demonstrates output edge
profile.
For example, with a 5 V pull-up, if VOUT(HIGH) is at the upper limit
(90%), VOUT(HIGH)willbe4.5V.Withaτof3µsatroomtem-
perature, the output can briefly reach 4.6 V until it settles to 4.5 V.
Since VOUT(HIGH) is valid between 70% and 90%, or 3.5 and 4.5 V,
this condition is not out of specification. The Output Off Voltage
Overshoot specification pertains only to conditions where the over-
shoot is greater than the VOUT(HIGH)MAX specification.
Fault Detection and Retry
The fault detection diagnostics runs continuously in the background
during normal operation after the device has powered-on. In the
event a fault is detected, the output will immediately change to the
VOUT(FAULT) state. The diagnostics will continue to retry the diag-
nostics approximately every 2 ms. If the fault recovers, the output
will return to normal operation. See Figure 7.
Figure 7: Fault Detection and Retry
Figure 8: Output Overshoot
Output switches according
to external magne�c field
t
VOUT(LOW )
VOUT(FAU LT )
OUTPUT
VOUT(HIGH )
t
DIAG CHECK
Background
Diagnos�cs*
Background
Diagnos�cs*
Failure Detected Device Recovers
2 ms
Diag Retry**
2 ms
* 4x Diagnos�c Cycles completed every 0.025 ms (nom.)
** Diagnos�c Fault Retry Time interval is 2 ms (nom.)
Output switches according
to external magne�c field
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
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Allegro MicroSystems
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Typical Applications
For the LH and UA packages, an external bypass capacitor,
CBYP, should be connected (in close proximity to the Hall sen-
sor) between the supply and ground of the device to reduce both
external noise and noise generated by the chopper stabilization
technique. As is shown in Figure 9,a0.1µFbypasscapacitoris
typical, with an optional output capacitor, COUT (recommended
1 nF).
ThetimeconstantoftheRCcircuit(τ)onoutputmustbeless
than3µs,where:
τ =RPULLUP × COUT
=3kΩ×1nF
=3µs
The resistor, RPULLUP,mustbebetween2and30kΩ.
Temperature Compensation
To calculate the typical effect of the TCSENS on BOP (or BRP),
simply multiply the BOP at the starting temperature by TCSENS
and the change in temperature.
Sample BOP calculation for TCSENS compensation from 25°C to
150°C, for TCSENS = –0.12%/°C, and BOP(25C) = 180 G:
ΔTA = 150°C – 25°C = 125°C
BOP(150C) = BOP(25C) + (BOP(25C)×TC×ΔTA )
= 180 G + (180 G × –0.12%/°C × 125°C)
= 180 G + (–27 G)
= 153 G
APPLICATIONS INFORMATION
Figure 9: Typical Applications Circuits
Diagnostic Output
IC Output: Diagnostic Output
switching between V
OUT(LOW )
and V
OUT(HIGH )
VCC
VOUT
GND
R
PULL-UP
C
BYPASS
0.1 µF
R
SERIES
(optional)
C
OUT
(optional)
ECU
ADC
GPIO
V
PULL-UP
V
CC
Diagnostic Output*
VCC 3 to 30 V
VPU VCC
CBYP 0.1 µF
COUT τRC < 3 µs
RPU IOUT < 12 mA
τRC < 3 µs
2 kΩ < R < 30 kΩ
RS100 Ω*
* The following application circuit conditions are required
•TheτoftheRConoutputmustbe<3µs.
•2kΩ<RPU<30kΩ.
• VPU = VCC (recommend pulling VOUT up
to VCC).
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
18
Allegro MicroSystems
955 Perimeter Road
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Extensive applications information on magnets and Hall-effect
sensors is available in:
• Hall-Effect IC Applications Guide, AN27701
• Guidelines For Designing Subassemblies Using Hall-Effect
Devices, AN27703.1
• Soldering Methods for Allegro’s Products – SMT and Through-
Hole, AN26009
• Functional Safety Challenges to the Automotive Supply Chain
(https://www.allegromicro.com/en/Design-Center/Technical-
Documents/General-Semiconductor-Information/Functional-
Safety-Challenges-Automotive-Supply-Chain.aspx)
All are provided on the Allegro website:
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
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Allegro MicroSystems
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Amp
Regulator
Clock/Logic
Hall Element
Sample and
Hold
Low-Pass
Filter
Chopper Stabilization Technique
A limiting factor for switchpoint accuracy when using Hall-
effect technology is the small-signal voltage developed across
the Hall plate. This voltage is proportionally small relative to the
offset that can be produced at the output of the Hall sensor. This
makes it difficult to process the signal and maintain an accurate,
reliable output over the specified temperature and voltage range.
Chopper stabilization is a proven approach used to minimize
Hall offset.
The technique, dynamic quadrature offset cancellation, removes
key sources of the output drift induced by temperature and
package stress. This offset reduction technique is based on a
signal modulation-demodulation process. “Figure 10: Model of
Chopper Stabilization Circuit (Dynamic Offset Cancellation)”
illustrates how it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation. The
subsequent demodulation acts as a modulation process for the
offset causing the magnetically induced signal to recover its origi-
nal spectrum at baseband while the DC offset becomes a high-
frequency signal. Then, using a low-pass filter, the signal passes
while the modulated DC offset is suppressed. Allegro’s innovative
chopper-stabilization technique uses a high-frequency clock.
The high-frequency operation allows a greater sampling rate that
produces higher accuracy, reduced jitter, and faster signal pro-
cessing. Additionally, filtering is more effective and results in a
lower noise analog signal at the sensor output. Devices such as the
APS12450 that use this approach have an extremely stable quies-
cent Hall output voltage, are immune to thermal stress, and have
precise recoverability after temperature cycling. This technique is
made possible through the use of a BiCMOS process which allows
the use of low offset and low noise amplifiers in combination with
high-density logic and sample-and-hold circuits.
Figure 10: Model of Chopper Stabilization Circuit
(Dynamic O󰀨set Cancellation)
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
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The device must be operated below the maximum junction
temperature, TJ (max). Reliable operation may require derating
supplied power and/or improving the heat dissipation properties
of the application.
Thermal Resistance (junction to ambient), RθJA, is a figure of
merit summarizing the ability of the application and the device to
dissipate heat from the junction (die), through all paths to ambi-
ent air. RθJA is dominated by the Effective Thermal Conductivity,
K, of the printed circuit board which includes adjacent devices
and board layout. Thermal resistance from the die junction to
case, RθJC, is a relatively small component of RθJA. Ambient air
temperature, TA, and air motion are significant external factors in
determining a reliable thermal operating point.
The following three equations can be used to determine operation
points for given power and thermal conditions.
PD = VIN × IIN (1)
∆T=PD × RθJA (2)
TJ = TA+∆T (3)
For example, given common conditions: TA = 25°C, VCC = 12 V,
ICC = 4 mA, and RθJA = 110°C/W for the LH package, then:
PD = VCC × ICC = 12 V × 4 mA = 48 mW
∆T=PD × RθJA = 48 mW × 110°C/W = 5.28°C
TJ = TA+∆T=25°C+5.28°C=31.28°C
Determining Maximum VCC
For a given ambient temperature, TA, the maximum allow-
able power dissipation as a function of VCC can be calculated.
PD (max) represents the maximum allowable power level without
exceeding TJ (max) at a selected RθJA and TA.
Example: VCC at TA = 150°C, package UA, using low-K PCB.
Using the worst-case ratings for the device, specifically: RθJA =
165°C/W, TJ (max) = 165°C, VCC (max) = 24 V, and ICC (max) =
4 mA, calculate the maximum allowable power level, PD (max).
First, using equation 3:
∆T(max)=TJ (max) – TA = 165°C – 150°C = 15°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, from equation 2:
PD(max)=∆T(max)÷RθJA=15°C÷165°C/W=91mW
Finally, using equation 1, solve for maximum allowable VCC for
the given conditions:
VCC (est) = PD(max)÷ICC(max)=91mW÷4mA=22.8V
The result indicates that, at TA, the application and device can
dissipateadequateamountsofheatatvoltages≤VCC (est).
If the application requires VCC > VCC(est) then RθJA must by
improved. This can be accomplished by adjusting the layout,
PCB materials, or by controlling the ambient temperature.
Determining Maximum TA
In cases where the VCC (max) level is known, and the system
designer would like to determine the maximum allowable ambi-
ent temperature TA (max), for example, in a worst-case scenario
with conditions VCC (max) = 40 V, ICC (max) = 4 mA, and RθJA
= 228°C/W for the LH package using equation 1, the largest pos-
sible amount of dissipated power is:
PD = VIN × IIN
PD = 40 V × 4 mA = 160 mW
Then, by rearranging equation 3 and substituting with equation 2:
TA (max) = TJ(max)–ΔT
TA (max) = 165°C – (160 mW × 228°C/W)
TA(max)=165°C–36.5°C=128.5°C
In another example, the maximum supply voltage is equal to
VCC (min). Therefore, VCC (max) = 3 V and ICC (max) = 4 mA.
By using equation 1 the largest possible amount of dissipated
power is:
PD = VIN × IIN
PD=3V×4mA=12mW
Then, by rearranging equation 3 and substituting with equation 2:
TA (max) = TJ(max)–ΔT
TA (max) = 165°C – (12 mW × 228°C/W)
TA(max)=165°C–11.6°C=162.3°C
The example above indicates that at VCC = 3 V and ICC = 4 mA,
the TA (max) can be as high as 162.3°C without exceeding
TJ (max). However the TA (max) rating of the device is 150°C;
the device performance is not guaranteed above TA = 150°C.
POWER DERATING
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
21
Allegro MicroSystems
955 Perimeter Road
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Package LH, 3-Pin SOT23W
0.55 REF
Gauge Plane
Seating Plane
0.25 BSC
0.95 BSC
0.95
1.00
0.70
2.40
2
1
AActive Area Depth, 0.28 ±0.04 mm
B
C
C
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Branding scale and appearance at supplier discretion
A
PCB Layout Reference View
Standard Branding Reference View
1
Branded Face
Line 1 = Three digit assigned brand number
XXX
2.90 +0.10
–0.20
4°±4°
8× 10° ±5°
0.180+0.020
–0.053
0.05 +0.10
–0.05
0.25 MIN
1.91 +0.19
–0.06
2.975 +0.125
–0.75
1.00 ±0.13
0.40 ±0.10
For reference only; not for tooling use (reference DWG-0000628, Rev. 1).
Dimensions in millimeters.
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions.
Exact case and lead configuration at supplier discretion within limits shown.
DHall element, not to scale
D
D
D
1.49
0.96
3
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
22
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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Package UA, 3-Pin SIP, Matrix HD Style
2 31
1.27 NOM
1.02
MAX
45°
45°
C
1.52 ±0.05
B
Gate and tie bar burr area
A
B
C
Dambar removal protrusion (6×)
A
D
E
D
E
E
1.44 NOM
2.04 NOM
E
Active Area Depth, 0.50 ±0.08 mm
Branding scale and appearance at supplier discretion
Hall element (not to scale)
For reference only; not for tooling use (reference DWG-0000404, Rev. 1).
Dimensions in millimeters.
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions.
Exact case and lead configuration at supplier discretion within limits shown.
Standard Branding Reference View
XXX
1
Mold Ejector
Pin Indent
Line 1: Logo A
Line 2: Three digit assigned brand number
0.41 +0.03
–0.06
0.43 +0.05
–0.07
14.99 ±0.25
4.09 +0.08
–0.05
3.02 +0.08
–0.05
0.79 REF
10°
Branded
Face
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
23
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Copyright 2019, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
REVISION HISTORY
Number Date Description
– January 31, 2019 Initial release
1 April 23, 2019 Updated ASIL status