1/44
Description
The PC8240 combines a PowerPCTM 603e core microprocessor with a PCI bridge. The
PC8240’s PCI support will allow system designers to rapidly design systems using peripherals
already designed for PCI and the other standard interfaces. The PC8240 also integrates a high-
performance memory controller which supports various types of DRAM and ROM. The PC8240
is the first of a family of products that provide system level support for industry standard inter-
faces with a PowerPC microprocessor core.
The peripheral logic integrates a PCI bridge, memory controller, DMA controller , EPIC interrupt
controller, I2O controller, and an I2C controller. The 603e core is a full-featured, high-perfor-
mance processor with floating-point support, memory management, 16-Kbyte instruction
cache, 16-Kbyte data cache, and power management features. The integration reduces the
overall packaging requirements and the number of discrete devices required for an embedded
system.
The PC8240 contains an internal peripheral logic bus that interfaces the 603e core to the periph-
eral logic. The core can operate at a variety of frequencies, allowing the designer to trade of f
performance for power consumption. The 603e core is clocked from a separate PLL, which is
referenced to the peripheral logic PLL. This allows the microprocessor and the peripheral logic
block to operate at different frequencies, while maintaining a synchronous bus interface. The
interface uses a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit
address bus along with control signals that enable the interface between the processor and
peripheral logic to be optimized for performance. PCI accesses to the PC8240’s memory space
are passed to the processor bus for snooping purposes when snoop mode is enabled.
The PC8240’s features serve a variety of embedded applications. In this way, the 603e core and
peripheral logic remain general-purpose. The PC8240 can be used as either a PCI host or an
agent controller .
Features
H6.6 SPEC int 95, 5.5 SPECfp95 @ 266 MHz (estimated)
HSuperscalar 603e core
HInteger unit (IU), floating-point unit (FPU) (user enabled or disabled), load/
store unit (LSU), system register unit (SRU), and a branch processing unit
(BPU).
H16-Kbyte instruction cache
H16-Kbyte data cache
HLockable L1 caches-entire cache or on a per-way basis up to 3 of 4 ways.
HDynamic power management.
HHigh-bandwidth bus (32/64 bits data bus) to DRAM.
HSupports 1-Mbyte to 1-Gbyte DRAM memory.
H32-bit PCI interface operating up to 66 MHz.
HPCI 2.1-compliant, 5.0 V tolerance
HFint MAX = 250 MHz (tbc).
HFBus MAX = 66 MHz (tbc)
TBGA352
TP suffix
Tape Ball Grid Array
SCREENING/QUALITY/PACKAGING
This product is manufactured in full compliance with :
HUpscreening based upon TCS standards.
HFull military temperature range
(Tc = 55°C, Tc = +125°C)
HIndustrial temperature range
(Tc = -40°C, Tc = +110°C)
HCore power supply :
. 2.5 +/- 5 % V (L-Spec for 200 MHz)
. 2.50 V to 2.75 V (R-Spec for 250 MHz) (tbc)
HI/O power supply : 3.0 to 3.6 V
H352 Tape Ball Grid Array (TBGA).
PC8240
Integrated
Processor
Family
Preliminary
specification
alpha SITE
July 2000
2/44 PC8240
SUMMARY
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PC8240
3/44
A.GENERAL DESCRIPTION
1. BLOCK DIAGRAM
The PC8240 integrated processor is comprised of a peripheral logic block and a 32-bit superscalar PowerPC 603e core, as shown in
Figure 1.
Peripheral Logic
Instruction Unit
System Integer Load/Store Floating–
Address
Translator
DLL
Fanout
Buffers
PCI
Arbiter
Data Instruction
16–Kbyte
16–Kbyte
Message
Controller
(I2O)
I2C
Controller
DMA
Controller
Interrupt
Controller
EPIC
/Timers
PCI Bus
Interface Unit
Memory
Controller
Data Path
ECC Controller
Central
Control
Unit
32–Bit Oscillator
Five
Request/Grant
Pairs
I2C
5 IRQs/
603e Processor Core Block
Peripheral Logic Block
Processor
PLL
(64 bit) Two–instruction fetch
(64–bit) T wo–instruction dispatch
Peripheral Logic
PLL
SDRAM
PCI
PCI Bus
Data (64 bit)
Address Data Bus
(32– or 64–bit)
Memory/ROM/PortX
64 bit
PCI Interface Input
Clock In
Clocks
16 Serial
Interrupts
Branch
Processing
Unit
(BPU)
Bus
Configuration
Registers
Register
Unit
(SRU) Unit
(IU) Unit
(LSU) Point
Unit
(FPU)
(32 bit)
Data
Cache Instruction
Cache
MMUMMU
Additional features:
• JTAG/COP interface
• Power management
with 8–bit Parity
or ECC
Address and Control
Clocks
PC8240
Figure 1: Block Diagram
4/44 PC8240
2. PINOUT LISTINGS
Table 1 provides the pinout listing for the PC8240, 352 TBGA package.
Table 1. PC8240 Pinout Listing
Signal Name Package Pin Number Pin Type Power
Supply Output Driver Type Notes
PCI Interface Signals
C/BE[0–3] A25 F23 K23 P25 I/O OVdd DRV_PCI 6,15
DEVSEL H26 I/O OVdd DRV_PCI 8,15
FRAME J24 I/O OVdd DRV_PCI 8,15
IRDY K25 I/O OVdd DRV_PCI 8,15
LOCK J26 Input OVdd — 8
AD[0–31] C22 D22 B22 B23 D19 B24 A24
B26 A26 C26 D25 D26 E23 E25
E26 F24 L26 L25 M25 M26 N23
N25 N26 R26 R25 T26 T25 U23
U24 U26 U25 V25
I/O OVdd DRV_PCI 6,15
PAR G25 I/O OVdd DRV_PCI 15
GNT[0–3] V26 W23 W24 W25 Output OVdd DRV_PCI 6,15
GNT4/DA5 W26 Output OVdd DRV_PCI 7,15
REQ[0–3] AB26 AA25 AA26 Y25 Input OVdd — 6,12
REQ4/DA4 Y26 Input OVdd — 12
PERR G26 I/O OVdd DRV_PCI 8,15,18
SERR F26 I/O OVdd DRV_PCI 8,15,16
STOP H25 I/O OVdd DRV_PCI 8,15
TRDY K26 I/O OVdd DRV_PCI 8,15
INTA AC26 Output OVdd DRV_PCI 15,16
IDSEL P26 Input OVdd — —
Memory Interface Signals
MDL[0–31] AD17 AE17 AE15 AF15 AC14
AE13 AF13 AF12 AF11 AF10 AF9
AD8 AF8 AF7 AF6 AE5 B1 A1 A3
A4 A5 A6 A7 D7 A8 B8 A10 D10
A12 B11 B12 A14
I/O Gvdd DRV_MEM_DATA 5,6,13
MDH[0–31] AC17 AF16 AE16 AE14 AF14
AC13 AE12 AE11 AE10 AE9 AE8
AC7 AE7 AE6 AF5 AC5 E4 A2 B3
D4 B4 B5 D6 C6 B7 C9 A9 B10
A11 A13 B13 A15
I/O Gvdd DRV_MEM_DATA 6,13
PC8240
5/44
Signal Name NotesOutput Driver Type
Power
Supply
Pin TypePackage Pin Number
CAS/DQM[0–7] AB1 AB2 K3 K2 AC1 AC2 K1 J1 Output Gvdd DRV_MEM_ADDR 6
RAS/CS[0–7] Y4 AA3 AA4 AC4 M2 L2 M1 L1 Output Gvdd DRV_MEM_ADDR 6
FOE H1 I/O Gvdd DRV_MEM_ADDR 3,4
RCS0 N4 I/O Gvdd DRV_MEM_ADDR 3,4
RCS1 N2 Output Gvdd DRV_MEM_ADDR
SDMA[11 – 0] N1 R1 R2 T1 T2 U4 U2 U1 V1 V3
W1 W2 Output Gvdd DRV_MEM_ADDR 6,14
SDMA12/SDBA1 P1 Output Gvdd DRV_MEM_ADDR 14
SDBA0 P2 Output Gvdd DRV_MEM_ADDR —
PAR[0–7] AF3 AE3 G4 E2 AE4 AF4 D2 C2 I/O Gvdd DRV_MEM_DATA 6,13,14
SDRAS AD1 Output Gvdd DRV_MEM_ADDR 3
SDCAS AD2 Output Gvdd DRV_MEM_ADDR 3
CKE H2 Output Gvdd DRV_MEM_ADDR 3,4
WE AA1 Output Gvdd DRV_MEM_ADDR —
AS Y1 Output Gvdd DRV_MEM_ADDR 3,4
EPIC Control Signals
IRQ_0 / S_INT C19 Input Ovdd — —
IRQ_1 / S_CLK B21 I/O Ovdd DR V_PCI —
IRQ_2 / S_RST AC22 I/O Ovdd DRV_PCI —
IRQ_3 / S_FRAME AE24 I/O Ovdd DRV_PCI —
IRQ_4/ L_INT A23 I/O Ovdd DRV_PCI —
I2C Control Signals
SDA AE20 I/O Ovdd DRV_STD 10,16
SCL AF21 I/O Ovdd DRV_STD 10,16
Clock Out Signals
PCI_CLK [0–3] AC25 AB25 AE26 AF25 Output GVdd DRV_PCI_CLK 6
PCI_CLK4/DA3 AF26 Output GVdd DRV_PCI_CLK —
PCI_SYNC_OUT AD25 Output GVdd DRV_PCI_CLK —
PCI_SYNC_IN AB23 Input GVdd — —
SDRAM_CLK [0–3] D1 G1 G2 E1 Output GVdd DR V_MEM_ADDR 6
6/44 PC8240
Signal Name NotesOutput Driver Type
Power
Supply
Pin TypePackage Pin Number
SDRAM_SYNC_OUT C1 Output GVdd DRV_MEM_ADDR —
SDRAM_SYNC_IN H3 Input GVdd — —
CKO/DA1 B15 Output Ovdd DRV_STD —
OSC_IN AD21 Input Ovdd — —
Miscellaneous Signals
HRST_CTRL A20 Input OVdd — —
HRST_CPU A19 Input OVdd — —
MCP A17 Output OVdd DRV_STD 3,4,17
NMI D16 Input OVdd — —
SMI A18 Input OVdd — 10
SRESET B16 Input OVdd — 10
TBEN B14 Input OVdd — 10
QACK/DA0 F2 Output OVdd DRV_STD 3,4
CHKSTOP_IN D14 Input OVdd — 10
MAA[0–2] AF2 AF1 AE1 Output GVdd DR V_MEM_DATA 3,4,6
MIV A16 Output OVdd DRV_STD —
PMAA[0–2] AD18 AF18 AE19 Output OVdd DRV_STD 3,4,6,15
T est/Configuration Signals
PLL_CFG[0–4]/
DA[10–6] A22 B19 A21 B18 B17 Input OVdd — 4,6
TEST[0–1] AD22 B20 Input OVdd — 1,6,9
TEST2 Y2 Input GVdd — 11
TEST3 AF20 Input OVdd — 10
TEST4 AC18 I/O OVdd DRV_STD 10
TCK AF22 Input OVdd — 9,12
TDI AF23 Input OVdd — 9,12
TDO AC21 Output OVdd DRV_PCI —
TMS AE22 Input OVdd — 9,12
TRST AE23 Input OVdd — 9,12
PC8240
7/44
Signal Name NotesOutput Driver Type
Power
Supply
Pin TypePackage Pin Number
Power and Ground Signals
GND AA2 AA23 AC12 AC15 AC24 AC3
AC6 AC9 AD11 AD14 AD16
AD19 AD23 AD4 AE18 AE2 AE21
AE25 B2 B25 B6 B9 C11 C13
C16 C23 C4 C8 D12 D15 D18
D21 D24 D3 F25 F4 H24 J25 J4
L24 L3 M23 M4 N24 P3 R23 R4
T24 T3 V2 V23 W3
Ground
52 terminals
— — —
LVdd AC20 AC23 D20 D23 G23 P23
Y23 Reference
voltage
3.3v,5.0v
LVdd — —
GVdd AB3 AB4 AC10 AC11 AC8 AD10
AD13 AD15 AD3 AD5 AD7 C10
C12 C3 C5 C7 D13 D5 D9 E3 G3
H4 K4 L4 N3 P4 R3 U3 V4 Y3
Power for
Memory
Drivers
2.5v,3.3v
GVdd — —
Ovdd AB24 AD20 AD24 C14 C20 C24
E24 G24 J23 K24 M24 P24 T23
Y24
PCI / Stnd
3.3v Ovdd — —
Vdd AA24 AC16 AC19 AD12 AD6
AD9 C15 C18 C21 D11 D8 F3
H23 J3 L23 M3 R24 T4 V24 W4
Power for
Core 2.5v Vdd — —
LAVdd D17 Power for
DLL 2.5v LAVdd — —
AVdd C17 Power for
PLL (CPU
Core Logic)
2.5v
AVdd — —
AVdd2 AF24 Power for
PLL
(Peripheral
Logic) 2.5v
AVdd2 — —
Manufacturing Pins
DA2 C25 I/O OVdd DRV_PCI 2
DA[11–13] AD26 AF17 AF19 I/O OVdd DRV_PCI 2,6
DA[14–15] F1 J2 I/O GVdd DRV_MEM_ADDR 2,6
Notes :
1Place pull-up resistors of 120 Ohms or less on the TEST[0–1] pins.
2Treat these pins as No Connects unless using debug address functionality.
3This pin has an internal pull-up resistor which is enabled only when the PC8240 is in the reset state. The value of the internal
pull-up resistor is not guaranteed, but is sufficient to insure that a ’1’ is read into configuration bits during reset.
4This pin is a reset configuration pin.
8/44 PC8240
5DL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the PC8240 is in the reset state.
The value of the internal pull-up resistor is not guaranteed, but is sufficient to insure that a ’1’ is read into configuration bits during
reset.
6Multi-pin signals such as AD[0–31] or DL[0–31] have their physical package pin numbers listed in order corresponding to the
signal names. Ex: AD0 is on pin C22, AD1 is on pin D22,... AD31 is on pin V25.
7GNT4 is a reset configuration pin and has an internal pull-up resistor which is enabled only when the PC8240 is in the reset state.
The value of the internal pull-up resistor is not guaranteed, but is sufficient to insure that a ’1’ is read into configuration bits during
reset.
8Recommend a weak pull-up resistor (2K – 10K Ohm) be placed on this PCI control pin to LVdd.
9VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table “. DC Electrical Specifications”.
10 Recommend a weak pull-up resistor (2K – 10K Ohm) be placed on this pin to OVdd.
11 Recommend a weak pull-up resistor (2K – 10K Ohm) be placed on this pin to GVdd.
12 This pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is sufficient to prevent
unused inputs from floating.
13 Output V alid specifications for this pin are memory interface mode dependent (Registered or Flow-through), see T able “. Output
AC Timing Specifications”.
14 Non-DRAM Access Output Valid specification applies to this pin during non-DRAM accesses, see specification 12b3 in Table
“Output AC Timing Specifications”.
15 This pin is affected by programmable PCI_HOLD_DEL parameter, see Section AUCUN LIEN “PCI Signal Output Hold Timing”.
16 This pin is an open drain signal.
17 This pin can be programmed to be driven (default) or can be programmed to be open drain; see PMCR2 register description in
the MOTOROLA PC8240 User’s Manual for details.
18 This pin is a Sustained Tri-State pin as defined by the
PCI Local Bus Specification.
PC8240
9/44
B.DETAILED SPECIFICATIONS
1. SCOPE
This drawing describes the specific requirements for the PC8240 processor, in compliance with TCS standard screening.
2. APPLICABLE DOCUMENTS
1) MIL-STD-883 : Test methods and procedures for electronics.
2) MIL-PRF-38535 : General specifications for microcircuits.
3. REQUIREMENTS
3.1. General
The microcircuits are in accordance with the applicable documents and as specified herein.
3.2. Design and construction
3.2.1. Terminal connections
The terminal connections are shown Table 1 (§ A. GENERAL DESCRIPTION).
3.3. Absolute maximum ratings
Absolute maximum ratings are stress rating only and functional operation at the maximum is not guaranteed. Stresses beyond those
listed may affect device reliability or cause permanent damage to the device.
Table 2. Absolute maximum rating for the PC8240
Characteristic1Symbol Range Unit
Supply Voltage - CPU Core and Peripheral Logic Vdd -0.3 to 2.75 V
Supply V oltage - Memory Bus Drivers GVdd -0.3 to 3.6 V
Supply V oltage - PCI and Standard I/O Buf fers OVdd -0.3 to 3.6 V
Supply Voltage - PLLs and DLL AVdd/AVdd2/LAVdd -0.3 to 2.75 V
Supply V oltage - PCI Reference VIN -0.3 to 3.6 V
Input Voltage2LVdd -0.3 to 5.4 V
Storage Temperature Range TSTG -55 to 150 C
Notes:
1Functional and tested operating conditions are given in T able 2. Absolute maximum ratings are stress ratings only, and functional
operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage ot the device.
2PCI inputs with LVdd = 5 V 5 % V DC may be correspondingly stressed at voltages exceeding LVdd + 0.5 V DC.
10/44 PC8240
3.4. Recommended Operating Conditions
Table 3. Recommended Operating Conditions
Characteristic1Symbol Recommended
Value Unit Notes
Supply Voltage Vdd 2.5 " 5 % V 4,6
I/O Buf fer supply for PCI and Standard OVdd 3.3 " 0.3 V 6
Supply V oltages for Memory Bus Drivers GVdd 3.3 " 5 % V 8
2.5 " 5 % V 8
PLL Supply Voltage - CPU Core Logic AVdd 2.5 " 5 % V 4,6
PLL Supply Voltage - Peripheral Logic AVdd2 2.5 " 5 % V 4,7
DLL Supply Voltage LAVdd 2.5 " 5 % V 4,7
PCI Reference LVdd 5.0 " 5 % V 9,10
3.3 " 0.3 V 9,10
Input Voltage PCI Inputs VIN 0 to 3.6 or 5.75 V 2,3
All Other Inputs 0 to 3.6 V 5
Operating Temperature TC-55 to +125 C
Note :
1These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaran-
teed.
2PCI pins are designed to withstand LVdd + 0.5 V dc when LVdd is connected to a 5.0V dc power supply.
3PCI pins are designed to withstand LVdd + 0.5 V dc when LVdd is connected to a 3.3 V dc power supply.
4Voltage specification is 2.50 V to 2.70 V for R-Spec (250 MHz)
Cautions:
5Input voltage (VIN) must not be greater than the supply voltage (Vdd/AVdd/AVdd2/LAVdd) by more than 2.5 V at all times including
during power-on reset.
6OVdd must not exceed Vdd/AVdd/AVdd2/LAVdd by more than 1.8 V at any time including during power-on reset.
7Vdd/AVdd/AVdd2/LAVdd must not exceed OVdd by more than 0.6 V at any time including during power-on reset.
8GVdd must not exceed Vdd/AVdd/AVdd2/LAVdd by more than 1.8 V at any time including during power-on reset.
9LVdd must not exceed Vdd/AVdd/AVdd2/LAVdd by more than 5.4 V at any time including during power-on reset.
10 LVdd must not exceed OVdd by more than 3.6 V at any time including during power-on reset.
PC8240
11/44
.
OVdd/GVdd/(LVdd@3.3V – – – –)
Vdd/AVdd/AVdd2/LAVdd
LVdd@5V
Time
3.3V
5V
2.5V
0
7
10 9
9
10
6,8
DC Power Supply Voltage
Voltage
Regulator
Reset
Configuration Pins
HRST_CPU &
HRST_CTRL
PLL
Relock
9 external memory
asserted 255
external memory
HRST_CPU &
HRST_CTRL
Vdd Stable
See Note 1 below.
VM = 1.4 V
Maximum rise time must be less than
100
µ
s
Time
3
Delay
2
Power Supply Ramp Up
2
Clock cycles
3
clock cycles setup time
4
one external memory clock cycle
5
Note :
1Numbers associated with waveform separations correspond to caution numbers listed in Table 3 “Recommended Operating
Conditions”.
2Refer to Paragraph “Power Supply V oltage Sequencing” (see summary) for additional information on this topic.
3Refer to Table 9 for additional information on PLL Relock and reset signal assertion timing requirements.
4Refer to Table 10 for additional information on reset configuration pin setup timing requirements.
5HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the device
to be in the non-reset state.
Figure 2: Supply Voltage Sequencing and Separation Cautions
12/44 PC8240
Figure 3 shows the undershoot and overshoot voltage of the memory interface of the PC8240.
Gnd
Gnd – 0.3V
Gnd – 1.0V
Not to exceed 10%
GVdd
of tSDRAM_CLK
GVdd + 5%
4 V
VIH
VIL
Figure 3: Overshoot/Undershoot Voltage
3.5. Thermal information
3.5.1. Thermal characteristics
Table 4 provides the package thermal characteristics for the PC8240.
Table 4. Package Thermal Characteristics
Characteristics Symbols Min Units
Die Junction-to-Case Thermal Resistance θJC 1.8 C/W
Die Junction-to-Board Thermal Resistance θJB 4.8 C/W
3.5.2. Thermal Management Information
This section provides thermal management information for the tape ball grid array (TBGA) package for air-cooled applications. Proper
thermal control design is primarily dependent upon the system-level design-the heat sink, airflow and thermal interface material. To
reduce the die-junction temperature, heat sinks may be attached to the package by several methods-adhesive, spring clip to holes in
the printed-circuit board or package, and mounting clip and screw assembly; see Figure 4.
Adhesive
or
Thermal Interface
Heat Sink TBGA Package
Heat Sink
Clip
Printed–Circuit Board Option
Material
Die
Figure 4: Package Exploded Cross-Sectional View with Several Heat Sink Options
PC8240
13/44
Figure 5 depicts the die junction-to-ambient thermal resistance for four typical cases:
1A heat sink is not attached to the TBGA package and there exists high board-level thermal loading of adjacent components.
2A heat sink is not attached to the TBGA package and there exists low board-level thermal loading of adjacent components.
3A heat sink (e.g. ChipCoolers #HTS255-P) is attached to the TBGA package and there exists high board-level thermal loading
of adjacent components.
4A heat sink (e.g. ChipCoolers #HTS255-P) is attached to the TBGA package and there exists low board-level thermal loading
of adjacent components.
2
4
6
8
10
12
14
16
18
0 0.5 1 1.5 2 2.5
Die Junction–to–Ambient Thermal Resistance (*ring*C/W)
Airflow Velocity (m/s)
No heat sink and high thermal board–level loading of
adjacent components
No heat sink and low thermal board–level loading of
adjacent components
Attached heat sink and high thermal board–level loading of
adjacent components
Attached heat sink and low thermal board–level loading of
adjacent components
Figure 5: Die Junction-to-Ambient Resistance
The board designer can choose between several types of heat sinks to place on the PC8240. There are several
commercially-available heat sinks for the PC8240 provided by the following vendors:
Chip Coolers Inc. 800-227-0254 (USA/Canada)
333 Strawberry Field Rd. 401-739-7600
W arwick, RI 02887-6979
Internet: www .chipcoolers.com
International Electronic Research Corporation (IERC) 818-842-7277
135 W . Magnolia Blvd.
Burbank, CA 91502
Internet: www .ctscorp.com
Thermalloy 972-243-4321
2021 W. Valley V iew Lane
Dallas, TX 75234-8993
Internet: www .thermalloy.com
14/44 PC8240
W akefield Engineering 781-406-3000
100 Cummings Center, Suite 157H
Beverly, MA 01915
Internet: www .wakefield.com
Aavid Engineering 972-551-7330
250 Apache Trail
Terrell, TX 75160
Internet: www .aavid.com
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air veloc-
ity, spatial volume, mass, attachment method, assembly, and cost.
3.5.3. Internal Package Conduction Resistance
For the TBGA, cavity down, packaging technology, shown in Figure 4, the intrinsic conduction thermal resistance paths are as fol-
lows:
DThe die junction-to-case thermal resistance
DThe die junction-to-ball thermal resistance
Figure 6 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
External Resistance
External Resistance
Internal Resistance
(Note the internal versus external package resistance)
Radiation Convection
Radiation Convection
Heat Sink
Printed–Circuit Board
Thermal Interface Material
Package/Leads
Die Junction
Die/Package
Figure 6: C4 Package with Heat Sink Mounted to a Printed-Circuit Board
For this cavity-down, wire-bond TBGA package, heat generated on the active side of the chip is conducted through the silicon, the die
attach and package spreader, then through the heat sink attach material (or thermal interface material), and finally to the heat sink
where it is removed by forced-air convection.
3.5.3.1. Adhesives and Thermal Interface Materials
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For
those applications where the heat sink is attached by spring clip mechanism, Figure 7 shows the thermal performance of three thin-
sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of
contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The
use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance
approximately 7 times greater than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 6). Therefore, the
synthetic grease offers the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal
interface material depends on many factors—thermal performance requirements, manufacturability, service temperature, dielectric
properties, cost, etc.
PC8240
15/44
0
0.5
1
1.5
2
0 1020304050607080
Silicone Sheet (0.006 inch)
Bare Joint
Floroether Oil Sheet (0.007 inch)
Graphite/Oil Sheet (0.005 inch)
Synthetic Grease
Contact Pressure (PSI)
Specific Thermal Resistance (Kin2/W)
Figure 7: Thermal Performance of Select Thermal Interface Material
The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based
upon high conductivity , yet adequate mechanical strength to meet equipment shock/vibration requirements. There are several com-
mercially-available thermal interfaces and adhesive materials provided by the following vendors:
Dow-Corning Corporation 800-248-2481
Dow-Corning Electronic Materials
PO Box 0997
Midland, MI 48686-0997
Internet: www .dow .com
Chomerics, Inc. 781-935-4850
77 Dragon Court
Woburn, MA 01888-4014
Internet: www .chomerics.com
Thermagon Inc. 888-246-9050
3256 West 25th Street
Cleveland, OH 44109-1668
Internet: www .thermagon.com
Loctite Corporation 860-571-5100
1001 Trout Brook Crossing
Rocky Hill, CT 06067-3910
Internet: www .loctite.com
The following section provides a heat sink selection example using one of the commercially available heat sinks.
16/44 PC8240
3.5.4. Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
TJ = TA + TR + (θJC + θINT + θSA) * PD
Where:
TJ is the die-junction temperature
TA is the inlet cabinet ambient temperature
TR is the air temperature rise within the computer cabinet
θJC is the junction-to-case thermal resistance
θINT is the adhesive or interface material thermal resistance
θSA is the heat sink base-to-ambient thermal resistance
PD is the power dissipated by the device
During operation the die-junction temperatures (TJ) should be maintained less than the value specified in Table . The temperature of
the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic
cabinet. An electronic cabinet inlet-air temperature (TA) may range from 30 to 40 ¡C. The air temperature rise within a cabinet (TR) may
be in the range of 5 to 10 ¡C. The thermal resistance of the thermal interface material (θINT) is typically about 1 ¡C/W. Assuming a TA of
30 ¡C, a TR of 5 ¡C, a TBGA package θJC = 1.8, and a power consumption (PD) of 5.0 watts, the following expression for TJ is obtained:
Die-junction temperature: TJ = 30 ¡C + 5 ¡C + (1.8 ¡C/W + 1.0 ¡C/W + θSA) * 5.0 W
For preliminary heat sink sizing, the heat sink base-to-ambient thermal resistance is needed from the heat sink manufacturer.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for compar-
ing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this
metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The
final die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design
and its operating conditions. In addition to the component’s power consumption, a number of factors affect the final operating die-junc-
tion temperature-airflow, board population (local heat flux of adjacent components), heat sink ef ficiency, heat sink attach, heat sink
placement, next-level interconnect technology, system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today’ s microelectronic equipment, the com-
bined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely . For these reasons, we recom-
mend using conjugate heat transfer models for the board, as well as, system-level designs. To expedite system-level thermal analy-
sis, several “compact” thermal-package models are available within FLOTHERM. These are available upon request.
PC8240
17/44
3.6. Power consideration
Table 5 provides
preliminary
power consumption data for the PC8240.
Table 5. Preliminary Power Consumption
At recommended operating conditions (see Table 3) with GVdd = 3.3 V " 5 % and LVdd = 3.3 V " 5%
Mode PCI Bus Clock / Memory Bus Clock
CPU Clock Frequency (MHz) Units Notes
33/66/
166 33/66/
200 33/66/
233 33/83/
250 33/100/
200 33/100/
250 66/100/
200 66/100/
250
Typical 2.5 2.8 3.2 3.4 3.0 3.5 3.0 3.6 W1, 5
Max - FP 3.0 3.4 3.8 4.1 3.6 4.2 3.6 4.3 W1, 2
Max - INT 2.7 3.0 3.4 3.7 3.3 3.8 3.4 3.8 W1, 3
Doze 1.8 2.0 2.2 2.4 2.2 2.6 2.2 2.6 W1, 4, 6
Nap 700 700 700 800 900 900 900 900 mW 1, 4, 6
Sleep 500 500 500 500 500 500 800 800 mW 1, 4, 6
I/O Power Supplies
Mode Minimum Maximum Units Notes
Typ - OVdd 200 600 mW 7,8
Typ - GVdd 300 900 mW 7,9
Notes:
1The values include Vdd, AVdd, AVdd2, and LVdd but do not include I/O Supply Power, see Section 6.3.3 for information on OVdd
and GVdd supply power.
2Maximum - FP power is measured at Vdd = 2.625V with dynamic power management enabled while running an entirely cache-
resident, looping, floating point multiplication instruction.
3Maximum - INT power is measured at Vdd = 2.625V with dynamic power management enabled while running entirely cache-resi-
dent, looping, integer instructions.
4Power saving mode maximums are measured at Vdd = 2.625V while the device is in doze, nap, or sleep mode.
5Typical power is measured at Vdd = AVdd = 2.5V, OVdd = 3.3V where a nominal FP value, a nominal INT value, and a value
where there is a continuous flush of cache lines with alternating ones and zeroes on 64 bit boundaries to local memory are aver-
aged.
6Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7The typical minimum I/O power values were results of the PC8240 performing cache resident integer operations at the slowest
frequency combination of 33:66:166 (PCI:Mem:CPU) MHz.
8The typical maximum OVdd value resulted from the PC8240 operating at the fastest frequency combination of 66:100:250
(PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeroes to PCI memory.
9The typical maximum GVdd value resulted from the PC8240 operating at the fastest frequency combination of 66:100:250
(PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeroes on 64 bit boundaries
to local memory.
Note:
To calculate the power consumption at low temperature (-55°C), use a 1.25 factor .
18/44 PC8240
3.7. Marking
The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible and
permanently marked with the following information as minimum :
- ATMEL Logo,
- Manufacturer’s part number,
- Class B identification if applicable,
- Date-code of inspection lot,
- ESD identifier if available,
- Country of manufacturing.
4. ELECTRICAL CHARACTERISTICS
4.1. Static characteristics
Table 6 provides the DC electrical characteristics for the PC8240.
Table 6. DC Electrical Specifications
At recommended operating conditions (See Table 3)
Characteristics Conditions4Symbols Min Max Units
Input High Voltage PCI only VIH 0.5*OVdd LVdd V
Input Low Voltage PCI only VIL — .3*OVdd V
Input High Voltage All other pins (GVdd = 3.3V) VIH 2.0 3.3 V
Input High Voltage All other pins (GVdd = 2.5V) VIH 1.8 2.5 V
Input Low Voltage All inputs except OSC_IN VIL GND 0.8 V
PCI_SYNC_IN Input High Voltage CVIH 0.5*OVdd — V
PCI_SYNC_IN Input Low Voltage CVIL GND 0.3*OVdd V
Input Leakage Current5 for pins
using DRV_PCI driver . 0.5 V VIN 2.7 V
@ LVdd = 4.75 IL— 70 A
Input Leakage Current5 for pins
using DRV_PCI driver . 0.5 V VIN 5.5 V
@ LVdd = 5.5 IL— TBD A
Input Leakage Current5 all others LVdd = 3.6 V
GVdd 3.465 IL— 10 A
Output High Voltage IOH=N/A3 (GVdd = 3.3V) VOH 2.4 — V
Output Low Voltage IOL=N/A3 (GVdd = 3.3V) VOL — 0.4 V
Output High Voltage IOH=N/A3 (GVdd = 2.5V) VOH 1.85 — V
Output Low Voltage IOL=N/A3 (GVdd = 2.5V) VOL — 0.6 V
Capacitance2VIN=0 V, f=1MHz CIN — 7.0 pF
PC8240
19/44
Notes:
1See Table for pins with internal pull-up resistors.
2Capacitance is periodically sampled rather than 100% tested.
3See Table for the typical drive capability of a specific signal pin based upon the type of output driver associated with that pin
as listed in .
4These specifications are for the default driver strengths indicated in Table .
5Leakage current is measured on input pins and on output pins in the high impedance state. The leakage current is measured
for nominal OVdd/LVdd and Vdd or both Ovdd/LVdd and Vdd must vary in the same direction.
T able 7 provides information on the characteristics of the output drivers referenced in . The values are from the PC8240 IBIS model
(v1.0) and are not tested, for additional detailed information see the complete IBIS model listing at http://www.mot.com/SPS/Pow-
erPC/teksupport/tools/IBIS/kahlua_1.ibs.txt
Table 7. Drive Capability of PC8240 Output Pins
Driver Type Programmable
Output
Impedance (Ohms)
Supply
Voltage IOH IOL Units Notes
DRV_STD 20 OVdd = 3.3V TBD TBD mA 2, 5
40 (default) OVdd = 3.3V TBD TBD mA 2, 5
25 LVdd = 3.3 11.0 20.6 mA 1, 4
DRV_PCI LVdd = 5.0 5.6 10.3 mA 1,4
50 (default) LVdd = 3.3 5.6 10.3 mA 1, 4
LVdd = 5.0 5.6 10.3 mA 1, 4
8 (default) GVdd = 2.5 TBD TBD mA 3, 6
GVdd = 3.3 89.0 76.3 mA 2, 5
DRV_MEM_ADDR 13.3 GVdd = 2.5 TBD TBD mA 3, 6
DRV_PCI_CLK GVdd = 3.3 55.9 46.4 mA 2, 5
20 GVdd = 2.5 TBD TBD mA 3, 6
GVdd = 3.3 36.7 30.0 mA 2, 5
40 GVdd = 2.5 TBD TBD mA 3, 6
GVdd = 3.3 TBD TBD mA 2, 5
20 (default) GVdd = 2.5 TBD TBD mA 3, 6
GVdd = 3.3 36.7 30.0 mA 2, 5
DRV_MEM_DATA 40 GVdd = 2.5 TBD TBD mA 3, 6
GVdd = 3.3 18.7 15.0 mA 2, 5
20/44 PC8240
Notes:
1For DRV_PCI, IOH read from the listing in the pull-up mode, I(Min) column, at the 0.33V label by interpolating between the 0.3 V
and 0.4 V table entries’ current values which corresponds to the PCI VOH = 2.97 = 0.9*LVdd (LVdd = 3.3 V) where Table Entry
Voltage = LVdd - PCI VOH.
2For all others with Ovdd or GVdd = 3.3 V, IOH read from the listing in the pull-up mode, I(Min) column, at the 0.9 V table entry
which corresponds to the VOH = 2.4 V where Table Entry Voltage = O/GVdd - PCI VOH.
3For GVdd = 2.5 V, IOH read from the listing in the pull-up mode, I(Min) column, at the TBD V table entry which corresponds to
the VOH = TBD V where Table Entry V oltage = GVdd - V OH.
4For DRV_PCI, IOL read from the listing in the pull-down mode, I(Max) column, at 0.33 V = PCI VOL = 0.1*LVdd (LVdd = 3.3 V)
by interpolating between the 0.3 V and 0.4 V table entries.
5For all others with OVdd or GVdd = 3.3 V , IOL read from the listing in the pull-down mode, I(Max) column, at the 0.4 V table entry .
6For GVdd = 2.5 V, IOL read from the listing in the pull-down mode, I(Max) column, at the TBD V table entry.
4.2. Dynamic Electrical Characteristics
This section provides the AC electrical characteristics for the PC8240. After fabrication, functional parts are sorted by maximum pro-
cessor core frequency as shown in Table and Section , “ Clock AC Timing Specifications” in table 9 and tested for conformance to
the AC specifications for that frequency. The processor core frequency is determined by the bus (PCI_SYNC_IN) clock frequency and
the settings of the PLL_CFG[0-4] signals. Parts are sold by maximum processor core frequency; see Section <1>. , “Ordering
Information”.
Table 8 provides the operating frequency information for the PC8240.
Table 8. Operating Frequency
At recommended operating conditions (See Table 3) with GVdd = 3.3 V " 5% and LVdd = 3.3 V " 5%
Characteristic1 200 MHz 250 MHz Units
Min Max Min Max
Processor Frequency (CPU) 100 200 100 250 MHz
Memory Bus Frequency 25 – 100 MHz
PCI Input Frequency 25 – 66 MHz
Notes:
1Caution: The PCI_SYNC_IN frequency and PLL_CFG[0–4] settings must be chosen such that the resulting peripheral logic/
memory bus frequency, CPU (core) frequency , and PLL (VCO) frequencies do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL_CFG[0–4] signal description in Section 6.2., “PLL Configuration,” for valid
PLL_CFG[0–4] settings and PCI_SYNC_IN frequencies.
PC8240
21/44
4.2.1. Clock AC Specifications
Table 9 provides the clock AC timing specifications as defined in Section
Table 9. Clock AC Timing Specifications
At recommended operating conditions (See Table 3) with GVdd = 3.3 V " 5% and LVdd = 3.3 V " 5%
Num Characteristics and Conditions 1Min Max Unit Notes
Frequency of Operation (PCI_SYNC_IN) 25 66 MHz
1PCI_SYNC_IN Cycle Time 40 15 ns
2,3 PCI_SYNC_IN Rise and Fall Times — 2.0 ns 2
4PCI_SYNC_IN Duty Cycle Measured at 1.4 V. 40 60 %
5a PCI_SYNC_IN Pulse Width High Measured at 1.4V 6 9 ns 3
5b PCI_SYNC_IN Pulse Width Low Measured at 1.4V 6 9 ns 3
7PCI_SYNC_IN Short Term Jitter (Cycle to Cycle) — <500 ps
8a PCI_CLK[0–4] Skew (Pin to Pin) 0 500 ps
8b SDRAM_CLK[0–3] Skew (Pin to Pin) TBD TBD ps 8
9PCI_SYNC_IN Long Term Jitter — <500 ps
10 Internal PLL Relock Time — 100 µs 3,4,6
DLL Lock Range with DLL_EXTEND = 0 disabled (Default) 0 (NTclk - tloop - tfix0) 7 ns 7
DLL Lock Range with DLL_EXTEND = 1 enabled 0 (NTclk - Tclk/2 - tloop - tfix0) 7 ns 7
Frequency of Operation (OSC_IN) 25 66 MHz
OSC_IN Cycle Time 40 15 ns
OSC_IN Rise and Fall Times — 5 ns 5
OSC_IN Duty Cycle Measured at 1.4 V. 40 60 %
OSC_IN Frequency Stability — 100 ppm
OSC_IN Jitter (Cycle to Cycle) — <TBD ps
OSC_IN VIH (Loaded) TBD V
OSC_IN VIL (Loaded) TBD V
Notes:
1These specifications are for the default driver strengths indicated in Table 7.
2Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.
3Specification value at maximum frequency of operation.
4Relock time is guaranteed by design and characterization. Relock time is not tested.
5Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are not
tested.
22/44 PC8240
6Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable Vdd
and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRST_CPU / HRST_CTRL must be held asserted for a minimum
of 255 bus clocks after the PLL-relock time during the reset sequence.
7DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (1, 2, 3, ...). Tclk is the period of one
SDRAM_SYNC_OUT clock cycle in ns. tloop is the propagation delay of the DLL synchronization feedback loop (PC board run-
ner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner) corresponds
to approximately 1 ns of delay. tfix0 is a fixed delay inherent in the design when the DLL is at tap point 0 and the DLL is contributing
no delay; tfix0 equals approximately 3 ns. See Figure 9 for DLL locking ranges.
8Pin to pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any intentional skew
added to the clocking signals from the variable length DLL synchronization feedback loop, i.e. the amount of variance between
the internal sys-logic_clk and the SDRAM_SYNC_IN signal after the DLL is locked. While pin to pin skew between
SDRAM_CLKs can be measured, the relationship between the internal sys-logic_clk and the external SDRAM_SYNC_IN can
not be measured and is guaranteed by design.
.
5a 5b
VM
VM = Midpoint Voltage (1.4V)
2 3
CVIL
CVIH
1
PCI_SYNC_IN VM VM
Figure 8: PCI_SYNC_IN Input Clock Timing Diagram
DLL not guaranteed to lock
N = 1
DLL_EXTEND = 0
N = 2
DLL_EXTEND = 0
N = 1
DLL_EXTEND = 1
N = 2
DLL_EXTEND = 1
DLL will lock
0 ns
Tloop Propagation Delay Time in Nanoseconds
Tclk SDRAM_SYNC_OUT Period and Frequency
5 ns 10 ns 15 ns
100 MHz
10 ns
50 MHz
20 ns
33 MHz
30 ns
25 MHz
40 ns
Figure 9: DLL Locking Range Loop Delay vs. Frequency of Operation
PC8240
23/44
4.2.2. Input AC Timing Specifications
Table 10 provides the input AC timing specifications. See Figure 10 and Figure 11.
Table 10. Input AC Timing Specifications
At recommended operating conditions (See Table 3) with GVdd = 3.3 V " 5% and LVdd = 3.3 V " 5%
Num Characteristic Min Max Units Notes
10a PCI Input Signals Valid to PCI_SYNC_IN (Input Setup) 2.0 — ns 2,3
10b1 Memory Control & Data Input Signals in Flow Through Mode
Valid to SDRAM_SYNC_IN (Input Setup) 4.0 — ns 1,3
10b2 Memory Control & Data Input Signals in Registered Mode
Valid to SDRAM_SYNC_IN (Input Setup) TBD — ns 1,3
10c Epic, Misc. Debug Input Signals Valid to SDRAM_SYNC_IN
(Input Setup) TBD — ns 1,3
10d I2C Input Signals Valid to SDRAM_SYNC_IN (Input Setup) TBD — ns 1,3
10e Mode select Inputs Valid to HRST_CPU / HRST_CTRL (Input Setup) 9*tCLK — ns 1,3-5
11a PCI_SYNC_IN (SDRAM_SYNC_IN) to Inputs Invalid (Input Hold) 1.0 — ns 1,2,3
11b HRST_CPU / HRST_CTRL to Mode select Inputs Invalid (Input Hold) TBD — ns 1,3,5
Notes:
1All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question
to the VM = 1.4 V of the rising edge of the memory bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same as
PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every
rising and falling edge of PCI_SYNC_IN). See Figure 10.
2All PCI signals are measured from OVdd/2 of the rising edge of PCI_SYNC_IN to 0.4*OVdd of the signal in question for 3.3 V
PCI signaling levels. See Figure 11.
3Input timings are measured at the pin.
4tCLK is the time of one SDRAM_SYNC_IN clock cycle.
5All mode select input signals specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the VM
= 1.4 V of the rising edge of the HRST_CPU / HRST_CTRL signal. See Figure 12.
.
11a
VM
VM = Midpoint Voltage (1.4V)
MEMORY
10b–d
PCI_SYNC_IN
INPUTS/OUTPUTS
13b
14b
VM
VM
SDRAM_SYNC_IN
shown in 2:1 mode
Input Timing Output Timing
12b–d
2.0 V
0.8 V
0.8 V
2.0 V
Figure 10: Input - Output Timing Diagram Referenced to SDRAM_SYNC_IN
24/44 PC8240
OVdd?2
10a
11a
PCI_SYNC_IN
PCI
12a 13a
14a
OVdd?2
OVdd?2
0.4*OVdd
0.615*OVdd
0.285*OVdd
Input Timing Output T iming
INPUTS/OUTPUTS
Figure 11: Input - Output Timing Diagram Referenced to PCI_SYNC_IN
.
VM
VM = Midpoint Voltage (1.4V)
11b
MODE PINS
10e
HRST_CPU / HRST_CTRL
2.0 V
0.8 V
Figure 12: . Input Timing Diagram for Mode Select Signals
PC8240
25/44
4.2.3. Output AC Timing Specification
Table 11 provides the processor bus AC timing specifications for the PC8240. See Figure 10 and Figure 11.
Table 11. Output AC Timing Specifications
At recommended operating conditions (See Table 3) with GVdd = 3.3 V " 5% and LVdd = 3.3 V " 5%
Num Characteristic3,6 Min Max Units Notes
12a PCI_SYNC_IN to Output Valid, 66 MHz PCI, with MCP pulled-down
to logic 0 state. See Table . — 6.0 ns 2,4
PCI_SYNC_IN to Output Valid, 33 MHz PCI, with MCP in the
default logic 1 state. See Table . — 8.0 ns 2,4
12b1 SDRAM_SYNC_IN to Output Valid
(For Memory Control & Data Signals accessing DRAM in Flow
Through Mode)
— 7.0 ns 1
12b2 SDRAM_SYNC_IN to Output Valid
(For Memory Control & Data Signals accessing DRAM in Registered
Mode)
— TBD ns 1
12b3 SDRAM_SYNC_IN to Output Valid
(For Memory Control & Data Signals accessing non-DRAM.) — TBD ns 1
12c SDRAM_SYNC_IN to Output Valid (For All Others) — 7.0 ns 1
12d SDRAM_SYNC_IN to Output Valid (For I2C) — TBD ns 1
13a Output Hold, 66 MHz PCI, with MCP and CKE pulled-down to logic 0
states. See Table 12. 0.5 — ns 2,4,5
Output Hold, 33 MHz PCI, with MCP in the default logic 1 state and
CKE pulled-down to logic 0 state. See Table 12. 2.0 — ns 2,4,5
13b Output Hold (All Others) 0 — ns 1
14a PCI_SYNC_IN to Output High Impedance (For PCI) — TBD ns 2,4
14b SDRAM_SYNC_IN to Output High Impedance (For All Others) — TBD ns 1
Notes:
1All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of the memory
bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0 V) of the signal in question. SDRAM_SYNC_IN is the same as
PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every
rising and falling edge of PCI_SYNC_IN). See Figure 10.
2All PCI signals are measured from OVdd/2 of the rising edge of PCI_SYNC_IN to 0.285*OVdd or 0.615*OVdd of the signal in
question for 3.3 V PCI signaling levels. See Figure 11.
3All output timings assume a purely resistive 50 ohm load (See Figure 13). Output timings are measured at the pin; time-of-flight
delays must be added for trace lengths, vias, and connectors in the system.
4PCI Bussed signals are composed of the following signals: LOCK, IRDY, C/BE[0–3], PAR, TRDY, FRAME, STOP, DEVSEL,
PERR, SERR, AD[0–31], REQ[4–0], GNT[4–0], IDSEL, INTA.
5PCI hold times can be varied, see AUCUN LIEN “PCI Signal Output Hold Timing” section for information on programmable PCI
output hold times. The values shown for item 13a are for PCI compliance.
6These specifications are for the default driver strengths indicated in Table 3.
.
26/44 PC8240
OUTPUT Z0 = 50W OVdd/2
RL = 50W
PIN
Output measurements are made at the device pin.
Figure 13: AC Test Load for the PC8240
4.2.3.1. PCI Signal Output Hold Timing
In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33 MHz and 66 MHz PCI systems, the PC8240
has a programmable output hold delay for PCI signals. The initial value of the output hold delay is determined by the values on the
MCP and CKE reset configuration signals. Further output hold delay values are available by programming the PCI_HOLD_DEL value
of the PMCR2 configuration register.
Table 12 describes the bit values for the PCI_HOLD_DEL values in PMCR2.
Table 12. Power Management Configuration Register 2-0x72
Bit Name Reset
Value Description
6–4 PCI_HOLD_DEL xx0 PCI output hold delay values relative to PCI_SYNC_IN. The initial
values of bits 6 and 5 are determined by the reset configuration pins
MCP and CKE, respectively. As these two pins have internal pull-up
resistors, the default value after reset is 0b110.
While the minimum hold times are guaranteed at shown values,
changes in the actual hold time can be made by incrementing or
decrementing the value in these bit fields of this register via software
or hardware configuration. The increment is in approximately 400
picosecond steps. Lowering the value in the three bit field decreases
the amount of output hold available.
000 66 MHz PCI. Pull-down MCP configuration pin with a 2K or
less value resistor. This setting guarantees the minimum output
hold, item 13a, and the maximum output valid, item 12a, times
as specified in Table are met for a 66 MHz PCI system. See
Figure 14.
001
010
011
100 33 MHz PCI. This setting guarantees the minimum output hold,
item 13a, and the maximum output valid, item 12a, times as
specified in Table are met for a 33 MHz PCI system. See
Figure 14.
101
110 (Default if reset configuration pins left unconnected)
111
PC8240
27/44
PCI_SYNC_IN
PCI INPUTS/OUTPUTS
33 MHz PCI
12a, 8 ns for 33 MHz PCI
PCI_HOLD_DEL = 100
12a, 6 ns for 66 MHz PCI
PCI_HOLD_DEL = 000
13a, 2 ns for 33 MHz PCI
PCI_HOLD_DEL = 100
13a, 1 ns for 66 MHz PCI
PCI_HOLD_DEL = 000
OUTPUT VALID OUTPUT HOLD
Diagram Not to Scale
As PCI_HOLD_DEL
values decrease
As PCI_HOLD_DEL
values increase
PCI INPUTS
and OUTPUTS
PCI INPUTS/OUTPUTS
66 MHz PCI
0Vdd 2 0Vdd 2
Figure 14: PCI_HOLD_DEL Affect on Output Valid and Hold Time
28/44 PC8240
4.2.4. I2C AC T iming Specifications
Table 13 provides the I2C input AC timing specifications for the PC8240.
Table 13. I2C Input AC Timing Specifications
At recommended operating conditions (See Table 3) with GVdd = 3.3 V " 5% and LVdd = 3.3 V " 5%
Num Characteristic Min Max Unit Notes
1Start condition hold time 4.0 — CLKs 1,2
2Clock low period
(The time before the PC8240 will
drive SCL low as a transmitting
slave after detecting SCL low as
driven by an external master.)
8.0 + (16 x 2FDR[4:2]) x (5 -
4({FDR[5],FDR[1]} == b’10) -
3({FDR[5],FDR[1]} == b’1 1) -
2({FDR[5],FDR[1]} == b’00) -
1({FDR[5],FDR[1]} == b’01))
— CLKs 1,2,4, 5
3SCL/SDA rise time (from 0.5v to
2.4v) — 1 mS
4Data hold time 0 — nS 2
5SCL/SDA fall time (from 2.4 to 0.5v) — 1 mS
6Clock high period
(T ime needed to either receive a
data bit or generate a START or
STOP.)
5.0 — CLKs 1,2, 5
7Data setup time 3.0 — ns 3
8Start condition setup time (for
repeated start condition only) 4.0 — CLKs 1,2
9Stop condition setup time 4.0 — CLKs 1,2
Notes:
1Units for these specifications are in SDRAM_CLK units.
2The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency Divider
Register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified SCL and SDA
are delayed signals from what is seen in real time on the I2C bus. The qualified SCL, SDA signals are delayed by the
SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay value is added to the value in the table
(where this note is referenced). See Figure 16.
3Timing is relative to the Sampling Clock (not SCL).
4FDR[x] refers to the Frequency Divider Register I2CFDR bit x.
5Input clock low and high periods in combination with the FDR value in the Frequency Divider Register (I2CFDR) determine the
maximum I2C input frequency. See Table 13.
PC8240
29/44
Table 14 provides the I2C Frequency Divider Register (I2CFDR) information for the PC8240.
Table 14. PC8240 Maximum I2C Input Frequency
FDR
Hex2Divider2 (Dec) Max I2C Input Frequency1
SDRAM_CLK
@ 25 MHz SDRAM_CLK
@ 33 MHz SDRAM_CLK
@ 50 MHz SDRAM_CLK
@ 100 MHz
20, 21 160, 192 862 1.13 MHz 1.72 MHz 3.44 MHz
22, 23, 24, 25 224, 256, 320, 384 555 733 1.11 MHz 2.22 MHz
0, 1 288, 320 409 540 819 1.63 MHz
2, 3, 26, 27, 28,
29 384, 448, 480, 512, 640,
768 324 428 649 1.29 MHz
4, 5 576, 640 229 302 458 917
6, 7, 2A, 2B, 2C,
2D 768, 896, 960, 1024, 1280,
1536 177 234 354 709
8, 9 1152, 1280 121 160 243 487
A, B, 2E, 2F,
30, 31 1536, 1792, 1920, 2048,
2560, 3072 92 122 185 371
C, D 2304, 2560 62 83 125 251
E, F, 32, 33,
34, 35 3072, 3584, 3840, 4096,
5120, 6144 47 62 95 190
10, 11 4608, 5120 32 42 64 128
12, 13, 36, 37,
38, 39 6144, 7168, 7680, 8192,
10240, 12288 24 31 48 96
14, 15 9216, 10240 16 21 32 64
16, 17, 3A,
3B, 3C, 3D 12288, 14336, 15360,
16384, 20480, 24576 12 16 24 48
18, 19 18432, 20480 8 10 16 32
1A, 1B, 3E,
3F 24576, 28672, 30720,
32768 6 8 12 24
1C, 1D 36864, 40960 4 5 8 16
1E, 1F 49152, 61440 3 4 6 12
Notes:
1Values are in KHz unless otherwise specified.
2FDR Hex and Divider (Dec) values are listed in corresponding order.
3Multiple Divider (Dec) values will generate the same input frequency but each Divider (Dec) value will generate a unique output
frequency as shown in Table .
30/44 PC8240
Table 15 provides the I2C output AC timing specifications for the PC8240.
Table 15. I2C Output AC Timing Specifications
At recommended operating conditions (See Table 3) with GVdd = 3.3 V " 5% and L Vdd = 3.3 V " 5%
Num Characteristic Min Max Unit Notes
1Start condition hold time (FDR[5] == 0) x (DFDR/16) / 2N +
(FDR[5] == 1) x (DFDR/16) / 2M — CLKs 1,2,5
2Clock low period DFDR / 2 — CLKs 1,2,5
3SCL/SDA rise time
(from 0.5 V to 2.4 V) — — mS 3
4Data hold time 8.0 + (16 x 2FDR[4:2]) x (5 -
4({FDR[5],FDR[1]} == b’10) -
3({FDR[5],FDR[1]} == b’1 1) -
2({FDR[5],FDR[1]} == b’00) -
1({FDR[5],FDR[1]} == b’01))
— CLKs 1,2,5
5SCL/SDA fall time
(from 2.4 V to 0.5 V) —< 5 ns 4
6Clock high time DFDR / 2 — CLKs 1,2,5
7Data setup time
(PC8240 as a master only.) (DFDR / 2) - (Output data hold time) — CLKs 1,5
8Start condition setup time
(for repeated start condition only) DFDR + (Output start condition hold
time) — CLKs 1,2,5
9Stop condition setup time 4.0 — CLKs 1,2
Notes:
1Units for these specifications are in SDRAM_CLK units.
2The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency Divider
Register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified SCL and SDA
are delayed signals from what is seen in real time on the I2C bus. The qualified SCL, SDA signals are delayed by the
SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay value is added to the value in the table
(where this note is referenced). See Figure 16.
3Since SCL and SDA are open-drain type outputs, which the PC8240 can only drive low, the time required for SCL or SDA to reach
a high level depends on external signal capacitance and pull-up resistor values.
4Specified at a nominal 50pF load.
5DFDR is the decimal divider number indexed by FDR[5:0] value. Refer to the I2C Interface chapter’s Serial Bit Clock Frequency
Divider Selections table. FDR[x] refers to the Frequency Divider Register I2CFDR bit x. N is equal to a variable number that would
make the result of the divide (Data Hold T ime value) equal to a number less than 16. M is equal to a variable number that would
make the result of the divide (Data Hold Time value) equal to a number less than 9.
PC8240
31/44
. I
SCL
SDA
VM VM
6
2
1 4
Figure 15: I2C Timing Diagram I
SCL
SDA
VM
VL
VH
9
8
3
5
Figure 16: I2C Timing Diagram II
INPUT DATA VALID
DFFSR FILTER CLK1
SDA
7
Notes:
1 DFFSR Filter Clock is the SDRAM_CLK clock times DFFSR value.
Figure 17: I2C Timing Diagram III
.
SCL/SDArealtime VM
SCL/SDAqualified VM
Delay1
Notes:
1The delay is the Local Memory clock times DFFSR times 2 plus 1 Local Memory clock.
Figure 18: I2C Timing Diagram IV (Qualified Signal)
4.2.5. EPIC Serial Interrupt Mode AC Timing Specifications
Table 16 provides the EPIC serial interrupt mode AC timing specifications for the PC8240.
32/44 PC8240
Table 16. EPIC Serial Interrupt Mode AC Timing Specifications
At recommended operating conditions (See Table 3) with GVdd = 3.3 V " 5% and LVdd = 3.3 V " 5%
Num Characteristic Min Max Unit Notes
1S_CLK Frequency 1/14 SDRAM_SYNC_IN 1/2 SDRAM_SYNC_IN MHz 1
2S_CLK Duty Cycle 40 60 %
3S_CLK Output Valid Time –TBD = x nS
4Output Hold Time 0 – nS
5 S_FRAME, S_RST Output Valid
Time –1 sys_logic_clk period +
xnS 2
6S_INT Input Setup Time to
S_CLK 1 sys_logic_clk period +
TBD – nS 2
7S_INT Inputs Invalid (Hold
Time) to S_CLK – 0 nS 2
Notes:
1See the PC8240 User’s Manual for a description of the EPIC Interrupt Control Register (EICR) describing S_CLK frequency pro-
gramming.
2S_RST, S_FRAME, and S_INT shown in Figure 19 and Figure 20 depict timing relationships to sys_logic_clk and S_CLK and
do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the Motorola’s PC8240 User’s Manual
for a complete description of the functional relationships between these signals.
3The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL;
sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is imple-
mented and the DLL is locked. See the Motorola’s PC8240 User’s Manual for a complete clocking description.
S_CLK
S_RST
VM
VM
VM
S_FRAME
sys_logic_clk3
VM
VM
VM
VM
4
3
54
Figure 19: EPIC Serial Interrupt Mode Output Timing Diagram
6
S_CLK
S_INT
7
VM
Figure 20: EPIC Serial Interrupt Mode Input Timing Diagram
4.2.6. IEEE 1149.1 (JTAG) AC Timing Specifications
Table 17 provides the JTAG AC timing specifications for the PC8240 while in the JTAG operating mode.
PC8240
33/44
Table 17. JTAG AC Timing Specification (Independent of PCI_SYNC_IN)
At recommended operating conditions (See Table 3) with GVdd = 3.3 V " 5% and LVdd = 3.3 V " 5%
Num Characteristic4,5 Min Max Unit Notes
TCK Frequency of Operation 0 25 MHz
1TCK Cycle Time 40 — ns
2TCK Clock Pulse Width Measured at 1.5 V 20 — ns
3TCK Rise and Fall Times 0 3 ns
4TRST_ Setup Time to TCK Falling Edge 10 — ns 1
5TRST_ Assert Time 10 — ns
6Input Data Setup Time 5 — ns 2
7Input Data Hold Time 15 — ns 2
8TCK to Output Data Valid 0 30 ns 3
9TCK to Output High Impedance 0 30 ns 3
10 TMS, TDI Data Setup Time 5 — ns
11 TMS, TDI Data Hold Time 15 — ns
12 TCK to TDO Data Valid 0 15 ns
13 TCK to TDO High Impedance 0 15 ns
Notes:
1TRST is an asynchronous signal. The setup time is for test purposes only.
2Non-test (other than TDI and TMS) signal input timing with respect to TCK.
3Non-test (other than TDO) signal output timing with respect to TCK.
4Timings are independent of the system clock (PCI_SYNC_IN).
.
TCK
22
1
VM
VM
VM
33
VM = Midpoint Voltage
Figure 21: JTAG Clock Input Timing Diagram
.
4
5
TRST_
TCK
Figure 22: JTAG TRST Timing Diagram
34/44 PC8240
.
67
INPUT DATA VALID
8
9
OUTPUT DATA VALID
TCK
DATA INPUTS
DATA OUTPUTS
DATA OUTPUTS
Figure 23: JTAG Boundary Scan Timing Diagram
.
10 11
INPUT DATA VALID
12
13
OUTPUT DATA VALID
TCK
TDI, TMS
TDO
TDO
Figure 24: Test Access Port Timing Diagram
5. PREPARATION FOR DELIVERY
5.1. Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.
5.2. Certificate of compliance
TCS offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-STD-883
and guarantying the parameters not tested at temperature extermes for the entire temperature range.
PC8240
35/44
6. HANDLING
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection
devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are
recommended :
a) Devices should be handled on benches with conductive and grounded surfaces.
b) Ground test equipment, tools and operator.
c) Do not handle devices by the leads.
d) Store devices in conductive foam or carriers.
e) Avoid use of plastic, rubber, or silk in MOS areas.
f) Maintain relative humidity above 50 percent if practical.
6.1. Package description
6.1.1. Package Parameters for the PC8240
The PC8240 uses a 35 mm x 35 mm, cavity down, 352 pin Tape Ball Grid Array (TBGA) package. The package parameters are as
provided in the following list.
Package Outline 35 mm x 35 mm
Interconnects 352
Pitch 1.27mm
Solder Balls 63/37 Sn/Pb
Solder Ball Diameter 0.75 mm
Maximum Module Height 1.65 mm
Co-planarity Specification0.15 mm
Maximum Force 6.0 lbs. total, uniformly distributed over package (8 grams/ball)
36/44 PC8240
6.1.2. Pin Assignments and Package Dimensions
Figure 25 shows the top surface, side profile, and pinout of the PC8240, 352 TBGA package.
B
A
C
– E –
– F –
0.150
– T –
T
H
G
25 23 21 19 17 15 13 11 9 7 5 3 1
A
C
E
G
J
L
N
R
U
W
AA
AC
AE
352X j D
All measurements are in mm.
Top V iew
26 24 22 20 18 16 14 12 10 8 6 4 2
B
D
F
H
K
M
P
T
V
Y
AB
AD
AF
CORNER
K
L
Bottom V iew
K
MIN MAX
A 34.8 35.2
B 34.8 35.2
C 1.45 1.65
D .60 .90
G 1.27 BASIC
H .85 .95
K 31.75 BASIC
L .50 .70
Notes:
1Drawing not to scale.
2All measurements are in millimeters (mm).
Figure 25: PC8240Package Dimensions and Pinout Assignments
PC8240
37/44
6.2. PLL Configuration
The PC8240’s internal PLLs are configured by the PLL_CFG[0–4] signals. For a given PCI_SYNC_IN (PCI bus) frequency , the PLL
configuration signals set both the Peripheral Logic/Memory Bus PLL (VCO) frequency of operation for the PCI-to-Memory frequency
multiplying and the 603e CPU PLL (VCO) frequency of operation for Memory-to-CPU frequency multiplying. The PLL configurations
for the PC8240 is shown in Table 18.
Table 18. PC8240 Microprocessor PLL Configuration
Ref
PLL_
CFG
[0–4]1,3
CPU2
HID1
[0–4] 250 MHz Part9200 MHz Part9Ratios4,5
PCI Clock
Input (PCI_
SYNC_IN)
Range1
(MHz)
Periph Logic/
Mem
Bus Clock
Range (MHz)
CPU
Clock
Range (MHz)
PCI Clock
Input (PCI_
SYNC_IN)
Range1
(MHz)
Periph
Logic/
Mem
Bus Clock
Range (MHz)
CPU
Clock
Range (MHz)
PCI to Mem
(Mem VCO)
Multiplier
Mem to CPU
(CPU VCO)
Multiplier
0
00000 00110 25 – 33 75 – 100 188 – 250 25 – 26 75 – 80 188 – 200 3 (6) 2.5 (5)
1
00001 TBD 25 – 27 75 – 83 225 – 250 NOT USABLE 3 (6) 3 (6)
2
00010 TBD 50 – 56650 – 56 100 – 1 12 50 – 56650 – 56 100 – 1 12 1 (4) 2 (8)
3
00011 TBD Bypass Bypass Bypass 2 (8)
4
00100 00101 25 – 28650 – 56 100 – 1 13 25 – 28650 – 56 100 – 1 13 2 (8) 2 (8)
5
00101 TBD Bypass Bypass Bypass 2.5 (5)
7
00111 TBD Bypass Bypass Bypass 3 (6)
8
01000 11000 337 – 56633 – 56 100 – 168 337 – 56633 – 56 100 – 168 1 (4) 3 (6)
A
01010 TBD 25 – 27 50 – 55 225 – 250 NOT USABLE 2 (4) 4.5 (9)
C
01100 00110 25 – 50 50 – 100 125 – 250 25 – 40 50 – 80 125 – 200 2 (4) 2.5 (5)
E
01110 11000 25 – 41 50 – 83 150 – 250 25 – 33 50 – 66 150 – 200 2 (4) 3 (6)
10
10000 00100 25 – 33 75 – 100 150 – 200 25 – 33 75 – 100 150 – 200 3 (6) 2 (4)
12
10010 00100 33 – 66 50 – 100 100 – 200 338– 66 50 – 100 100 – 200 1.5 (3) 2 (4)
14
10100 11110 25 – 35 50 – 71 175 – 250 25 – 28 50 – 56 175 – 200 2 (4) 3.5 (7)
16
10110 11010 25 – 31 50 – 62 200 – 250 25 50 200 2 (4) 4 (8)
18
11000 11000 25 – 33 62 – 83 186 – 250 25 – 26 62 – 65 186 – 200 2.5 (5) 3 (6)
1A
11010 11010 508 – 62 50 – 62 200 – 250 50 50 200 1 (2) 4 (8)
1C
11100 11000 338 – 55 50 – 83 150 – 250 3 – 44 50 – 66 150 – 200 1.5 (3) 3 (6)
1D
11101 00110 338 – 66 50 – 100 125 – 250 338 – 53 50 – 80 125 – 200 1.5 (3) 2.5 (5)
1E
11110 TBD NOT USABLE Off Off
1F
11111 TBD NOT USABLE Off Off
38/44 PC8240
Notes:
1Caution: The PCI_SYNC_IN frequency and PLL_CFG[0–4] settings must be chosen such that the resulting peripheral logic/
memory bus frequency, CPU (core) frequency , and PLL (VCO) frequencies do not exceed their respective maximum or minimum
operating frequencies shown in Table . Bold font numerical pairs indicate input range limit and limiting parameter .
2The processor HID1 values only represent the multiplier of the processor’s PLL (Memory to Processor Multiplier), thus multiple
PC8240 PLL_CFG[0–4] values may have the same processor HID1 value. This implies that system software can not read the
HID1 register and associate it with a unique PLL_CFG[0–4] value.
3PLL_CFG[0–4] settings not listed (00110, 01001, 01011, 01101, 01111, 10001, 10011, 10101, 10111, 11001, and 11011) are
reserved.
4In PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly , the peripheral logic PLL is disabled,
and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for factory use only . The AC timing specifica-
tions given in this document do not apply in PLL Bypass mode.
5In Clock Off mode, no clocking occurs inside the PC8240 regardless of the PCI_SYNC_IN input.
6Limited due to maximum memory VCO = 225 MHz.
7Limited due to minimum CPU VCO = 200 MHz.
8Limited due to minimum memory VCO = 100 MHz.
9Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
6.3. System Design Information
This section provides electrical and thermal design recommendations for successful application of the PC8240.
6.3.1. PLL Power Supply Filtering
The A Vdd, AVdd2, and LA Vdd power signals are provided on the PC8240 to provide power to the peripheral logic/memory bus PLL,
the 603e processor PLL, and the SDRAM clock delay-locked loop (DLL), respectively. To ensure stability of the internal clocks, the
power supplied to the AVdd, AVdd2, and LAVdd input signals should be filtered of any noise in the 500kHz to 10MHz resonant fre-
quency range of the PLLs. A separate circuit similar to the one shown in Figure 26 using surface mount capacitors with minimum
ef fective series inductance (ESL) is recommended for each of the AVdd, AVdd2, and LA Vdd power signal pins. Consistent with the
recommendations of Dr . Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993),
multiple small capacitors of equal value are recommended over using multiple values.
The circuits should be placed as close as possible to the respective input signal pins to minimize noise coupled from nearby circuits.
Routing directly as possible from the capacitors to the input signal pins with minimal inductance of vias is important but proportionately
less critical for the LAVdd pin.
Vdd AVdd, AVdd2, or LAVdd
10 ?
2.2 ?F 2.2 ?F
GND
Low ESL surface mount capacitors
Figure 26: PLL Power Supply Filter Circuit
PC8240
39/44
6.3.2. Power Supply Voltage Sequencing
The notes in Table contain cautions illustrated in about the sequencing of the external bus voltages and internal voltages of the
PC8240. These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic discharge (ESD)
protection diodes will be forward biased and excessive current can flow through these diodes. Figure 27 shows a typical ramping
voltage sequence where the DC power sources (voltage regulators and/or power supplies) are connected as shown in Figure 27. The
voltage regulator delay shown in can be zero if the various DC voltage levels are all applied to the target board at the same time. The
ramping voltage sequence shows a scenario in which the Vdd/A Vdd/A Vdd2/LA Vdd power plane is not loaded as much as the OVdd/
GVdd power plane and thus Vdd/AVdd/AVdd2/LAVdd ramps at a faster rate than OVdd/GVdd.
If the system power supply design does not control the voltage sequencing, the circuit of Figure 27 can be added to meet these
requirements. The MUR420 diodes of Figure 27 control the maximum potential difference between the 3.3 bus and internal voltages
on power-up and the 1N5820 Schottky diodes regulate the maximum potential difference on power-down.
3.3V
MUR420
1N5820
MUR420
1N5820
2.5V
+3.3V
+2.5V
Source
+5V
Source
Source 5V
3.3V
2.5V
Figure 27: Example Voltage Sequencing Circuits
6.3.3. Power Supply Sizing
The power consumption numbers provided in Table do not reflect power from the OVdd and GVdd power supplies which are non-
negligible for the PC8240. In typical application measurements, the OVdd power ranged from 200 to 600 mW and the GVdd power
ranged from 300 to 900 mW. The ranges’ low end power numbers were results of the PC8240 performing cache resident integer
operations at the slowest frequency combination of 33:66:166 (PCI:Mem:CPU) MHz. The OVdd high end range’s value resulted from
the PC8240 performing continuous flushes of cache lines with alternating ones and zeroes to PCI memory. The GVdd high end
range’s value resulted from the PC8240 operating at the fastest frequency combination of 66:100:250 (PCI:Mem:CPU) MHz and per-
forming continuous flushes of cache lines with alternating ones and zeroes on 64 bit boundaries to local memory.
6.3.4. Decoupling Recommendations
Due to the PC8240’s dynamic power management feature, large address and data buses, and high operating frequencies, the
PC8240 can generate transient power surges and high frequency noise in its power supply , especially while driving large capacitive
loads. This noise must be prevented from reaching other components in the PC8240 system, and the PC8240 itself requires a clean,
tightly regulated source of power . Therefore, it is recommended that the system designer place at least one decoupling capacitor at
each Vdd, OVdd, GVdd, and L Vdd pin of the PC8240. It is also recommended that these decoupling capacitors receive their power
from separate Vdd, OVdd, GVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors
should have a value of 0.1 F . Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance,
preferably 0508 or 0603, oriented such that connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the Vdd, OVdd,
GVdd, and LVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR
(equivalent series resistance) rating to ensure the quick response time necessary . They should also be connected to the power and
ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS tantalum or Sanyo
OSCON).
6.3.5. Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low
inputs should be tied to OVdd. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain
unconnected.
Power and ground connections must be made to all external Vdd, OVdd, GVdd, LVdd and GND pins of the PC8240.
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to the PCI_SYNC_IN input of
the PC8240.
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then returned to the
SDRAM_SYNC_IN input of the PC8240. The trace length may be used to skew or adjust the timing window as needed. See Motorola
application note AN1794/D for more information on this topic.
40/44 PC8240
6.3.6. Pull-up/Pull-down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress; therefore, they do not require pull-up
resistors on the bus. The data bus signals are: DH[0–31], DL[0–31], and PAR[0–7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (DL[0–31], and PAR[4–7]) will be
disabled, and their outputs will drive logic zeros when they would otherwise normally be driven. For this mode, these pins do not
require pull-up resistors, and should be left unconnected by the system to minimize possible output switching.
The TEST[0–1] pins require pull-up resistors of 120 Ohms or less connected to OVdd.
It is recommended that TEST2 have weak pull-up resistor (2K – 10K Ohms) connected to GVdd.
It is recommended that the following signals be pulled up to OVdd with weak pull-up resistors (2K – 10K Ohms): SDA, SCL, SMI,
SRESET, TBEN, CHKSTOP_IN , TEST3, and TEST4.
It is recommended that the following PCI control signals be pulled up to L Vdd with weak pull-up resistors (2K – 10K Ohms): DEVSEL,
FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The resistor values may need to be adjusted stronger to reduce induced
noise on specific board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[0–3], REQ4/DA4, TCK, TDI, TMS, and TRST . See Table .
PC8240 Pinout Listing for more information.
The following pins have internal pull-up resistors enabled only while device is in the reset state: GNT4/DA5, DL0, FOE, RCS0,
SDRAS, SDCAS, CKE, AS, MCP, MAA[0–2], PMAA[0–2]. See Table . PC8240 Pinout Listing for more information.
The following pins are reset configuration pins: GNT4/DA5, DL0, FOE, RCS0, CKE, AS, MCP, QACK/DA0, MAA[0–2], PMAA[0–2],
and PLL_CFG[0–4]/DA[10–6]. These pins are sampled during reset to configure the device.
Reset configuration pins should be tied to GND via 1K Ohm pull-down resistors to insure a logic zero level is read into the configuration
bits during reset if the default logic one level is not desired.
Any other unused active low input pins should be tied to a logic one level via weak pull-up resistors (2K – 10K Ohms) to the appropriate
power supply listed in . Unused active high input pins should be tied to GND via weak pull-down resistors (2K – 10K Ohms).
6.3.7. JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the PC8240 are available on the internet
at www.mot.com/SPS/PowerPC/teksupport/tools/BSDL/) The TRST signal is optional in the IEEE 1149.1 specification but is pro-
vided on all PowerPC implementations. While it is possible to force the T AP controller to the reset state using only the TCK and TMS
signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Since the
JTAG interface is also used for accessing the common on-chip processor (COP) function of PowerPC processors, simply tying
TRST to HRST_CPU/HRST_CTRL is not practical. Note that the two hard reset signals on the PC8240 (HRST_CPU and
HRST_CTRL) must be asserted and negated together to guarantee normal operation.
The common on-chip processor (COP) function of PowerPC processors allows a remote computer system (typically a PC with dedi-
cated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects
primarily through the JT AG port of the processor, with some additional status monitoring signals. The COP port requires the ability to
independently assert HRST_CPU/HRST_CTRL or TRST in order to fully control the processor. If the target system has indepen-
dent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset
signals must be merged into these signals with logic.
The arrangement shown in allows the COP to independently assert HRST_CPU/HRST_CTRL or TRST while insuring that the
target can drive HRST_CPU/HRST_CTRL as well. The COP header shown, adds many benefits including breakpoints, watch-
points, register and memory examination/modification and other standard debugger features are possible through this interface.
Availability of these features can be as inexpensive as an unpopulated footprint for a header to be added when needed.
PC8240
41/44
.
PC8240
HRESET HRST_CPU
HRST_CTRL
From Tar get
Board Sources
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No pin
HRESET
13 SRESET
SRESET SRESET
NC
NC
NC
11
VDD_SENSE
6
52
153
2 K?
10 K?
10 K?
10 K?
OVdd
OVdd
OVdd
OVdd
CKSTP_IN CKSTP_IN
8TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4TRST
7
16
2
10
12
(if any)
COP Header
144
Key
COP Connector
Physical Pin Out
QACK1
OVdd
OVdd
10 K? OVdd
1 K?5 GND
TRST
10 K? OVdd
10 K?
10 K?
Notes:
1QACK is an output on the PC8240 and is not required at the COP header for emulation.
2RUN/ST OP normally found on pin 5 of the COP header is not implemented on the PC8240. Connect pin 5 of the COP header
to OVdd with a 10 K pull-up resistor.
3CKSTP_OUT normally found on pin 15 of the COP header is not implemented on the PC8240. Connect pin 15 of the COP header
to OVdd with a 10 K pull-up resistor.
4Pin 14 is not physically present on the COP header.
5Component not populated.
Figure 28: COP Connector Diagram
The COP interface has a standard header for connection to the target system, based on the 0.025” square-post 0.100” centered
header assembly (often called a “Berg” header). The connector typically has pin 14 removed as a connector key, as shown in .
There is no standardized way to number the COP header shown in Figure 28 ; consequently , many different pin numbers have been
observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bot-
tom, while still others number the pins counter clockwise from pin one (as with an IC). Regardless of the numbering, the signal place-
ment recommended in is common to all known emulators.
42/44 PC8240
7. DEFINITIONS
Datasheet status Validity
Objective specification This datasheet contains target and goal specifi-
cation for discussion with customer and applica-
tion validation.
Before design phase.
Target specification This datasheet contains target or goal specifica-
tion for product development. Valid during the design
phase.
Preliminary specification ∝ site This datasheet contains preliminary data. Addi-
tional data may be published later ; could include
simulation result.
Valid before characteriza-
tion phase.
Preliminary specification b site This datasheet contains also characterization
results. Valid before the industrial-
ization phase.
Product specification This datasheet contains final product specifica-
tion. Valid for production pur-
pose.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury . ATMEL-GRENOBLE customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify A TMEL-GRENOBLE for any damages resulting from such improper
use or sale.
8. DIFFERENCES WITH COMMERCIAL PART
Commercial part Military part
Temperature range Tj = 0 to 105°CTc = -55 to 125°C
Power consumption use a 1.25 factor to calculate at low
temperature (-55°C)
Spec 13a (output hold) 1 ns 0.5 ns
PC8240
43/44
9. ORDERING INFORMATION
Type
(PCX8240 if prototype)
Temperature range : TC
Screening leve
l
(1)
:
Package :
PC8240 M TP 200
M : -55, +125 °C
V : -40, +110 °C
U
TP : TBGA
Max internal processor speed
(1)
200 : 200 MHz
250 : 250 MHz (tbc)
(1) For availability of the dif ferent versions, contact your A TMEL sale of fice
U : Upscreening
(C )
Revision level
Information furnished is believed to be accurate and reliable. However Atmel-Grenoble assumes no responsibility for the conse-
quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Atmel-Grenoble. Specifications mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. Atmel-
Grenoble products are not authorized for use as critical components in life support devices or systems without express written
approval from Atmel-Grenoble.
2000 Atmel-Grenoble- Printed in France - All rights reserved.
This product is manufactured by Atmel-Grenoble- 38521 SAINT-EGREVE - FRANCE.
For further information please contact :
Atmel-Grenoble - Route Départementale 128 - B.P. 46 - 91401 ORSAY Cedex - FRANCE -
Phone +33 (0)1 69 33 00 00 - Fax +33 (0)1 69 33 03 21.
Internet:http://www.atmel-grenoble.com
44/44 PC8240
