NT1GT72U4PA0FU-5A - Nanya Technology

NT1GT72U4PA0FU

1GB: 128M x 72

Low Profile Registered DDR2 SDRAM DIMM

REV 0.1 1

12/2003 © NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

240pin Low Profile Registered DDR2 SDRAM MODULE Based on 128Mx4 DDR2 SDRAM

Features

• 128Mx72 Low Profile Registered DDR2 DIMM based on

128Mx4 DDR2 SDRAM

• JEDEC Standard 240-pin Dual In-Line Memory Module

• Error Check Correction (ECC) Support

• Phase-lock loop (PLL) clock driver to reduce loading

• Registered inputs with one-clock delay

• Performance:

PC2-3200

Speed Sort -5

DIMM CAS Latency* 4

Unit

f CK Clock Frequency 200 MHz

t CK Clock Cycle 5 ns

f DQ DQ Burst Frequency 400 MHz

• Intended for 200 MHz applications

• Inputs and outputs are SSTL-18 compatible

• VDD = 1.8Volt ± 0.1, VDDQ = 1.8Volt ± 0.1

• SDRAMs have 4 internal banks for concurrent operation

• Differential clock inputs

• Data is read or written on both clock edges

• Bi-directional data strobe with one clock cycle preamble and

one-half clock post-amble

• Address and control signals are fully synchronous to positive

clock edge

• Programmable Operation:

- Device CAS Latency: 3, 4, 5

- Burst Type: Sequential or Interleave

- Burst Length: 4, 8

- Operation: Burst Read and Write

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 14/11/2 Addressing (row/column/bank)

• 7.8 µs Max. Average Periodic Refresh Interval

• Serial Presence Detect

• Gold contacts

• SDRAMs in 84-ball FBGA Package

• One clock cycle added for registered DIMMs to account for input

Description

NT1GT72U4PA0FU is a Low Profile Registered 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Dual In-Line Memory Module

(DIMM), organized as a one-ban k 128Mx72 high-speed memory array. The module uses nine 128Mx4 DDR2 SDRAMs in FBGA

packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these

common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance,

flexible 8-byte interface in a 5.25” long space-saving footprint.

The DIMM is intended for use in applications operating up to 200 MHz clock speeds and achieves high-speed data transfer rates of up to

400 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the

DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle.

The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of

serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.

Ordering Information

Part Number Speed Organization Leads Power

NT1GT72U4PA0FU-5A 200MHz (5ns @ CL = 4) DDR2-400 PC2-3200 128Mx72 Gold 1.8V

NT1GT72U4PA0FU

1GB: 128M x 72

Low Profile Registered DDR2 SDRAM DIMM

REV 0.1 2

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Description

CK0, CK0 Differential Clock Inputs DQ0-DQ63 Data input/output

CKE0, CKE1 Clock Enable CB0-CB7 ECC Check Bit Data Input/Output

RAS Row Address Strobe DQS0-DQS8 Bidirectional data strobes

CAS Column Address Strobe DM0-DM8/DQS9-17 Input Data Mask/High Data Strobes

WE Write Enable DQS0-DQS17 Differential data strobes

CS0, CS1 Chip Selects VDD Power (1.8V)

A0-A9, A11-A13 Address Inputs VREF Ref. Voltage for SSTL_18 inputs

A10/AP Column Address Input/Auto-precharge VDDSPD Serial EEPROM positive power supply

BA0, BA1 SDRAM Bank Address Inputs VSS Ground

RESET Reset pin SCL Serial Presence Detect Clock Input

ODT0, ODT1 Active termination control lines SDA Serial Presence Detect Data input/output

NC No Connect SA0-2 Serial Presence Detect Address Inputs

NT1GT72U4PA0FU

1GB: 128M x 72

Low Profile Registered DDR2 SDRAM DIMM

REV 0.1 3

12/2003 © NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pinout

Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back

1 VREF 42 CB0 82 VSS 123 DQ5 164 DM8, DQS17 204 VSS

2 VSS 43 CB1 83

DQS4 124 VSS 165 DQS17 205 DQ38

3 DQ0 44 VSS 84 DQS4 125 DM0, DQS9 166 VSS 206 DQ39

4 DQ1 45

DQS8 85 VSS 126 DQS9 167 CB6 207 VSS

5 VSS 46 DQS8 86 DQ34 127 VSS 168 CB7 208 DQ44

6 DQS0 47 VSS 87 DQ35 128 DQ6 169 VSS 209 DQ45

7 DQS0 48 CB2 88 VSS 129 DQ7 170 VDDQ 210 VSS

8 VSS 49 CB3 89 DQ40 130 VSS 171 NC, CKE1 211 DM5, DQS14

9 DQ2 50 VSS 90 DQ41 131 DQ12 172 VDD 212

DQS14

10 DQ3 51 VDDQ 91 VSS 132 DQ13 173 NC 213 VSS

11 VSS 52 CKE0 92

DQS5 133 VSS 174 NC 214 DQ46

12 DQ8 53 VDD 93 DQS5 134 DM1, DQS10 175 VDDQ 215 DQ47

13 DQ9 54 NC 94 VSS 135 DQS10 176 A12 216 VSS

14 VSS 55 NC 95 DQ42 136 VSS 177 A9 217 DQ52

15 DQS1 56 VDDQ 96 DQ43 137 NC 178 VDD 218 DQ53

16 DQS1 57 A11 97 VSS 138 NC 179 A8 219 VSS

17 VSS 58 A7 98 DQ48 139 VSS 180 A6 220 NC

18 RESET 59 VDD 99 DQ49 140 DQ14 181 VDDQ 221 NC

19 NC 60 A5 100 VSS 141 DQ15 182 A3 222 VSS

20 VSS 61 A4 101 SA2 142 VSS 183 A1 223 DM6, DQS15

21 DQ10 62 VDDQ 102 NC 143 DQ20 184 VDD 224

DQS15

22 DQ11 63 A2 103 VSS 144 DQ21 KEY 225 VSS

23 VSS 64 VDD 104

DQS6 145 VSS 185 CK0 226 DQ54

24 DQ16 KEY 105 DQS6 146 DM2, DQS11 186 CK0 227 DQ55

25 DQ17 65 VSS 106 VSS 147 DQS11 187 VDD 228 VSS

26 VSS 66 VSS 107 DQ50 148 VSS 188 A0 229 DQ60

27 DQS2 67 VDD 108 DQ51 149 DQ22 189 VDD 230 DQ61

28 DQS2 68 NC 109 VSS 150 DQ23 190 BA1 231 VSS

29 VSS 69 VDD 110 DQ56 151 VSS 191 VDDQ 232 DM7, DQS16

30 DQ18 70 A10/AP 111 DQ57 152 DQ28 192 RAS 233 DQS16

31 DQ19 71 BA0 112 VSS 153 DQ29 193 CS0 234 VSS

32 VSS 72 VDDQ 113 DQS7 154 VSS 194 VDDQ 235 DQ62

33 DQ24 73 WE 114 DQS7 155 DM3, DQS12 195 ODT0 236 DQ63

34 DQ25 74 CAS 115 VSS 156 DQS12 196 A13 237 VSS

35 Vss 75 VDDQ 116 DQ58 157 VSS 197 VDD 238 VDDSPD

36 DQS3 76 CS1 117 DQ59 158 DQ30 198 VSS 239 SA0

37 DQS3 77 ODT1 118 VSS 159 DQ31 199 DQ36 240 SA1

38 Vss 78 VDDQ 119 SDA 160 VSS 200 DQ37

39 DQ26 79 Vss 120 SCL 161 CB4 201 VSS

40 DQ27 80 DQ32 121 VSS 162 CB5 202 DM4, DQS13

41 Vss 81 DQ33 122 DQ4 163 VSS 203 DQS13

NT1GT72U4PA0FU

1GB: 128M x 72

Low Profile Registered DDR2 SDRAM DIMM

REV 0.1 4

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input/Output Functional Description

Symbol Type Polarity Function

CK0 (SSTL) Positive

Edge

The positive line of the differential pair of system clock inputs which drives the input to

the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the

rising edge of their associated clocks.

CK0 (SSTL) Negative

Edge The negative line of the differential pair of system clock inputs which drives the input to

the on-DIMM PLL.

CKE0, CKE1 (SSTL) Active

High

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By

deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh

mode.

CS0, CS1 (SSTL) Active

Low

Enables the associated SDRAM command decoder when low and disables the

command decoder when high. When the command decoder is disabled, new commands

are ignored but previous operations continue.

RAS, CAS, WE (SSTL) Active

Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the

operation to be executed by the SDRAM.

VREF Supply Reference voltage for SSTL-18 inputs

VDDQ Supply

Isolated power supply for the DDR SDRAM output buffers to provide improved noise

immunity

ODT0, ODT1 Input Active

High On-Die Termination control signals

BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active.

A0 - A9

A10/AP

A11, A12 (SSTL) -

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9, A11 defines the column address

(CA0-CA10) when sampled at the rising clock edge. In addition to the column address,

AP is used to invoke Autoprecharge operation at the end of the Bur st Read or Write

cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be

precharged. If AP is low, autoprecharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to

pre-charge.

DQ0 – DQ63

CB0 – CB7 (SSTL) Active

High Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM

configurations.

VDD, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic

DQS0 – DQS17

DQS0 – DQS17 (SSTL)

Negative

and

Positive

Edge

Data strobe for input and output data

DM0 – DM8 Input Active

High

The data write masks, associated with one data byte. In Write mode, DM operates as a

byte mask by allowing input data to be written if it is low but blocks the write operation if

it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits

CB0-CB7, and is not used on x64 modules.

RESET Input Active

Low

The RESET pin is connected to the RST pin on the register and to the OE pin on the

PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs

and the registers will be set to low level. The PLL will remain synchronized with the input

clock.

SA0 – SA2 -

Address inputs. Connected to either VDD or VSS on the system board to configure the

Serial Presence Detect EEPROM address.

SDA -

This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to V DD to act as a pull-up.

SCL -

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to V DD to act as a pull-up.

V DDSPD Supply Serial EEPROM positive power supply.

NT1GT72U4PA0FU

1GB: 128M x 72

Low Profile Registered DDR2 SDRAM DIMM

REV 0.1 5

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Functional Block Diagram (1Rank, 128Mx4 DDR SDRAMs)

Serial PD

A0 A2A1

SCL

WP SDA

SA0 SA2SA1

Serial PDV

DDSPD

DDQ

REF

DDID

D0-D17

Strap : see Note 4

* Wire per Clock Loading Table/Wiring Diagrams

CK0, CK0 --------- PLL*

DQS0

I/O 3

RS0

I/O 0

I/O 1

I/O 3

I/O 2

DQS CS

I/O 3

DQS9

DQ4

DQ5

DQ6

DQ7

Notes : 1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/CS relationships are maintained as shown.

3. DQ/DQS resistors are 22 Ohms.

4. V

DDID

strap connections (for memory device V

DDQ

STRAP OU T (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

5. Address and control resistors are 22 Ohms.

DQ0

DQ1

DQ2

DQ3

I/O 0

I/O 1

I/O 2

DQS CS

DQS0

DQS

I/O 3

DQ11

DQS1

DQ8

DQ9

DQ10

I/O 0

I/O 1

I/O 2

DQS CS

DQS1

DQS

I/O 3

DQ35

DQS4

DQ32

DQ33

DQ34

I/O 0

I/O 1

I/O 2

DQS CS

DQS4

DQS

I/O 3

DQ43

DQS5

DQ40

DQ41

DQ42

I/O 0

I/O 1

I/O 2

DQS CS

DQS5

DQS

I/O 3

DQ51

DQS6

DQ48

DQ49

DQ50

I/O 0

I/O 1

I/O 2

DQS CS

DQS6

DQS

I/O 3

DQ59

DQS7

DQ56

DQ57

DQ58

I/O 0

I/O 1

I/O 2

DQS CS

DQS7

DQS

I/O 3

CB3

DQS8

CB0

CB1

CB2

I/O 0

I/O 1

I/O 2

DQS CS

DQS8

DQS

I/O 3

DQ19

DQS2

DQ16

DQ17

DQ18

I/O 0

I/O 1

I/O 2

DQS CS

DQS2

DQS

I/O 3

DQ27

DQS3

DQ24

DQ25

DQ26

I/O 0

I/O 1

I/O 2

DQS CS

DQS3

DQS

I/O 3

DQ15

DQS10

DQ12

DQ13

DQ14

I/O 0

I/O 1

I/O 2

DQS CS

D10

DQS10

DQS

I/O 3

DQ23

DQS11

DQ20

DQ21

DQ22

I/O 0

I/O 1

I/O 2

DQS CS

D11

DQS11

DQS

I/O 3

DQ31

DQS12

DQ28

DQ29

DQ30

I/O 0

I/O 1

I/O 2

DQS CS

D12

DQS12

DQS

I/O 3

DQ39

DQS13

DQ36

DQ37

DQ38

I/O 0

I/O 1

I/O 2

DQS CS

D13

DQS13

DQS

I/O 3

DQ47

DQS14

DQ44

DQ45

DQ46

I/O 0

I/O 1

I/O 2

DQS CS

D14

DQS14

DQS

I/O 3

DQ55

DQS15

DQ52

DQ53

DQ54

I/O 0

I/O 1

I/O 2

DQS CS

D15

DQS15

DQS

I/O 3

DQ63

DQS16

DQ60

DQ61

DQ62

I/O 0

I/O 1

I/O 2

DQS CS

D16

DQS16

DQS

I/O 3

CB7

DQS17

CB4

CB5

CB6

I/O 0

I/O 1

I/O 2

DQS CS

D17

DQS17

DQS

I/O 3

DQS9

DQS

A0-A13 : SDRAMs D0-D8

BA0-BA1 : SDRAMs D0-D8

RAS : SDRAMs D0-D8

CKE : SDRAMs D0-D8

CAS : SDRAMs D0-D8

ODT0 : SDRAMs D0-D8

BA0-BA1

A0-A13

RAS

CAS

CKE0

ODT0

CS0

RA0-RA13

RBA0-RBA1

RRAS

RCAS

RODT0

RCKE0

RS0 CS : SDRAMs D0-D8

PCK

PCK RESET

WE : SDRAMs D0-D8

WE RWE

NT1GT72U4PA0FU

1GB: 128M x 72

Low Profile Registered DDR2 SDRAM DIMM

REV 0.1 6

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Serial Presence Detect -- Part 1 of 2

128Mx72 1 BANK REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD

SPD Entry Value Serial PD Data Entry

(Hexadecimal) Note

Byte Description DDR2-400

-5A DDR2-400

-5A

0 Number of Serial PD Bytes Written during Production 128 80

1 Total Number of Bytes in Serial PD device 256 08

2 Fundamental Memory Type DDR2-SDRAM 08

3 Number of Row Addresses on Assembly 14 0E

4 Number of Column Addresses on Assembly 10 0A

5 Number of DIMM Bank 1 60

6 Data Width of Assembly X72 48

7 Reserved Undefined 00

8 Voltage Interface Level of this Assembly SSTL_1.8 05

9 DDR2 SDRAM Device Cycle Time at CL=5 5ns 50

10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.6ns 60

11 DIMM Configuration Type ECC 02

12 Refresh Rate/Type SR/1x(7.8us) 82

13 Primary DDR SDRAM Width X8 08

14 Error Checking DDR SDRAM Device Width X8 08

15 Reserved Undefined 00

16 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C

17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04

18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 4/5 38

19 Reserved Undefined 00

20 DDR2 SDRAM DIMM Type Information Reg. DIMM 01

21 DDR2 SDRAM Module Attributes: Normal DIMM 00

22 DDR2 SDRAM Device Attributes: General Include weak driver 01

23 Minimum Clock Cycle at CL=4 5ns 50

24 Maximum Data Access Time from Clock at CL=4 0.6ns 60

25 Minimum Clock Cycle Time at CL=3 5ns 50

26 Maximum Data Access Time from Clock at CL=3 0.6ns 60

27 Minimum Row Precharge Time (tRP) 20ns 50

28 Minimum Row Active to Row Active delay (tRRD) 15ns 3C

29 Minimum RAS to CAS delay (tRCD) 15ns 3C

30 Minimum RAS Pulse Width (tRAS) 45ns 2D

31 Module Bank Density 512MB 80

32 Address and Command Setup Time Before Clock (tIS) 0.6ns 60

33 Address and Command Hold Time After Clock (tIH) 0.6ns 60

34 Data Input Setup Time Before Clock (tDS) 0.4ns 40

35 Data Input Hold Time After Clock (tDH) 0.4ns 40

36 Write Recovery Time (tWR) 15ns 3C

37 Internal Write to Read Command delay (tWTR) 10ns 28

38 Internal Read to Precharge delay (tRTP) 7.5ns 1E

39 Reserved Undefined 00

40 Extension of Byte 41 tRC and Byte 42 tRFC 60ns 3C

41 Minimum Core Cycle Time (tRC) 60ns 3C

42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69

43 Maximum Clock Cycle Time (tCK) 8ns 80

NT1GT72U4PA0FU

1GB: 128M x 72

Low Profile Registered DDR2 SDRAM DIMM

REV 0.1 7

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Serial Presence Detect -- Part 2 of 2

128Mx72 1 BANK REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD

SPD Entry Value Serial PD Data Entry

(Hexadecimal)

Byte Description DDR2-400

-5A DDR2-400

-5A

Note

44 Max. DQS-DQ Skew Factor (tQHS) 0.35ns 23

45 Read Data Hold Skew Factor (tQHS) 0.45ns 2D

46 PLL Relock Time 15us 0F

47-61 Reserved Undefined 00

62 SPD Revision Initial 00

63 Checksum Data D7

64-71 Manufacturer’s JEDEC ID Code NANYA 7F7F7F0B00000000

72 Module Manufacturing Location N/A 00

73-90 Module Part number N/A 00

91-92 Module Revision Code N/A 00

93-94 Module Manufacturing Data Year/Week Code yy/ww 1, 2

95-98 Module Serial Number Serial Number 00

99-255 Reserved Undefined 00

yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)

ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)

NT1GT72U4PA0FU

1GB: 128M x 72

Low Profile Registered DDR2 SDRAM DIMM

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Absolute Maximum Ratings

Symbol Parameter Rating Units

VIN, VOUT Voltage on I/O pins relative to Vss -0.5 to VDDQ+0.5 V

VIN Voltage on Input relative to Vss -0.5 to +2.3 V

VDD Voltage on VDD supply relative to Vss -0.5 to +2.3 V

VDDQ Voltage on VDDQ supply relative to Vss -0.5 to +2.3 V

TA Operating Temperature (Ambient) 0 to +70 °C

TSTG Storage Temperature (Plastic) -55 to +100 °C

PD Power Dissipation TBD W

IOUT Short Circuit Output Current TBD mA

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is

stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Capacitance Parameter Symbol Max. Units Notes

Input Capacitance: CK0, CK0 CI1 TBD pF 1

Input Capacitance: A0-A12, BA0, BA1, WE, RAS, CAS, CKE0, S0 CI2 TBD pF 1

Input Capacitance: RESET CI3 TBD pF 1

Input Capacitance: SA0-SA2, SCL CI4 TBD pF 1

Input/Output Capacitance DQ0-63; DQS0-8, CB0-7 CIO1 TBD pF 1, 2

Input/Output Capacitance: SDA CIO3 TBD pF

1. VDDQ = VDD = 1.8V ± 0.1V, f = 100 MHz, TA = 25 °C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V.

2. DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching

at the board level.

NT1GT72U4PA0FU

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Low Profile Registered DDR2 SDRAM DIMM

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DC Electrical Characteristics and Operating Conditions

(TA = 0 °C ~ 70 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics)

Symbol Parameter Min Max Units Notes

VDD Supply Voltage 1.7 1.9 V 1

VDDQ I/O Supply Voltage 1.7 1.9 V 1

VSS, VSSQ Supply Voltage, I/O Supply Voltage 0 0 V

VREF I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2

VTT I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3

VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V 1

VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1

VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1

VID (DC) Input Differential Voltage, CK and CK Inputs 0.30 V DDQ + 0.6 V 1, 4

IIL Input Leakage Current

Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V) -5 5 uA 1

IOZ Output Leakage Current

(DQs are disabled; 0V ≤ Vout ≤ VDDQ -5 5 uA 1

IOH Output High Current

(VOUT = VDDQ -0.373V, min VREF, min VTT) TBD - mA 1

IOL Output Low Current

(VOUT = 0.373, max VREF, max VTT) TBD - mA 1

1. Inputs are not recognized as valid until VREF stabilizes.

2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same.

Peak-to-peak noise on VREF may not exceed 2% of the DC value.

3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF,

and must track variations in the DC level of VREF.

4. VID is the magnitude of the difference between the input level on CK and the input level on CK.

NT1GT72U4PA0FU

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Low Profile Registered DDR2 SDRAM DIMM

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AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating,

Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but

the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.

4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or

to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use

conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified.

5. The AC and DC input level specifications are as defined in the SSTL_18 Standard (i.e. the receiver effectively switches as a result of

the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input

LOW (HIGH) level.

AC Output Load Circuits

Timing Reference Point

50 ohms

30 pF

Output

OUT

AC Operating Conditions

(TA = 0 °C ~ 70 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics)

Symbol Parameter/Condition Min Max Unit Notes

VIH (AC) Input High (Logic 1) Voltage V REF + 0.31 - V 1, 2

VIL (AC) Input Low (Logic 0) Voltage - V REF - 0.31 V 1, 2

VID (AC) Input Differential Voltage, CK and CK Inputs 0.7 V DDQ + 0.6 V 1, 2, 3

VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs 0.5 x VDDQ - 0.2 0.5 x VDDQ + 0.2 V 1, 2, 4

1. Input slew rate = 1V/ ns.

2. Inputs are not recognized as valid until VREF stabilizes.

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of VIX is expected to equal 0.5 x VDDQ of the transmitting device and must track variations in the DC level of the same.

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Operating, Standby, and Refresh Currents

(TA = 0 °C ~ 70 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics)

Symbol Parameter/Condition PC2-3200

(-5A) Unit Notes

I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK

(MIN); DQ, DM, and DQS inputs changing t wice per clock cycle; address

and control inputs changing once per clock cycle TBD mA 1, 2

I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; t RC = tRC

(MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs

changing once per clock cycle TBD mA 1, 2

I DD2P Precharge Power-Down Standby Current: all banks idle; power-down

mode; CKE ≤ VIL (MAX); tCK = tCK (MIN) TBD mA 1, 2

I DD2N Idle Standby Current: CS ≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK =

tCK (MIN); address and control inputs changing once per clock cycle TBD mA 1, 2

I DD3P Active Power-Down Standby Current: one bank active; power-down mode;

CKE ≤ VIL (MAX); tCK = tCK (MIN) TBD mA 1, 2

I DD3N

Active Standby Current: one bank; active/precharge; CS ≥ VIH (MIN); CKE ≥

VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs

changing twice per clock cycle; address and control inputs changing once

per clock cycle

TBD mA 1, 2

I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address

and control inputs changing once per clock cycle; DQ and DQS outputs

changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA TBD mA 1, 2

I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address

and control inputs changing once per clock cycle; DQ and DQS inputs

changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) TBD mA 1, 2

I DD5 Auto-Refresh Current: tRC = tRFC (MIN) TBD mA 1, 2, 4

I DD6 Self-Refresh Current: CKE ≤ 0.2V TBD mA 1, 2

I DD7 Operating Current: four bank; four bank interleaving with BL = 4, ad dress

and control inputs randomly changing; 50% of data changing at every

transfer; tRC = tRC (min); IOUT = 0mA. TBD mA 1, 2

1. I DD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns.

3. Enables on-chip refresh and address counters.

4. Current at 7.8 µs is time-averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs.

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AC Timing Specifications for DDR2 SDRAM Devices Used on Module

(TA = 0 °C ~ 70 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics) (Part 1 of 2)

-5A

Symbol Parameter Min. Max.

Unit Notes

tAC DQ output access time from CK/CK -0.6 +0.6 ns 1-4

tDQSCK DQS output access time from CK/CK -0.5 +0.5 ns 1-4

tCH CK high-level width 0.45 0.55 tCK 1-4

tCL CK low-level width 0.45 0.55 tCK 1-4

tHP Minimum half clk period for any given cycle;

defined by clk high (tCH) or clk low (tCL) time

tCH

tCL t

CK 1-4

tCK Clock cycle time CL=4, 5 5 8 ns 1-4

tDH DQ and DM input hold time 0.4 ns 1-4, 15,

tDS DQ and DM input setup time 0.4 ns 1-4, 15,

tIPW Input pulse width 2.2 ns 2-4, 12

tDIPW DQ and DM input pulse width (each input) 0.35 ns 1-4

tHZ Data-out high-impedance time from CK/CK tAC ns 1-4, 5

tLZ Data-out low-impedance time fro m CK/CK tAC ns 1-4, 5

tDQSQ DQS-DQ skew (DQS & associated DQ signals) 0.35 ns 1-4

tQHS Data hold Skew Factor 0.45ns tCK 1-4

tQH Data output hold time from DQS tHP -

tQHS t

CK 1-4

tDQSS Write command to 1st DQS latching transition -0.25 +0.25 tCK 1-4

tDQSL,(H) DQS input low (high) pulse width

(write cycle) 0.35 tCK 1-4

tDSS DQS falling edge to CK setup time

(write cycle) 0.2 tCK 1-4

tDSH DQS falling edge hold time from CK

(write cycle) 0.2 tCK 1-4

tMRD Mode register set command cycle time 2 tCK 1-4

tWPRES Write preamble setup time 0 ns 1-4, 7

tWPST Write postamble 0.40 0.60 tCK 1-4, 6

tWPRE Write preamble 0.25 tCK 1-4

tIH Address and control input hold time

0.6 ns

2-4, 9,

11, 12

tIS Address and control input setup time 0.6 ns 2-4, 9,

11, 12

tRPRE Read preamble 0.9 1.1 tCK 1-4

tRPST Read postamble 0.40 0.60 tCK 1-4

tRAS Active to Precharge command 45 120,000 ns 1-4

tRRD Active bank A to Active bank B command 7.5 ns 1-4

tCCD CAS to CAS 2 tCK 1-4

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AC Timing Specifications for DDR2 SDRAM Devices Used on Module

(TA = 0 °C ~ 70 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics) (Part 2 of 2)

-5A

Symbol Parameter Min. Max.

Unit Notes

tWR Write recovery time 15 ns 1-4

tDAL Auto precharge write recovery + precharge time (tWR/tCK ) +

(tRP/tCK ) t

CK 1-4, 13

tWTR Internal write to read command delay 10 tCK 1-4

tRTP Internal read to precharge command delay 7.5 ns 1-4

tXSNR Exit self refresh to a Non-read command tRFC+10 ns 1-4

tXSRD Exit self refresh to a Read command 200 tCK 1-4

tXP Exit precharge power down to any Non- read

command 2 tCK 1-4

tXARD Exit active power down to read command 2 tCK 1-4

tXARDS Exit active power down to read command 6-AL tCK 1-4

tCKE CKE minimum pulse width 3 tCK 1-4

tAOND ODT turn-on delay 2 tCK 1-4

tAON ODT turn-on tAC (min) tAC (max) +1 tCK 1-4

tAONPD ODT turn-on (Power down mode) tAC (min) +2 2tCK + 2tAC

(max) +1 tCK 1-4

tAOFD ODT turn-off delay 2.5 tCK 1-4

tAOF ODT turn-off tAC (min) tAC (max)

+0.6 tCK 1-4

tAOFPD ODT turn-off (Power down mode) tAC (min)+2 2.5tCK +

2tAC

(max) +1 tCK 1-4

tANPD ODT to power down entry latency 3 tCK 1-4

tAXPD ODT power down exit latency 8 tCK 1-4

tOIT OCD drive mode output delay 0 12 ns 1-4

tDelay Minimum time clocks remains ON after CKE

asynchronously drops Low tIS + tCK +

tIH ns 1-4

tRCD Active to Read or Write delay 15 ns 1-4

tRP Precharge command period 15 ns 1-4

tREFI Average Periodic Refresh Interval 7.8 µs 1-4, 8

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1GB: 128M x 72

Low Profile Registered DDR2 SDRAM DIMM

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Package Dimensions

FRONT

1.50

Detail A

0.039

Detail B

0.8 Width

BACK

0.059

3.80

0.15

0.157

4.00

0.031

1.00 Pitch

Detail A Detail B

0.098

2.5

10.0

0.394

133.35

131.35

128.95

5.250

5.171

5.077

PLL

17.80

3.0

0.118

0.700

30.00

1.180

(2X) 4.00

0.157

Note: All dimensions are typical with tolerances of +/- 0.15 (0. 006) unless otherwise stated.

Units: Millimeters (Inches)

NT1GT72U4PA0FU

1GB: 128M x 72

Low Profile Registered DDR2 SDRAM DIMM

REV 0.1 15

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Revision Log

Rev Date Modification

0.1 12/2003 Preliminary Release