NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM 240pin Low Profile Registered DDR2 SDRAM MODULE Based on 128Mx4 DDR2 SDRAM Features * 128Mx72 Low Profile Registered DDR2 DIMM based on * Data is read or written on both clock edges 128Mx4 DDR2 SDRAM * Bi-directional data strobe with one clock cycle preamble and * JEDEC Standard 240-pin Dual In-Line Memory Module one-half clock post-amble * Error Check Correction (ECC) Support * Address and control signals are fully synchronous to positive * Phase-lock loop (PLL) clock driver to reduce loading clock edge * Registered inputs with one-clock delay * Programmable Operation: - Device CAS Latency: 3, 4, 5 * Performance: - Burst Type: Sequential or Interleave PC2-3200 Speed Sort -5 * DIMM CAS Latency - Burst Length: 4, 8 Unit - Operation: Burst Read and Write 4 f CK Clock Frequency 200 t CK Clock Cycle f DQ DQ Burst Frequency * Auto Refresh (CBR) and Self Refresh Modes MHz 5 ns 400 MHz * Automatic and controlled precharge commands * 14/11/2 Addressing (row/column/bank) * Intended for 200 MHz applications * 7.8 s Max. Average Periodic Refresh Interval * Inputs and outputs are SSTL-18 compatible * Serial Presence Detect * VDD = 1.8Volt 0.1, VDDQ = 1.8Volt 0.1 * Gold contacts * SDRAMs have 4 internal banks for concurrent operation * SDRAMs in 84-ball FBGA Package * Differential clock inputs * One clock cycle added for registered DIMMs to account for input register. Description NT1GT72U4PA0FU is a Low Profile Registered 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank 128Mx72 high-speed memory array. The module uses nine 128Mx4 DDR2 SDRAMs in FBGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 200 MHz clock speeds and achieves high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. Ordering Information Part Number NT1GT72U4PA0FU-5A REV 0.1 12/2003 Speed 200MHz (5ns @ CL = 4) DDR2-400 PC2-3200 Organization Leads Power 128Mx72 Gold 1.8V 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM Pin Description CK0, CK0 CKE0, CKE1 Differential Clock Inputs DQ0-DQ63 Clock Enable CB0-CB7 Data input/output ECC Check Bit Data Input/Output RAS Row Address Strobe CAS Column Address Strobe WE Write Enable DQS0-DQS17 CS0, CS1 Chip Selects VDD Power (1.8V) VREF Ref. Voltage for SSTL_18 inputs A0-A9, A11-A13 A10/AP BA0, BA1 RESET ODT0, ODT1 NC REV 0.1 12/2003 DQS0-DQS8 Bidirectional data strobes DM0-DM8/DQS9-17 Input Data Mask/High Data Strobes Address Inputs Column Address Input/Auto-precharge VDDSPD Differential data strobes Serial EEPROM positive power supply SDRAM Bank Address Inputs VSS Reset pin SCL Serial Presence Detect Clock Input Active termination control lines SDA Serial Presence Detect Data input/output No Connect SA0-2 Ground Serial Presence Detect Address Inputs 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM Pinout Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 VREF 42 CB0 82 VSS 123 DQ5 164 DM8, DQS17 204 VSS 2 VSS 43 CB1 83 DQS4 124 VSS 165 DQS17 205 DQ38 3 DQ0 44 VSS 84 DQS4 125 DM0, DQS9 166 VSS 206 DQ39 4 DQ1 45 DQS8 85 VSS 126 DQS9 167 CB6 207 VSS 5 VSS 46 DQS8 86 DQ34 127 VSS 168 CB7 208 DQ44 6 DQS0 47 VSS 87 DQ35 128 DQ6 169 VSS 209 DQ45 7 DQS0 48 CB2 88 VSS 129 DQ7 170 VDDQ 210 VSS 8 VSS 49 CB3 89 DQ40 130 VSS 171 NC, CKE1 211 DM5, DQS14 9 DQ2 50 VSS 90 DQ41 131 DQ12 172 VDD 212 DQS14 10 DQ3 51 VDDQ 91 VSS 132 DQ13 173 NC 213 VSS 11 VSS 52 CKE0 92 DQS5 133 VSS 174 NC 214 DQ46 12 DQ8 53 VDD 93 DQS5 134 DM1, DQS10 175 VDDQ 215 DQ47 13 DQ9 54 NC 94 VSS 135 DQS10 176 A12 216 VSS 14 VSS 55 NC 95 DQ42 136 VSS 177 A9 217 DQ52 15 DQS1 56 VDDQ 96 DQ43 137 NC 178 VDD 218 DQ53 16 DQS1 57 A11 97 VSS 138 NC 179 A8 219 VSS 17 VSS 58 A7 98 DQ48 139 VSS 180 A6 220 NC 18 RESET 59 VDD 99 DQ49 140 DQ14 181 VDDQ 221 NC 19 NC 60 A5 100 VSS 141 DQ15 182 A3 222 VSS 20 VSS 61 A4 101 SA2 142 VSS 183 A1 223 DM6, DQS15 21 DQ10 62 VDDQ 102 NC 143 DQ20 184 VDD 224 DQS15 22 DQ11 63 A2 103 VSS 144 DQ21 225 VSS 23 VSS 64 VDD 104 DQS6 145 VSS 185 CK0 226 DQ54 24 DQ16 105 DQS6 146 DM2, DQS11 186 CK0 227 DQ55 25 DQ17 65 VSS 106 VSS 147 DQS11 187 VDD 228 VSS 26 VSS 66 VSS 107 DQ50 148 VSS 188 A0 229 DQ60 27 DQS2 67 VDD 108 DQ51 149 DQ22 189 VDD 230 DQ61 28 DQS2 68 NC 109 VSS 150 DQ23 190 BA1 231 VSS 29 VSS 69 VDD 110 DQ56 151 VSS 191 VDDQ 232 DM7, DQS16 30 DQ18 70 A10/AP 111 DQ57 152 DQ28 192 RAS 233 DQS16 31 DQ19 71 BA0 112 VSS 153 DQ29 193 CS0 234 VSS 32 VSS 72 VDDQ 113 DQS7 154 VSS 194 VDDQ 235 DQ62 33 DQ24 73 WE 114 DQS7 155 DM3, DQS12 195 ODT0 236 DQ63 34 DQ25 74 CAS 115 VSS 156 DQS12 196 A13 237 VSS 35 Vss 75 VDDQ 116 DQ58 157 VSS 197 VDD 238 VDDSPD 36 DQS3 76 CS1 117 DQ59 158 DQ30 198 VSS 239 SA0 37 DQS3 77 ODT1 118 VSS 159 DQ31 199 DQ36 240 SA1 38 Vss 78 VDDQ 119 SDA 160 VSS 200 DQ37 KEY KEY 39 DQ26 79 Vss 120 SCL 161 CB4 201 VSS 40 DQ27 80 DQ32 121 VSS 162 CB5 202 DM4, DQS13 41 Vss 81 DQ33 122 DQ4 163 VSS 203 DQS13 REV 0.1 12/2003 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM Input/Output Functional Description Symbol Type Polarity Function CK0 (SSTL) The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. CK0 (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. CS0, CS1 (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE (SSTL) Active Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. VREF Supply Reference voltage for SSTL-18 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. A0 - A9 A10/AP A11, A12 (SSTL) - DQ0 - DQ63 CB0 - CB7 (SSTL) Active High VDD, VSS Supply DQS0 - DQS17 DQS0 - DQS17 (SSTL) DM0 - DM8 RESET On-Die Termination control signals Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM configurations. Power and ground for the DDR SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Input Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Input Active Low The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and the registers will be set to low level. The PLL will remain synchronized with the input clock. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. V DDSPD REV 0.1 12/2003 Supply Serial EEPROM positive power supply. 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM Functional Block Diagram (1Rank, 128Mx4 DDR SDRAMs) VSS RS0 DQS0 DQS0 DQS9 DQS DQS CS DM I/O 0 I/O 1 D0 I/O 2 I/O 3 DQ0 DQ1 DQ2 DQ3 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQ12 DQ13 DQ14 DQ15 DQS11 DQS11 DQ20 DQ21 DQ22 DQ23 DQS12 DQS12 DQS DQS CS DM I/O 0 I/O 1 D3 I/O 2 I/O 3 DQ24 DQ25 DQ26 DQ27 DQS4 DQS4 DQ28 DQ29 DQ30 DQ31 DQS13 DQS13 DQS DQS CS DM I/O 0 I/O 1 D4 I/O 2 I/O 3 DQ32 DQ33 DQ34 DQ35 DQS5 DQS5 DQ36 DQ37 DQ38 DQ39 DQS14 DQS14 DQS DQS CS DM I/O 0 I/O 1 D5 I/O 2 I/O 3 DQ40 DQ41 DQ42 DQ43 DQS6 DQS6 DQ44 DQ45 DQ46 DQ47 DQS15 DQS15 DQS DQS CS DM I/O 0 I/O 1 D6 I/O 2 I/O 3 DQ48 DQ49 DQ50 DQ51 DQS7 DQS7 DQ52 DQ53 DQ54 DQ55 DQS16 DQS16 DQS DQS CS DM I/O 0 I/O 1 D7 I/O 2 I/O 3 DQ56 DQ57 DQ58 DQ59 DQS8 DQS8 DQ60 DQ61 DQ62 DQ63 DQS17 DQS17 DQS DQS CS DM I/O 0 I/O 1 D8 I/O 2 I/O 3 CB0 CB1 CB2 CB3 R E G I S T E R PCK DQS10 DQS10 DQS DQS CS DM I/O 0 I/O 1 D2 I/O 2 I/O 3 DQ16 DQ17 DQ18 DQ19 PCK DQ4 DQ5 DQ6 DQ7 DQS DQS CS DM I/O 0 I/O 1 D1 I/O 2 I/O 3 DQ8 DQ9 DQ10 DQ11 CS0 BA0-BA1 A0-A13 RAS CAS WE CKE0 ODT0 DQS9 RS0 RBA0-RBA1 RA0-RA13 RRAS RCAS RWE RCKE0 RODT0 CB4 CB5 CB6 CB7 DQS DQS CS DM I/O 0 I/O 1 D9 I/O 2 I/O 3 DQS DQS CS DM I/O 0 I/O 1 D10 I/O 2 I/O 3 DQS DQS CS DM I/O 0 I/O 1 D11 I/O 2 I/O 3 DQS DQS CS DM I/O 0 I/O 1 D12 I/O 2 I/O 3 DQS DQS CS DM I/O 0 I/O 1 D13 I/O 2 I/O 3 DQS DQS CS DM I/O 0 I/O 1 D14 I/O 2 I/O 3 DQS DQS CS DM I/O 0 I/O 1 D15 I/O 2 I/O 3 DQS DQS CS DM I/O 0 I/O 1 D16 I/O 2 I/O 3 DQS DQS CS DM I/O 0 I/O 1 D17 I/O 2 I/O 3 VDDSPD VDDQ VDD VREF VSS VDDID CS : SDRAMs D0-D8 BA0-BA1 : SDRAMs D0-D8 A0-A13 : SDRAMs D0-D8 RAS : SDRAMs D0-D8 CAS : SDRAMs D0-D8 WE : SDRAMs D0-D8 CKE : SDRAMs D0-D8 ODT0 : SDRAMs D0-D8 Serial PD D0-D17 D0-D17 D0-D17 D0-D17 Strap : see Note 4 Serial PD RESET SCL WP A0 Notes : REV 0.1 12/2003 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/CS relationships are maintained as shown. 3. DQ/DQS resistors are 22 Ohms. 4. VDDID strap connections (for memory device VDD,VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ 5. Address and control resistors are 22 Ohms. SA0 A1 A2 SA1 SA2 SDA CK0, CK0 --------- PLL* * Wire per Clock Loading Table/Wiring Diagrams 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 128Mx72 1 BANK REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-400 -5A DDR2-400 -5A Description 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type DDR2-SDRAM 08 3 Number of Row Addresses on Assembly 14 0E 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Bank 1 60 6 Data Width of Assembly X72 48 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8 05 9 DDR2 SDRAM Device Cycle Time at CL=5 5ns 50 10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.6ns 60 11 DIMM Configuration Type ECC 02 12 Refresh Rate/Type SR/1x(7.8us) 82 13 Primary DDR SDRAM Width X8 08 X8 08 14 Error Checking DDR SDRAM Device Width 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported Undefined 00 4,8 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 4/5 38 19 Reserved Undefined 00 20 DDR2 SDRAM DIMM Type Information Reg. DIMM 01 21 DDR2 SDRAM Module Attributes: Normal DIMM 00 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 24 Maximum Data Access Time from Clock at CL=4 25 Minimum Clock Cycle Time at CL=3 Include weak driver 01 5ns 50 0.6ns 60 5ns 50 26 Maximum Data Access Time from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 20ns 50 28 Minimum Row Active to Row Active delay (tRRD) 15ns 3C 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 31 Module Bank Density 512MB 80 32 Address and Command Setup Time Before Clock (tIS) 0.6ns 60 33 Address and Command Hold Time After Clock (tIH) 0.6ns 60 34 Data Input Setup Time Before Clock (tDS) 0.4ns 40 35 Data Input Hold Time After Clock (tDH) 0.4ns 40 36 Write Recovery Time (tWR) 15ns 3C 37 Internal Write to Read Command delay (tWTR) 10ns 28 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Reserved Undefined 00 40 Extension of Byte 41 tRC and Byte 42 tRFC 60ns 3C 41 Minimum Core Cycle Time (tRC) 60ns 3C 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 43 Maximum Clock Cycle Time (tCK) 8ns 80 REV 0.1 12/2003 Note 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 128Mx72 1 BANK REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-400 -5A DDR2-400 -5A Description 44 Max. DQS-DQ Skew Factor (tQHS) 0.35ns 23 45 Read Data Hold Skew Factor (tQHS) 0.45ns 2D 46 PLL Relock Time 15us 0F 47-61 Reserved 62 SPD Revision 63 Checksum Data 00 Initial 00 NANYA 7F7F7F0B00000000 N/A 00 D7 64-71 Manufacturer's JEDEC ID Code 72 Undefined Note Module Manufacturing Location 73-90 Module Part number N/A 00 91-92 Module Revision Code N/A 00 Year/Week Code yy/ww Serial Number 00 Undefined 00 93-94 Module Manufacturing Data 95-98 Module Serial Number 99-255 Reserved 1, 2 yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex) ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) REV 0.1 12/2003 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM Absolute Maximum Ratings Symbol VIN, VOUT Parameter Voltage on I/O pins relative to Vss Rating Units -0.5 to VDDQ+0.5 V VIN Voltage on Input relative to Vss -0.5 to +2.3 V VDD Voltage on VDD supply relative to Vss -0.5 to +2.3 V Voltage on VDDQ supply relative to Vss -0.5 to +2.3 V 0 to +70 C -55 to +100 C Power Dissipation TBD W Short Circuit Output Current TBD mA VDDQ TA TSTG PD IOUT Operating Temperature (Ambient) Storage Temperature (Plastic) Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance Parameter Symbol Max. Units Notes Input Capacitance: CK0, CK0 CI1 TBD pF 1 Input Capacitance: A0-A12, BA0, BA1, WE, RAS, CAS, CKE0, S0 CI2 TBD pF 1 Input Capacitance: RESET CI3 TBD pF 1 Input Capacitance: SA0-SA2, SCL CI4 TBD pF 1 Input/Output Capacitance DQ0-63; DQS0-8, CB0-7 CIO1 TBD pF 1, 2 Input/Output Capacitance: SDA CIO3 TBD pF 1. 2. VDDQ = VDD = 1.8V 0.1V, f = 100 MHz, TA = 25 C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V. DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level. REV 0.1 12/2003 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM DC Electrical Characteristics and Operating Conditions (TA = 0 C ~ 70 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) Symbol VDD VDDQ VSS, VSSQ VREF VTT 3. 4. Parameter Max Units Notes 1.7 1.9 V 1 I/O Supply Voltage 1.7 1.9 V 1 0 0 V I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3 1 Supply Voltage, I/O Supply Voltage VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1 Input Differential Voltage, CK and CK Inputs VID (DC) 1. 2. Min Supply Voltage 0.30 V DDQ + 0.6 V 1, 4 IIL Input Leakage Current Any input 0V VIN VDD; (All other pins not under test = 0V) -5 5 uA 1 IOZ Output Leakage Current (DQs are disabled; 0V Vout VDDQ -5 5 uA 1 IOH Output High Current (VOUT = VDDQ -0.373V, min VREF, min VTT) TBD - mA 1 IOL Output Low Current (VOUT = 0.373, max VREF, max VTT) TBD - mA 1 Inputs are not recognized as valid until VREF stabilizes. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. VID is the magnitude of the difference between the input level on CK and the input level on CK. REV 0.1 12/2003 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_18 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. AC Output Load Circuits VTT 50 ohms Output Timing Reference Point VOUT 30 pF AC Operating Conditions (TA = 0 C ~ 70 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) Symbol Parameter/Condition Min Max Unit Notes VIH (AC) Input High (Logic 1) Voltage V REF + 0.31 - V 1, 2 VIL (AC) Input Low (Logic 0) Voltage - V REF - 0.31 V 1, 2 0.7 V DDQ + 0.6 V 1, 2, 3 0.5 x VDDQ - 0.2 0.5 x VDDQ + 0.2 V 1, 2, 4 VID (AC) Input Differential Voltage, CK and CK Inputs VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs 1. 2. 3. 4. Input slew rate = 1V/ ns. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to equal 0.5 x VDDQ of the transmitting device and must track variations in the DC level of the same. REV 0.1 12/2003 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents (TA = 0 C ~ 70 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) Symbol Parameter/Condition PC2-3200 (-5A) Unit Notes I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle TBD mA 1, 2 I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle TBD mA 1, 2 I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) TBD mA 1, 2 I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle TBD mA 1, 2 I DD3P Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) TBD mA 1, 2 I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle TBD mA 1, 2 I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA TBD mA 1, 2 I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) TBD mA 1, 2 I DD5 Auto-Refresh Current: tRC = tRFC (MIN) TBD mA 1, 2, 4 I DD6 Self-Refresh Current: CKE 0.2V TBD mA 1, 2 I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. TBD mA 1, 2 1. 2. 3. 4. I DD specifications are tested after the device is properly initialized. Input slew rate = 1V/ ns. Enables on-chip refresh and address counters. Current at 7.8 s is time-averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s. REV 0.1 12/2003 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TA = 0 C ~ 70 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol tAC tDQSCK -5A Parameter Unit Notes +0.6 ns 1-4 +0.5 ns 1-4 Min. Max. DQ output access time from CK/CK -0.6 DQS output access time from CK/CK -0.5 tCH CK high-level width 0.45 0.55 tCK 1-4 tCL CK low-level width 0.45 0.55 tCK 1-4 tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCH or tCL tCK 1-4 tCK Clock cycle time ns 1-4 tDH DQ and DM input hold time 0.4 ns 1-4, 15, 16 tDS DQ and DM input setup time 0.4 ns 1-4, 15, 16 tIPW Input pulse width 2.2 ns 2-4, 12 tDIPW DQ and DM input pulse width (each input) 0.35 ns 1-4 tHZ Data-out high-impedance time from CK/CK tAC ns 1-4, 5 tLZ Data-out low-impedance time from CK/CK tAC ns 1-4, 5 0.35 ns 1-4 0.45ns tCK 1-4 tCK 1-4 tCK 1-4 tDQSQ tQHS tQH tDQSS CL=4, 5 5 DQS-DQ skew (DQS & associated DQ signals) Data hold Skew Factor Data output hold time from DQS tHP tQHS 8 Write command to 1st DQS latching transition -0.25 DQS input low (high) pulse width (write cycle) 0.35 tCK 1-4 tDSS DQS falling edge to CK setup time (write cycle) 0.2 tCK 1-4 tDSH DQS falling edge hold time from CK (write cycle) 0.2 tCK 1-4 tMRD Mode register set command cycle time 2 tCK 1-4 Write preamble setup time 0 ns 1-4, 7 tDQSL,(H) tWPRES +0.25 tWPST Write postamble 0.40 tCK 1-4, 6 tWPRE Write preamble 0.25 tCK 1-4 0.6 ns 2-4, 9, 11, 12 Address and control input setup time 0.6 ns 2-4, 9, 11, 12 Read preamble 0.9 1.1 tCK 1-4 tRPST Read postamble 0.40 0.60 tCK 1-4 tRAS Active to Precharge command 45 120,000 ns 1-4 tRRD Active bank A to Active bank B command 7.5 ns 1-4 tCCD CAS to CAS 2 tCK 1-4 tIH tIS tRPRE REV 0.1 12/2003 Address and control input hold time 0.60 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TA = 0 C ~ 70 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol -5A Parameter Min. tWR Write recovery time tDAL Auto precharge write recovery + precharge time tWTR Internal write to read command delay tRTP Internal read to precharge command delay tXSNR Exit self refresh to a Non-read command tXSRD Exit self refresh to a Read command tXP Unit Notes Max. 15 ns 1-4 (tWR/tCK ) + (tRP/tCK ) tCK 1-4, 13 10 tCK 1-4 7.5 ns 1-4 tRFC+10 ns 1-4 200 tCK 1-4 2 tCK 1-4 Exit precharge power down to any Non- read command tXARD Exit active power down to read command 2 tCK 1-4 tXARDS Exit active power down to read command 6-AL tCK 1-4 3 tCK 1-4 tCKE CKE minimum pulse width tAOND ODT turn-on delay tAON ODT turn-on tAONPD ODT turn-on (Power down mode) tAOFD ODT turn-off delay tAOF ODT turn-off tCK 1-4 tAC (min) 2 tAC (max) +1 tCK 1-4 tAC (min) +2 2tCK + 2tAC (max) +1 tCK 1-4 tCK 1-4 2.5 tAC (min) tAC (max) +0.6 tCK 1-4 2.5tCK + 2tAC (max) +1 tCK 1-4 1-4 tAOFPD ODT turn-off (Power down mode) tAC (min)+2 tANPD ODT to power down entry latency 3 tCK tAXPD ODT power down exit latency 8 tCK 1-4 tOIT OCD drive mode output delay 0 ns 1-4 tIS + tCK + tIH ns 1-4 1-4 12 tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tRCD Active to Read or Write delay 15 ns Precharge command period 15 ns 1-4 s 1-4, 8 tRP tREFI REV 0.1 12/2003 Average Periodic Refresh Interval 7.8 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM Package Dimensions FRONT 131.35 5.171 10.0 0.394 Register (2X) 4.00 0.157 128.95 5.077 30.00 1.180 133.35 5.250 Detail B 17.80 0.700 Detail A 2.5 0.098 3.0 0.118 PLL Register BACK Detail B 3.80 0.15 4.00 0.157 Detail A 1.50 0.059 0.8 Width 0.031 1.00 Pitch 0.039 Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) REV 0.1 12/2003 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM Revision Log Rev Date 0.1 12/2003 REV 0.1 12/2003 Modification Preliminary Release 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.