Datasheet Serial EEPROM Series Standard EEPROM I2C BUS EEPROM (2-Wire) BR24T64-W General Description BR24T64-W is a serial EEPROM of I2C BUS Interface Method Features Packages W(Typ) x D(Typ) x H(Max) Completely conforming to the world standard I 2C BUS. All controls available by 2 ports of serial clock (SCL) and serial data (SDA) Other devices than EEPROM can be connected to the same port, saving microcontroller port 1.6V to 5.5V Single Power Source Operation most suitable for battery use 1.6V to 5.5V wide limit of operation voltage, possible FAST MODE 400KHz operation Page Write Mode useful for initial value write at factory shipment Self-timed Programming Cycle Low Current Consumption Prevention of Write Mistake Write (Write Protect) Function added Prevention of Write Mistake at Low Voltage More than 1 million write cycles More than 40 years data retention Noise filter built in SCL / SDA terminal Initial delivery state FFh DIP-T8 TSSOP-B8 9.30mm x 6.50mm x 7.10mm 3.00mm x 6.40mm x 1.20mm DIP8K TSSOP-B8J 9.27mm x 6.35mm x 8.63mm 3.00mm x 4.90mm x 1.10mm SOP8 MSOP8 5.00mm x 6.20mm x 1.71mm 2.90mm x 4.00mm x 0.90mm SOP-J8 VSON008X2030 4.90mm x 6.00mm x 1.65mm 2.00mm x 3.00mm x 0.60mm SSOP-B8 3.00mm x 6.40mm x 1.35mm Figure 1. BR24T64-W Capacity Bit Format Type Power Source Voltage DIP-T8 (1) BR24T64-W 64Kbit 8Kx8 Package BR24T64-WZ DIP8K BR24T64F-W SOP8 BR24T64FJ-W SOP-J8 BR24T64FV-W 1.6V to 5.5V SSOP-B8 BR24T64FVT-W TSSOP-B8 BR24T64FVJ-W TSSOP-B8J BR24T64FVM-W MSOP8 BR24T64NUX-W VSON008X2030 (1) Not Recommended for New Designs. Recommend BR24T64-WZ. Product structureSilicon monolithic integrated circuit www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211114001 This product has no designed protection against radioactive rays 1/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Absolute Maximum Ratings (Ta=25C) Parameter Symbol Rating Unit Vcc -0.3 to +6.5 V Supply Voltage Power Dissipation 450 (SOP8) Derate by 4.5mW/C when operating above Ta=25C 450 (SOP-J8) Derate by 4.5mW/C when operating above Ta=25C 300 (SSOP-B8) Derate by 3.0mW/C when operating above Ta=25C 330 (TSSOP-B8) Derate by 3.3mW/C when operating above Ta=25C 310 (TSSOP-B8J) Pd Remark mW Derate by 3.1mW/C when operating above Ta=25C 310 (MSOP8) Derate by 3.1mW/C when operating above Ta=25C 300 (VSON008X2030) Derate by 3.0mW/C when operating above Ta=25C 800 (DIP-T8 (1)) Derate by 8.0mW/C when operating above Ta=25C Derate by 8.52mW/C when operating above Ta=25C When mounted (on 114.5 mm x 101.5 mm x 1.6 mm thick, glass epoxy on single-layer substrate). 852 (DIP8K) Storage Temperature Tstg -65 to +150 C Operating Temperature Topr -40 to +85 C Input Voltage / Output Voltage Junction Temperature Electrostatic discharge voltage (human body model) -0.3 to Vcc+1.0 V Tjmax 150 C VESD -4000 to +4000 V The Max value of input voltage / output voltage is not over 6.5V. When the pulse width is 50ns or less, the Min value of input voltage / output voltage is not lower than -1.0V. Junction temperature at the storage condition (1) Not Recommended for New Designs. Recommend BR24T64-WZ. Memory Cell Characteristics (Ta=25C, Vcc=1.6V to 5.5V) Parameter Min 1,000,000 40 Write Cycles (1) Data Retention(1) Limit Typ - Max - Unit Times Years (1) Not 100% TESTED Recommended Operating Ratings Parameter Power Source Voltage Input Voltage Symbol Vcc VIN Rating 1.6 to 5.5 0 to Vcc Unit V DC Characteristics (Unless otherwise specified, Ta=-40C to +85C, Vcc=1.6V to 5.5V) Parameter Symbol Input High Voltage1 VIH1 Limit Unit Conditions Min Typ Max 0.7Vcc - Vcc+1.0 V 1.7VVcc5.5V (2) Input Low Voltage1 VIL1 -0.3 - +0.3Vcc V 1.7VVcc5.5V Input High Voltage2 VIH2 0.8Vcc - Vcc+1.0 V 1.6VVcc1.7V - +0.2Vcc V 1.6VVcc1.7V (2) Input Low Voltage2 VIL2 -0.3 Output Low Voltage1 VOL1 - - 0.4 V IOL=3.0mA, 2.5VVcc5.5V (SDA) Output Low Voltage2 VOL2 - - 0.2 V IOL=0.7mA, 1.6VVcc2.5V (SDA) Input Leakage Current ILI -1 - +1 A VIN=0 to Vcc Output Leakage Current ILO -1 - +1 A Supply Current (Write) ICC1 - - 2.0 mA Supply Current (Read) ICC2 - - 0.5 mA Standby Current ISB - - 2.0 A VOUT=0 to Vcc (SDA) Vcc=5.5V, fSCL=400kHz, tWR=5ms, Byte write, Page write Vcc=5.5V, fSCL=400kHz Random read, current read, sequential read Vcc=5.5V, SDASCL=Vcc A0,A1,A2=GND,WP=GND (2) When the pulse width is 50ns or less, it is -1.0V. www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 2/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W AC Characteristics (Unless otherwise specified, Ta=-40C to +85C, Vcc=1.6V to 5.5V) Parameter Limit Symbol Min Typ Max Unit Clock Frequency fSCL - - 400 kHz Data Clock High Period tHIGH 0.6 - - s Data Clock Low Period tLOW 1.2 - - s tR - - 1.0 s SDA,SCL(INPUT) Rise Time (1) SDA,SCL (INPUT)Fall Time (1) tF1 - - 1.0 s SDA(OUTPUT)Fall Time (1) tF2 - - 0.3 s Start Condition Hold Time tHD:STA 0.6 - - s Start Condition Setup Time tSU:STA 0.6 - - s Input Data Hold Time tHD:DAT 0 - - ns Input Data Setup Time tSU:DAT 100 - - ns Output Data Delay Time tPD 0.1 - 0.9 s Output Data Hold Time tDH 0.1 - - s Stop Condition Setup Time tSU:STO 0.6 - - s Bus Free Time tBUF 1.2 - - s Write Cycle Time tWR - - 5 ms tI - - 0.1 s tHD:WP 1.0 - - s WP Setup Time tSU:WP 0.1 - - s WP High Period tHIGH:WP 1.0 - - s Noise Spike Width (SDA and SCL) WP Hold Time (1) Not 100% TESTED. Condition Input Data Level:VIL=0.2xVcc VIH=0.8xVcc Input Data Timing Reference Level: 0.3xVcc/0.7xVcc Output Data Timing Reference Level: 0.3xVcc/0.7xVcc Rise/Fall Time : 20ns Serial Input / Output Timing tR SCL tF1 30% 70% 70% tHD:DAT tSU:DAT 70% 70% SDA 30% tWR 30% 30% 30% tF2 Input read at the rise edge of SCL 70% SDA (output) tSU:WP tSU:WP tHD:WP STOP STOP CONDITION CONDITION 70% Data output in sync with the fall of SCL 30% 30% Figure 2-(a). Serial Input / Output Timing Figure 2-(d). WP Timing at Write Execution 70% D1 D1 tSU:STA tHD:STA tSU:STO STOP CONDITION START CONDITION D0 ACK ACK ACK 70% 70% tWR tWR Fig1-(5) WP timing at write execution 30% Fig1-(6) WP timing at write cancel FigureSTART 2-(b). Start-Stop Bit Timing STOP CONDITION CONDITION write data (n-th address) ACK ACK 70% 70% 70% Fig1-(4) Write70% cycle timing 30% 30% D0 D0 tHIGH:WP tHIGH:WP 70% 30% DATA(n) DATA(n) DATA(1) DATA(1) 70% 70% 70% ACK ACK 30% 70% 70% () (OUTPUT) D0 D1 tDH tPD tBUF DATA(n) DATA(1) 70% 30% 30% SDA () (INPUT) 70% 30% 30% 30% tLOW tHD:STA 70% tHIGH 70% 70% 70% Figure 2-(e). WP Timing at Write Cancel 70% 70% tWR STOP CONDITION START CONDITION Figure 2-(c). Write Cycle Timing Fig1-(5) WP timing at write execution Fig1-(6) WP timing at write cancel www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 3/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Block Diagram A0 1 64Kbit EEPROM Array 8 VCC 7 WP 6 SCL 8bit A1 Address Decoder 2 Word Address Register 13bit START A2 3 Data Register STOP Control Circuit ACK High Voltage Generating Circuit GND 4 Power Source Voltage Detection 5 SDA Figure 3. Block Diagram Pin Configuration (TOP VIEW) A0 1 A1 2 8 VCC 7 WP BR24T64-W A2 3 6 SCL GND 4 5 SDA Pin Descriptions Terminal Name Input/ Output A0 Input Slave address setting* A1 Input Slave address setting* A2 Input Slave address setting* GND SCL Input/ Output Input WP Input VCC - SDA Descriptions Reference voltage of all input / output, 0V Serial data input serial data output Serial clock input Write protect terminal Connect the power source. *A0, A1 and A2 are not allowed to use as open. www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 4/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Typical Performance Curves 6 6 5 Ta=-40 Ta= 25 Ta= 85 4 Input Low Voltage: VIL1(V) 5 Input High Voltage: VIH1 (V) Ta=-40 Ta= 25 Ta= 85 SPEC 3 2 4 3 2 1 1 SPEC 0 0 0 1 2 3 4 5 6 0 1 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 5. Input Low Voltage1,2 vs Supply Voltage (A0, A1, A2, SCL, SDA, WP) Figure 4. Input High Voltage1,2 vs Supply Voltage (A0, A1, A2, SCL, SDA, WP) 1 1 Ta=-40 Ta= 25 Ta= 85 0.8 Output Low Voltage2: VOL2(V) Output Low Voltage1: VOL1(V) 2 0.6 SPEC 0.4 0.2 Ta=-40 Ta= 25 Ta= 85 0.8 0.6 0.4 SPEC 0.2 0 0 0 1 2 3 4 5 0 6 2 3 4 5 6 Output Low Current: IOL(mA) Output Low Current: IOL(mA) Fig 6. Output Low Voltage1 vs Output Low Current (Vcc=2.5V) www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 1 Fig 7. Output Low Voltage2 vs Output Low Current (Vcc=1.6V) 5/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Typical Performance Curvescontinued 1.2 1.2 SPEC SPEC Output Leakage Current: I LO(A) Input Leakage Current : I LI (A) 1 Ta=-40 Ta= 25 Ta= 85 0.8 0.6 0.4 1 0.6 0.4 0.2 0.2 0 0 0 1 2 3 4 5 Ta=-40 Ta= 25 Ta= 85 0.8 0 6 1 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 8. Input Leakage Current vs Supply Voltage (A0, A1, A2, SCL, WP) Figure 9. Output Leakage Current vs Supply Voltage (SDA) 3 0.6 2.5 0.5 Supply Current (Read): Icc 2(mA) Supply Current (Write): Icc1(mA) SPEC SPEC 2 1.5 Ta=-40 Ta= 25 Ta= 85 1 Ta=-40 Ta= 25 Ta= 85 0.4 0.3 0.2 0.1 0.5 0 0 0 1 2 3 4 5 0 6 1 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 10. Supply Current (Write) vs Supply Voltage (fSCL=400kHz) Figure 11. Supply Current (Read) vs Supply Voltage (fSCL=400kHz) www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 6/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Typical Performance Curvescontinued 2.5 10000 SPEC 1000 Clock Frequency: fscl(kHz) Standby Current: I SB (A) 2 Ta=-40 Ta= 25 Ta= 85 1.5 1 0.5 SPEC 100 Ta=-40 Ta= 25 Ta= 85 10 1 0 0 1 2 3 4 5 0.1 6 0 1 2 Supply Voltage: Vcc(V) 4 5 6 Supply Voltage: Vcc(V) Figure 13. Clock Frequency vs Supply Voltage Figure 12. Standby Current vs Supply Voltage 1 1.5 Data Clock Low Period : t LOW(s) Data Clock High Period : t HIGH(s) 3 0.8 SPEC 0.6 Ta=-40 Ta= 25 Ta= 85 0.4 0.2 0 0 1 2 3 4 5 Ta=-40 Ta= 25 Ta= 85 0.9 0.6 0.3 0 6 0 Supply Voltage: Vcc(V) 1 2 3 4 5 6 Supply Voltage: Vcc(V) Figure 14. Data Clock High Period vs Supply Voltage www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 SPEC 1.2 Figure 15. Data Clock Low Period vs Supply Voltage 7/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Typical Performance Curvescontinued 1 Start Condition Setup Time: t SU:STA (s) Start Condition Hold Time: t HD:STA(s) 1 0.8 SPEC 0.6 Ta=-40 Ta= 25 Ta= 85 0.4 0.2 0.8 SPEC 0.6 Ta=-40 Ta= 25 Ta= 85 0.4 0.2 0 -0.2 0 0 1 2 3 4 5 0 6 1 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 17. Start Condition Setup Time vs Supply Voltage Figure 16. Start Condition Hold Time vs Supply Voltage 50 50 SPEC Input Data Hold Time: t HD:DAT(ns) Input Data Hold Time: t HD:DAT (ns) 2 0 -50 -100 Ta=-40 Ta= 25 Ta= 85 -150 SPEC 0 -50 Ta=-40 Ta= 25 Ta= 85 -100 -150 -200 -200 0 1 2 3 4 5 6 1 2 3 4 5 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 18. Input Data Hold Time vs Supply Voltage (HIGH) www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 0 Figure 19. Input Data Hold Time vs Supply Voltage (LOW) 8/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 6 Datasheet BR24T64-W Typical Performance Curvescontinued 300 Input Data Setup Time: t SU:DAT(ns) Input Data Setup Time: t SU:DAT(ns) 300 200 SPEC 100 0 Ta=-40 Ta= 25 Ta= 85 -100 -200 200 SPEC 100 0 Ta=-40 Ta= 25 Ta= 85 -100 -200 0 1 2 3 4 5 6 0 1 Supply Voltage: Vcc(V) 3 4 5 6 Supply Voltage: Vcc(V) Figure 20. Input Data Setup Time vs Supply Voltage (HIGH) Figure 21. Input Data Setup Time vs Supply Voltage (LOW) 2 `H' Output Data Delay Time: t PD (s) 2 `L' Output Data Delay Time: t PD(s) 2 Ta=-40 Ta= 25 Ta= 85 1.5 SPEC 1 0.5 Ta=-40 Ta= 25 Ta= 85 1.5 SPEC 1 0.5 SPEC SPEC 0 0 0 1 2 3 4 5 0 6 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 22. `L' Output Data Delay Time vs Supply Voltage www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 1 9/34 Figure 23. `H' Output Data Delay Time vs Supply Voltage TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Typical Performance Curvescontinued 2 Ta=-40 Ta= 25 Ta= 85 1.5 Bus Free Time : t BUF(s) Stop Condition Setup Time: t SU:STO(s) 2 1 SPEC 0.5 1.5 SPEC 1 Ta=-40 Ta= 25 Ta= 85 0.5 0 -0.5 0 0 1 2 3 4 5 0 6 1 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 24. Stop Condition Setup Time vs Supply Voltage Figure 25. Bus Free Time vs Supply Voltage 0.6 6 SPEC Noise Spike Width:tI(SCL H)(s) Write Cycle Time: t WR(ms) 5 4 3 2 Ta=-40 Ta= 25 Ta= 85 1 0.5 Ta=-40 Ta= 25 Ta= 85 0.4 0.3 0.2 0.1 SPEC 0 0 0 1 2 3 4 5 6 1 2 3 4 5 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 27. Noise Spike Width vs Supply Voltage (SCL H) Figure 26. Write Cycle Time vs Supply Voltage www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 0 10/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 6 Datasheet BR24T64-W Typical Performance Curvescontinued 0.6 0.5 Ta=-40 Ta= 25 Ta= 85 0.4 0.5 Noise Spike Width(SDA H): tI(s) Noise Spike Width(SCL L): tI(s) 0.6 0.3 0.2 0.1 Ta=-40 Ta= 25 Ta= 85 0.4 0.3 0.2 0.1 SPEC 0 SPEC 0 0 1 2 3 4 5 6 0 1 2 Supply Voltage: Vcc(V) 3 4 5 6 Supply Voltage: Vcc(V) Figure 29. Noise Spike Width vs Supply Voltage (SDA H) Figure 28. Noise Spike Width vs Supply Voltage (SCL L) 0.6 1.2 0.5 1 Ta=-40 Ta= 25 Ta= 85 0.4 WP Hold Time: t HD:WP(s) Noise Spike Width(SDA L): tI(s) SPEC 0.3 0.2 0.1 0.8 Ta=-40 Ta= 25 Ta= 85 0.6 0.4 0.2 SPEC 0 0 0 1 2 3 4 5 6 Supply Voltage: Vcc(V) 1 2 3 4 5 Supply Voltage: Vcc(V) Figure 30. Noise Spike Width vs Supply Voltage (SDA L) www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 0 11/34 Figure 31. WP Hold Time vs Supply Voltage TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 6 Datasheet BR24T64-W Typical Performance Curvescontinued 0.2 1.2 SPEC SPEC 0 WP High Period : t HIGH:WP ( s) WP Setup Time: t SU:WP(s) 0.1 Ta=-40 Ta= 25 Ta= 85 -0.1 -0.2 -0.3 -0.4 1 0.8 Ta=-40 Ta= 25 Ta= 85 0.6 0.4 0.2 -0.5 0 -0.6 0 0 1 2 3 4 5 1 2 3 4 5 6 Supply Voltage: Vcc(V) Supply Voltage: Vcc(V) Figure 32. WP Setup Time vs Supply Voltage www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 Figure 33. WP High Period vs Supply Voltage 12/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 6 Datasheet BR24T64-W Timing Chart 1. I2C BUS Data Communication I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte. I 2C BUS data communication with several devices is possible by connecting with 2 communication lines: serial data (SDA) and serial clock (SCL). Among the devices, there should be a "master" that generates clock and control communication start and end. The rest become "slave" which are controlled by an address peculiar to each device, like this EEPROM. The device that outputs data to the bus during data communication is called "transmitter", and the device that receives data is called "receiver".. SDA 1-7 SCL S START ADDRESS condition 8 9 R/W ACK 1-7 8 DATA 9 ACK 1-7 DATA 8 9 ACK P STOP condition Figure 34. Data Transfer Timing 2. Start Condition (Start Bit Recognition) (1) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH' is necessary. (2) This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is satisfied, any command cannot be executed. 3. Stop Condition (Stop Bit Recongition) (1) Each command can be ended by a stop condition (stop bit) where SDA goes from 'LOW' to 'HIGH' while SCL is 'HIGH'. 4. Acknowledge (ACK) Signal (1) The acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In a master-slave communication, the device (Ex. -COM sends slave address input for write or read command, to this IC ) at the transmitter (sending) side releases the bus after output of 8bit data. (2) The device (Ex. This IC receives the slave address input for write or read command from the -COM) at the receiver (receiving) side sets SDA 'LOW' during the 9th clock cycle, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data. (3) This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'. (4) After receiving 8bit data (word address and write data) during each write operation, this IC outputs acknowledge signal (ACK signal) 'LOW'. (5) During read operation, this IC outputs 8bit data (read data) and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (-COM) side, this IC continues to output data. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, recognizes stop condition (stop bit), and ends read operation. Then this IC becomes ready for another transmission. 5. Device Addressing (1) Slave address comes after start condition from master. (2) The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'. (3) Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. (4) The most insignificant bit ( R / W --- READ / WRITE ) of slave address is used for designating write or read operation, and is as shown below. Setting R / W to 0 ------- write (setting 0 to word address setting of random read) Setting R / W to 1 ------- read Maximum Number of Connected Buses Slave Address 1 0 1 0 A2 A1 A0 www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 R/ W 8 13/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Write Command 1. Write Cycle (1) Arbitrary data can be written to this EEPROM. When writing only 1 byte, Byte Write is normally used, and when writing continuous data of 2 bytes or more, simultaneous write is possible by Page Write cycle. The maximum number of bytes is specified per device of each capacity. Up to 8 arbitrary bytes can be written. S T A R T SDA LINE W R I T E SLAVE ADDRESS 1st WORD ADDRESS 1 0 1 0 A2 A1 A0 * * * 2nd WORD ADDRESS DATA WAWA 12 11 WA 0 A C K R A / C W K S T O P D7 D0 A C K *Don't Care bit A C K Figure 35. Byte Write Cycle S T A R T SDA LINE W R I T E SLAVE ADDRESS 1 0 1 0 A2 A1 A0 1st WORD ADDRESS(n) *** 2nd WORD ADDRESS(n) DATA(n) WA WA WA 12 11 0 R A / C W K A C K D7 S T O P DATA(n+31) D0 D0 *Don't Care bit A C K A C K A C K Figure 36. Page Write Cycle (2) (3) (4) (5) (6) During internal write execution, all input commands are ignored, therefore ACK is not returned. Data is written to the address designated by word address (n-th address) By issuing stop bit after 8bit data input, internal write to memory cell starts. When internal write is started, command is not accepted for tWR (5ms at maximum). Using page write cycle, writing in bulk is done as follows: When data of more than 32 bytes is sent, the bytes in excess overwrite the data already sent first. (Refer to "Internal address increment".) (7) As for page write cycle of BR24T64-W, where 2 or more bytes of data is intended to be written, after the 8 significant bits of word address are designated arbitrarily, only the value of 5 least significant bits in the address is incremented internally, so that data up to 32 bytes of memory only can be. In the case BR24T64-W, 1 page=32bytes, but the page write cycle time is 5ms at maximum for 32byte bulk write. It does not stand 5ms at maximum x 32byte=160ms(Max) 2. Internal Address Increment Page write mode (in the case of BR24T64-W) 1Eh WA7 WA6 WA5 WA4 WA3 WA2 WA1 WA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 0 Significant bit is fixed. No digit up Increment For example, when it is started from address 1Eh, then, increment is made as below, 1Eh1Fh00h01h please take note. 1Eh1E in hexadecimal, therefore, 00011110 becomes a binary number. 3. Write Protect (WP) Terminal Write Protect (WP) Function When WP terminal is set at Vcc (H level), data rewrite of all addresses is prohibited. When it is set at GND (L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not leave it open. In case of using it as an ROM, it is recommended to connect it to pull up or Vcc. At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', write error can be prevented. www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 14/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Read Command 1. Read Cycle Read cycle is when data of EEPROM is read. Read cycle could be random read cycle or current read cycle. Random read cycle is a command to read data by designating a specific address, and is used generally. Current read cycle is a command to read data of internal address register without designating an address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available where the next address data can be read in succession. S T A R T SDA LINE SLAVE ADDRESS W R I T E 1st WORD ADDRESS 1 0 A2 A1 A0 0 0 R E A D SLAVE ADDRESS S T O P DATA(n) *Don't Care bit WA WAWA 1 0 S T A R T 2nd WORD ADDRESS(n) 10 1 0 0 * * * 12 11 R A / C WK A C K A C K A2 A1A0 0 0 D7 D0 R A / C W K A C K Figure 37. Random Read Cycle S T A R T SDA LINE R E A D SLAVE ADDRESS 1 0 1 0 A2A1A0 0 S T O P DATA(n) D7 D0 A C K R A / C WK Figure 38. Current Read Cycle S T A R T SDA LINE SLAVE ADDRESS R E A D 1 0 1 0 A2 A1A0 0 DATA(n) D7 S T O P DATA(n+x) D0 D7 D0 0 R A / C W K A C K A C K A C K Figure 39. Sequential Read Cycle (in the case of current read cycle) (1) In random read cycle, data of designated word address can be read. (2) When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th, i.e., data of the (n+1)-th address is output. (3) When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (-COM) side, the next address data can be read in succession. (4) Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal goes from `L' to `H' while SCL signal is 'H'. (5) When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output. Therefore, read command cycle cannot be ended. To end read command cycle, be sure to input 'H' to ACK signal after D0, and the stop condition where SDA goes from `L' to `H' while SCL signal is 'H'. (6) Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is asserted from `L' to `H' while SCL signal is 'H'. www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 15/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Software Reset Software reset is executed to avoid malfunction after power on and during command input. Software reset has several kinds and 3 kinds of them are shown in the figure below. (Refer to Figure 40-(a), Figure 40-(b), and Figure 40-(c).) Within the dummy clock input area, the SDA bus is released ('H' by pull up) and ACK output and read data '0' (both 'L' level) may be output from EEPROM. Therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. Dummy clockx14 SCL 1 Startx2 13 2 Normal command 14 SDA Normal command Figure 40-(a). The Case of Dummy clockx14 + START+START+ Command Input SCL Start Dummy clockx9 Start 1 2 8 Normal command 9 SDA Normal command Figure 40-(b). The Case of START + Dummy Clockx9 + START + Command Input Startx9 SCL 1 2 3 8 7 Normal command 9 SDA Normal command SD A Figure 40-(c). STARTx9 + Command Input Start command from START input. Acknowledge Polling During internal write execution, all input commands are ignored, therefore ACK is not returned. During internal automatic write execution after write cycle input, next command (slave address) is sent. If the first ACK signal sends back 'L', then it means end of write operation, else 'H' is returned, which means writing is still in progress. By the use of acknowledge polling, next command can be executed without waiting for tWR = 5ms. To write continuously, R / W = 0, then to carry out current read cycle after write, slave address with R / W = 1 is sent. If ACK signal sends back 'L', and then execute word address input and data output and so forth.. During internal write, ACK = HIGH is returned. First write command S T A R T Write Command S T O P S T Slave A R Address T S T Slave A R Address T A C K H A C K H ... tWR Second write command ... S T Slave A R Address T A C K H S T Slave A R Address T A C K L Word Address A C K L Data A C K L S T O P tWR After completion of internal write, ACK=LOW is returned, so input next word address and data in succession. Figure 41. Case of Continuous Write by Acknowledge Polling www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 16/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W WP Valid Timing (Write Cancel) WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so on, observe the following WP valid timing. During write cycle execution, inside cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to take in D0 of data(in page write cycle, the first byte data) is the cancel invalid area. WP input in this area becomes `Don't care'. The area from the rise of SCL to take in D0 to the stop condition input is the cancel valid area. Furthermore, after the execution of forced end by WP, the IC enters standby status. Rise of SDA Rise of D0 taken clock SCL SDA SCL D1 D0 ACK SDA Enlarged view SDA S T Slave A R Address T A C Word K Address L ACK D0 Enlarged view A C D7 D6 D5 D4 D3 D2 D1 D0 K L WP cancel invalid area A C K L Data A C K L S T O P WP cancel valid area tWR WP cancel invalid area WP Data is not written. Figure 42. WP Valid Timing Command Cancel by Start Condition and Stop Condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Figure 43.) However, within ACK output area and during data read, SDA bus may output 'L'. In this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. When command is cancelled by start-stop condition during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined. Therefore, it is not possible to carry out current read cycle in succession. To carry out read cycle in succession, carry out random read cycle. SCL SDA 1 0 1 0 Start condition Stop condition Figure 43. Case of cancel by start, stop condition during slave address input www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 17/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W I/O Peripheral Circuit 1. Pull-up Resistance of SDA Terminal SDA is NMOS open drain, so it requires a pull up resistor. As for this resistance value (RPU), select an appropriate value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, operating frequency is limited. The smaller the RPU, the larger is the supply current (Read). 2. Maximum Value of RPU The maximum value of RPU is determined by the following factors. (1) SDA rise time to be determined by the capacitance (CBUS) of bus line and RPU of SDA should be tR or lower. Furthermore, AC timing should be satisfied even when SDA rise time is slow. (2) The bus. electric potential A to be determined by the input current leak total (IL) of device connected to bus at output of 'H' to the SDA line and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin of 0.2Vcc. VCC-ILRPU-0.2 VCC VIH RPU 0.8VccVIH IL Microcontroller BR24TXX RPU Ex.) Vcc =3V IL=10A VIH=0.7 Vcc From (2) 0.8x30.7x3 RPU 10x10-6 SDA terminal A IL 30 [k] IL Bus line capacity CBUS Figure 44. I/O Circuit Diagram 3. Minimum Value of RPU The minimum value of RPU is determined by the following factors. (1) When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA. VccVOL IOL RPU VccVOL RPU IOL (2) VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc. VOLMAX VIL-0.1 VCC Ex.) VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc from (1) 30.4 RPU 3x103 And 867 [] VOL=0.4 [V] VIL=0.3x3 =0.9 [V] Therefore, the condition (2) is satisfied. 4. Pull-up Resistance of SCL Terminal When SCL control is made at the CMOS output port, there is no need for a pull up resistor. But when there is a time where SCL becomes 'Hi-Z', add a pull up resistor. As for the pull up resistor value, one of several k to several ten k is recommended in consideration of drive performance of output port of microcontroller. www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 18/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Cautions on Microcontroller Connection 1. RS In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when using CMOS input / output of tri state to SDA port, insert a series resistance RS between the pull up resistor RPU and the SDA terminal of EEPROM. This is to control over current that may occur when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. RS also plays the role of protecting the SDA terminal against surge. Therefore, even when SDA port is open drain input/output, RS can be used. ACK SCL RPU RS SDA 'H' output of microcontroller 'L' output of EEPROM Microcontroller EEPROM Over current flows to SDA line by 'H' output of microcontroller and 'L' output of EEPROM. Figure 45. I/O Circuit Diagram Figure 46. Input / Output Collision Timing 2. Maximum Value of RS The maximum value of RS is determined by the following relations. (1) SDA rise time to be determined by the capacitance (CBUS) of bus line and RPU of SDA should be tR or lower. Furthermore, AC timing should be satisfied even when SDA rise time is slow. (2) The bus' electric potential A to be determined by RPU and RS the moment when EEPROM outputs 'L' to SDA bus should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin of 0.1Vcc. (VccVOL)xRS +VOL+0.1VccVIL RPU+RS VCC RPU A RS RS VOL Ex)VCC=3V VIL=0.3VCC IOL Bus line capacity CBUS VIL VILVOL0.1Vcc xRPU 1.1VccVIL RS VOL=0.4V RPU=20k 0.3x30.40.1x3 x20x103 1.1x30.3x3 EEPROM Micro controller 1.67 [k] Figure 47. I/O Circuit Diagram 3. Minimum Value of RS The minimum value of RS is determined by over current at bus collision. When over current flows, noises in power source line and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of the impedance of power source line in set and so forth. Set the over current to EEPROM at 10mA or lower. Vcc RS I RPU 'L'output RS RS Vcc I EX) VCC=3V I=10mA Over current I RS 'H' output 3 10x103 300 [] Microcontroller EEPROM Figure 48. I/O Circuit Diagram www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 19/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W I/O Equivalence Circuit 1. Input (A0, A1, A2, SCL, WP) Figure 49. Input Pin Circuit Diagram 2. Input / Output (SDA) Figure 50. Input / Output Pin Circuit Diagram www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 20/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Power-Up / Down Conditions At power ON, the IC's internal circuits may go through unstable low voltage area as the Vcc rises, making the IC's internal logic circuit not completely reset, hence, malfunction may occur. To prevent this, the IC is equipped with POR circuit and LVCC circuit. To assure the operation, observe the following conditions at power ON. 1. Set SDA = 'H' and SCL ='L' or 'H' 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit. tR Recommended Conditions of tR, tOFF,Vbot VCC tR tOFF Vbot 0 tOFF Vbot 10ms or below 10ms or larger 0.3V or below 100ms or below 10ms or larger 0.2V or below Figure 51. Rise Waveform Diagram 3. Set SDA and SCL so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. (1) In the case when the above condition 1 cannot be observed such that SDA becomes 'L' at power ON. Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'. VCC tLOW SCL SDA After Vcc becomes stable After Vcc becomes stable tDH tSU:DAT Figure 52. When SCL= 'H' and SDA= 'L' tSU:DAT Figure 53. When SCL='L' and SDA='L' (2) In the case when the above condition 2 cannot be observed. After power source becomes stable, execute software reset (Page 18). (3) In the case when the above conditions 1 and 2 cannot be observed. Carry out (1), and then carry out (2). Low Voltage Malfunction Prevention Function LVCC circuit prevents data rewrite operation at low power, and prevents write error. At LVCC voltage (Typ =1.2V) or below, data rewrite is prevented. Noise Countermeasures 1. Bypass Capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, it is recommended to connect a bypass capacitor (0.1F) between IC Vcc and GND pins. Connect the capacitor as close to IC as possible. In addition, it is also recommended to connect a bypass capacitor between board's Vcc and GND. www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 21/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Operational Notes 1. Described numeric values and data are design representative values only, and the values are not guaranteed. 2. We believe that the application circuit examples in this document are recommendable. However, in actual use, confirm characteristics further sufficiently. If changing the fixed number of external parts is desired, make your decision with sufficient margin in consideration of static characteristics, transient characteristics, and fluctuations of external parts and our LSI. 3. Absolute maximum ratings If the absolute maximum ratings such as supply voltage, operating temperature range, and so on are exceeded, LSI may be destroyed. Do not supply voltage or subject the IC to temperatures exceeding the absolute maximum ratings. In the case of fear of exceeding the absolute maximum ratings, take physical safety countermeasures such as adding fuses, and see to it that conditions exceeding the absolute maximum ratings should not be supplied to the LSI. 4. GND electric potential Set the voltage of GND terminal lowest at any operating condition. Make sure that each terminal voltage is not lower than that of GND terminal. 5. Thermal design Use a thermal design that allows for a sufficient margin by taking into account the permissible power dissipation (Pd) in actual operating conditions. 6. Short between pins and mounting errors Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong orientation or if pins are shorted together. Short circuit may be caused by conductive particles caught between the pins. 7. Operating the IC in the presence of strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 22/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Part Numbering B R 2 4 T 6 4 x x x - W x x x BUS Type 24I2C Operating Temperature/ Power Source Voltage -40C to+85C/ 1.6V to 5.5V Capacity 64=64K Package Blank :DIP-T8 (1), DIP8K F :SOP8 FJ :SOP-J8 FV : SSOP-B8 FVT : TSSOP-B8 FVJ : TSSOP-B8J FVM : MSOP8 NUX : VSON008X2030 Double Cell Blank Z :DIP-T8 (1), SOP8, SOP-J8, SSOP-B8, TSSOP-B8, TSSOP-B8J, MSOP8, VSON008X2030 :DIP8K Packaging and Forming Specification E2 TR None : Embossed tape and reel (SOP8,SOP-J8, SSOP-B8,TSSOP-B8, TSSOP-B8J) : Embossed tape and reel (MSOP8, VSON008X2030) : Tube (DIP-T8 (1), DIP8K) (1) Not Recommended for New Designs. Recommend BR24T64-WZ. www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 23/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Physical Dimension and Packing Information Package Name DIP-T8 <Container Information> www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 24/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Physical Dimension and Packing Information - continued Package Name www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 DIP8K 25/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Physical Dimension and Packing Information - continued Package Name SOP8 (Max 5.35 (include.BURR)) (UNIT: mm) PKG: SOP8 Drawing No.: EX112-5001-1 www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 26/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Physical Dimension and Packing Information - continued Package Name www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 SOP-J8 27/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Physical Dimension and Packing Information - continued Package Name www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 SSOP-B8 28/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Physical Dimension and Packing Information - continued Package Name www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 TSSOP-B8 29/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Physical Dimension and Packing Information - continued Package Name www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 TSSOP-B8J 30/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Physical Dimension and Packing Information - continued Package Name www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 MSOP8 31/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Physical Dimension and Packing Information - continued Package Name www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 VSON008X2030 32/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Marking Diagrams (TOP VIEW) SOP8 (TOP VIEW) DIP-T8 (TOP VIEW) Part Number Marking Part Number Marking BR24T64 T64 LOT Number LOT Number 1PIN MARK DIP8K (TOP VIEW) SSOP-B8 (TOP VIEW) Part Number Marking BR24T64 Part Number Marking T64 LOT Number LOT Number 1PIN MARK SOP-J8 (TOP VIEW) TSSOP-B8J (TOP VIEW) Part Number Marking Part Number Marking T64 T64 LOT Number LOT Number 1PIN MARK 1PIN MARK VSON008X2030 (TOP VIEW) TSSOP-B8 (TOP VIEW) Part Number Marking T64 Part Number Marking T64 LOT Number LOT Number 1PIN MARK 1PIN MARK MSOP8 (TOP VIEW) Part Number Marking T64 LOT Number 1PIN MARK www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 33/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Datasheet BR24T64-W Revision History Date Revision 18.May.2012 001 25.Feb.2013 002 31.May.2013 003 04.Feb.2015 004 03.Sep.2018 005 www.rohm.com (c)2013 ROHM Co., Ltd. All rights reserved. TSZ2211115001 Changes New Release Update some English words, sentences' descriptions, grammar and formatting. Add tF2 in Serial Input / Output Timing P1 Change format of package line-up table. P.2 Add VESD in Absolute Maximum Ratings P.4 Add directions in Pin Descriptions P.32 Modified Marking Diagram of SSOP-B8 and VSON008X2030 (Deleted 2nd row of LOT Number). Add DIP8K Change DIP-T8 to Not Recommended for New Designs Change Physical Dimension Tape and Reel Information 34/34 TSZ02201-0R2R0G100120-1-2 03.Sep.2018 Rev.005 Notice Precaution on using ROHM Products 1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment, OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you (Note 1) intend to use our Products in devices requiring extremely high reliability (such as medical equipment , transport equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property ("Specific Applications"), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM's Products for Specific Applications. (Note1) Medical Equipment Classification of the Specific Applications JAPAN USA EU CHINA CLASS CLASSb CLASS CLASS CLASS CLASS 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM's Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] Sealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8. Confirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / Circuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification Notice-PGA-E (c) 2015 ROHM Co., Ltd. All rights reserved. Rev.003 Precautions Regarding Application Examples and External Circuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for Storage / Transportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label A two-dimensional barcode printed on ROHM Products label is for ROHM's internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign Trade act Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. Precaution Regarding Intellectual Property Rights 1. All information and data including but not limited to application example contained in this document is for reference only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the Products with other articles such as components, circuits, systems or external equipment (including software). 3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the Products, subject to the terms and conditions herein. Other Precaution 1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. The proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice-PGA-E (c) 2015 ROHM Co., Ltd. All rights reserved. Rev.003 Datasheet General Precaution 1. Before you use our Products, you are requested to carefully read this document and fully understand its contents. ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any ROHM's Products against warning, caution or note contained in this document. 2. All information contained in this document is current as of the issuing date and subject to change without any prior notice. Before purchasing or using ROHM's Products, please confirm the latest information with a ROHM sales representative. 3. The information contained in this document is provided on an "as is" basis and ROHM does not warrant that all information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or concerning such information. Notice - WE (c) 2015 ROHM Co., Ltd. All rights reserved. Rev.001