+
-
VOUT
VDD
VGG
ZCD
FB
CL DRV
GND
MOT
UCC28610
VIN
AC
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
GREEN-MODE FLYBACK CONTROLLER
Check for Samples: UCC28610
1FEATURES APPLICATIONS
•Cascoded Configuration Allows Fully •Universal Input AC/DC Adapters, 12 W to 65 W
Integrated Current Control Without External •High Efficiency Housekeeping and Auxillary
Sense Resistor Power Supplies
•Fast Start Up With Low Standby Power •Offline Battery Chargers
Achieved by Cascode Configuration •Consumer Electronics (DVD Players, Set-Top
•Frequency and Peak Current Modulation for Boxes, DTV, Gaming, Printers, etc.)
Optimum Efficiency Over Entire Operating
Range DESCRIPTION
•Green-Mode (GM) Burst Switching Packets The UCC28610 brings a new level of performance
Improve No-Load Efficiency and reliability to the AC/DC consumer power supply
•Advanced Overcurrent Protection Limits RMS solution.
Input and Output Currents A PWM modulation algorithm varies both the
•Thermal Shutdown switching frequency and primary current while
•Timed Overload With Retry or Latch-Off maintaining discontinuous or transition mode
Response operation over the entire operating range. Combined
•Programmable Opto-Less Output Over-Voltage with a cascoded architecture, these innovations result
Protection in efficiency, reliability, and system cost
improvements over a conventional flyback
•Fast Latched Fault Recovery architecture.
•8-Pin SOIC Package and 8-Pin PDIP Lead-Free
Packages The UCC28610 offers a predictable maximum power
threshold and a timed response to an overload,
allowing safe handling of surge power requirements.
Overload fault response is user-programmed for retry
or latch-off mode. Additional protection features
include output overvoltage detection, programmable
maximum on-time, and thermal shutdown.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©2009–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
OPERATING PACKAGE ORDERABLE PART
TEMPERATURE PINS PACKAGE TRANSPORT MEDIA UNITS
LEAD NUMBER
RANGE, TA8 Plastic Small Outline SOIC D Tape and Reel 2500 UCC28610DR
–40°C to 125°C8 Plastic Dual In-Line PDIP P Tube 50 UCC28610P
ABSOLUTE MAXIMUM RATINGS(1)
All voltages are with respect to GND, –40°C<TJ= TA<125°C, all currents are positive into and negative out of the specified
terminal (unless otherwise noted) UCC28610 UNIT
VDD –0.5 to +25
DRV, during conduction –0.5 to +2.0
DRV, during non-conduction 20
Input voltage range VGG(2) –0.5 to +16 V
ZCD, MOT, CL (3) –0.5 to +7
FB(3) –0.5 to +1.0
VDD –VGG –7 to +10
Continuous input current IVGG (2) 10 mA
Input current range IZCD, IMOT, ICL, IFB (3) –3 to +1
DRV -5
Peak output current A
DRV, pulsed 200ns, 2% duty cycle –5 to +1.5
TJOperating junction temperature range –40 to +150
Tstg Storage temperature range –65 to +150 °C
Lead Temperature (soldering, 10 sec.) +260
(1) These are stress ratings only. Stress beyond these limits may cause permanent damage to the device. Functional operation of the
device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to
absolute maximum rated conditions for extended periods of time may affect device reliability
(2) Voltage on VGG is internally clamped. The clamp level varies with operating conditions. In normal use, VGG is current fed with the
voltage internally limited
(3) In normal use, MOT, CL, ZCD, and FB are connected to resistors to GND and internally limited in voltage swing
PACKAGE DISSIPATION RATINGS(1) (2)
θJA, THERMAL θJB, THERMAL TA= 25°C TA= 85°C TB= 85°C
IMPEDANCE JUNCTION IMPEDANCE JUNCTION
PACKAGE POWER RATING POWER RATING POWER RATING
TO AMBIENT, NO TO BOARD, NO AIRFLOW (mW)(3) (mW)(3) (mW)(2) (3)
AIRFLOW (°C/W)(1) (°C/W)(2)
SOIC-8 (D) 165 55 606 242 730
PDIP-8 (P) 110 37 909 364 1080
(1) Tested per JEDEC EIA/JESD51-1. Thermal resistance is a function of board construction and layout. Air flow reducex thermal
resistance. This number is included only as a general guideline; see TI document (SPRA953) IC Package Thermal Metrics.
(2) Thermal resistance to the circuit board is lower. Measured with standard single-sided PCB construction. Board temperature, TB,
measured approximately 1 cm from the lead to board interface. This number is provided only as a general guideline.
(3) Maximum junction temperature, TJ, equal to 125°C
2Copyright ©2009–2011, Texas Instruments Incorporated
CBULK
CVGG
RZCD2
RZCD1
RCL
RSTART
RMOT
RFB
CVDD DBIAS
+
-
VOUT
VDD
VGG
ZCD
FB
CL DRV
GND
MOT
UCC28610
VIN
AC
D1
CBP
NP
NB
NS
Q1
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
RECOMMENDED OPERATING CONDITIONS
Unless otherwise noted, all voltages are with respect to GND, -40°C<TJ= TA<125°C. Components reference, Figure 1.
MIN MAX UNIT
VDD Input voltage 9 20 V
VGG Input voltage from low- impedance source 9 13
IVGG Input current from a high impedance source 10 2000 μA
RMOT Resistor to GND Shutdown/Retry mode 25 100
Latch-off mode 150 750 kΩ
RCL Resistor to GND 24.3 100
RZCD1 Resistor to auxiliary winding 50 200
CVGG VGG capacitor 33 200 nF
CBP VDD bypass capacitor, ceramic 0.1 1 μF
Figure 1. Recommended Operating Conditions Application
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
over operating free-air temperature range (unless otherwise noted) MAX UNIT
ESD Rating, Human Body Model (HBM) 2 kV
ESD Rating, Charged Device Model (CDM) 500 V
Copyright ©2009–2011, Texas Instruments Incorporated 3
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: VDD = 12 V, VGG=12 V, ZCD = 1 V, FB = 0 V, GND = 0 V, a 0.1-μF capacitor between VDD and
GND, a 0.1-μF capacitor between VGG and GND, RCL = 33.2 kΩ, RMOT = 380 kΩ,–40°C<TA<+125°C, TJ= TA
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
VDD and VGG SUPPLY
VGG(OPERATING) VGG voltage, operating VDD = 14 V, IVGG = 2.0 mA 13 14 15
VGG(DISABLED) VGG voltage, PWM disabled VDD = 12 V, IVGG = 15 μA, IFB = 350 μA 15 16 17 V
Rise in VGG clamping voltage
ΔVGG VGG(DISABLED) –VGG(OPERATING) 1.75 2.00 2.15
during UVLO, GM, or Fault VGG = VGG(DISABLED) -–100 mV, VDD =
IVGG(SREG) VGG shunt regulator current 6 10 μA
12 V
ΔVGG(SREG) VGG shunt load regulation 10 μA≤IVGG ≤5 mA, IFB = 350 μA 125 200 mV
VGG(LREG) VGG LDO regulation voltage VDD = 20 V, IVGG =–2 mA 13
VGG(LREG, DO) VGG LDO Dropout Voltage VDD –VGG, VDD = 11 V, IVGG =–2 mA 1.5 2 2.5
VDD(ON) UVLO turn-on threshold 9.7 10.2 10.7 V
VDD(OFF) UVLO turn-off threshold 7.55 8 8.5
ΔVDD(UVLO) UVLO hysteresis 1.9 2.2 2.5
IVDD(OPERATING) Operating current VDD = 20 V 2.5 3 3.7 mA
IVDD(GM) Idle current between bursts IFB = 350 μA 550 900 μA
IVDD(UVLO) Current for VDD <UVLO VDD = VDD(ON) –100 mV, increasing 225 310
VDD Switch on resistance, DRV to
RDS,ON(VDD) VGG = 12 V, VDD = 7V, IDRV = 50 mA 4 10 Ω
VDD
VDD(FAULT RESET) VDD for fault latch reset 5.6 6 6.4 V
MODULATION
Minimum switching period,
tS(HF) (1) IFB = 0 μA, (1) 7.125 7.5 7.875
frequency modulation (FM) mode
μs
Maximum switching period,
tS(LF) (1) reached at end of FM modulation IFB = IFB, CNR3 –20 μA, (1) 31 34 38
range IFB = 0 μA, RCL = 33. 2 kΩ2.85 3 3.15
Maximum peak driver current over
IDRVpk(max) amplitude modulation(AM) range IFB = 0 μA, RCL = 100 kΩ0.80 0.90 1.0 A
Minimum peak driver current IFB, CNR2 + 10 μA, RCL = 33.2 kΩ0.7 0.85 1.1
IDRVpk(min) reached at end of AM modulation IFB, CNR2 + 10 μA, RCL = 100 kΩ0.2 0.33 0.5
range
KPMaximum power constant For IDRVpk(max) = 3 A 0.54 0.60 0.66 W/μH
Minimum peak driver independent
IDRVpk(absmin) RCL = OPEN 0.3 0.45 0.6 A
of RCL or AM control
Leading edge current limit blanking IFB = 0 μA, RCL = 100 kΩ, 1.2-A pull-up on
tBLANK(Ilim) 120 220 450 ns
time DRV
IFB = 0 μA 2.94 3 3.06
VCL Voltage of CL pin V
IFB = (IFB,CNR3 –20 μA)(1) 0.95 1 1.05
IFB increasing, tS= tS(LF),
IFB,CNR1 (2) IFB range for FM modulation 145 165 195
IDRVpk = IDRVpk(max)
IFB,CNR2 –IFB,CNR1 tS= tS(LF), IDRVpk ranges from
IFB range for AM modulation 35 45 65
(2) IDRVpk(max) to IDRVpk(min)
μA
IFB,CNR3 –IFB,CNR2 IFB range for Green Mode (GM) IFB increasing until PWM action is disabled 50 70 90
(2) modulation entering a burst-off state
IFB hysteresis during GM
IFB, GM-HYST (2) modulation to enter burst on and IFB decreasing from above IFB,CNR3 10 25 40
off states
VFB Voltage of FB pin IFB = 10 μA 0.34 0.7 0.84 V
(1) tSsets a minimum switching period. Following the starting edge of a PWM on time, under normal conditions, the next on time is initiated
following the first zero crossing at ZCD after tS. The value of tSis modulated by IFB between a minimum of tS(HF) and a maximum of
tS(LF) In normal operation, tS(HF) sets the maximum operating frequency of the power supply and tS(LF) sets the minimum operating
frequency of the power supply.
(2) Refer to Figure 2.
4Copyright ©2009–2011, Texas Instruments Incorporated
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated: VDD = 12 V, VGG=12 V, ZCD = 1 V, FB = 0 V, GND = 0 V, a 0.1-μF capacitor between VDD and
GND, a 0.1-μF capacitor between VGG and GND, RCL = 33.2 kΩ, RMOT = 380 kΩ,–40°C<TA<+125°C, TJ= TA
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
ZERO CROSSING DETECTION
ZCD high to low generates switching period
ZCD(TH) ZCD zero crossing threshold 5 20 50 mV
(tShas expired)
ZCD(CLAMP) ZCD low clamp voltage IZCD =–10 μA -200 -160 -100 mV
ZCD voltage threshold to enable Driver switching periods generated at start
ZCD(START) 0.1 0.15 0.2 V
the internal start timer timer rate
Delay from zero crossing to Driver
tDLY(ZCD) 150-Ωpull-up to 12-V on DRV 150 ns
turn-on
Wait time for zero crossing Driver turn-on edge generated following tS
tWAIT(ZCD) 2 2.4 2.8
detection with previous zero crossing detected μs
tST Starter time-out period ZCD = 0 V 150 240 300
DRIVER
RDS(on)(DRV) Driver on-resistance IDRV = 4.0 A 90 190 mΩ
IDRV(OFF) Driver off-leakage current DRV = 12 V 1.5 20 μA
RDS(on)(HSDRV) High-side driver on-resistance IDRV =–50 mA 6 11 Ω
IDRV(DSCH) DRV bulk discharge current VDD open, DRV= 12 V, Fault latch set 2 2.8 3.6 mA
OVERVOLTAGE FAULT
ZCD(OVP) Overvoltage fault threshold at ZCD Fault latch set 4.85 5 5.15 V
ZCD blanking and OVP sample
tBLANK(OVP) 0.6 1 1.7 μs
time from the turn-off edge of DRV
IZCD(bias) ZCD Input bias current ZCD = 5 V -0.1 -0.05 0.1 μA
OVERLOAD FAULT
Current to trigger overload delay
IFB(OL) 0 1.5 3 μA
timer
tOL Delay to overload fault IFB = 0 A continuously 200 250 325 ms
Retry delay in retry mode or after
tRETRY RMOT = 76 kΩ750
shutdown command
Boundary RMOT between latch-off
RMOT(TH) See (3) 100 120 150 kΩ
and retry modes
SHUTDOWN THRESHOLD
MOT(SR) Shutdown-Retry threshold MOT high to low 0.7 1 1.3 V
MOT current when MOT is pulled
IMOT MOT = 1 V –600 –450 –300 μA
low
MAXIMUM ON TIME
Latch-OFF RMOT = 383 kΩ3.43 3.83 4.23
tMOT μs
Shutdown-retry RMOT = 76 kΩ3.4 3.8 4.2
MOT MOT voltage 2.7 3 3.3 V
THERMAL SHUTDOWN
TSD (4) Shutdown temperature TJ, temperature rising(4) 165
°C
TJ, temperature falling, degrees belowTSD
TSD_HYS (4) Hysteresis 15
(4)
(3) A latch-off or a shutdown and retry fault response to a sustained overload is selected by the range of RMOT.
To select the latch-off mode, RMOT should be greater than 150 kΩand tMOT is given by RMOT ×(1.0 ×10-11).
To select the shutdown-retry mode, RMOT should be less than 100 kΩand tMOT is given by RMOT ×(5.0 ×10-11).
(4) Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance at or near thermal shutdown
temperature is not specified or assured.
Copyright ©2009–2011, Texas Instruments Incorporated 5
0100 200
150 25050
IFB -Feedback Current - μA
300
133
30
33
IFB,CNR1
(165uA)
IFB,CNR2
(210uA)
IFB,CNR3
(275uA)
IGM,HYST
(20uA)
IFB,CNR2
- IFB,CNR1
(45uA)
IFB,CNR3
- IFB,CNR2
(65uA)
FM AM GM
100
ID R V ,P K - P ercent of M axim um P eak D R V C urrent - %fS- S w itch ing F req u en cy - k H z
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
Figure 2. FB Electrical Condition Detail
6Copyright ©2009–2011, Texas Instruments Incorporated
FB 1
2
3
4
ZCD
CL
MOT
VDD
GND
DRV
VGG
8
7
6
5
FB 1
2
3
4
ZCD
CL
MOT
VDD
GND
DRV
VGG
8
7
6
5
D PACKAGE
(Top View)
P PACKAGE
(Top View)
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
DEVICE INFORMATION
PIN CONFIGURATION
PIN DESCRIPTIONS
NAME PIN I/O DESCRIPTION
(Current Limit) This pin programs the peak primary inductor current that is reached each switching cycle. Program
CL 3 I with a resistor between CL and GND.
(DRiVe) This pin drives the source of an external high voltage power MOSFET. The DRV pin carries the full
DRV 6 O primary current of the converter. Connect a Schottky diode between DRV and VDD to provide initial bias at start up.
(FeedBack) The FB current, IFB, commands the operating mode of the UCC28610. The FB voltage is always 0.7 V.
FB 1 I This pin only detects current.
(GrouND) This pin is the current return terminal for both the analog and power signals in the UCC28610. This
GND 7 —terminal carries the full primary current of the converter. Separate the return path of the bulk capacitor from the
return path of FB, ZCD, MOT, and CL.
(Maximum On Time) This pin has three functions:
1. MOT programs the allowed maximum on-time, tMOT, of the internal driver.
2. MOT programs the converter’s reaction to overload and power input under-voltage conditions with either a
MOT 4 I shutdown/retry response or a latch-off response.
3. MOT can be used to externally shut down the power supply by pulling MOT to GND. When the pin is released,
the converter will start after a restart delay, tRETRY.
Functions 1 and 2 are programmed with a resistor between MOT and GND.
This is the bias supply pin for the UCC28610. It can be derived from an external source or an auxiliary winding.
VDD 8 —This pin must be decoupled with a 0.1-μF ceramic capacitor placed between VDD and GND, as close to the device
as possible.
This pin provides a DC voltage for the gate of the external high voltage MOSFET. This pin must be decoupled with
VGG 5 —a 0.1-μF ceramic capacitor placed between VGG and GND, as close to the device as possible. This pin also
initiates start-up bias through a large value resistor that is connected to the input bulk voltage.
(Zero Current Detection) This pin has two functions:
1. ZCD senses the transformer reset based on a valid zero current detection signal.
ZCD 2 I 2. ZCD programs the output Over Voltage Protection (OVP) feature using a resistive divider on the primary side
bias winding of the Flyback transformer.
Copyright ©2009–2011, Texas Instruments Incorporated 7
8
2.8
2.6
10 12 16 18 20
3.2
3.4
4.0
3.6
IVDD – Bias Supply Current – mA
VDD – Bias Supply Voltage – V
14
IFB = 10 mA
VZCD = 1V
VVGG = OPEN
VVDD decreasing from 20 V
3.0
3.8
600
550
20
700
900
8 10 12 16 18
VDD – Bias Supply Voltage – V
14
650
750
850
800
IVDD – Bias Supply Current – mA
IFB = 280.4 mA
VVGG = OPEN
VVDD decreasing from 20 V
-40 -25 -10 125
TJ– Junction Temperature – °C
600
550
700
900
650
750
850
800
IVDD – Bias Supply Current – mA
5 20 35 50 65 80 95 110
0 20
VDD – Bias Voltage – V
0.5
0.0
1.5
3.5
1.0
2.0
3.0
2.5
IVDD – Bias Supply Current – mA
5 10 15
VDD rising
0 V to 20V
IFB= 10 mA,
VDD falling
20V to 0 V
IFB= 0 mA,
VDD falling
20V to 0 V
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS
Unless otherwise stated: VDD = 12V, VGG = 12V, ZCD = 1 V, FB = 0 V, GND = 0 V, a 0.1-μF capacitor between VDD and
GND, a 0.1-μF capacitor between VGG and GND, RCL = 33.2 kΩ, RMOT = 380 kΩ,–40°C<TA<+125°C, TJ= TA
BIAS SUPPLY CURRENT BIAS SUPPLY CURRENT
vs vs
BIAS SUPPLY VOLTAGE DURING OPERATION BIAS SUPPLY VOLTAGE DURING GREEN MODE
Figure 3. Figure 4.
BIAS SUPPLY CURRENT OPERATIONAL IVDD –BIAS CURRENT
vs vs
TEMPERATURE DURING GREEN MODE BIAS VOLTAGE
Figure 5. Figure 6.
8Copyright ©2009–2011, Texas Instruments Incorporated
8
20
0
50 100 200 250 300
60
100
160
120
fS– Switching Frequency – kHz
IFB – Feedback Control Current – mA
150
40
140
80
7.0
7.6
8.0
7.8
7.2
7.4
tS,HF – Minimum Switching Period – ms
-40 -25 -10 125
TA– Ambient Temperature – °C
5 20 35 50 65 80 95 110
0
0.5
0.0
50 100 200 250 300
2.0
1.5
3.5
3.0
IDRV(pk) – Peak DRV Current – A
IFB - Feedback Current - mA
Ambient
Temperature
(°C)
25
125
–40
150
1.0
2.5
TA= 125°C
TA= 25°C
TA= –40°C
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
TYPICAL CHARACTERISTICS (continued)
Unless otherwise stated: VDD = 12V, VGG = 12V, ZCD = 1 V, FB = 0 V, GND = 0 V, a 0.1-μF capacitor between VDD and
GND, a 0.1-μF capacitor between VGG and GND, RCL = 33.2 kΩ, RMOT = 380 kΩ,–40°C<TA<+125°C, TJ= TA
OSCILLATOR FREQUENCY MINIMUM SWITCHING PERIOD
vs vs
FEEDBACK CURRENT TEMPERATURE
Figure 7. Figure 8.
SWITCHING PERIOD DURING AMPLITUDE MODULALTION PEAK DRV CURRENT
vs vs
AMBIENT TEMPERATURE FEEDBACK CURRENT
Figure 9. Figure 10.
Copyright ©2009–2011, Texas Instruments Incorporated 9
0
1
0
10 20 30 40 50
3
2
5
4
IDRV(pk) – Peak DRV Current – A
1/RCL –mS
Avoid Operation Here
Best Results
24.3 kW< RCL< 100 kW
2.9
2.8
3.0
3.2
3.1
IDRV(pk) – Peak DRV Current – A
-40 -25 -10 125
TA– Ambient Temperature – °C
5 20 35 50 65 80 95 110
IFB = 0 mA
0
1
0
100 200 400 500 600
3
6
4
tMOT – Maximum On-Time – ms
RMOT – Maximum On-Time Resistor – kW
300
2
5
Latch Off
Shutdown/Retry
MODE
3.3
3.9
4.3
4.2
3.5
3.7
3.6
4.1
3.4
3.8
4.0
tMOT – Maximum On-Time – ms
-40 -25 -10 125
TJ– Junction Temperature – °C
5 20 35 50 65 80 95 110
RMOT = 383 kW
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Unless otherwise stated: VDD = 12V, VGG = 12V, ZCD = 1 V, FB = 0 V, GND = 0 V, a 0.1-μF capacitor between VDD and
GND, a 0.1-μF capacitor between VGG and GND, RCL = 33.2 kΩ, RMOT = 380 kΩ,–40°C<TA<+125°C, TJ= TA
PEAK DRV CURRENT PEAK DRV CURRENT
vs vs
TRANSCONDUCTANCE (1/RCL) AMBIENT TEMPERATURE
Figure 11. Figure 12.
MAXIMUM ON TIME MAXIMUM ON TIME
vs vs
MAXIMUM ON-TIME RESISTANCE JUNCTION TEMPERATURE
Figure 13. Figure 14.
10 Copyright ©2009–2011, Texas Instruments Incorporated
20
180
40
60
160
100
120
RDS(on) – On-Time Resistance – mW
-40 -25 -10 125
TA– Ambient Temperature – °C
5 20 35 50 65 80 95 110
80
140
2
0
4
6
12
8
10
-40 -25 -10 125
TA– Ambient Temperature – °C
5 20 35 50 65 80 95 110
RDS(on) – On-Time Resistance – W
High-Side Drive
VDD Switch
-40 -20 120
TB– Board Temperature – °C
0 20 40 60 80 100
PDISS – Power Dissipation – W
0
1.5
2.5
0.5
1.0
2.0
SOIC (D)
DIP (P)
Package
0
PDISS – Power Dissipation – W
10
0.0
20
60
30
50
40
qJB – Thermal Coefficient – °C/W
0.50 1.000.25 0.75
SOIC (D)
DIP (P)
Package
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
TYPICAL CHARACTERISTICS (continued)
Unless otherwise stated: VDD = 12V, VGG = 12V, ZCD = 1 V, FB = 0 V, GND = 0 V, a 0.1-μF capacitor between VDD and
GND, a 0.1-μF capacitor between VGG and GND, RCL = 33.2 kΩ, RMOT = 380 kΩ,–40°C<TA<+125°C, TJ= TA
DRIVER RDS(on) RDS(on) of HIGH SIDE DRIVE and VDD Switch
vs vs
AMBIENT TEMPERATURE TEMPERATURE
Figure 15. Figure 16.
SAFE OPERATING AREA THERMAL COEFFICIENT – θJB
vs vs
BOARD TEMPERATURE POWER DISSIPATION
Figure 17. Figure 18.
Copyright ©2009–2011, Texas Instruments Incorporated 11
Q
Q
D
DRV
GND
VGATE
+
VDD
10V/8V
Enable
PWM
MOT
3V
Shutdown
and
Restart
1V
ZCD Zero Current
Detect
Fault Timing
& Control
CL
FB
Output
Voltage
Sense
Maximum On Time
& Fault Response
Control
UVLO
Latch
or
Retry
2V
VGG
UCC28610
Block Diagram
5V
OV
Fault
Driver
Bulk
Discharge
VGATE
Enable
PWM
13V
10V/6V
Fault Latch
Reset
Fault Latch
Reset
HS
Drive
VDD
Switch
VGG
LDO
Reg
VGG
Shunt
0mA < IFB < 200mA
IFB > 200mA
IFB = 0 Overload
Green-mode
Modulators
IFB
Feedback
Processing
Thermal
Shutdown
6
5
7
3
4
2
1
8
++
UVLO
IFB
TSW
1/tS
Freq. Modulator
IFB
IFB
IP
Current
Modulator
IFB
IFB
7.5kW
+
IMOT Fault
14V
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
Block Diagram
Figure 19. Symplified Block Diagram
12 Copyright ©2009–2011, Texas Instruments Incorporated
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
APPLICATION INFORMATION
General Operation
The flyback converter is attractive for low power AC/DC applications because it provides output isolation and
wide input operating abilities using a minimum number of components. Operation of the flyback converter in
Discontinuous Conduction Mode (DCM) is especially attractive because it eliminates reverse recovery losses in
the output rectifier and it simplifies control.
The UCC28610 is a flyback controller for 12-W to 65-W, peak AC/DC power supply applications that require both
low AC line power during no-load operation and high average efficiency. This controller limits the converter to
DCM operation. It does not allow Continuous Conduction Mode (CCM) operation. Forced DCM operation results
in a uniquely safe current limit characteristic that is insensitive to AC line variations. The peak current mode
modulator does not need slope compensation because the converter operates in DCM.
The operation of the UCC28610 is facilitated by driving the external high voltage MOSFET through the source.
This configuration is called a cascode driver. It features fast start-up and low input power under no-load
conditions without having high voltage connections to the control device. The cascode driver has no effect on the
general operation of the flyback converter.
The feedback pin uses current rather than voltage. This unique feature minimizes primary side power
consumption during no-load operation by avoiding external resistive conversion from opto-coupler current to
voltage.
Average efficiency is optimized by the UCC28610 between peak power and 22% peak power with constant peak
current, variable off-time modulation. This modulation tends to make the efficiency constant between 22% and
100% peak load, eliminating the need to over-design to meet average efficiency levels that are required by
EnergyStar™.
Copyright ©2009–2011, Texas Instruments Incorporated 13
NPS
S( HF ) ON DM DT
t t t t= + +
DS IN(max) leakage_spike
PS
OUT
V - 2 V V
N = V
-
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
Transformer Selection
To begin a power supply design, the power supply designer needs to know the peak power to be delivered by
the converter, the input voltage range, the output voltage, and an estimate of the maximum allowable bulk
voltage ripple. Select the maximum allowable stress voltage for the external power MOSFET. The stress voltage,
VDS, determines the reflected secondary voltage that resets the flyback transformer and the turn ratio between
primary and secondary. A simplified diagram of the converter and its waveforms are shown in Figure 20.
Figure 20. Basic Flyback Converter and Waveforms at Peak Load and Minimum VBULK Voltage
Peak power is the maximum power level that must be regulated by the converter control system. Loads that last
longer than the control loop time constant (100 μs - 300 μs) are directly considered “peak power”. Loads lasting
less than the control loop time constant can be averaged over the control loop time constant.
The minimum switching period is when the converter is operating in the Frequency Modulation (FM) mode,
referred to as tS(HF). This switching period must equal the sum of the switching intervals at minimum input
voltage, maximum load, as shown in Figure 20 and described in Equation 1. The switching intervals are tON, the
conduction time of the MOSFET; tDM the demagnetization time of the transformer and tDT, the duration of the
deadtime, equal to half of the resonant cycle, after the transformer is de-energized.
(1)
Solve for the primary to secondary turn ratio, NPS, using the maximum allowable VDS, the maximum input line
voltage, the predicted voltage spike due to leakage inductance and the desired regulated output voltage of the
converter, VOUT.
(2)
14 Copyright ©2009–2011, Texas Instruments Incorporated
0 05
DT S( HF )
t . t= ´
BULK (min) ON OUT PS DM
V t V N t´ = ´ ´
DM S( HF ) ON DT
t t t t= - -
OUT PS S( HF ) DT
ON
BULK (min) OUT PS
V N (t t )
tV (V N )
´ ´ -
=+ ´
( )2
BULK(min) ON
OUT
IN
M S(HF)
V t
P
Pefficiency 2 L t
´
= = ´ ´
( )2
2
BULK (min) ON
M
IN S( HF )
V t
LP t
´
=´ ´
P M
CL
IN
K L
R 33.2k P
´
= W´
DRV(PK )
CL
100kV
IR
=
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
Assume a deadtime, tDT, of 5% of the total minimum switching period to allow for variations in the output
capacitance of the HVMOSFET and the leakage inductance value:
(3)
Using volt-seconds balance, set the volt-seconds on equal to the volt-seconds for demagnetizing and solve for
the on-time:
(4)
(5)
(6)
The maximum input power, PIN, to the converter, in addition to being equal to the output power divided by the
overall efficiency, is always equal to:
(7)
Solve for the primary inductance value:
(8)
This equation is an approximation of the primary inductance value that is the best choice to minimize the primary
side RMS current. In the actual circuit, when the resonance and delay due to leakage inductance can be
measured, the magnetizing inductance value may need to be iterated for optimized low voltage switching.
Select the CL resistor, RCL, based upon the maximum power constant of the controller, KP, The tolerance of LM
should be considered (such as 10% lower for a typical inductor) and the minimum value of LMshould be used to
calculate the value of the CL resistor.
To avoid tripping the overload protection feature of the controller during the normal operating range, use the
minimum value of KPfrom the Electrical Characteristics Table:
(9)
Once RCL is selected, the peak DRV current is calculated using Equation 10:
(10)
For high efficiency, the bias winding turn ratio, NPB, should be designed to maintain the VDD voltage above the
VGG clamp, which is equal to VGG(DISABLED), when the converter is in burst mode. If VDD discharges below this
value, minus the threshold voltage of the HVMOSFET, the HVMOSFET will turn on and linearly supply the VDD
current from the high voltage rail instead of from the bias windings. Adding a zener diode on VDD will protect
VDD from exceeding its absolute maximum rating in the event of a spike due to excess leakage inductance.
Copyright ©2009–2011, Texas Instruments Incorporated 15
GateBias
14VDC
Bulk
PWM
Control
Primary
Winding
External
HVMOSFET
Internal
LowVoltage
DRIVER
Cascoded
MOSFET
Pair
GateBias
14VDC
Bulk
PWM
Control
Primary
Winding
External
HVMOSFET
Internal
LowVoltage
DRIVER
OFF
Vth
+
_
(a) (b)
ON
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
Cascode Bias and Start-Up
The UCC28610 uses a cascode drive and bias to control the high voltage power MOSFET and provide initial
bias at start-up. Thus, the external high voltage power MOSFET provides the start-up function in addition to the
power switching function during converter operation. The cascode architecture utilizes a low voltage switch
operating between ground and the source of a high voltage MOSFET (HVMOSFET) configured in a common
gate configuration, as shown in Figure 21. There are some key points to note.
1. The gate of the external HVMOSFET is held at a DC voltage.
2. The HVMOSFET is driven through the source, not the gate.
3. The entire primary winding current passes through the internal low voltage Driver MOSFET (both DRV and
GND pins).
Figure 21. Cascoded Architecture
16 Copyright ©2009–2011, Texas Instruments Incorporated
RSTART
CVGG
14V
Bulk
VGG
DRV
GND
6
5
HS
Drive
HVMOSFET
Primary
Winding
PWM
Control 7
Driver
8
CVDD
2V
UVLO
Fault Enable
PWM
VDD
+
10V/8V
VDD
Switch
Bias
Winding
VGG
Shunt
VDDOperatingandGMCurrent
VDDStart-upCurrent
D1
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
The UCC28610 integrates the low voltage switch in the form of a 90-mΩFET along with all associated current
sensing and drive. The HVMOSFET is forced to track the fast internal low voltage driver. The drain-gate charge
in the HVMOSFET does not affect the turn-off speed because the gate is connected to a low impedance DC
source. The cascode configuration results in very fast turn-off of the HVMOSFET, which keeps MOSFET
switching losses low.
Cascode drive circuits are well known for high speed voltage gain. This topology can have small signal
bandwidth over 100 MHz and it can exhibit high frequency ringing. High frequency ringing can cause EMI
problems and become destructive in some situations. The sub-intervals during and immediately following the
turn-on and turn-off transients are particularly susceptible to oscillation. For avoidance or solutions, see the
application section, Solving High Frequency Ringing.
The cascode configuration permits a unique start-up sequence that is fast yet low-loss. Start-up bias uses a low
level bleed current from either the AC line or the rectified and filtered AC line, or bulk voltage (via RSTART) as
shown in Figure 22. This current charges a small VGG capacitor, CVGG, raising the HVMOSFET gate. The VGG
pin will typically draw approximately 6 μA (IVGG(SREG)) during this time, allowing the bulk bias current to be small
and still charge the VGG capacitor. The HVMOSFET acts as a source follower once VGG reaches the threshold
voltage of the HVMOSFET. Then, the HVMOSFET will bring up the DRV voltage as VGG continues to rise.
During this time the UCC28610 is in UVLO and the Enable PWM signal is low. This turns on the VDD switch
connecting VDD to DRV, allowing VDD to rise with the source of the HVMOSFET and charging CVDD. An
external Schottky diode, D1, is required between DRV and VDD. This diode passes potentially high switching
currents that could otherwise flow through the body diode of the internal VDD Switch.
Figure 22. Start-Up Currents for the Cascode Architecture.
Copyright ©2009–2011, Texas Instruments Incorporated 17
Time (ms)
Volts
5
10
15
20
VGG
VDD
VOUT
0
VBULK
50
100
150
Volts
5 10 15 20 25 30
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
In order to achieve the lowest possible no-load power, select the number of turns in the bias winding so that VDD
is higher than 16 V –VTH of the HVMOSFET. A bias winding voltage between 17 V and 20 V usually achieves
minimum loss. The bias winding often tracks the primary leakage inductance turn-off voltage spike. Place a 20-V
Zener diode between VDD and GND in applications where heavy loads cause excessive VDD voltage.
Figure 23. Typical Start-Up Waveforms for a 17-V Bias Winding Voltage
Typical start-up waveforms are shown in Figure 23. As VGG rises, VDD will follow, minus the threshold voltage
of the HVMOSFET. When VDD reaches approximately 10 V, the UCC28610 initiates switching. The bias supply
current, IVDD, rises to its operating level and it is supplied from the VDD capacitor. Start-up times can be kept
under 200 ms by selecting the VGG capacitor in the range of 33 nF to 1000 nF and selecting RSTART to have a
current of 15 μA at the minimum AC line voltage. Select capacitor CVDD to have enough capacitance to provide
operating bias current to the controller for the time it takes the auxiliary winding to take over. No-load burst
operation may impose a requirement for additional CVDD capacitance.
The voltage on VGG is shunt regulated to 16 V whenever the PWM action is disabled. This is reduced to 14 V
during switching to limit voltage stress on the gate of the external HVMOSFET. The external HVMOSFET should
have a threshold voltage of less than 6 V in order to permit proper starting.
18 Copyright ©2009–2011, Texas Instruments Incorporated
IFB
To Modulators FB
1
RFB
RFB fi lte r
CFBf i lter
VDD
IFB
0uA < IFB < 200uA
IFB > 200uA
IFB = 0A
GM
OverLoad
FeedBack Processing
1
2
FB
FBfilter FBfilter
fR Cp
=´ ´ ´
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
Feedback Function
Modulation and modes are controlled by applying current to the FB pin. The FB pin is usually used to feed back
the output error signal to the modulator. The UCC28610 uses internal current mirrors to apply the FB current to
the Feedback Processing block, and then to the Frequency Modulator and Current Modulator blocks. The voltage
of the FB pin is a constant 0.7 V. AC filtering of the output of the opto-coupler must be applied to the emitter of
the opto-coupler, as shown in Figure 24. The corner frequency of the filter in Figure 24 should be at least a
decade above the maximum switching frequency of the converter, as given in Equation 11. A 100-kΩresistor,
RFB, between the FB pin and GND prevents ground noise from resetting the overload timer by biasing the FB pin
with a negative current. An opto-coupler with a low Current Transfer Ratio (CTR) often gives better no-load
performance than a high CTR device due to the bias current of the secondary reference. The low CTR also
offers better noise immunity than a high CTR device.
Figure 24. FB Details
(11)
Copyright ©2009–2011, Texas Instruments Incorporated 19
Peak
Current
Control
Current Modulator
IF B
TSW
1 /tS
Freq. Modulator
IF B
IFB
VGATE
3
RCL
0100 2 00
150 25050
IFB -Fee dbac k Curren t - µA
300
133
30
33
IFB,CNR1
(165uA )
IFB,CNR2
(210uA)
IFB,CNR3
(275uA)
IGM,HYST
(20uA)
IFB,CNR2 - IFB,CNR1
(45uA)
IFB,CNR3 - IFB,CNR2
(65uA)
FM A M GM
100
IDR V ,PK - P e rc e n t o f M axi m u m P ea k D R V Cu r ren t - %f S- S wi tc hi ng F r e q ue n c y -
k H z
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
Modulation Modes
Under normal operating conditions, the FB current commands the operating mode of the UCC28610, as shown
in Figure 25 and Figure 26. The FB current commands the UCC28610 to operate the converter in one of three
modes: Frequency Modulation (FM) mode, Amplitude Modulation (AM) mode, and Green Mode (GM).
The converter operates in FM mode with a large power load (22% to 100% the peak regulated power). The peak
HVMOSFET current reaches its maximum programmed value and FB current regulates the output voltage by
varying the switching frequency, which is inversely proportional to tS. The switching frequency is modulated from
30 kHz (22% peak power) to 133 kHz (100% peak power), the on time is constant, and the IDRV peak current is
constant. The maximum programmable HVMOSFET current, IDRV,PK(max), is set by a resistor on the CL pin, as
described in Equation 10.
The converter operates in AM mode at moderate power levels (2.5% to 22% of the peak regulated power). The
FB current regulates the output voltage by modulating the amplitude of the peak HVMOSFET current from 33%
to 100% of the maximum programmed value while the switching frequency is fixed at approximately 30 kHz. The
UCC28610 modulates the voltage on the CL pin from 3 V to 1 V to vary the commanded peak current, as shown
in Figure 25 and Figure 26.
The converter operates in GM at light load (0% to 2.5% of the peak regulated power). The FB current regulates
the output voltage in the Green Mode with hysteretic bursts of pulses using FB current thresholds. The peak
HVMOSFET current is 33% of the maximum programmed value. The switching frequency within a burst of pulses
is approximately 30 kHz. The duration between bursts is regulated by the power supply control dynamics and the
FB hysteresis. The UCC28610 reduces internal bias power between bursts in order to conserve energy during
light-load and no-load conditions.
Figure 25. Modulation Control Blocks Figure 26. Control Diagram with Operating Modes
20 Copyright ©2009–2011, Texas Instruments Incorporated
RCL
CL ICL
Peak
Current
Control
IFB
IFB
IDRV
DRV
GND
Driver
IDRV
IFB FB FromEmitter
ofOpto-
Coupler
FromSource
of
HVMOSFET
tBLANK,(Ilim)
PWM
Comparator
100000
ICL
PWMFlip-
FlopCLR
CurrentModulator
1
6
7
3
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
Primary Current Sense
The UCC28610 uses a current mirror technique to sense primary current in the Current Modulator. See Figure 27
for details. All of the primary current passes into the DRV pin, through the Driver MOSFET and out of the GND
pin. The Driver MOSFET current is scaled and reflected to the PWM Comparator where it is compared with the
CL current. At the beginning of each switching cycle a blanking pulse, tBLANK,(Ilim), of approximately 220 ns is
applied to the internal current limiter to allow the driver to turn on without false limiting on the leading edge
capacitive discharge currents normally present in the circuit.
Figure 27. CL pin and DRV Current Sense
Copyright ©2009–2011, Texas Instruments Incorporated 21
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
Zero Crossing Detection
The modulator requires three conditions in order to initiate the next switching cycle:
1. The time since the last turn-on edge must be equal to or greater than the time that is requested by the
Feedback Processor as determined by the feedback current, IFB.
2. The time since the last turn-on edge must be longer than the minimum period that is built into the UCC28610
(nominally 7.5 μs which equals 133 kHz).
3. Immediately following a high-to-low zero crossing of the ZCD voltage. Or, it has been longer than tWAIT,ZCD
(~2.4 μs) since the last zero crossing has been detected.
Every switching cycle is preceded by at least one zero crossing detection by the ZCD pin. The modulator allows
the resonant ring to damp between pulses if the period needs to exceed the damping limit, allowing long pauses
between pulses during no-load operation.
The switching frequency is not allowed to exceed 133 kHz (nominally). This sets the maximum power limit so
that it will be constant for all bulk voltages that exceed the minimum line voltage value.
Figure 28 illustrates a set of switching cycle waveforms over a range of operating conditions. The UCC28610 is
designed to always keep the inductor current discontinuous. This prevents current tailing during start-up or short
circuit conditions and accommodates control of the maximum power delivered.
Figure 28. Switching Cycle Waveforms
22 Copyright ©2009–2011, Texas Instruments Incorporated
RZ CD 1
RZC D2
ZCD
NB
NPNS
Zero
Current
Detect
Output
Voltage
Sense
5V
PWM
Flip-Flop
Fault Timing
and Control
OV
Fault
2
CZ C D
OUT F B
ZCD1
S
V + V N
R = 100 A N
´
m
(ovp) ZCD1
ZCD2
B
OUT(pk) (ovp)
S
ZCD R
R = N
V × -ZCD
N
´
æ ö
ç ÷
è ø
UCC28610
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SLUS888E –JANUARY 2009–REVISED JULY 2011
Zero crossing is detected using a resistive divider across the bias winding, as shown in Figure 29. The bias
winding operates in phase with the output winding. The ZCD function detects transformer demagnetization when
the ZCD voltage has a high to low crossing of the 20-mV ZCD threshold, ZCDTH. The voltage at the ZCD pin is
internally clamped to contain negative excursions at -160mV (ZCDCLAMP). A small delay, 50 ns to 200 ns, can be
added with CZCD to align the turn-on of the primary switch with the resonant valley of the primary winding
waveform.
Figure 29. Zero Crossing Detection.
(12)
(13)
Copyright ©2009–2011, Texas Instruments Incorporated 23
I(DRV)
VOUT
0
VDD VGG
VOUT
100
33
67
%IDRV,PK(MAX)
12.0
12.1
11.9
11.8
12
13
14
15
16
VGG
Time(ms)
250 260 270 280 290
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
Green Mode Operation
During light load operation the UCC28610 cycles between two states: GM-on and GM-off. The details are shown
in Figure 30. During the GM-on state, the controller is active while the modulator issues a burst of one or more
pulses. During the GM-off state the controller reduces its operating current and switching action is inhibited. The
rate and duration of the on and off states are controlled by the current into the FB pin as it cycles between the
two hysteretic thresholds separated by IFB, GM_HYST, the load current, the output filter capacitor, and the details of
the feedback circuit.
During the GM-off state the VDD supply current is reduced to approximately 550 μA, IVDD(GM). The Enable PWM
signal goes low which inhibits switching, sets the VGG shunt regulation to ~16 V, VGG(DISABLED), and turns on the
VDD switch. The VGG node quickly charges to 16V and the low VDD current is supplied from the VDD capacitor.
During the GM-on state the UCC28610 controls the peak primary current to 33% of IDRV,PK(max), at a 30-kHz rate.
When switching, the VGG shunt regulator pulls the VGG voltage down to ~14 V. VDD is charged by the auxiliary
winding during this time as long as VDD does not discharge below 14 V. The converter’s output voltage is
charged until the feedback network forces the FB current to the GM off threshold, IFB,CNR3, and puts the controller
back into the GM off state.
At very light loads the time between PWM bursts can be long. To obtain the lowest no-load power, it is important
that VDD not discharge below 16 V by more than the threshold voltage of the HVMOSFET or the HVMOSFET
will turn-on and linearly supply the VDD current from the high-voltage bulk rail. The VDD voltage can be
extended by increasing the CVDD capacitance without significant impact on start-up time.
Figure 30. Green Mode Operation
24 Copyright ©2009–2011, Texas Instruments Incorporated
2
2
m DRV(pk) S(max)
IN(max)
L I f
P = ´ ´
12
1
DRV ,PK (min)
IN
P W
I A
³
³
0
1
0
10 20 30 40 50
3
2
5
4
IDRV(pk) – Peak DRV Current – A
1/RCL –mS
Avoid Operation Here
Best Results
24.3 kW< RCL< 100 kW
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
Maximum Converter Power Limitation
The suggested peak power range of the UCC28610 is 12 W to 65 W based on a universal AC line converter
(90-VAC to 265-VAC input line voltage), using an external high voltage MOSFET with a voltage rating of 600 V.
This power range may depend on application and external MOSFET stress voltage. Ultimately, the peak primary
current is the limiting factor because this current must pass through the UCC28610. The limit on the peak
primary current imposes a limit on the peak primary power. The peak power must be less than 65 W, not the
average power. The peak power is defined as the highest power level where the controller must maintain
regulation.
At all power levels, program the UCC28610 to control the power limit with the primary inductance, peak current
and maximum switching frequency (133 kHz). The maximum peak input power level is given by Equation 14. The
accuracy of the power limit is twice as sensitive to IDRV(PK) errors than LMerrors and fS(max) errors. If the load
demands more power than the programmed level, the power supply output voltage sags and the overload timer
is initiated.
(14)
Minimum Converter Power Limitation
The dynamics of the DRV current sense imposes the 12-W minimum power level limit for this controller. The
power level limits are found from DRV current estimates for typical universal AC adapters that use a 600-V
MOSFET. The power range and its associated peak current range are given in Equation 15.
(15)
The minimum power level is due to a loss of linearity of the current mirror, as shown in Figure 31. A programmed
IDRV,PK level between 0.66 A and 1 A (by using 100 kΩ≤RCL ≤150 kΩ) allows only a 2:1 amplitude modulation
range of the peak DRV current. The amplitude of IDRV modulates linearly if IDRV,PK is programmed within its
recommended operating range (1.0 A <IDRV,PK <4.1 A, corresponding to 100 kΩ > RCL >24.3 kΩrespectively.
Figure 31. Dynamic Operating Range
Copyright ©2009–2011, Texas Instruments Incorporated 25
( )
( )
2
3
PS DRV ( PEAK )
SECONDARY ,AVG SHORTEDLOAD
PS DRV ( PEAK )
SECONDARY ,RMS SHORTEDLOAD
N I
I
N I
I
´
=
´
=
tOL = 250ms
50 300
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
Fault Recovery
The UCC28610 reacts with the programmed overload response if the overload lasts longer than tOL (nominally
250 ms). The overload fault responses are either (1) latch-off or (2) shutdown/retry after a retry delay of 750 ms.
The overload response is programmed with the MOT pin. The forced DCM feature prevents transformer
saturation and limits the average and RMS output currents of the secondary winding of the transformer. Even
under short circuit load conditions, the output current of the transformer is limited to the levels that are shown in
Equation 16, where NPS is the primary-to-secondary turns ratio. Typical behavior for a shorted load is shown in
Figure 32.
(16)
In shutdown/retry mode switching will be re-enabled after the 750-ms retry delay. In latch-off mode, a 7.5-kΩload
is activated at the DRV pin upon the activation by a fault condition. The internal 7.5-kΩload draws current from
the bulk capacitor through the HVMOSFET and the transformer primary winding. The bias voltage, VDD, is also
regulated by the HVMOSFET during the latch-off state. Once the AC line is removed, a 2.8-mA current,
IDRV,DSCH, will discharge the bulk capacitor. Ultimately, VDD will discharge when the bulk voltage becomes
sufficiently low. A normal start-up cycle can occur if the input voltage is applied after VDD falls below the fault
reset level, VDD(FAULT RESET), which is approximately equal to 6 V.
Figure 32. Overload Behavior with a Shorted Output
26 Copyright ©2009–2011, Texas Instruments Incorporated
kk
k
k
RMOT
tMOT
11
MOT MOT
R = t 1 10 s
W
æ ö
´ ´
ç ÷
è ø
MOT
MOT
150 k R 500 k
1.5 s t 5 s
W £ £ W
£ £m m
10
MOT MOT
R = t 2 10 s
W
æ ö
´ ´
ç ÷
è ø
MOT
MOT
25 k R 100 k
1.5 s t 5 s
W £ £ W
£ £m m
UCC28610
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SLUS888E –JANUARY 2009–REVISED JULY 2011
Maximum On-Time and Brown Out
The forced DCM feature provides protection against excessive primary currents in the event that the input
voltage becomes very low. The highest possible secondary currents can be described by Equation 16. The
UCC28610 adds further protection by allowing the user to program the maximum on-time.
The Maximum On-Time (MOT) function causes the converter to react as if there is an overload condition if the
load is sufficiently large during a line sag condition. During low line conditions the MOT function limits the on-time
of the primary switch which limits the peak current in the primary power stage. Figure 33 shows how the MOT
period, tMOT, is programmed over the range of 1.5 μsto5μs for either range of programming resistors. The
resistor range determines the controller’s response to a sustained overload fault –to either Latch-off or to
Shutdown/Retry, which is the same response for a line-sag, or brown out, condition.
External Shutdown Using the MOT Pin
Many applications require the ability to shutdown the power supply with external means. This feature is easily
implemented by connecting the collector and emitter of an NPN transistor between MOT and GND, respectively.
The NPN transistor can be the photo-transistor of an opto-isolator for isolated applications.
Figure 33. Programming MOT and Overload Fault Response
For latch-off response to over-current or brownout:
(17)
where:
(18)
For shut-down/retry response to over-current or brownout:
(19)
where:
(20)
Copyright ©2009–2011, Texas Instruments Incorporated 27
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
Over Voltage Detection
The UCC28610 controller monitors the output voltage by sampling the voltage at the auxiliary winding. The
sampling time has a fixed delay of 1 μs, tBLANK,OVP, after the internal driver turns off. This allows the auxiliary
winding to be sampled after the bias winding voltage settles from the transient. This same delay is used to blank
the ZCD input to avoid unintended zero crossing detection should the ringing be large enough to cross the ZCD
zero crossing threshold.
The output over-voltage (OV) threshold is set using the turn ratio of the auxiliary winding to the output secondary
and a resistive divider into the ZCD input pin. The UCC28610 will always enter a latched-off state if it detects an
OV condition. The VDD supply must cycle below the fault reset threshold to re-start in order to recover. The
functionality of the over-voltage detection function is shown in Figure 34.
Figure 34. Output Over-Voltage Protection with ZCD Pin
Solving for High Frequency Ringing
Cascode drive circuits are well known for high speed voltage gain. This topology can have small signal
bandwidth well over 100 MHz and it can exhibit high frequency ringing. The internal HS Drive MOSFET shorts
the gate to source of the external HVMOSFET during the turn-off interval of the switch cycle. This prevents the
HVMOSFET from undesirably exciting the LC resonant circuit in the converter (the magnetizing inductance of the
transformer and the stray drain capacitance). High frequency ringing can appear within the built-in dead-time
between the turn-off of DRV and the turn-on of the HS Drive. A large amount of energy is transferred through the
power components during this dead-time. Excessive high frequency ringing can cause EMI problems and
become destructive in some situations.
Identification of High Frequency Ringing
The high frequency ringing is the result of stray capacitances ringing with the stray inductance between the
source of the HVMOSFET and the DRV pin. Low threshold voltage of the high voltage MOSFET and large peak
DRV current can make the ringing worse. In destructive ringing situations, the converter may easily power up and
attain regulation the first time, never to start-up again.
The ringing can be observed in either or both of the following conditions:
•The very first HVMOSFET turn-off event during a cold start of the converter (VGG >VDD).
•HVMOSFET turn-off edge under steady state, where the converter switches the HVMOSFET at the
programmed IDRV,PK level (VDD >VGG).
28 Copyright ©2009–2011, Texas Instruments Incorporated
VGG
DRV
GND
UCC28610 Ferrite chip
or bead
Bulk Voltage Primary
RG-ON
DG
( a )
VGG
DRV
GND
UCC28610
Bulk Voltage Primary
RG-ON
DG
( b )
CDRV
VGG
DRV
GND
UCC28610
Bulk Voltage Primary
RG-ON
DG
( c )
RG- OFF
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
Avoid HF Ringing
High frequency ringing problems with cascode MOSFET drives can often be avoided. Many converters will not
have this problem because they use an HVMOSFET with a large Vth, large RDS(on), low transconductance gain, or
operate at low current. Ringing problems can also be avoided by minimizing stray inductance. The trace between
the HVMOSFET source and the DRV pin must be kept very short, less than 1 cm. Do not add current probe
loops to the source lead of the HVMOSFET. Do not place ferrite beads on the source lead of the HVMOSFET.
If ringing cannot be avoided, the most efficient and effective methods to solve ringing during switching transients
are:
1. A ferrite chip or bead connected to the gate of the HVMOSFET,
2. A small capacitor connected from DRV to GND and
3. A gate turn-off resistor. These three techniques can be used separately or combined, as shown in Figure 35.
Figure 35. High Frequency Ringing Solutions, (a) ferrite chip, (b) CDRV and (c) RG-OFF
Copyright ©2009–2011, Texas Instruments Incorporated 29
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
Ferrite Chip or Bead Solution
The ferrite chip or bead connected to the gate of the HVMOSFET provides the best result because it suppresses
ringing in the gate, source, and drain circuits of the HVMOSFET with minimal added losses. Select the ferrite
chip for its resistance value in the ringing frequency range (for example, 60 Ωat 100 MHz). The peak current
rating of the ferrite chip or bead must be sufficient for the drain –gate discharge current that occurs during the
turn-off transient. Excessively large bead reactance can result in low frequency surges of VGG at peak load.
Normally, good results can be achieved with a 0603 ferrite chip device.
DRV Capacitor Solution
A capacitor between DRV and GND can reduce ringing on VGG. Select the DRV capacitor experimentally by
observing the effect on the VGG pin during the first turn-off edge and during the turn-off edge at full load
operation. The capacitor should be less than 3.3 nF so that it does not significantly reduce efficiency. Use a
capacitor with a low Q, such as one with Y5V dielectric. This technique will not completely damp the ringing yet it
can provide sufficient protection against stray inductance between the source of the HVMOSFET and the DRV
pin.
Gate Turn-Off Resistor Solution
A gate turn-off resistor in the range 0 Ω < RG-OFF <5Ωcan damp ringing. The turn-off resistance is limited in
order to prevent the stray source inductance of the HVMOSFET from over charging VGG through the body diode
of the HS Drive MOSFET, in addition to any peak current error problems that would be caused by additional
delay. The damping effect of the gate resistor works better in applications with low current and small source
inductance.
A much larger resistance can be tolerated during the HVMOSFET turn-on transition due to DCM operation. The
recommended turn-on resistance range is 0 Ω <RG-ON <200 Ωin order to prevent the turn-on delay from
interfering with valley switching.
Thermal Shutdown
The UCC28610 protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown point, TSD, the UCC28610 initiates a shutdown event and permits
retry after the retry time, tRETRY. Shutdown/Retry cycles continue if the junction temperature is not less than TSD
minus TSD_HYST.
30 Copyright ©2009–2011, Texas Instruments Incorporated
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
Typical Schematic and Layout
It is possible to design a power supply on a single layer board using the UCC28610. Figure 36 and Figure 37
show an example of a typical layout and design, respectively. Proper use of ground planes can solve EMI and
thermal problems. For best results, create a quiet ground plane for the components associated with pins 1
through 4. This offers shielding for the control signals. Also, do not extend the ground plane under heat sinks,
thermistors or snubbers so that these components do not heat the UCC28610.
Figure 36. Typical Layout of the Device on a Single Layer PCB
NOTE
The reference designators correspond to the components shown in the schematic of
Figure 37.
Copyright ©2009–2011, Texas Instruments Incorporated 31
+
+ +
+
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
Figure 37. Typical Design Schematic
32 Copyright ©2009–2011, Texas Instruments Incorporated
P M
CL
IN
K L
R 33.2k P
´
= W ´
DRV(PK)
CL
100 kV
I = R
11
MOT MOT
R = t 1 10 W
æ ö
´ ´
ç ÷
è ø
s
10
MOT MOT
R = t 2 10 W
æ ö
´ ´
ç ÷
è ø
s
( )
VDD(GM) BURST
VDD
BURST
I t
CVDD
´
=D
( )
BULK max
PS
DBIAS OUT
PB PB
V
N
V V +
N N
³
UCC28610
www.ti.com
SLUS888E –JANUARY 2009–REVISED JULY 2011
Terminal Components
For reference designators refer to Figure 1.
Table 1. Terminal Components
NAME TERMINAL DESCRIPTION
CL 3
Where KP= 0.54W/ μH
LMis the minimum value of the primary inductance
PIN = POUT/η
η= efficiency
Q1, power MOSFET with adequate voltage and current ratings, VVGS must have at least 20-V static rating.
DRV 6 D1, Schottky diode, rated for at least 30 V, placed between DRV and VDD
FB 1 RFB = 100 kΩ
GND 7 Bypass capacitor to VDD, CBP = 0.1-μF, ceramic
For latch-off response to overcurrent faults:
tMOT = user programmable maximum on-time after 250-ms delay.
where
MOT 4 •150 kΩ ≤ RMOT ≤500 kΩ
For shutdown-retry response to overcurrent faults:
•25 kΩ ≤ RMOT ≤100 kΩand tMOT ≤5μs
where:
ΔVDD(BURST) is the allowed VDD ripple during burst operation
tBURST is the estimated burst period,
The typical CVDD value is approximately 47 μF
VDD 8 DBIAS must have a voltage rating greater than:
where:
VDBIAS is the reverse voltage rating of diode D2
VBULK(max) is the maximum rectified voltage of CBULK at the highest line voltage
minimize the length of the CVGG connection to GND
VGG 5 CVGG = at least 10x CGS of HVMOSFET, usually
CVGG = 0.1 μF.
Copyright ©2009–2011, Texas Instruments Incorporated 33
OUT F PS
ZCD1
PB
V + V N
R = 100 A N
´
m
(ovp) ZCD1
ZCD2
PS
OUT(pk) (ovp)
PB
ZCD R
R = N
V × -ZCD
N
´
æ ö
ç ÷
è ø
UCC28610
SLUS888E –JANUARY 2009–REVISED JULY 2011
www.ti.com
Table 1. Terminal Components (continued)
NAME TERMINAL DESCRIPTION
ZCD 2 where:
ZCD(ovp) is the overvoltage fault threshold at ZCD
NPS is the primary to secondary turns ratio
NPB is the primary to bias turns ratio
VOUT is the average output voltage of the secondary
VFis the forward bias voltage of the secondary rectifier
VOUT,PEAK is the desired output overvoltage fault level
Note 1. Refer to the Electrical Characteristics table for all constants and measured values, unless otherwise noted.
Note 2. Refer to Figure 1 for all component locations in the Table 1.
Revision History
Changes from Revision C (January, 2009) to Revision D Page
•Deleted Equation 2 ............................................................................................................................................................. 14
34 Copyright ©2009–2011, Texas Instruments Incorporated
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC28610DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Jul-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC28610DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Jul-2011
Pack Materials-Page 2
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