UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com GREEN-MODE FLYBACK CONTROLLER Check for Samples: UCC28610 FEATURES APPLICATIONS * * * 1 * * * * * * * * * Cascoded Configuration Allows Fully Integrated Current Control Without External Sense Resistor Fast Start Up With Low Standby Power Achieved by Cascode Configuration Frequency and Peak Current Modulation for Optimum Efficiency Over Entire Operating Range Green-Mode (GM) Burst Switching Packets Improve No-Load Efficiency Advanced Overcurrent Protection Limits RMS Input and Output Currents Thermal Shutdown Timed Overload With Retry or Latch-Off Response Programmable Opto-Less Output Over-Voltage Protection Fast Latched Fault Recovery 8-Pin SOIC Package and 8-Pin PDIP Lead-Free Packages * * Universal Input AC/DC Adapters, 12 W to 65 W High Efficiency Housekeeping and Auxillary Power Supplies Offline Battery Chargers Consumer Electronics (DVD Players, Set-Top Boxes, DTV, Gaming, Printers, etc.) DESCRIPTION The UCC28610 brings a new level of performance and reliability to the AC/DC consumer power supply solution. A PWM modulation algorithm varies both the switching frequency and primary current while maintaining discontinuous or transition mode operation over the entire operating range. Combined with a cascoded architecture, these innovations result in efficiency, reliability, and system cost improvements over a conventional flyback architecture. The UCC28610 offers a predictable maximum power threshold and a timed response to an overload, allowing safe handling of surge power requirements. Overload fault response is user-programmed for retry or latch-off mode. Additional protection features include output overvoltage detection, programmable maximum on-time, and thermal shutdown. + VOUT VIN AC - UCC28610 MOT VGG CL DRV ZCD GND FB VDD 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION OPERATING TEMPERATURE RANGE, TA -40C to 125C PINS PACKAGE PACKAGE LEAD TRANSPORT MEDIA UNITS ORDERABLE PART NUMBER 8 Plastic Small Outline SOIC D Tape and Reel 2500 UCC28610DR 8 Plastic Dual In-Line PDIP P Tube 50 UCC28610P ABSOLUTE MAXIMUM RATINGS (1) All voltages are with respect to GND, -40C < TJ = TA < 125C, all currents are positive into and negative out of the specified terminal (unless otherwise noted) UCC28610 VDD -0.5 to +25 DRV, during conduction -0.5 to +2.0 DRV, during non-conduction 20 VGG (2) Input voltage range ZCD, MOT, CL -0.5 to +16 (3) -0.5 to +1.0 VDD - VGG -7 to +10 (2) Continuous input current IVGG Input current range IZCD, IMOT, ICL, IFB 10 (3) mA -3 to +1 DRV -5 A -5 to +1.5 DRV, pulsed 200ns, 2% duty cycle TJ Operating junction temperature range -40 to +150 Tstg Storage temperature range -65 to +150 Lead Temperature (soldering, 10 sec.) (1) (2) (3) (2) (3) 2 C +260 These are stress ratings only. Stress beyond these limits may cause permanent damage to the device. Functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability Voltage on VGG is internally clamped. The clamp level varies with operating conditions. In normal use, VGG is current fed with the voltage internally limited In normal use, MOT, CL, ZCD, and FB are connected to resistors to GND and internally limited in voltage swing PACKAGE DISSIPATION RATINGS (1) (1) V -0.5 to +7 FB (3) Peak output current UNIT (2) PACKAGE JA, THERMAL IMPEDANCE JUNCTION TO AMBIENT, NO AIRFLOW (C/W) (1) JB, THERMAL IMPEDANCE JUNCTION TO BOARD, NO AIRFLOW (C/W) (2) TA = 25C POWER RATING (mW) (3) TA = 85C POWER RATING (mW) (3) SOIC-8 (D) 165 55 606 242 730 PDIP-8 (P) 110 37 909 364 1080 TB = 85C POWER RATING (mW) (2) (3) Tested per JEDEC EIA/JESD51-1. Thermal resistance is a function of board construction and layout. Air flow reducex thermal resistance. This number is included only as a general guideline; see TI document (SPRA953) IC Package Thermal Metrics. Thermal resistance to the circuit board is lower. Measured with standard single-sided PCB construction. Board temperature, TB, measured approximately 1 cm from the lead to board interface. This number is provided only as a general guideline. Maximum junction temperature, TJ, equal to 125C Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS Unless otherwise noted, all voltages are with respect to GND, -40C < TJ = TA < 125C. Components reference, Figure 1. MIN MAX VDD Input voltage 9 20 VGG Input voltage from low- impedance source 9 13 IVGG Input current from a high impedance source 10 2000 RMOT Resistor to GND 25 100 RCL Resistor to GND RZCD1 Resistor to auxiliary winding CVGG CBP Shutdown/Retry mode Latch-off mode UNIT V A 150 750 24.3 100 50 200 VGG capacitor 33 200 nF VDD bypass capacitor, ceramic 0.1 1 F CBULK VIN AC NP R START NS k + VOUT - C VGG Q1 NB RMOT UCC28610 MOT VGG RCL CL DRV ZCD GND RZCD2 R FB CBP FB D1 VDD R ZCD1 C VDD D BIAS Figure 1. Recommended Operating Conditions Application ELECTROSTATIC DISCHARGE (ESD) PROTECTION over operating free-air temperature range (unless otherwise noted) ESD Rating, Human Body Model (HBM) ESD Rating, Charged Device Model (CDM) Copyright (c) 2009-2011, Texas Instruments Incorporated MAX UNIT 2 kV 500 V 3 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise stated: VDD = 12 V, VGG=12 V, ZCD = 1 V, FB = 0 V, GND = 0 V, a 0.1-F capacitor between VDD and GND, a 0.1-F capacitor between VGG and GND, RCL = 33.2 k, RMOT = 380 k, -40C < TA < +125C, TJ = TA PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VDD and VGG SUPPLY VGG(OPERATING) VGG voltage, operating VDD = 14 V, IVGG = 2.0 mA 13 14 15 VGG(DISABLED) VGG voltage, PWM disabled VDD = 12 V, IVGG = 15 A, IFB = 350 A 15 16 17 VGG Rise in VGG clamping voltage during UVLO, GM, or Fault VGG(DISABLED) - VGG(OPERATING) 1.75 2.00 2.15 IVGG(SREG) VGG shunt regulator current VGG = VGG(DISABLED) -- 100 mV, VDD = 12 V 6 10 A VGG(SREG) VGG shunt load regulation 10 A IVGG 5 mA, IFB = 350 A 125 200 mV VGG(LREG) VGG LDO regulation voltage VDD = 20 V, IVGG = - 2 mA VGG(LREG, DO) VGG LDO Dropout Voltage VDD - VGG, VDD = 11 V, IVGG = - 2 mA VDD(ON) V 13 1.5 2 2.5 UVLO turn-on threshold 9.7 10.2 10.7 VDD(OFF) UVLO turn-off threshold 7.55 8 8.5 VDD(UVLO) UVLO hysteresis 1.9 2.2 2.5 IVDD(OPERATING) Operating current VDD = 20 V 2.5 3 3.7 IVDD(GM) Idle current between bursts IFB = 350 A 550 900 IVDD(UVLO) Current for VDD < UVLO VDD = VDD(ON) - 100 mV, increasing 225 310 RDS,ON(VDD) VDD Switch on resistance, DRV to VDD VGG = 12 V, VDD = 7V, IDRV = 50 mA 4 10 VDD(FAULT VDD for fault latch reset 5.6 6 6.4 V 7.125 7.5 7.875 31 34 38 RESET) V mA A MODULATION tS(HF) (1) Minimum switching period, frequency modulation (FM) mode IFB = 0 A, tS(LF) (1) Maximum switching period, reached at end of FM modulation range IFB = IFB, CNR3 - 20 A, (1) s (1) IDRVpk(max) Maximum peak driver current over amplitude modulation(AM) range IFB = 0 A, RCL = 33. 2 k 2.85 3 3.15 IFB = 0 A, RCL = 100 k 0.80 0.90 1.0 IFB, CNR2 + 10 A, RCL = 33.2 k 0.7 0.85 1.1 IDRVpk(min) Minimum peak driver current reached at end of AM modulation range IFB, CNR2 + 10 A, RCL = 100 k 0.2 0.33 0.5 KP Maximum power constant For IDRVpk(max) = 3 A 0.54 0.60 0.66 W/H IDRVpk(absmin) Minimum peak driver independent of RCL or AM control RCL = OPEN 0.3 0.45 0.6 A tBLANK(Ilim) Leading edge current limit blanking IFB = 0 A, RCL = 100 k, 1.2-A pull-up on time DRV 120 220 450 ns VCL Voltage of CL pin 2.94 3 3.06 0.95 1 1.05 145 165 195 IFB = 0 A IFB = (IFB,CNR3 - 20 A) (1) IFB range for FM modulation IFB increasing, tS = tS(LF), IDRVpk = IDRVpk(max) (2) IFB range for AM modulation tS = tS(LF), IDRVpk ranges from IDRVpk(max) to IDRVpk(min) 35 45 65 IFB,CNR3 - IFB,CNR2 IFB range for Green Mode (GM) modulation IFB increasing until PWM action is disabled entering a burst-off state 50 70 90 IFB hysteresis during GM modulation to enter burst on and off states IFB decreasing from above IFB,CNR3 10 25 40 Voltage of FB pin IFB = 10 A 0.34 0.7 0.84 IFB,CNR1 (2) IFB,CNR2 - IFB,CNR1 (2) IFB, VFB (1) (2) 4 GM-HYST (2) A V A V tS sets a minimum switching period. Following the starting edge of a PWM on time, under normal conditions, the next on time is initiated following the first zero crossing at ZCD after tS. The value of tS is modulated by IFB between a minimum of tS(HF) and a maximum of tS(LF) In normal operation, tS(HF) sets the maximum operating frequency of the power supply and tS(LF) sets the minimum operating frequency of the power supply. Refer to Figure 2. Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated: VDD = 12 V, VGG=12 V, ZCD = 1 V, FB = 0 V, GND = 0 V, a 0.1-F capacitor between VDD and GND, a 0.1-F capacitor between VGG and GND, RCL = 33.2 k, RMOT = 380 k, -40C < TA < +125C, TJ = TA PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 5 20 50 mV -200 -160 -100 mV 0.1 0.15 0.2 ZERO CROSSING DETECTION ZCD(TH) ZCD zero crossing threshold ZCD high to low generates switching period (tS has expired) ZCD(CLAMP) ZCD low clamp voltage IZCD = -10 A ZCD(START) ZCD voltage threshold to enable the internal start timer Driver switching periods generated at start timer rate tDLY(ZCD) Delay from zero crossing to Driver turn-on 150- pull-up to 12-V on DRV tWAIT(ZCD) Wait time for zero crossing detection Driver turn-on edge generated following tS with previous zero crossing detected tST Starter time-out period ZCD = 0 V RDS(on)(DRV) Driver on-resistance IDRV(OFF) Driver off-leakage current RDS(on)(HSDRV) High-side driver on-resistance IDRV = -50 mA IDRV(DSCH) DRV bulk discharge current VDD open, DRV= 12 V, Fault latch set 150 V ns 2 2.4 2.8 150 240 300 IDRV = 4.0 A 90 190 m DRV = 12 V 1.5 20 A 6 11 2 2.8 3.6 mA 4.85 5 5.15 V 0.6 1 1.7 s -0.1 -0.05 0.1 A 0 1.5 3 A 200 250 325 s DRIVER OVERVOLTAGE FAULT ZCD(OVP) Overvoltage fault threshold at ZCD tBLANK(OVP) ZCD blanking and OVP sample time from the turn-off edge of DRV IZCD(bias) ZCD Input bias current Fault latch set ZCD = 5 V OVERLOAD FAULT IFB(OL) Current to trigger overload delay timer tOL Delay to overload fault IFB = 0 A continuously tRETRY Retry delay in retry mode or after shutdown command RMOT = 76 k RMOT(TH) Boundary RMOT between latch-off and retry modes See (3) ms 750 100 120 150 k 0.7 1 1.3 V A SHUTDOWN THRESHOLD MOT(SR) Shutdown-Retry threshold MOT high to low IMOT MOT current when MOT is pulled low MOT = 1 V -600 -450 -300 Latch-OFF RMOT = 383 k 3.43 3.83 4.23 Shutdown-retry RMOT = 76 k 3.4 3.8 4.2 2.7 3 3.3 MAXIMUM ON TIME tMOT MOT MOT voltage s V THERMAL SHUTDOWN TSD (4) TSD_HYS (3) (4) (4) Shutdown temperature TJ, temperature rising (4) Hysteresis TJ, temperature falling, degrees belowTSD (4) 165 15 C A latch-off or a shutdown and retry fault response to a sustained overload is selected by the range of RMOT. To select the latch-off mode, RMOT should be greater than 150 k and tMOT is given by RMOT x (1.0 x 10-11). To select the shutdown-retry mode, RMOT should be less than 100 k and tMOT is given by RMOT x (5.0 x 10-11). Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance at or near thermal shutdown temperature is not specified or assured. Copyright (c) 2009-2011, Texas Instruments Incorporated 5 UCC28610 I D R V ,P K - P ercen t o f M axim u m P eak D R V C u rren t - % SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com AM FM IFB,CNR1 (165uA) 100 GM IFB,CNR2 (210uA) IFB,CNR3 (275uA) IFB,CNR3- IFB,CNR2 (65uA) 33 133 f S - S w itch in g F req u en cy - kH z IFB,CNR2- IFB,CNR1 (45uA) IGM,HYST (20uA) 30 0 50 100 150 200 250 300 IFB - Feedback Current - A Figure 2. FB Electrical Condition Detail 6 Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com DEVICE INFORMATION PIN CONFIGURATION D PACKAGE (Top View) P PACKAGE (Top View) FB 1 8 VDD FB 1 8 VDD ZCD 2 7 GND ZCD 2 7 GND CL 3 6 DRV CL 3 6 DRV MOT 4 5 VGG MOT 4 5 VGG PIN DESCRIPTIONS NAME PIN I/O DESCRIPTION CL 3 I (Current Limit) This pin programs the peak primary inductor current that is reached each switching cycle. Program with a resistor between CL and GND. DRV 6 O (DRiVe) This pin drives the source of an external high voltage power MOSFET. The DRV pin carries the full primary current of the converter. Connect a Schottky diode between DRV and VDD to provide initial bias at start up. FB 1 I (FeedBack) The FB current, IFB, commands the operating mode of the UCC28610. The FB voltage is always 0.7 V. This pin only detects current. GND 7 -- (GrouND) This pin is the current return terminal for both the analog and power signals in the UCC28610. This terminal carries the full primary current of the converter. Separate the return path of the bulk capacitor from the return path of FB, ZCD, MOT, and CL. MOT 4 I (Maximum On Time) This pin has three functions: 1. MOT programs the allowed maximum on-time, tMOT, of the internal driver. 2. MOT programs the converter's reaction to overload and power input under-voltage conditions with either a shutdown/retry response or a latch-off response. 3. MOT can be used to externally shut down the power supply by pulling MOT to GND. When the pin is released, the converter will start after a restart delay, tRETRY. Functions 1 and 2 are programmed with a resistor between MOT and GND. VDD 8 -- This is the bias supply pin for the UCC28610. It can be derived from an external source or an auxiliary winding. This pin must be decoupled with a 0.1-F ceramic capacitor placed between VDD and GND, as close to the device as possible. VGG 5 -- This pin provides a DC voltage for the gate of the external high voltage MOSFET. This pin must be decoupled with a 0.1-F ceramic capacitor placed between VGG and GND, as close to the device as possible. This pin also initiates start-up bias through a large value resistor that is connected to the input bulk voltage. I (Zero Current Detection) This pin has two functions: 1. ZCD senses the transformer reset based on a valid zero current detection signal. 2. ZCD programs the output Over Voltage Protection (OVP) feature using a resistive divider on the primary side bias winding of the Flyback transformer. ZCD 2 Copyright (c) 2009-2011, Texas Instruments Incorporated 7 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS Unless otherwise stated: VDD = 12V, VGG = 12V, ZCD = 1 V, FB = 0 V, GND = 0 V, a 0.1-F capacitor between VDD and GND, a 0.1-F capacitor between VGG and GND, RCL = 33.2 k, RMOT = 380 k, -40C < TA < +125C, TJ = TA BIAS SUPPLY CURRENT vs BIAS SUPPLY VOLTAGE DURING OPERATION BIAS SUPPLY CURRENT vs BIAS SUPPLY VOLTAGE DURING GREEN MODE 4.0 900 IFB = 10 mA 850 VVGG = OPEN IVDD - Bias Supply Current - mA IVDD - Bias Supply Current - mA IFB = 280.4 mA VZCD = 1V 3.8 VVDD decreasing from 20 V 3.6 3.4 3.2 3.0 2.8 VVGG = OPEN VVDD decreasing from 20 V 800 750 700 650 600 2.6 550 8 10 12 16 14 18 20 8 14 16 18 Figure 3. Figure 4. BIAS SUPPLY CURRENT vs TEMPERATURE DURING GREEN MODE OPERATIONAL IVDD - BIAS CURRENT vs BIAS VOLTAGE 900 3.5 850 3.0 800 750 700 650 550 -40 -25 -10 20 2.5 2.0 VDD rising 0 V to 20V 1.5 IFB= 10 mA, VDD falling 20V to 0 V 1.0 IFB= 0 mA, VDD falling 20V to 0 V 0.5 600 0.0 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - C Figure 5. 8 12 VDD - Bias Supply Voltage - V IVDD - Bias Supply Current - mA IVDD - Bias Supply Current - mA VDD - Bias Supply Voltage - V 10 0 5 10 15 20 VDD - Bias Voltage - V Figure 6. Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Unless otherwise stated: VDD = 12V, VGG = 12V, ZCD = 1 V, FB = 0 V, GND = 0 V, a 0.1-F capacitor between VDD and GND, a 0.1-F capacitor between VGG and GND, RCL = 33.2 k, RMOT = 380 k, -40C < TA < +125C, TJ = TA OSCILLATOR FREQUENCY vs FEEDBACK CURRENT MINIMUM SWITCHING PERIOD vs TEMPERATURE 8.0 160 tS,HF - Minimum Switching Period - ms fS - Switching Frequency - kHz 140 120 100 80 60 40 7.8 7.6 7.4 7.2 20 7.0 -40 -25 -10 0 8 50 150 100 200 250 300 IFB - Feedback Control Current - mA 20 35 50 65 Figure 7. Figure 8. SWITCHING PERIOD DURING AMPLITUDE MODULALTION vs AMBIENT TEMPERATURE PEAK DRV CURRENT vs FEEDBACK CURRENT 38 3.5 37 3.0 IDRV(pk) - Peak DRV Current - A tS(LF) - Minimum Switching Period - ms 5 36 35 34 33 31 -40 -25 -10 95 110 125 TA = -40C 2.5 2.0 TA = 25C 1.5 Ambient Temperature (C) -40 25 125 1.0 0.5 32 80 TA - Ambient Temperature - C TA = 125C 0.0 5 20 35 50 65 80 95 110 125 TA - Ambient Temperature - C Figure 9. Copyright (c) 2009-2011, Texas Instruments Incorporated 0 50 100 150 200 250 300 IFB - Feedback Current - mA Figure 10. 9 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Unless otherwise stated: VDD = 12V, VGG = 12V, ZCD = 1 V, FB = 0 V, GND = 0 V, a 0.1-F capacitor between VDD and GND, a 0.1-F capacitor between VGG and GND, RCL = 33.2 k, RMOT = 380 k, -40C < TA < +125C, TJ = TA PEAK DRV CURRENT vs TRANSCONDUCTANCE (1/RCL) PEAK DRV CURRENT vs AMBIENT TEMPERATURE 3.2 5 IFB = 0 mA 4 IDRV(pk) - Peak DRV Current - A IDRV(pk) - Peak DRV Current - A Best Results 24.3 kW < RCL< 100 kW 3 2 1 3.1 3.0 2.9 Avoid Operation Here 2.8 -40 -25 -10 0 0 10 20 30 40 50 1/RCL - mS 35 50 65 80 Figure 12. MAXIMUM ON TIME vs MAXIMUM ON-TIME RESISTANCE MAXIMUM ON TIME vs JUNCTION TEMPERATURE 95 110 125 4.3 4.2 tMOT - Maximum On-Time - ms 5 tMOT - Maximum On-Time - ms 20 Figure 11. 6 4 3 2 MODE Latch Off Shutdown/Retry 1 0 100 200 300 400 500 RMOT - Maximum On-Time Resistor - kW Figure 13. RMOT = 383 kW 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 0 10 5 TA - Ambient Temperature - C 600 3.3 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - C Figure 14. Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Unless otherwise stated: VDD = 12V, VGG = 12V, ZCD = 1 V, FB = 0 V, GND = 0 V, a 0.1-F capacitor between VDD and GND, a 0.1-F capacitor between VGG and GND, RCL = 33.2 k, RMOT = 380 k, -40C < TA < +125C, TJ = TA DRIVER RDS(on) vs AMBIENT TEMPERATURE RDS(on) of HIGH SIDE DRIVE and VDD Switch vs TEMPERATURE 180 12 RDS(on) - On-Time Resistance - W RDS(on) - On-Time Resistance - mW 160 140 120 100 80 60 High-Side Drive VDD Switch 10 8 6 4 2 40 20 -40 -25 -10 5 20 35 50 65 80 0 -40 -25 -10 95 110 125 50 65 80 SAFE OPERATING AREA vs BOARD TEMPERATURE THERMAL COEFFICIENT - JB vs POWER DISSIPATION 95 110 125 60 50 qJB - Thermal Coefficient - C/W PDISS - Power Dissipation - W 35 Figure 16. 2.0 1.5 1.0 0 -40 20 Figure 15. 2.5 0.5 5 TA - Ambient Temperature - C TA - Ambient Temperature - C Package SOIC (D) DIP (P) 40 30 20 Package SOIC (D) DIP (P) 10 0.0 -20 0 20 40 60 80 TB - Board Temperature - C Figure 17. Copyright (c) 2009-2011, Texas Instruments Incorporated 100 120 0 0.25 0.50 0.75 1.00 PDISS - Power Dissipation - W Figure 18. 11 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Block Diagram Fault Latch Reset 13V + VGG LDO Reg VDD Switch + 10V/6V VDD VGG Shunt 8 VGG 6 DRV 7 GND 3 CL 14V HS Drive UVLO + 5 2V 10V/8V Enable PWM IFB FB 1 IFB IFB Feedback Processing 0mA < IFB < 200mA IFB > 200mA 1/tS Modulators Green-mode IFB = 0 ZCD Freq. Modulator TSW IFB Enable PWM Overload D Zero Current Detect 2 Q VGATE Driver Q Bulk Discharge OV Fault Output Voltage Sense 7.5kW 5V Maximum On Time & Fault Response Control IFB Fault Timing & Control IMOT VGATE + 1V MOT 4 Fault IP Latch or Retry 3V Shutdown and Restart Current Modulator IFB Fault Latch Reset UVLO UCC28610 Block Diagram Thermal Shutdown Figure 19. Symplified Block Diagram 12 Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com APPLICATION INFORMATION General Operation The flyback converter is attractive for low power AC/DC applications because it provides output isolation and wide input operating abilities using a minimum number of components. Operation of the flyback converter in Discontinuous Conduction Mode (DCM) is especially attractive because it eliminates reverse recovery losses in the output rectifier and it simplifies control. The UCC28610 is a flyback controller for 12-W to 65-W, peak AC/DC power supply applications that require both low AC line power during no-load operation and high average efficiency. This controller limits the converter to DCM operation. It does not allow Continuous Conduction Mode (CCM) operation. Forced DCM operation results in a uniquely safe current limit characteristic that is insensitive to AC line variations. The peak current mode modulator does not need slope compensation because the converter operates in DCM. The operation of the UCC28610 is facilitated by driving the external high voltage MOSFET through the source. This configuration is called a cascode driver. It features fast start-up and low input power under no-load conditions without having high voltage connections to the control device. The cascode driver has no effect on the general operation of the flyback converter. The feedback pin uses current rather than voltage. This unique feature minimizes primary side power consumption during no-load operation by avoiding external resistive conversion from opto-coupler current to voltage. Average efficiency is optimized by the UCC28610 between peak power and 22% peak power with constant peak current, variable off-time modulation. This modulation tends to make the efficiency constant between 22% and 100% peak load, eliminating the need to over-design to meet average efficiency levels that are required by EnergyStarTM. Copyright (c) 2009-2011, Texas Instruments Incorporated 13 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Transformer Selection To begin a power supply design, the power supply designer needs to know the peak power to be delivered by the converter, the input voltage range, the output voltage, and an estimate of the maximum allowable bulk voltage ripple. Select the maximum allowable stress voltage for the external power MOSFET. The stress voltage, VDS, determines the reflected secondary voltage that resets the flyback transformer and the turn ratio between primary and secondary. A simplified diagram of the converter and its waveforms are shown in Figure 20. N PS Figure 20. Basic Flyback Converter and Waveforms at Peak Load and Minimum VBULK Voltage Peak power is the maximum power level that must be regulated by the converter control system. Loads that last longer than the control loop time constant (100 s - 300 s) are directly considered "peak power". Loads lasting less than the control loop time constant can be averaged over the control loop time constant. The minimum switching period is when the converter is operating in the Frequency Modulation (FM) mode, referred to as tS(HF). This switching period must equal the sum of the switching intervals at minimum input voltage, maximum load, as shown in Figure 20 and described in Equation 1. The switching intervals are tON, the conduction time of the MOSFET; tDM the demagnetization time of the transformer and tDT, the duration of the deadtime, equal to half of the resonant cycle, after the transformer is de-energized. tS( HF ) = tON + tDM + tDT (1) Solve for the primary to secondary turn ratio, NPS, using the maximum allowable VDS, the maximum input line voltage, the predicted voltage spike due to leakage inductance and the desired regulated output voltage of the converter, VOUT. NPS = 14 VDS - 2 VIN(max) - Vleakage_spike VOUT (2) Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Assume a deadtime, tDT, of 5% of the total minimum switching period to allow for variations in the output capacitance of the HVMOSFET and the leakage inductance value: tDT = 0.05 tS( HF ) (3) Using volt-seconds balance, set the volt-seconds on equal to the volt-seconds for demagnetizing and solve for the on-time: VBULK (min) tON = VOUT NPS tDM (4) tDM = tS( HF ) - tON - tDT tON = (5) VOUT NPS ( tS( HF ) - tDT ) VBULK (min) + (VOUT NPS ) (6) The maximum input power, PIN, to the converter, in addition to being equal to the output power divided by the overall efficiency, is always equal to: 2 (VBULK(min) tON ) POUT PIN = = efficiency 2 LM t S(HF) (7) Solve for the primary inductance value: LM (V = 2 BULK (min) tON ) 2 PIN tS( HF ) (8) This equation is an approximation of the primary inductance value that is the best choice to minimize the primary side RMS current. In the actual circuit, when the resonance and delay due to leakage inductance can be measured, the magnetizing inductance value may need to be iterated for optimized low voltage switching. Select the CL resistor, RCL, based upon the maximum power constant of the controller, KP, The tolerance of LM should be considered (such as 10% lower for a typical inductor) and the minimum value of LM should be used to calculate the value of the CL resistor. To avoid tripping the overload protection feature of the controller during the normal operating range, use the minimum value of KP from the Electrical Characteristics Table: RCL = 33.2kW K P LM PIN (9) Once RCL is selected, the peak DRV current is calculated using Equation 10: IDRV(PK ) = 100kV RCL (10) For high efficiency, the bias winding turn ratio, NPB, should be designed to maintain the VDD voltage above the VGG clamp, which is equal to VGG(DISABLED), when the converter is in burst mode. If VDD discharges below this value, minus the threshold voltage of the HVMOSFET, the HVMOSFET will turn on and linearly supply the VDD current from the high voltage rail instead of from the bias windings. Adding a zener diode on VDD will protect VDD from exceeding its absolute maximum rating in the event of a spike due to excess leakage inductance. Copyright (c) 2009-2011, Texas Instruments Incorporated 15 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Cascode Bias and Start-Up The UCC28610 uses a cascode drive and bias to control the high voltage power MOSFET and provide initial bias at start-up. Thus, the external high voltage power MOSFET provides the start-up function in addition to the power switching function during converter operation. The cascode architecture utilizes a low voltage switch operating between ground and the source of a high voltage MOSFET (HVMOSFET) configured in a common gate configuration, as shown in Figure 21. There are some key points to note. 1. The gate of the external HVMOSFET is held at a DC voltage. 2. The HVMOSFET is driven through the source, not the gate. 3. The entire primary winding current passes through the internal low voltage Driver MOSFET (both DRV and GND pins). Bulk Bulk Primary Winding Primary Winding External HVMOSFET External HVMOSFET + Gate Bias 14VDC PWM Control Cascoded MOSFET Pair Internal Low Voltage DRIVER ON Gate Bias 14VDC PWM Control (a) V th _ Internal Low Voltage DRIVER OFF (b) Figure 21. Cascoded Architecture 16 Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com The UCC28610 integrates the low voltage switch in the form of a 90-m FET along with all associated current sensing and drive. The HVMOSFET is forced to track the fast internal low voltage driver. The drain-gate charge in the HVMOSFET does not affect the turn-off speed because the gate is connected to a low impedance DC source. The cascode configuration results in very fast turn-off of the HVMOSFET, which keeps MOSFET switching losses low. Cascode drive circuits are well known for high speed voltage gain. This topology can have small signal bandwidth over 100 MHz and it can exhibit high frequency ringing. High frequency ringing can cause EMI problems and become destructive in some situations. The sub-intervals during and immediately following the turn-on and turn-off transients are particularly susceptible to oscillation. For avoidance or solutions, see the application section, Solving High Frequency Ringing. The cascode configuration permits a unique start-up sequence that is fast yet low-loss. Start-up bias uses a low level bleed current from either the AC line or the rectified and filtered AC line, or bulk voltage (via RSTART) as shown in Figure 22. This current charges a small VGG capacitor, CVGG, raising the HVMOSFET gate. The VGG pin will typically draw approximately 6 A (IVGG(SREG)) during this time, allowing the bulk bias current to be small and still charge the VGG capacitor. The HVMOSFET acts as a source follower once VGG reaches the threshold voltage of the HVMOSFET. Then, the HVMOSFET will bring up the DRV voltage as VGG continues to rise. During this time the UCC28610 is in UVLO and the Enable PWM signal is low. This turns on the VDD switch connecting VDD to DRV, allowing VDD to rise with the source of the HVMOSFET and charging CVDD. An external Schottky diode, D1, is required between DRV and VDD. This diode passes potentially high switching currents that could otherwise flow through the body diode of the internal VDD Switch. Bulk Primary Winding RSTART HVMOSFET CVGG D1 VDD Start-up Current CVDD VDD Operating and GM Current 8 VDD 5 VDD Switch VGG Shunt 10V/8V Fault HS Drive 6 UVLO + 14V Bias Winding VGG 2V DRV Enable PWM Driver PWM Control 7 GND Figure 22. Start-Up Currents for the Cascode Architecture. Copyright (c) 2009-2011, Texas Instruments Incorporated 17 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com In order to achieve the lowest possible no-load power, select the number of turns in the bias winding so that VDD is higher than 16 V - VTH of the HVMOSFET. A bias winding voltage between 17 V and 20 V usually achieves minimum loss. The bias winding often tracks the primary leakage inductance turn-off voltage spike. Place a 20-V Zener diode between VDD and GND in applications where heavy loads cause excessive VDD voltage. Volts 20 15 VGG 10 V OUT VDD 5 0 Volts 150 100 V BULK 50 5 10 15 20 25 30 Time (ms) Figure 23. Typical Start-Up Waveforms for a 17-V Bias Winding Voltage Typical start-up waveforms are shown in Figure 23. As VGG rises, VDD will follow, minus the threshold voltage of the HVMOSFET. When VDD reaches approximately 10 V, the UCC28610 initiates switching. The bias supply current, IVDD, rises to its operating level and it is supplied from the VDD capacitor. Start-up times can be kept under 200 ms by selecting the VGG capacitor in the range of 33 nF to 1000 nF and selecting RSTART to have a current of 15 A at the minimum AC line voltage. Select capacitor CVDD to have enough capacitance to provide operating bias current to the controller for the time it takes the auxiliary winding to take over. No-load burst operation may impose a requirement for additional CVDD capacitance. The voltage on VGG is shunt regulated to 16 V whenever the PWM action is disabled. This is reduced to 14 V during switching to limit voltage stress on the gate of the external HVMOSFET. The external HVMOSFET should have a threshold voltage of less than 6 V in order to permit proper starting. 18 Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Feedback Function Modulation and modes are controlled by applying current to the FB pin. The FB pin is usually used to feed back the output error signal to the modulator. The UCC28610 uses internal current mirrors to apply the FB current to the Feedback Processing block, and then to the Frequency Modulator and Current Modulator blocks. The voltage of the FB pin is a constant 0.7 V. AC filtering of the output of the opto-coupler must be applied to the emitter of the opto-coupler, as shown in Figure 24. The corner frequency of the filter in Figure 24 should be at least a decade above the maximum switching frequency of the converter, as given in Equation 11. A 100-k resistor, RFB, between the FB pin and GND prevents ground noise from resetting the overload timer by biasing the FB pin with a negative current. An opto-coupler with a low Current Transfer Ratio (CTR) often gives better no-load performance than a high CTR device due to the bias current of the secondary reference. The low CTR also offers better noise immunity than a high CTR device. VDD IFB FeedBack Processing To Modulators GM OverLoad I FB 0uA < IFB < 200uA IFB > 200uA IFB = 0A RFB filte r 1 FB RFB CFBf ilter Figure 24. FB Details fFB = 1 2 p RFBfilter CFBfilter Copyright (c) 2009-2011, Texas Instruments Incorporated (11) 19 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Modulation Modes Under normal operating conditions, the FB current commands the operating mode of the UCC28610, as shown in Figure 25 and Figure 26. The FB current commands the UCC28610 to operate the converter in one of three modes: Frequency Modulation (FM) mode, Amplitude Modulation (AM) mode, and Green Mode (GM). The converter operates in FM mode with a large power load (22% to 100% the peak regulated power). The peak HVMOSFET current reaches its maximum programmed value and FB current regulates the output voltage by varying the switching frequency, which is inversely proportional to tS. The switching frequency is modulated from 30 kHz (22% peak power) to 133 kHz (100% peak power), the on time is constant, and the IDRV peak current is constant. The maximum programmable HVMOSFET current, IDRV,PK(max), is set by a resistor on the CL pin, as described in Equation 10. The converter operates in AM mode at moderate power levels (2.5% to 22% of the peak regulated power). The FB current regulates the output voltage by modulating the amplitude of the peak HVMOSFET current from 33% to 100% of the maximum programmed value while the switching frequency is fixed at approximately 30 kHz. The UCC28610 modulates the voltage on the CL pin from 3 V to 1 V to vary the commanded peak current, as shown in Figure 25 and Figure 26. IFB Current Modulator Peak Current Control 3 RCL IFB AM FM IFB,CNR1 ( 165uA ) 100 GM IFB,CNR2 ( 210u A) IFB,CNR3 ( 275 uA) IFB,CNR3 - IFB,CNR2 (65 uA ) 33 I DR V ,PK Freq. Modulator - Pe rc en t o f M axi m u m Pea k D R V Cu rren t - % The converter operates in GM at light load (0% to 2.5% of the peak regulated power). The FB current regulates the output voltage in the Green Mode with hysteretic bursts of pulses using FB current thresholds. The peak HVMOSFET current is 33% of the maximum programmed value. The switching frequency within a burst of pulses is approximately 30 kHz. The duration between bursts is regulated by the power supply control dynamics and the FB hysteresis. The UCC28610 reduces internal bias power between bursts in order to conserve energy during light-load and no-load conditions. 1 /tS TS W VGAT E I FB 133 kHz - Sw i tc hi ng F re q ue n cy - I FB,CNR2 - IFB,CNR1 (45 uA) f S IGM,HYST (20 uA ) 30 0 50 100 150 200 250 300 IFB - Feedbac k C urrent - A Figure 25. Modulation Control Blocks 20 Figure 26. Control Diagram with Operating Modes Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Primary Current Sense The UCC28610 uses a current mirror technique to sense primary current in the Current Modulator. See Figure 27 for details. All of the primary current passes into the DRV pin, through the Driver MOSFET and out of the GND pin. The Driver MOSFET current is scaled and reflected to the PWM Comparator where it is compared with the CL current. At the beginning of each switching cycle a blanking pulse, tBLANK,(Ilim), of approximately 220 ns is applied to the internal current limiter to allow the driver to turn on without false limiting on the leading edge capacitive discharge currents normally present in the circuit. Current Modulator Peak Current Control CL IFB IFB ICL 1 3 FB From Emitter of OptoCoupler IFB RCL ICL IDRV IDRV 100000 6 DRV From Source of HVMOSFET PWM Comparator PWM FlipFlop CLR Driver GND 7 t BLANK,(Ilim) Figure 27. CL pin and DRV Current Sense Copyright (c) 2009-2011, Texas Instruments Incorporated 21 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Zero Crossing Detection The modulator requires three conditions in order to initiate the next switching cycle: 1. The time since the last turn-on edge must be equal to or greater than the time that is requested by the Feedback Processor as determined by the feedback current, IFB. 2. The time since the last turn-on edge must be longer than the minimum period that is built into the UCC28610 (nominally 7.5 s which equals 133 kHz). 3. Immediately following a high-to-low zero crossing of the ZCD voltage. Or, it has been longer than tWAIT,ZCD (~2.4 s) since the last zero crossing has been detected. Every switching cycle is preceded by at least one zero crossing detection by the ZCD pin. The modulator allows the resonant ring to damp between pulses if the period needs to exceed the damping limit, allowing long pauses between pulses during no-load operation. The switching frequency is not allowed to exceed 133 kHz (nominally). This sets the maximum power limit so that it will be constant for all bulk voltages that exceed the minimum line voltage value. Figure 28 illustrates a set of switching cycle waveforms over a range of operating conditions. The UCC28610 is designed to always keep the inductor current discontinuous. This prevents current tailing during start-up or short circuit conditions and accommodates control of the maximum power delivered. Figure 28. Switching Cycle Waveforms 22 Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Zero crossing is detected using a resistive divider across the bias winding, as shown in Figure 29. The bias winding operates in phase with the output winding. The ZCD function detects transformer demagnetization when the ZCD voltage has a high to low crossing of the 20-mV ZCD threshold, ZCDTH. The voltage at the ZCD pin is internally clamped to contain negative excursions at -160mV (ZCDCLAMP). A small delay, 50 ns to 200 ns, can be added with CZCD to align the turn-on of the primary switch with the resonant valley of the primary winding waveform. NP NS NB RZ CD 1 ZCD R ZC D 2 2 Zero Current Detect PWM Flip-Flop CZ C D OV Fault Output Voltage Sense Fault Timing and Control 5V Figure 29. Zero Crossing Detection. R ZCD1 = R ZCD2 = VOUT + VF N B 100 m A NS (12) ZCD(ovp) R ZCD1 ae NB o c VOUT(pk) x / -ZCD(ovp) NS o e (13) Copyright (c) 2009-2011, Texas Instruments Incorporated 23 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Green Mode Operation During light load operation the UCC28610 cycles between two states: GM-on and GM-off. The details are shown in Figure 30. During the GM-on state, the controller is active while the modulator issues a burst of one or more pulses. During the GM-off state the controller reduces its operating current and switching action is inhibited. The rate and duration of the on and off states are controlled by the current into the FB pin as it cycles between the two hysteretic thresholds separated by IFB, GM_HYST, the load current, the output filter capacitor, and the details of the feedback circuit. During the GM-off state the VDD supply current is reduced to approximately 550 A, IVDD(GM). The Enable PWM signal goes low which inhibits switching, sets the VGG shunt regulation to ~16 V, VGG(DISABLED), and turns on the VDD switch. The VGG node quickly charges to 16V and the low VDD current is supplied from the VDD capacitor. During the GM-on state the UCC28610 controls the peak primary current to 33% of IDRV,PK(max), at a 30-kHz rate. When switching, the VGG shunt regulator pulls the VGG voltage down to ~14 V. VDD is charged by the auxiliary winding during this time as long as VDD does not discharge below 14 V. The converter's output voltage is charged until the feedback network forces the FB current to the GM off threshold, IFB,CNR3, and puts the controller back into the GM off state. At very light loads the time between PWM bursts can be long. To obtain the lowest no-load power, it is important that VDD not discharge below 16 V by more than the threshold voltage of the HVMOSFET or the HVMOSFET will turn-on and linearly supply the VDD current from the high-voltage bulk rail. The VDD voltage can be extended by increasing the CVDD capacitance without significant impact on start-up time. VGG 16 15 14 13 12 VDD VGG V OUT 12.1 12.0 11.9 11.8 VOUT % IDRV, PK(MAX) 100 67 I(DRV) 33 0 250 260 270 Time (ms) 280 290 Figure 30. Green Mode Operation 24 Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Maximum Converter Power Limitation The suggested peak power range of the UCC28610 is 12 W to 65 W based on a universal AC line converter (90-VAC to 265-VAC input line voltage), using an external high voltage MOSFET with a voltage rating of 600 V. This power range may depend on application and external MOSFET stress voltage. Ultimately, the peak primary current is the limiting factor because this current must pass through the UCC28610. The limit on the peak primary current imposes a limit on the peak primary power. The peak power must be less than 65 W, not the average power. The peak power is defined as the highest power level where the controller must maintain regulation. At all power levels, program the UCC28610 to control the power limit with the primary inductance, peak current and maximum switching frequency (133 kHz). The maximum peak input power level is given by Equation 14. The accuracy of the power limit is twice as sensitive to IDRV(PK) errors than LM errors and fS(max) errors. If the load demands more power than the programmed level, the power supply output voltage sags and the overload timer is initiated. PIN(max) = Lm IDRV(pk)2 fS(max) 2 (14) Minimum Converter Power Limitation The dynamics of the DRV current sense imposes the 12-W minimum power level limit for this controller. The power level limits are found from DRV current estimates for typical universal AC adapters that use a 600-V MOSFET. The power range and its associated peak current range are given in Equation 15. PIN 12W I DRV ,PK (min) 1A (15) The minimum power level is due to a loss of linearity of the current mirror, as shown in Figure 31. A programmed IDRV,PK level between 0.66 A and 1 A (by using 100 k RCL 150 k) allows only a 2:1 amplitude modulation range of the peak DRV current. The amplitude of IDRV modulates linearly if IDRV,PK is programmed within its recommended operating range (1.0 A < IDRV,PK < 4.1 A, corresponding to 100 k > RCL > 24.3 k respectively. 5 IDRV(pk) - Peak DRV Current - A Best Results 24.3 kW < RCL< 100 kW 4 3 2 1 Avoid Operation Here 0 0 10 20 30 40 50 1/RCL - mS Figure 31. Dynamic Operating Range Copyright (c) 2009-2011, Texas Instruments Incorporated 25 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Fault Recovery The UCC28610 reacts with the programmed overload response if the overload lasts longer than tOL (nominally 250 ms). The overload fault responses are either (1) latch-off or (2) shutdown/retry after a retry delay of 750 ms. The overload response is programmed with the MOT pin. The forced DCM feature prevents transformer saturation and limits the average and RMS output currents of the secondary winding of the transformer. Even under short circuit load conditions, the output current of the transformer is limited to the levels that are shown in Equation 16, where NPS is the primary-to-secondary turns ratio. Typical behavior for a shorted load is shown in Figure 32. ISECONDARY ,AVG (SHORTEDLOAD ) = ISECONDARY ,RMS (SHORTEDLOAD ) = NPS IDRV ( PEAK ) 2 NPS IDRV ( PEAK ) 3 (16) In shutdown/retry mode switching will be re-enabled after the 750-ms retry delay. In latch-off mode, a 7.5-k load is activated at the DRV pin upon the activation by a fault condition. The internal 7.5-k load draws current from the bulk capacitor through the HVMOSFET and the transformer primary winding. The bias voltage, VDD, is also regulated by the HVMOSFET during the latch-off state. Once the AC line is removed, a 2.8-mA current, IDRV,DSCH, will discharge the bulk capacitor. Ultimately, VDD will discharge when the bulk voltage becomes sufficiently low. A normal start-up cycle can occur if the input voltage is applied after VDD falls below the fault reset level, VDD(FAULT RESET), which is approximately equal to 6 V. tOL = 250ms 50 300 Figure 32. Overload Behavior with a Shorted Output 26 Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Maximum On-Time and Brown Out The forced DCM feature provides protection against excessive primary currents in the event that the input voltage becomes very low. The highest possible secondary currents can be described by Equation 16. The UCC28610 adds further protection by allowing the user to program the maximum on-time. The Maximum On-Time (MOT) function causes the converter to react as if there is an overload condition if the load is sufficiently large during a line sag condition. During low line conditions the MOT function limits the on-time of the primary switch which limits the peak current in the primary power stage. Figure 33 shows how the MOT period, tMOT, is programmed over the range of 1.5 s to 5 s for either range of programming resistors. The resistor range determines the controller's response to a sustained overload fault - to either Latch-off or to Shutdown/Retry, which is the same response for a line-sag, or brown out, condition. External Shutdown Using the MOT Pin Many applications require the ability to shutdown the power supply with external means. This feature is easily implemented by connecting the collector and emitter of an NPN transistor between MOT and GND, respectively. The NPN transistor can be the photo-transistor of an opto-isolator for isolated applications. t MOT k k RMOT k k Figure 33. Programming MOT and Overload Fault Response For latch-off response to over-current or brownout: Wo ae RMOT = tMOT c 1 1011 / so e (17) where: 150 kW RMOT 500 kW 1.5 m s tMOT 5 m s For shut-down/retry response to over-current or brownout: Wo ae RMOT = tMOT c 2 1010 / so e (18) (19) where: 25 k W R MOT 100 k W 1.5 m s t MOT 5 m s Copyright (c) 2009-2011, Texas Instruments Incorporated (20) 27 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Over Voltage Detection The UCC28610 controller monitors the output voltage by sampling the voltage at the auxiliary winding. The sampling time has a fixed delay of 1 s, tBLANK,OVP, after the internal driver turns off. This allows the auxiliary winding to be sampled after the bias winding voltage settles from the transient. This same delay is used to blank the ZCD input to avoid unintended zero crossing detection should the ringing be large enough to cross the ZCD zero crossing threshold. The output over-voltage (OV) threshold is set using the turn ratio of the auxiliary winding to the output secondary and a resistive divider into the ZCD input pin. The UCC28610 will always enter a latched-off state if it detects an OV condition. The VDD supply must cycle below the fault reset threshold to re-start in order to recover. The functionality of the over-voltage detection function is shown in Figure 34. Figure 34. Output Over-Voltage Protection with ZCD Pin Solving for High Frequency Ringing Cascode drive circuits are well known for high speed voltage gain. This topology can have small signal bandwidth well over 100 MHz and it can exhibit high frequency ringing. The internal HS Drive MOSFET shorts the gate to source of the external HVMOSFET during the turn-off interval of the switch cycle. This prevents the HVMOSFET from undesirably exciting the LC resonant circuit in the converter (the magnetizing inductance of the transformer and the stray drain capacitance). High frequency ringing can appear within the built-in dead-time between the turn-off of DRV and the turn-on of the HS Drive. A large amount of energy is transferred through the power components during this dead-time. Excessive high frequency ringing can cause EMI problems and become destructive in some situations. Identification of High Frequency Ringing The high frequency ringing is the result of stray capacitances ringing with the stray inductance between the source of the HVMOSFET and the DRV pin. Low threshold voltage of the high voltage MOSFET and large peak DRV current can make the ringing worse. In destructive ringing situations, the converter may easily power up and attain regulation the first time, never to start-up again. The ringing can be observed in either or both of the following conditions: * The very first HVMOSFET turn-off event during a cold start of the converter (VGG > VDD). * HVMOSFET turn-off edge under steady state, where the converter switches the HVMOSFET at the programmed IDRV,PK level (VDD > VGG). 28 Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Avoid HF Ringing High frequency ringing problems with cascode MOSFET drives can often be avoided. Many converters will not have this problem because they use an HVMOSFET with a large Vth, large RDS(on), low transconductance gain, or operate at low current. Ringing problems can also be avoided by minimizing stray inductance. The trace between the HVMOSFET source and the DRV pin must be kept very short, less than 1 cm. Do not add current probe loops to the source lead of the HVMOSFET. Do not place ferrite beads on the source lead of the HVMOSFET. If ringing cannot be avoided, the most efficient and effective methods to solve ringing during switching transients are: 1. A ferrite chip or bead connected to the gate of the HVMOSFET, 2. A small capacitor connected from DRV to GND and 3. A gate turn-off resistor. These three techniques can be used separately or combined, as shown in Figure 35. Bulk Voltage Primary Bulk Voltage DG VGG Bulk Voltage DG RG-ON UCC28610 Primary DG RG-ON Ferrite chip or bead DRV Primary UCC28610 RG-OFF RG-ON UCC28610 VGG VGG DRV DRV CDRV GND GND (a) GND (b) (c) Figure 35. High Frequency Ringing Solutions, (a) ferrite chip, (b) CDRV and (c) RG-OFF Copyright (c) 2009-2011, Texas Instruments Incorporated 29 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Ferrite Chip or Bead Solution The ferrite chip or bead connected to the gate of the HVMOSFET provides the best result because it suppresses ringing in the gate, source, and drain circuits of the HVMOSFET with minimal added losses. Select the ferrite chip for its resistance value in the ringing frequency range (for example, 60 at 100 MHz). The peak current rating of the ferrite chip or bead must be sufficient for the drain - gate discharge current that occurs during the turn-off transient. Excessively large bead reactance can result in low frequency surges of VGG at peak load. Normally, good results can be achieved with a 0603 ferrite chip device. DRV Capacitor Solution A capacitor between DRV and GND can reduce ringing on VGG. Select the DRV capacitor experimentally by observing the effect on the VGG pin during the first turn-off edge and during the turn-off edge at full load operation. The capacitor should be less than 3.3 nF so that it does not significantly reduce efficiency. Use a capacitor with a low Q, such as one with Y5V dielectric. This technique will not completely damp the ringing yet it can provide sufficient protection against stray inductance between the source of the HVMOSFET and the DRV pin. Gate Turn-Off Resistor Solution A gate turn-off resistor in the range 0 < RG-OFF < 5 can damp ringing. The turn-off resistance is limited in order to prevent the stray source inductance of the HVMOSFET from over charging VGG through the body diode of the HS Drive MOSFET, in addition to any peak current error problems that would be caused by additional delay. The damping effect of the gate resistor works better in applications with low current and small source inductance. A much larger resistance can be tolerated during the HVMOSFET turn-on transition due to DCM operation. The recommended turn-on resistance range is 0 <RG-ON < 200 in order to prevent the turn-on delay from interfering with valley switching. Thermal Shutdown The UCC28610 protects itself from overheating with an internal thermal shutdown circuit. If the junction temperature exceeds the thermal shutdown point, TSD, the UCC28610 initiates a shutdown event and permits retry after the retry time, tRETRY. Shutdown/Retry cycles continue if the junction temperature is not less than TSD minus TSD_HYST. 30 Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Typical Schematic and Layout It is possible to design a power supply on a single layer board using the UCC28610. Figure 36 and Figure 37 show an example of a typical layout and design, respectively. Proper use of ground planes can solve EMI and thermal problems. For best results, create a quiet ground plane for the components associated with pins 1 through 4. This offers shielding for the control signals. Also, do not extend the ground plane under heat sinks, thermistors or snubbers so that these components do not heat the UCC28610. Figure 36. Typical Layout of the Device on a Single Layer PCB NOTE The reference designators correspond to the components shown in the schematic of Figure 37. Copyright (c) 2009-2011, Texas Instruments Incorporated 31 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 + + + + www.ti.com Figure 37. Typical Design Schematic 32 Copyright (c) 2009-2011, Texas Instruments Incorporated UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Terminal Components For reference designators refer to Figure 1. Table 1. Terminal Components NAME TERMINAL DESCRIPTION R CL = 33.2k W CL IDRV(PK) = 3 K P LM PIN 100 kV RCL Where KP = 0.54W/ H LM is the minimum value of the primary inductance PIN = POUT/ = efficiency Q1, power MOSFET with adequate voltage and current ratings, VVGS must have at least 20-V static rating. DRV 6 FB 1 RFB = 100 k GND 7 Bypass capacitor to VDD, CBP = 0.1-F, ceramic D1, Schottky diode, rated for at least 30 V, placed between DRV and VDD For latch-off response to overcurrent faults: tMOT = user programmable maximum on-time after 250-ms delay. Wo ae R MOT = t MOT c 1 1011 s /o e MOT 4 where * 150 k RMOT 500 k For shutdown-retry response to overcurrent faults: Wo ae RMOT = tMOT c 2 1010 / so e * 25 k RMOT 100 k and tMOT 5 s CVDD = IVDD(GM) tBURST DVDD(BURST ) where: VDD(BURST) is the allowed VDD ripple during burst operation tBURST is the estimated burst period, VDD 8 The typical CVDD value is approximately 47 F DBIAS must have a voltage rating greater than: VDBIAS VOUT NPS VBULK (max ) + NPB NPB where: VDBIAS is the reverse voltage rating of diode D2 VBULK(max) is the maximum rectified voltage of CBULK at the highest line voltage minimize the length of the CVGG connection to GND VGG 5 CVGG = at least 10x CGS of HVMOSFET, usually CVGG = 0.1 F. Copyright (c) 2009-2011, Texas Instruments Incorporated 33 UCC28610 SLUS888E - JANUARY 2009 - REVISED JULY 2011 www.ti.com Table 1. Terminal Components (continued) NAME TERMINAL DESCRIPTION R ZCD1 = R ZCD2 = ZCD 2 VOUT + VF NPS 100 m A NPB ZCD(ovp) R ZCD1 ae NPS c VOUT(pk) x NPB e o / -ZCD(ovp) o where: ZCD(ovp) is the overvoltage fault threshold at ZCD NPS is the primary to secondary turns ratio NPB is the primary to bias turns ratio VOUT is the average output voltage of the secondary VF is the forward bias voltage of the secondary rectifier VOUT,PEAK is the desired output overvoltage fault level Note 1. Refer to the Electrical Characteristics table for all constants and measured values, unless otherwise noted. Note 2. Refer to Figure 1 for all component locations in the Table 1. Revision History Changes from Revision C (January, 2009) to Revision D * 34 Page Deleted Equation 2 ............................................................................................................................................................. 14 Copyright (c) 2009-2011, Texas Instruments Incorporated PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC28610DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC28610DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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