TTL HD74/HD74S Series MPERFORMANCE (per gate) MMAIN CHARACTERISTICS (Ta=20~-+ 75C) Performance HDTA Series |HDT4S Series Series | HD?4 Series LL HDTMS Series _ Den Te 10-ns tons Parameter min. max. min. man - : Vortfo. max} 4 I 0.5 Diosination 10mW 20 mi Vowifor= 400A) 24v aw fo Seed-Power | Vii o.8 0.a Peet _ 100 pl Spd Viv | av - ay OO i: = lfm) | 2m A Fa(iw min) - ea OHA WM SELECTION GUIDE #NAND,NOR/AND/OR GATES Fouaction HO?d4Series HUMS Series Quad. 2-input Positive NANT Gates wo i - Quad, 2-input Positive NAND Gates (with Open Collector Gutput} i Quad, Peinput Positive WOR Cates oe fiz Quad. Positive SAND Gates (with Open Collector Qutpot! Ob tg = Hex Inverters 04 oM- Hex Inverters (with Open Collockor Output) | 05 = ih -- Hex Jnverter Buffers,/Drivers (with Open Collector High-volenge Chvipot) 0b = Hex Buffers,Drivers iwith Open Coblector High-valiage Ontput ! or . Quad. 2-input Positive AND Gates Oe _ fluad. 2-input Positive AND Gates (with Opes Collector Output } og _| = Triple 3-ingut Positive NAND Gates sstsi<iSsS 10 i I . Triple 3-input Positive ANT) Gates - | il Triple 3-input Positive NAKED Gates iwith Open Collector Output) | 1? = 12 = Dual 4-inpat Schmitt NAND Gates | 13 < Hex Sehmitt-trigger Inverters 14 - Triple a-input Positive AND Gates (with Open Collector Qutput) - 18 Hex Inverter Bulfers/Drivers (with Open Collector High-voliage Output) | 16 Hex Buffers/Drivers (with Open Collector High-voltage Qutput | 1? - Dual 4-inpat Positive NAND Gates 20 20 - Daal 4-inpat Positive RAND Gates (with Open Collector Output} ao | ane Expandable Dual 4-input Positive NOR Gates (with Strobe} | 230 | - Dual 4-input Positive NOR Gates | 257 - Quad. 2-ingut High-voltage Interface RAND Gates 26 =_ Triple 3-input Positive NOR Gates 27 | d-input Positive NAND Gate ee | wn | - Quad. 2-input Positive OR Gates qa ~ - Quad, 2-input Positive MAND Buffers on Cjuad. 2-inpul Positive MAND Buffers (with Opea Collector Output | Ag Cual 4-input Positive NAND Buffers 4a" aa Quad. Bus Buffer Gates with I-state Output ([nverting| Wh - - ~ Ghuaad, Bus Buffer Gates with d-state Chutpat (Noninverting) a 14 , = - Chad. 2-input Pouitive MAND Schmitt Triggers Miz - 13-inpat Positive NAN Gate - i 12-input Positive NAND Gate (with J-state Oot.) 1H Dual 4-ioput Poastive WAND Line Drivers i = 14 . 268 @ HITACHI (to be continued | TTL HD74/74S Series @#AND-OR-INVERT GATES Fumetion HOW4 Series HDMS Series Expandable Dual 2-wide 2-input AND-OR-INVERT Gates | Dwal Z-wide 2-input AND-OR-INVERT Gates Sl - Expandable 4-wide 2-input AND-OR-[NVERT Gate 53 _ d-wide 2-input AND-OR-INVERT Gate 54 _ 4-2-3-2-input AND-OR-INVERT Gate Me d-2-3-2-input AND-QR-INVERT Gate (with Open Collector Output) _ $5" # EXPANDER Function HOT4 Series HOM4S Series Dual 4-input Expanders atk =" | _ @FLIP FLOPS Furmttion Hit Series HDS Series J-K Master-Flip Flop (AND Unputs) 7 Dual J-K Flip Flops ' id - Dual D-type Edge-triggered Flip Flops 4 74 Dual J-K Flip Flops (with PR and CLR) 76 Dual J-K Flip Flops | 107 = Dual J-K Negutive-edgestriggered Flip Flops (with PR and CLR) | _ Zz -- Lusl J-K Negative-edge-triggered Flip Flops (with PR) - Ws. Thal J-K Negative-edge-triggered Flip Flops (with PR, Common CLR, and Common OK) | _ | lid Monostable Multivibrator CC . 1 = - Twal Retriggerable Monostable Multivibrators jag - Hex D-type Flip Flops fwith CLE! v4 Wa Quad. D-type Flip Flops {with CLR] 175 17h. * Dual Monostable Multivibrators (with Schmitt Trigger! gel i COUNTERS Function HIW4 Series HDTM4S Series Decade Counter 50 = _ Diividesby-Twelve Counter q24 - 4-bit Binary Counter oA Presettable Decade Counter, Latch | L76 | = 4-bit Binary Counter/Latch iW7 Syochronows Decade Counter _ i f 1D = Syachronous 4-bit Binary Counter 161 i - Fully Synchronous Decade Counter bz | _ Fully Synchronous 4-bit Binary Counter 163 - Synchromus Decade Decimal Hate Multiplier 16F Synchronous Decade Up/Down Counter 190 - Synchronous 4-bit Binary Up/Down (Counter TT 191 a Srichronous Perake Up/Down Counter 192 | - Srachronous 4-bit Binary Up/Down Counter | wa Decade Counter 2a" | - 4-bit Binary Counter 23 _ @ HITACHI io be continsed | 269 TTL HD74/74S Series 04-BliT, 5-BIT SHIFT/STORAGE REGISTERS Function HOT Series HOTMS Series d-bit Right-shift, Left-shilt Register a _ 5-bit Shift Register {Dual Parallel-in, Parallel-out } 96 =_ 4-bit D-tvpe Register (with d-state Output! 173 4-bit Parallel-in, Parallel-out Bidirectional Shift Register 194.7 = d-bit Fsrallel-in, Parallel-got Shift Register (J-K [opuis For First Stage | 195 =" #&-B/T SHIFT REGISTERS Function HDT4 Series | HDS Series B-bit Shift Register | 1A - A-bit Parallel-out Shift Register | el | Parallel-load -bit Shift Register lh | _ B=bit Parallel=in, Parallel-out Bidirectional Shift Register | 198 | B-bit Farallelin, Parallel-our Shift Register | J-K Inputs for First Stage) | 1a #ENCODERS Funetion 10-line-to-d-line Priocity Encoder 8-line-te-3-Lline Priority Eneoder HDT Series hav 148 HDMS Series # DECODERS,DEMULTIPLEXERS Functian Fa D-to- Cecioal Decoder Exeess 3-te-Deeimal Decoder Excess S-Oray-te-Decinal Uecoder 4-line-to-16-line Decoder Demultiplexer Dwal 2-line-to-d-line Decodere,Demultiphexers Dual 2-line-te-d-line Decoders; Demultipleners (with Open Callector Chutput.} 4-line-to-16-line Decoder Demultiplexer (with Open Collector Output | HDO?4 Series 42A 0 77 434 4A 154 -* 155 156 154 = HDMS Series #DECODERS/LAMP DRIVERS/BUFFERS Function HD?4 Series. HOMS Series AtCDeio-Decimal Decoder! Driver. with SV Out, 1 45 BCH-io-Decimal Decoder/Driver (with 15) Out, | 145 _ BCO-to-Seven Segment Decoders Driver (with MV Output) 464 BCD-te-Seven Segment Decoder, Driver (with SV Outport] 4A Bl O-to-Decimal Decoder/Driver iwith BOY Out. ! 141 ~ I = *#LATCHES Function HD? Series HORMS Series Quad, Bistable Latches Th ro _ Quad. 5-K Latches arg RANDOM ACCESS MEMORIES (less than 256-bit} Peet tia HD4 Series. HWS Series 64-bit Random Acvess Memory (165 by db} a 270 @ HITACHI fte be continwed | TTL HD74/74S Series @ ARITHMETIC ELEMENTS Function HD74 Series HD74S Series 4-bit Binary Full Adder 83A 4-bit Magnitude Comparator 85 Quad. 2-input Exclusive-OR Gates 86-7 86 o Quad. Exclusive-OR/NOR Gates _ 135 | Quad. 2-input Exelusive-OR Gates (with Open Collector Output ) 136 _ 8-bit Odd/Even Parity Generator/Checker 180 -~ _ 4-bit Arithmetic Logic Unit/Function Generator _ 181 Look-Ahead Carry Generator (for ALU) 182 182 Dual Carry Save Full Adders H183 ~~~ _ 9-bit Odd/Even Parity Generator/Checker _ 280 ~~ 4-bit Binary Full Adder (with Fast Carry) 283 - _ @DATA SELECTORS/MULTIPLEXERS Function HD74 Series HD74S Series 16-bit Data Selector/Multiplexer 150 --7 _ 8-bit Data Selector/Multiplexer (with Strobe) 15tA- ~- 151 8-bit Data Selector/Multipl exer _ _ Dual 4-line-to-1l-line Data Seleetors/Multiplexers 153 - _ Quad. 2-line-to-1-line Data Selectors/Multiplexers 157 157 2 - Quad. 2-line-to-1-line Data Selectors/Multiplexers _ 158 _~ 8-bit Data Selector/Multiplexer (with Stobe and 3-state Output ) 251-7 251 --- Quad. 2-line-to-1-line Data Selectors/Multiplexers (with 3-state Output ) _ 257 / Quad. 2-line-to-l-line Data Selectors/Multiplexers (with 3-state Output ) _ 258 OUTLINE DP-20 DP-24 @ HITACHI 27)