CY7C185D - Cypress Semiconductor

PRELIMINARY

64K (8K x 8) St atic RAM

CY7C185D

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-05466 Rev. *C Revised January 10, 2005

Features

• Pin- and function-compatible with CY7C185

•High speed

—t

AA = 10 ns

• Low active pow er

—I

CC = 60 mA @ 10 ns

• Low CMOS standby power

—I

SB2 = 3 mA

• CMOS for optimum speed/po we r

• Data Retention at 2.0V

• Easy memory expansion with CE1, CE2, and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• Available in Lead (Pb)-Free Packages

Functional Description[1]

The CY7C185D is a high-performance CMOS static RAM

organized as 8192 words by 8 bits. Easy memory expansion

is provided by an active LOW chip enable (CE1), an active

HIGH chip enable (CE2), and active LOW output enable (OE)

and three-state drivers. This device has an automatic

power-down feature (CE1 or CE2), reducing the power

consumption when deselected.

An active LOW write enable signal (WE) controls the

writing/reading operation of the memory. When CE 1 and WE

inputs are both LOW and CE2 is HIGH, data on the eight data

input/output pins (I/O0 through I/O7) is written into the memory

location addressed by the address present on the address

pins (A0 through A12). Reading the device is accomplished by

selecting the device and enabling the outputs, CE1 and OE

active LOW, CE2 active HIGH, while WE remains inactive or

HIGH. Under these conditions, the contents of the location

addressed by the informatio n on address p ins are pr esent on

the eight data input/output pins.

The input/output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and write enable

(WE) is HIGH.The CY7C185D is in a standard 28-pin

300-mil-wide DIP, SOJ, or SOIC Pb-Free package.

Note:

1. For guidelines on SRAM system design, please re fer to the ‘System Design Guidelines’ Cypress application note, a vailable on t he internet at www .cypress.com.

Logic Block Diagram Pin Configurations

I/O

VCC

CE2

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

A10

A11

A12

I/O0

I/O1

I/O2

GND

256 x 32 x 8

ARRAY

INPUT BU FFER

COLUMN DECODER

ROW DECODER

SENSE AMPS

POWER

DOWN

I/O

Top View

DIP/SOJ/SOIC

PRELIMINARY CY7C185D

Document #: 38-05466 Rev. *C Page 2 of 10

Selection Guide

CY7C185D-10 CY7C185D-12 CY7C185D-15 Unit

Maximum Access T i me 10 12 15 ns

Maximum Operating Current 60 50 40 mA

Maximum Standby Current 3 3 3 mA

PRELIMINARY CY7C185D

Document #: 38-05466 Rev. *C Page 3 of 10

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .............................. ...–65°C to +150°C

Ambient Temperature with

Power Applied........... ... ............................ ...–55°C to +125°C

Supply Voltage to Ground Potential...............–0.5V to +7.0V

DC Voltage Appli ed to Outputs

in High-Z S tate[2] ....................................... −0.5V to VCC + 0.5V

DC Input Voltage[2].................................... −0.5V to VCC + 0.5V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current............... ... ... ............................... > 200 mA

Operating Range

Range Ambient Temperature VCC

Commercial 0°C to +70°C 5V ± 10%

Industrial –40°C to +85°C 5V ± 10%

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

7C185D-10 7C185D-12

UnitMin. Max. Min. Max.

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V

VIH Input HIGH Voltage 2.0 VCC + 0.3V 2.0 VCC + 0. 3V V

VIL Input LOW Voltage[2] –0.5 0.8 –0.5 0.8 V

IIX Input Load Current GND ≤ VI ≤ VCC –1 +1 –1 +1 µA

IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled –1 +1 –1 +1 µA

IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND –300 –300 mA

ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA 60 50 mA

ISB1 Automatic Power-down Current Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL

Min. Duty Cycle = 100% 10 10 mA

ISB2 Automatic Power-down Current Max. VCC, CE1 ≥ VCC – 0.3V,

or CE2 ≤ 0.3V

VIN ≥ VCC – 0.3V or VIN ≤ 0.3V

3.0 3.0 mA

Parameter Description Test Con ditions

7C185D-15

UnitMin. Max.

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V

VIH Input HIGH Voltage 2.0 VCC + 0.3V V

VIL Input LOW Voltage[2] –0.5 0.8 V

IIX Input Load Current GND ≤ VI ≤ VCC –1 +1 µA

IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled –1 +1 µA

IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND –300 mA

ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA 40 mA

ISB1 Automatic Power-down Current Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL

Min. Duty Cycle = 100% 10 mA

ISB2 Automatic Power-down Current Max. VCC, CE1 ≥ VCC – 0.3V or CE2 ≤ 0.3V

VIN ≥ VCC – 0.3V or VIN ≤ 0.3V 3.0 mA

Capacitance[4]

Parameter Description Tes t Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 5.0V 7pF

COUT Output Capacitance 7 pF

Notes:

2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less th an 20 ns.

3. Not more than 1 output sh ould be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

4. Tested initially and after any design or process changes that may affect these parameters.

PRELIMINARY CY7C185D

Document #: 38-05466 Rev. *C Page 4 of 10

Thermal Resistance[4]

Parameter Description Test Conditions All-Packages Unit

ΘJA Thermal Resistance

(Junction to Ambient)[4] Still Air, soldered on a 3 × 4.5 inch, two-layer

printed circuit board TBD °C/W

ΘJC Thermal Resistance

(Junction to Case)[4] TBD °C/W

AC Test Loads and Waveforms

Switching Characteristics Over the Operating Range [6]

Parameter Description

7C185D-10 7C185D-12 7C185D-15

UnitMin. Max. Min. Max. Min. Max.

Read Cycle

tpower[5] VCC(typical) to the first access 100 100 100 µs

tRC Read Cycle Time 10 12 15 ns

tAA Address to Data Valid 10 12 15 ns

tOHA Data Hold from Address Change 3 3 3 ns

tACE1 CE1 LOW to Data Valid 10 12 15 ns

tACE2 CE2 HIGH to Data Valid 10 12 15 ns

tDOE OE LOW to Data Valid 5 6 8 ns

tLZOE OE LOW to Low Z 3 3 3 ns

tHZOE OE HIGH to High Z[7] 567ns

tLZCE1 CE1 LOW to Low Z[8] 333ns

tLZCE2 CE2 HIGH to Low Z 3 3 3 ns

tHZCE CE1 HIGH to High Z[7, 8]

CE2 LOW to High Z 567ns

tPU CE1 LOW to Power-Up

CE2 to HIGH to Power-Up 000ns

tPD CE1 HIGH to Power-Down

CE2 LOW to Power-Dow n 10 12 15 ns

Notes:

5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.

6. Test conditions assume signal transition time of 3 ns or less, timing ref erence levels of 1.5 V, input pulse levels of 0 to 3. 0V, and output loading of the specified

IOL/IOH and 30-pF load capacita nce.

7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady state voltage.

8. At any given temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device.

R1 481Ω

3.0V

OUTPUT

R1 481Ω

255Ω

30 pF

GND 90% 90%

10%

≤3ns ≤3ns

OUTPUT

255Ω

5pF

(b) (c)

OUTPUT 1.73V INCLUDING

JIG AND

SCOPE

INCLUDING

JIGAND

SCOPE

10%

Equivalent to: THÉVENIN EQUIVALENT

ALL INPUT PULSES

167Ω

* CAPACITIVE LOAD CONSISTS

OF ALL COMPONENTS OF THE

TEST ENVIRONMENT

30 pF*

OUTPUT Z = 50Ω

50Ω

1.5V

(a)

10-ns Device

12, 15-ns Devices High-Z characteristics:

PRELIMINARY CY7C185D

Document #: 38-05466 Rev. *C Page 5 of 10

Write Cycle[9]

tWC Write Cycle Time 10 12 15 ns

tSCE1 CE1 LOW to Write End 8 10 12 ns

tSCE2 CE2 HIGH to Write End 8 10 12 ns

tAW Address Set-up to Write End 7 10 12 ns

tHA Address Hold from Write End 0 0 0 ns

tSA Address Set-up to Write Start 0 0 0 ns

tPWE WE Pulse Width 7 10 12 ns

tSD Data Set-up to Write End 6 7 8 ns

tHD Data Hold from Write End 0 0 0 ns

tHZWE WE LOW to High Z[7] 667ns

tLZWE WE HIGH to Low Z 3 3 3 ns

Switching Characteristics Over the Operating Range (continued)[6]

Parameter Description

7C185D-10 7C185D-12 7C185D-15

UnitMin. Max. Min. Max. Min. Max.

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min. Max. Unit

VDR VCC for Data Retention 2.0 V

ICCDR Data Retention Current Non-L, Com’l / Ind’l VCC = VDR = 2.0V,

CE > VCC – 0.3V,

VIN > VCC – 0.3V or

VIN < 0.3V

3mA

L-Version Only 1.2 mA

tCDR [4] Chip Deselect to Data Retention Time 0 ns

tR[10] Operatio n Recovery Time tRC ns

Data Retention Waveform

Switching Waveforms

Read Cycle No.1[11,12]

Notes:

9. The internal write time of t he memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either

signal can terminate a write by going HIGH. The dat a inpu t set- up and hold ti ming should be ref erenced to the risi ng edge of the si gnal that terminates the write.

10.Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs.

11.Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.

12.WE is HIGH for read cycle.

4.5V4.5V

tCDR

VDR > 2V

DATA RETENTION MODE

VCC

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

PRELIMINARY CY7C185D

Document #: 38-05466 Rev. *C Page 6 of 10

Read Cycle No.2[13,14]

Write Cycle No. 1 (WE Controlled)[12,14]

Write Cycle No. 2 (CE Controlled)[14,15,16]

Notes:

13.Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL.

14.The internal write time of the memory is defi ned by the overlap of CE1 LOW, CE 2 HIGH and WE LOW . CE1 and WE must be LOW and CE2 must be HIGH to

initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the rising

edge of the signal that termin ates the write.

15.During this period, the I/Os are in the output state and input signals should not be applied.

16.The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

Switching Waveforms (continued)

50%

DATA VALID

ACE

DOE

LZOE

LZCE

HIGH IMPEDANCE IMPEDANCE

ICC

ISB

HZOE

HZCE

HIGH

DATA OUT

SUPPLY

CURRENT

PWE

HZOE

DATA

VALID

DATA I/O

SCEI

SCE2

ADDRESS

NOTE 15

SCE1

DATA I/O

ADDRESS

DATA

VALID

SCE2

PRELIMINARY CY7C185D

Document #: 38-05466 Rev. *C Page 7 of 10

Write Cycle No. 3 (WE Controlled, OE LOW)[14,15,16,17]

Truth Table

CE1CE2WE OE Input/Output Mode

H X X X High Z Deselect/Power-down

X L X X High Z Deselect/Power-down

L H H L Data Out Read

L H L X Data In Write

L H H H High Z Deselect

Ordering Information

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

10 CY7C185D-10PXC P21 28-Lead (300-Mil) Molded DIP (Pb-Free) Commercial

CY7C185D-10SXC S21 28 -Lead Molded SOIC (Pb-Free)

CY7C185D-10VXC V21 28 -Lead Molded SOJ (Pb-Free)

CY7C185D-10VXI V21 28-Lead Molded SOJ (Pb-Free) Industrial

12 CY7C185D-12PXC P21 28-Lead (300-Mil) Molded DIP (Pb-Free) Commercial

CY7C185D-12SXC S21 28 -Lead Molded SOIC (Pb-Free)

CY7C185D-12VXC V21 28 -Lead Molded SOJ (Pb-Free)

CY7C185D-12VXI V21 28-Lead Molded SOJ (Pb-Free) Industrial

15 CY7C185D-15PXC P21 28-Lead (300-Mil) Molded DIP (Pb-Free) Commercial

CY7C185D-15SXC S21 28 -Lead Molded SOIC (Pb-Free)

CY7C185D-15VXC V21 28 -Lead Molded SOJ (Pb-Free)

CY7C185D-15VXI V21 28-Lead Molded SOJ (Pb-Free) Industrial

Shaded areas conta i n advance information. Please contact your local Cypress sales representative for availability of these p arts.

Note:

17.If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.

Switching Waveforms (continued)

tHD

tSD

tLZWE

tSA

tHA

tAW

tWC

tHZWE

DATA IN VALID

tSCE1

tSCE2

CE1

CE2

ADDRESS

DATA I/O

NOTE 15

PRELIMINARY CY7C185D

Document #: 38-05466 Rev. *C Page 8 of 10

Package Diagrams

DIMENSIONS IN INCHES [MM] MIN.

MAX.

SEATING PLANE

0.260[6.60]

0.295[7.49]

0.090[2.28]

0.110[2.79]

0.055[1.39]

0.065[1.65]

0.015[0.38]

0.020[0.50]

0.015[0.38]

0.060[1.52]

0.120[3.05]

0.140[3.55]

0.009[0.23]

0.012[0.30]

0.310[7.87]

0.385[9.78]

0.290[7.36]

0.325[8.25]

0.030[0.76]

0.080[2.03]

0.115[2.92]

0.160[4.06]

0.140[3.55]

0.190[4.82]

1.345[34.16]

1.385[35.18]

3° MIN.

114

15 28

REFERENCE JEDEC MO-095

LEAD END OPTION

SEE LEAD END OPTION

(LEAD #1, 14, 15 & 28)

PACKAGE WEIGHT: 2.15 gms

28-Lead (300-Mil) PDIP P21

51-85014-*D

DIMENSIONS IN INCHES[MM] MIN.

MAX.

PIN1ID

0.291[7.39]

0.300[7.62]

0.394[10.01]

0.419[10.64]

0.050[1.27]

TYP.

0.092[2.33]

0.105[2.67]

0.004[0.10]

0.0118[0.30]

SEATING PLANE

0.0091[0.23]

0.0125[3.17]

0.015[0.38]

0.050[1.27]

0.013[0.33]

0.019[0.48]

0.026[0.66]

0.032[0.81]

0.697[17.70]

0.713[18.11]

0.004[0.10]

114

15 28

*REFERENCE JEDEC MO-119

PART #

S28.3 STANDARD PKG.

SZ28.3 LEAD FREE PKG.

PACKAGE WEIGHT 0.85gms

51-85026-*C

28-Lead (300-Mil) Molded SOIC S21

PRELIMINARY CY7C185D

Document #: 38-05466 Rev. *C Page 9 of 10

© Cypress Semi con duct or Cor po rati on , 20 05 . The information con t a in ed he re i n is subject to change wi t hou t notice. Cypress S emi con duct or Corpo ration assu mes no resp onsib ility for the u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furthermore , Cypress does not authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

All product and company names mentioned in this document may be the trademarks of their respective holders.

Package Diagrams (continued)

28-Lead (300-Mil) Molded SOJ V21

51-85031-*B

PRELIMINARY CY7C185D

Document #: 38-05466 Rev. *C Page 10 of 10

Document History Page

Document Title: CY7C185D 64K (8K x 8) Static RAM (Preliminary)

Document Number: 38-05466

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 201560 See ECN SWI Advance Datasheet for C9 IPP

*A 233715 See ECN RKF DC parameters are modified as per EROS (Spec # 01-2165)

Pb-free offering in Ordering Information

*B 262950 See ECN RKF Added Tpower Spec in Switching Characteristics table

Added Data Retention Characteristics table and waveforms

Shaded Ordering Information

*C 307593 See ECN RKF 1) Reduced Speed bins to -10, -12 and -15 ns

2) Added ‘Industrial’ grade parts to the Ordering Info on Page #6