14-Bit, 8-Channel, 250 kSPS PulSAR ADC AD7949-EP Enhanced Product FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Multichannel system monitoring Battery-powered equipment Medical instruments: ECG/EKG Mobile communications: GPS Power line monitoring Data acquisition Seismic data acquisition systems Instrumentation Process control Rev. B 0.5V TO VDD - 0.5V 0.1F 2.3V TO 5.5V 0.5V TO VDD 10F REFIN REF BAND GAP REF VDD AD7949-EP 1.8V VIO TO VDD TEMP SENSOR IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 CNV 14-BIT SAR ADC MUX SPI SERIAL INTERFACE ONE-POLE LPF SCK SDO DIN SEQUENCER COM 09822-001 14-bit resolution with no missing codes 8-channel multiplexer with choice of inputs Unipolar single-ended Differential (GND sense) Pseudobipolar Throughput: 250 kSPS INL/DNL: 0.5/0.25 LSB typical SINAD: 85 dB at 20 kHz THD: -100 dB at 20 kHz Analog input range: 0 V to VREF with VREF up to VDD Multiple reference types Internal selectable 2.5 V or 4.096 V External buffered (up to 4.096 V) External (up to VDD) Internal temperature sensor (TEMP) Channel sequencer, selectable 1-pole filter, busy indicator No pipeline delay, SAR architecture Single-supply 2.3 V to 5.5 V operation with 1.8 V to 5.5 V logic interface Serial interface compatible with SPI, MICROWIRE, QSPI, and DSP Power dissipation 2.9 mW at 2.5 V/200 kSPS 10.8 mW at 5 V/250 kSPS Standby current: 50 nA 20-lead 4 mm x 4 mm LFCSP package Supports defense and aerospace applications (AQEC standard) Military temperature range (-55C to +125C) Controlled manufacturing baseline Enhanced product change notification Qualification data available on request GND Figure 1. GENERAL DESCRIPTION The AD7949-EP is an 8-channel, 14-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) that operates from a single power supply, VDD. The AD7949-EP contains all components for use in a multichannel, low power data acquisition system, including a true 14-bit SAR ADC with no missing codes; an 8-channel, low crosstalk multiplexer that is useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order. The AD7949-EP uses a simple SPI interface for writing to the configuration register and receiving conversion results. The SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput. The AD7949-EP is housed in a tiny 20-lead LFCSP with operation specified from -55C to +125C. Full details about this enhanced product are available in the AD7949 data sheet, which should be consulted in conjunction with this data sheet. Table 1. Multichannel 14-/16-Bit PulSAR(R) ADCs Type 14-Bit 16-Bit 16-Bit Channels 8 4 8 250 kSPS AD7949 AD7682 AD7689 500 kSPS AD7699 ADC Driver ADA4841-1 ADA4841-1 ADA4841-1 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2011-2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7949-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 ESD Caution...................................................................................7 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions..............................8 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................9 Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 12 Specifications..................................................................................... 3 Ordering Guide .......................................................................... 12 Timing Specifications .................................................................. 5 REVISION HISTORY 5/2018--Rev. A to Rev. B Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 5/2015--Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 1 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 4/2011--Revision 0: Initial Version Rev. B | Page 2 of 12 Enhanced Product AD7949-EP SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, VREF = VDD, all specifications -55C to +125C, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current at 25C Input Impedance 1 THROUGHPUT Conversion Rate Full Bandwidth 2 1/4 Bandwidth2 Transient Response ACCURACY No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Gain Error 4 Gain Error Match Gain Error Temperature Drift Offset Error4 Offset Error Match Offset Error Temperature Drift Power Supply Sensitivity AC ACCURACY 5 Dynamic Range Signal-to-Noise SINAD Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk SAMPLING DYNAMICS -3 dB Input Bandwidth Aperture Delay Test Conditions/Comments Min 14 Unipolar mode Bipolar mode Positive input, unipolar and bipolar modes Negative or COM input, unipolar mode Negative or COM input, bipolar mode fIN = 250 kHz Acquisition phase 0 -VREF/2 -0.1 -0.1 VREF/2 - 0.1 VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V Full-scale step, full bandwidth Full-scale step, 1/4 bandwidth 0 0 0 0 14 -1 -1 Typ VREF/2 68 1 Max Unit Bits +VREF +VREF/2 VREF + 0.1 +0.1 VREF/2 + 0.1 V V dB nA 250 200 62.5 50 1.8 14.5 Bits LSB 3 LSB LSB LSB LSB ppm/C LSB LSB ppm/C LSB VDD = 5 V 5% 0.5 0.25 0.1 0.5 0.2 1 0.5 0.2 1 0.2 fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 4.096 V internal REF fIN = 20 kHz, VREF = 2.5 V internal REF fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 5 V, -60 dB input fIN = 20 kHz, VREF = 4.096 V internal REF fIN = 20 kHz, VREF = 2.5 V internal REF fIN = 20 kHz fIN = 20 kHz fIN = 100 kHz on adjacent channel(s) 85.6 85.5 85 84 85 33.5 85 84 -100 108 -125 dB 6 dB dB dB dB dB dB dB dB dB dB 1.7 0.425 2.5 MHz MHz ns REF = VDD = 5 V -5 -1 -1 Full bandwidth 1/4 bandwidth VDD = 5 V Rev. B | Page 3 of 12 84.5 84 +1 +1 kSPS kSPS kSPS kSPS s s +5 +1 +1 AD7949-EP Parameter INTERNAL REFERENCE REF Output Voltage REFIN Output Voltage 7 REF Output Current Temperature Drift Line Regulation Long-Term Drift Turn-On Settling Time EXTERNAL REFERENCE Voltage Range Current Drain TEMPERATURE SENSOR Output Voltage 8 Temperature Sensitivity DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format 9 Pipeline Delay 10 VOL VOH POWER SUPPLIES VDD VIO Standby Current 11, 12 Power Dissipation Energy per Conversion TEMPERATURE RANGE 13 Specified Performance Enhanced Product Test Conditions/Comments Min Typ Max Unit 2.5 V, at 25C 4.096 V, at 25C 2.5 V, at 25C 4.096 V, at 25C 2.490 4.086 2.500 4.096 1.2 2.3 300 10 15 50 5 2.510 4.106 V V V V A ppm/C ppm/V ppm ms VDD + 0.3 VDD - 0.5 50 V V A 283 1 mV mV/C VDD = 5 V 5% 1000 hours CREF = 10 F REF input REFIN input (buffered) 250 kSPS, REF = 5 V 0.5 0.5 At 25C -0.3 0.7 x VIO -1 -1 ISINK = +500 A ISOURCE = -500 A +0.3 x VIO VIO + 0.3 +1 +1 V V A A 0.4 V V 5.5 VDD + 0.3 VDD + 0.3 V V V nA W mW mW mW mW VIO - 0.3 Specified performance Specified performance Operating range VDD and VIO = 5 V, at 25C VDD = 2.5 V, 100 SPS throughput VDD = 2.5 V, 100 kSPS throughput VDD = 2.5 V, 200 kSPS throughput VDD = 5 V, 250 kSPS throughput VDD = 5 V, 250 kSPS throughput with internal reference 2.3 2.3 1.8 50 1.5 1.45 2.9 10.8 13.5 2.0 4.0 12.5 15.5 50 TMIN to TMAX -55 nJ +125 C See the AD7949 data sheet. The bandwidth is set in the configuration register. LSB means least significant bit. With the 5 V input range, one LSB = 305 V. 4 See the AD7949 data sheet. These specifications include full temperature range variation but not the error contribution from the external reference. 5 With VDD = 5 V, unless otherwise noted. 6 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 7 This is the output from the internal band gap. 8 The output voltage is internal and present on a dedicated multiplexer input. 9 Unipolar mode: serial 14-bit straight binary. Bipolar mode: serial 14-bit twos complement. 10 Conversion results available immediately after completed conversion. 11 With all digital inputs forced to VIO or GND as required. 12 During acquisition phase. 13 Contact an Analog Devices, Inc., sales representative for the extended temperature range. 1 2 3 Rev. B | Page 4 of 12 Enhanced Product AD7949-EP TIMING SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications -55C to +125C, unless otherwise noted. Table 3. Parameter 1 Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions Data Write/Read During Conversion CNV Pulse Width SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.8 V CNV Low to SDO D15 MSB Valid VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.8 V CNV High or Last SCK Falling Edge to SDO High Impedance CNV Low to SCK Rising Edge DIN Valid Setup Time from SCK Rising Edge DIN Valid Hold Time from SCK Rising Edge 1 Symbol tCONV tACQ tCYC tDATA tCNVH tSCK tSCKL tSCKH tHSDO tDSDO Min Typ Max 2.2 1.8 4.0 1.0 10 tDSDO + 2 11 11 4 Unit s s s s ns ns ns ns ns 18 23 28 ns ns ns 18 22 25 32 ns ns ns ns ns ns ns tEN tDIS tCLSCK tSDIN tHDIN See Figure 2 and Figure 3 for load conditions. Rev. B | Page 5 of 12 10 5 5 AD7949-EP Enhanced Product VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications -55C to +125C, unless otherwise noted. Table 4. Parameter 1 Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions Data Write/Read During Conversion CNV Pulse Width SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.8 V CNV Low to SDO D15 MSB Valid VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.8 V CNV High or Last SCK Falling Edge to SDO High Impedance CNV Low to SCK Rising Edge DIN Valid Setup Time from SCK Rising Edge DIN Valid Hold Time from SCK Rising Edge Min Max 3.2 1.2 10 tDSDO + 2 12 12 5 Unit s s s s ns ns ns ns ns 24 30 38 48 ns ns ns ns 21 27 35 45 50 ns ns ns ns ns ns ns ns tEN tDIS tCLSCK tSDIN tHDIN 10 5 5 See Figure 2 and Figure 3 for load conditions. 500A IOL 1.4V TO SDO CL 50pF 500A IOH Figure 2. Load Circuit for Digital Interface Timing 70% VIO 30% VIO tDELAY 2V OR VIO - 0.5V1 0.8V OR 0.5V2 2V OR VIO - 0.5V1 0.8V OR 0.5V2 2V IF VIO ABOVE 2.5V, VIO - 0.5V IF VIO BELOW 2.5V. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 3. Voltage Levels for Timing Rev. B | Page 6 of 12 09822-003 tDELAY 1 2 Typ 1.8 5 09822-002 1 Symbol tCONV tACQ tCYC tDATA tCNVH tSCK tSCKL tSCKH tHSDO tDSDO Enhanced Product AD7949-EP ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs INx, COM 1 REF, REFIN Supply Voltages VDD, VIO to GND VIO to VDD DIN, CNV, SCK to GND SDO to GND Storage Temperature Range Junction Temperature JA Thermal Impedance (LFCSP) JC Thermal Impedance (LFCSP) 1 Rating GND - 0.3 V to VDD + 0.3 V or VDD 130 mA GND - 0.3 V to VDD + 0.3 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VIO + 0.3 V -0.3 V to VIO + 0.3 V -65C to +150C 150C 47.6C/W 4.4C/W Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION See the AD7949 data sheet. Rev. B | Page 7 of 12 AD7949-EP Enhanced Product 20 19 18 17 16 VDD IN3 IN2 IN1 IN0 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 AD7949-EP TOP VIEW (Not to Scale) 15 14 13 12 11 VIO SDO SCK DIN CNV NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. 09822-004 IN4 6 IN5 7 IN6 8 IN7 9 COM 10 VDD REF REFIN GND GND Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 20 Mnemonic VDD Type1 P 2 REF AI/O 3 REFIN AI/O 4, 5 6 to 9 10 GND IN4 to IN7 COM P AI AI 11 CNV DI 12 DIN DI 13 SCK DI 14 SDO DO 15 VIO P 16 to 19 21 (EPAD) IN0 to IN3 Exposed Pad (EPAD) AI NC 1 Description Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 F and 100 nF capacitors. When using the internal reference for 2.5 V output, the minimum should be 3.0 V. When using the internal reference for 4.096 V output, the minimum should be 4.5 V. Reference Input/Output. See the AD7949 data sheet. When the internal reference is enabled, this pin produces a selectable system reference = 2.5 V or 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (4.096 V maximum), useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 F capacitor connected as close to REF as possible. See the AD7949 data sheet. Internal Reference Output/Reference Buffer Input. See the AD7949 data sheet. When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 F capacitor. When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered to the REF pin as described above. Power Supply Ground. Channel 4 through Channel 7 Analog Inputs. Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of 0 V or VREF/2 V. Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held high, the busy indictor is enabled. Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion. Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion. Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Channel 0 through Channel 3 Analog Inputs. The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power. Rev. B | Page 8 of 12 Enhanced Product AD7949-EP TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.5 0.5 DNL (LSB) 0 -0.5 0 4,096 8,192 12,288 16,384 CODES -1.0 259,473 250k 200k 200k 16,384 150k 150k 100k 100k 50k 50k 0 0 0 1 0 0 0 0 1FFC 1FFD 1FFE 1FFF 2000 2001 2002 2003 0 0 09822-006 VREF = VDD = 2.5V 0 0 955 1FFC 1FFD 1FFE 1FFF 2000 693 0 0 0 2001 2002 2003 2004 CODE IN HEX Figure 6. Histogram of a DC Input at Code Center 09822-009 COUNTS 250k CODE IN HEX Figure 9. Histogram of a DC Input at Code Center 0 0 VREF = VDD = 5V fS= 250kSPS fIN = 19.9kHz SNR = 85.3dB SINAD = 85.2dB THD = -100dB SFDR = 103dB SECOND HARMONIC = -110dB THIRD HARMONIC = -103dB -40 -60 VREF = VDD = 2.5V fs= 200kSPS fIN = 19.9kHz SNR = 84.2dB SINAD = 82.4dB THD = -84dB SFDR = 85dB SECOND HARMONIC = -100dB THIRD HARMONIC = -85dB -20 AMPLITUDE (dB of Full-Scale) -20 -80 -100 -120 -140 -40 -60 -80 -100 -120 -140 -160 0 25 50 75 100 FREQUENCY (kHz) 125 09822-007 AMPLITUDE (dB of Full-Scale) 12,288 300k VREF = VDD = 5V 261,120 -160 8,192 Figure 8. Differential Nonlinearity vs. Code, VREF = VDD = 5 V 300k 0 4,096 CODES Figure 5. Integral Nonlinearity vs. Code, VREF = VDD = 5 V COUNTS 0 09822-008 -0.5 09822-005 -1.0 0 Figure 7. 20 kHz FFT, VREF = VDD = 5 V -180 0 25 50 75 FREQUENCY (kHz) Figure 10. 20 kHz FFT, VREF = VDD = 2.5 V Rev. B | Page 9 of 12 100 09822-010 INL (LSB) VDD = 2.5 V to 5.5 V, VREF = 2.5 V to 5 V, VIO = 2.3 V to VDD, unless otherwise noted. Enhanced Product 90 90 85 85 80 80 SINAD (dB) 75 75 70 70 50 100 150 200 FREQUENCY (kHz) 60 0 50 100 150 200 FREQUENCY (kHz) Figure 11. SNR vs. Frequency Figure 14. SINAD vs. Frequency 88 15.5 SNR SINAD ENOB 86 82 14.0 SFDR (dB) 14.5 ENOB (Bits) 15.0 84 130 -60 125 -65 120 -70 115 -75 110 -80 SFDR 105 -85 100 -90 95 -95 THD 90 -100 85 80 -105 13.5 78 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 80 -110 75 -115 70 1.0 09822-012 13.0 1.5 REFERENCE VOLTAGE (V) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -120 5.5 5.0 REFERENCE VOLTAGE (V) Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage Figure 15. SFDR and THD vs. Reference Voltage 90 -90 fIN = 20kHz fIN = 20kHz VDD = VREF = 5V 85 -95 VDD = VREF = 2.5V VDD = VREF = 5V THD (dB) 80 75 VDD = VREF = 2.5V -100 70 -105 60 -55 -35 -15 5 25 45 65 85 TEMPERATURE (C) 105 125 -110 -55 -35 -15 5 25 45 65 TEMPERATURE (C) Figure 13. SNR vs. Temperature Figure 16. THD vs. Temperature Rev. B | Page 10 of 12 85 105 125 09822-016 65 09822-013 SNR (dB) SNR, SINAD (dB) = 5V, -0.5dB = 5V, -10dB = 2.5V, -0.5dB = 2.5V, -10dB 09822-014 65 60 0 VDD = VREF VDD = VREF VDD = VREF VDD = VREF THD (dB) 65 = 5V, -0.5dB = 5V, -10dB = 2.5V, -0.5dB = 2.5V, -10dB 09822-011 VDD = VREF VDD = VREF VDD = VREF VDD = VREF 09822-015 SNR (dB) AD7949-EP Enhanced Product AD7949-EP 2750 VDD CURRENT (A) 2250 THD (dB) -80 -90 -100 = 5V, -0.5dB = 2.5V, -0.5dB = 2.5V, -10dB = 5V, -10dB -120 0 50 100 150 200 FREQUENCY (kHz) 80 70 60 1500 50 1250 40 1000 30 750 2.5 3.0 3.5 4.0 4.5 20 5.5 5.0 VDD SUPPLY (V) Figure 17. THD vs. Frequency Figure 20. Operating Currents vs. Supply 90 89 90 1750 09822-017 VDD = VREF VDD = VREF VDD = VREF VDD = VREF -110 2000 fS = 200kSPS VIO CURRENT (A) 2500 -70 100 2.5V INTERNAL REF 4.096V INTERNAL REF INTERNAL BUFFER, TEMP ON INTERNAL BUFFER, TEMP OFF EXTERNAL REF, TEMP ON EXTERNAL REF, TEMP OFF VIO 09822-020 -60 180 3000 fIN = 20kHz fS = 200kSPS 160 2750 88 85 84 VDD = VREF = 2.5V 83 82 VDD = 5V, INTERNAL 4.096V REF 120 2250 100 2000 VDD = 5V, EXTERNAL REF 80 1750 1500 81 80 60 VIO VDD = 2.5, EXTERNAL REF VIO CURRENT (A) VDD CURRENT (A) VDD = VREF = 5V 86 SNR (dB) 140 2500 87 40 1250 -4 -6 -8 0 -2 INPUT LEVEL (dB) Figure 18. SNR vs. Input Level 0 UNIPOLAR ZERO UNIPOLAR GAIN BIPOLAR ZERO BIPOLAR GAIN -35 -15 5 25 45 65 85 105 TEMPERATURE (C) 125 09822-019 OFFSET ERROR AND GAIN ERROR (LSB) 1 -2 -55 -35 -15 5 25 45 65 85 105 TEMPERATURE (C) Figure 21. Operating Currents vs. Temperature 2 -1 1000 -55 Figure 19. Offset and Gain Errors vs. Temperature Rev. B | Page 11 of 12 20 125 09822-021 78 -10 09822-018 79 AD7949-EP Enhanced Product OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.20 16 0.50 BSC PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 20 1 15 2.65 2.50 SQ 2.35 EXPOSED PAD 5 11 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-003578 SEATING PLANE 0.50 0.40 0.30 10 6 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-11. 10-12-2017-C PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 22. 20-Lead Lead Frame Chip Scale Package (LFCSP) 4 mm x 4 mm Body and 0.75 mm Package Height (CP-20-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7949SCPZ-EP-RL7 AD7949SCPZ-EP-R2 1 Temperature Range -55C to +125C -55C to +125C Package Description 20-Lead LFCSP, 7" Tape and Reel 20-Lead LFCSP, 7" Tape and Reel Z = RoHS Compliant Part. (c)2011-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09822-0-5/18(B) Rev. B | Page 12 of 12 Package Option CP-20-10 CP-20-10 Ordering Quantity 1,500 1,500