7-876
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4043BMS
CD4044BMS
CMOS Quad 3 State R/S Latches
Pinout
CD4043BMS
TOP VIEW
CD4044BMS
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q4
Q1
R1
S1
ENABLE
S2
VSS
R2
VDD
S4
NC
S3
R3
Q3
Q2
R4
NC = NO CONNECTION
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q4
NC
S1
R1
ENABLE
R2
VSS
S2
VDD
R4
Q1
R3
S3
Q3
Q2
S4
NC = NO CONNECTION
Features
• High Voltage Types (20V Rating)
• Quad NOR R/S Latch- CD4043BMS
• Quad NAND R/S Latch - CD4044BMS
• 3 State Outputs with Common Output ENABLE
• Separate SET and RESET Inputs for Each Latch
• NOR and NAND Configuration
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µa at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of ‘B’
Series CMOS Devices”
Applications
• Holding Register in Multi-Register System
• Four Bits of Independent Storage with Output ENABLE
• Strobed Register
• General Digital Logic
• CD4043BMS for Positive Logic Systems
• CD4044BMS for Negative Logic Systems
Description
CD4043BMS types are quad cross-coupled 3-state CMOS NOR
latches and the CD4044BMS types are quad cross-coupled 3-
state CMOS NAND latches. Each latch has a separate Q output
and individual SET and RESET inputs. The Q outputs are con-
trolled by a common ENABLE input. A logic “1” or high on the
ENABLE input connects the latch states to the Q outputs. A logic
“0” or low on the ENABLE input disconnects the latch states from
the Q outputs, results in an open circuit feature allows common
busing of the outputs.
The CD4043BMS and CD4044BMS are supplied in these 16-
lead outline packages:
Braze Seal DIP *H4T †H4T
Frit Seal DIP *H1C †HIE
Ceramic Flatpack *H3X †H6W
*CD4043B Only †CD4044B Only
File Number 3311
December 1992
7-877
Specifications CD4043BMS, CD4044BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K). . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-2µA
2 +125oC - 200 µA
VDD = 18V, VIN = VDD or GND 3 -55oC-2µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low
(Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
Input Voltage High
(Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
Input Voltage Low
(Note 2) VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC- 4 V
Input Voltage High
(Note 2) VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC11 - V
Tri-State Output
Leakage IOZL VIN = VDD or GND
VOUT = 0V VDD = 20V 1 +25oC -0.4 - µA
2 +125oC -12 - µA
VDD = 18V 3 -55oC -0.4 - µA
Tri-State Output
Leakage IOZH VIN = VDD or GND
VOUT = VDD VDD = 20V 1 +25oC - 0.4 µA
2 +125oC-12µA
VDD = 18V 3 -55oC - 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
7-878
Specifications CD4043BMS, CD4044BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Propagation Delay
Set or Reset to Q TPHL
TPLH VDD = 5V, VIN = VDD or GND
(Notes 1, 2) 9 +25oC - 300 ns
10, 11 +125oC, -55oC - 405 ns
Propagation Delay
3 - State Enable to Q TPHZ
TPZH VDD = 5V, VIN = VDD or GND
(Notes 2, 3) 9 +25oC - 230 ns
10, 11 +125oC, -55oC - 311 ns
Propagation Delay
3 - State Enable to Q TPLZ
TPZL VDD = 5V, VIN = VDD or GND
(Notes 2, 3) 9 +25oC - 180 ns
10, 11 +125oC, -55oC - 243 ns
Transition Time TTHL
TTLH VDD = 5V, VIN = VDD or GND
(Notes 1, 2) 9 +25oC - 200 ns
10, 11 +125oC, -55oC - 270 ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
1. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 1 µA
+125oC-30µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA
+125oC-60µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA
+125oC - 120 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,
-55oC-50mV
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,
-55oC-50mV
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,
-55oC4.95 - V
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,
-55oC9.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -1.6 mA
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
7-879
Specifications CD4043BMS, CD4044BMS
Input Voltage Low VIL VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,
-55oC-3V
Input Voltage High VIH VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,
-55oC7-V
Propagation Delay
Set or Reset to Q TPLH
TPHL VDD = 10V 1, 2, 3 +25oC - 140 ns
VDD = 15V 1, 2, 3 +25oC - 100 ns
Propagation Delay
3 State Enable to Q TPHZ
TPZH VDD = 10V 1, 2, 4 +25oC - 110 ns
VDD = 15V 1, 2, 4 +25oC - 80 ns
Propagation Delay
3 State Enable to Q TPLZ
TPZL VDD = 10V 1, 2, 4 +25oC - 100 ns
VDD = 15V 1, 2, 4 +25oC - 70 ns
Transition Time TTHL
TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns
Minimum Set or Reset
Pulse Width TW VDD = 5V 1, 2, 3 +25oC - 160 ns
VDD = 10V 1, 2, 3 +25oC - 80 ns
VDD = 15V 1, 2, 3 +25oC - 40 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 7.5 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage
Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage
Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL
TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x
+25oC
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER SYMBOL DELTA LIMIT
Supply Current - MSI-1 IDD ± 0.2µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
7-880
Specifications CD4043BMS, CD4044BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP MIL-STD-883
METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS MIL-STD-883
METHOD
TEST READ AND RECORD
PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION OPEN GROUND VDD 9V ± -0.5V
OSCILLATOR
50kHz 25kHz
PART NUMBER CD4043BMS
Static Burn-In 1
Note 1 1, 2, 9, 10, 13 3 - 8, 11, 12, 14,
15 16
Static Burn-In 2
Note 1 1, 2, 9, 10, 13 8 3 - 7, 11, 12,
14 - 16
Dynamic Burn-
In Note 1 13 8 5, 16 1, 2, 9, 12 4, 6, 12, 14 3, 7, 11, 15
Irradiation
Note 2 1, 2, 9, 10, 13 8 3 - 7, 11, 12,
14 - 16
PART NUMBER CD4044BMS
Static Burn-In 1
Note 1 1, 2, 9, 10, 13 3 - 8, 11, 12, 14,
15 16
Static Burn-In 2
Note 1 1, 2, 9, 10, 13 8 3 - 7, 11, 12,
14 - 16
Dynamic Burn-
In Note 1 2 8 5, 16 1, 9, 10, 13 4, 6, 12, 14 3, 7, 11, 15
Irradiation
Note 2 1, 2, 9, 10, 13 8 3 - 7, 11, 12,
14 - 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-881
Specifications CD4043BMS, CD4044BMS
Functional Diagram
CD4043BMS CD4044BMS
Logic Diagram
CD4043BMS CD4044BMS
TRUTH TABLE
CD4043BMS CD4044BMS
SREQ SREQ
X X O OC* X X O OC*
O O 1 NC** 1 1 1 NC**
1O11 O111
O11O 1O1O
111∆OO1∆∆
* Open Circuit * Open Circuit
** No Change ** No Change
∆ Dominated by S = 1 input ∆∆ Dominated by R = O input
LATCH
12
4
3
LATCH
29
6
7
LATCH
310
12
11
LATCH
41
14
15
135ENABLE
8
VSS
16
VDD
Q1
Q2
Q3
Q4
NC
S1
R1
S2
R2
S3
R3
S4
R4
LATCH
113
4
3
LATCH
29
6
7
LATCH
310
12
11
LATCH
41
14
15
25ENABLE
8
VSS
16
VDD
Q1
Q2
Q3
Q4
NC
R1
S1
R2
S2
R3
S3
R4
S4
5
*
E
4
3
2
*
*
E
E
S1
R1
E
E
VDD
VSS
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
EQUIVALENT
NOR LATCH VDD
VSS
Q1
5
*
E
3
4
13
*
*
E
E
S1
R1
E
E
VDD
VSS
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
EQUIVALENT
NAND LATCH VDD
VSS
Q1
7-882
CD4043BMS, CD4044BMS
Typical Performance Characteristics
FIGURE 1. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 5. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE - SET, RESET, to Q, Q
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = 15V
0 5 10 15
15
10
5
20
25
30
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = 15V
0 5 10 15
7.5
5.0
2.5
10.0
12.5
15.0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = -5V
0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-20
-25
-30
0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
GATE-TO-SOURCE VOLT AGE (VGS) = -5V
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0 40 60 80 10020
0
50
100
150
200
SUPPLY VOLT AGE (VDD) = 5V
10V
15V
TRANSITION TIME (tTHL, tTLH) (ns)
25
LOAD CAPACIT ANCE (CL) (pF)
010
PROPAGA TION DELAY TIME (tPHL, tPLH) (ns)
SUPPLY VOLT AGE (VDD) = 5V
10V
15V
20 30 40 50 60 70 80 90 100
50
75
100
125
150
175
AMBIENT TEMPERATURE (T A) = +25oC
7-883
CD4043BMS, CD4044BMS
FIGURE 8. SWITCH BOUNCE ELIMINATOR
FIGURE 9. ENABLE PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORM
FIGURE 7. TYPICAL POWER DISSIPATION vs FREQUENCY
TEST IN IN A
tPHZ VDD VSS VSS
tPLZ VSS VDD VDD
tPZH VDD VSS VSS
tPZL VSS VDD VDD
Z = HIGH IMPEDANCE
Typical Performance Characteristics (Continued)
10V
5V 10V
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
105
103
10
1
106
POWER DISSIPATION PER DEVICE (PD) (µW)
102
104
INPUT FREQUENCY (fI) (kHz)
103104105106107
CL = 50pF
CL =15pF
LATCH
SQ
RLATCH
SQ
R
OUTPUT OUTPUT
1MΩ
1MΩ
1MΩ1MΩ
VDD
VDD
VDD
CD4044BMS CD4043BMS
14
15
16
13
12
11
10
9
1
2
3
4
5
7
6
8
ENABLE
A
VDD
IN
IN
1KΩ
CL = 50pF
VSS
50% 50% VDD
ENABLE
tPZH
tPHZ
tPLZ
tPZL
90%
10%
90% 10%
POINT A
(IN = VDD, IN = VSS)
POINT A
(IN = VSS, IN = VDD)
VSS
≈2/3 VDD
≈1/3 VDD
≈2/3 VDD
≈1/3 VDD
7-884
CD4043BMS
FIGURE 10. MULTIPLE BUS STORAGE
CD4043
1 OF 4
CD4001
3
4
10
11
2
5
6
8
9
12
13
BUS A
LOAD A
ENABLE A
4
6
12
14
3
7
11
15
2
9
10
1
5
1
CD4043
CD4001
3
4
10
11
2
5
6
8
9
12
13
BUS B
LOAD B
ENABLE B
4
6
12
14
3
7
11
15
2
9
10
1
5
1
CD4043
CD4001
3
4
10
11
2
5
6
8
9
12
13
BUS C
LOAD C
ENABLE C
4
6
12
14
3
7
11
15
2
9
10
1
5
1
CD4043
CD4001
3
4
10
11
2
5
6
8
9
12
13
BUS D
LOAD D
ENABLE D
4
6
12
14
3
7
11
15
2
9
10
1
5
1
2
4
6
10
3
5
7
9
RESET
2/3 CD4009
OUTPUT
DATA
BUS
885
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
CD4043BMS
METALLIZATION: Thickness: 11kÅ−14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
Chip Dimensions and Pad Layouts
CD4043BMSH CD4044BMSH
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
