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VMMK-3413 Biasing Information
Biasing and Operation
The VMMK-3413 is a 3 terminal device consisting of a
“through” 50 ohm line connecting directly between the RF
Input and RF Output ports and a directional coupler with a
full wave detector that provides a DC output proportional
to RF power input. As with any high frequency device,
good grounding is required on the common port under
the device for it to produce low loss in the “through” mode.
A suggested PCB layout with appropriate grounding will
be cover later in the application section.
With only 3 terminals available, the DC bias and detected
voltage are internally DC coupled to the input and output
terminals respectively. The key to successful operation
of the VMMK-3413 is the use of low loss bias decoupling
networks connected to both the RF Input and the RF
Output ports. Figure 7 shows a simple biasing circuit.
The bias decoupling networks provide a low loss AC
coupled RF path to the device, a means of biasing the
device on the input, and a means of extracting the detected
voltage on the output of the device. The detector needs
2 DC blocking caps, C1 and C2, on the input and output
ports. This can be accomplished by printing coupled lines
on the PCB or using SMT capacitors (ATC 600 series) with
bias
detector
R1
C1
R2
C2
C4 R3
VdetVb
C3
RFin RFout
Component Description
C1, C2 0.1 pF (ATC 600 series or printed
coupled lines)
R1 (Vb -1.5) / 0.00016 Ω
R2 10 kΩ
C3, C4 1 pF
R3 External load resistor (optional)
Figure 7. Biasing the VMMK-3413 Detector Module
values chosen for the frequency of operation. All SMT
components are recommended to be no larger than 0402
size. Nominal bias voltage of 1.5 V or 0.16 mA is required
for proper operation. Biasing on the input is by a way of a
large value resistor R1. Its value can be computed using
the following equation:
R1 = (Vb -1.5)/0.00016
where Vb is the supply voltage.
Detected DC voltage is extracted on the output by a way
of a large value resistor R2, in the range of 10 kΩ. Bypassing
capacitors C3 and C4 are needed to prevent RF influence
on the DC lines. Suggested value for bypass capacitors is
1 pF.
At zero RF input power, and at 1.5 V supply bias, a nominal
63 mV offset voltage appears at the detected output port.
The internal output source resistance for the detector is
approximately 20 kΩ. Resistor R3 can be used as an
external load resistor for the detector. Its value can be
optimized for the desired Vout vs. RF input curve.
Figure 8 shows a characterization PCB used to obtain the
Vdet vs. Input Power characterization data from 25 to 45
GHz. For ease in broadband characterization, two external
45 MHz – 50 GHz Bias Networks (HP 11612B) were used.
Figure 8. VMMK-3413 Characterization Board