60612HK B8-9103,8341/ 51202AS(OT)/83199TH(OT) No. 6123-1/18
http://onsemi.com
Semiconductor Components Industries, LLC, 2013
June, 2013
LC72722PM
Overview
The LC72722PM is a single-chip system IC that implement the signal processing required by the European
Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee)
RBDS (Radio Broadcast Data System) standard. This IC include band-pass filter, demodulator, synchronization, and
error correction circuits as well as data buffer RAM on chip and perform effective error correction using a soft-decision
error correction technique.
Functions
• Band-pass filter : switched capacitor filter (SCF)
• Demodulator : RDS data clock regeneration and demodulated data reliability information
• Synchronization : Block synchronization detection
(with variable backward and forward protection conditions)
• Error correction : Soft-decision/hard-decision error correction
• Buffer RAM : Adequate for 24 blocks of data (about 500ms) and flag memory
• Data I/O : CCB interface (power on reset)
Features
• Error correction capability improved by soft-decision error correction
• The load on the control microprocessor can be reduced by storing decoded data in the on-chip data buffer RAM.
• Two synchronization detection circuits provide continuous and stable detection of the synchronization.
• Data can be read out starting with the backward-protection block data after a synchronization reset.
• Fully adjustment free
Specifications
• Operating power-supply voltage : 4.5 to 5.5V
• Operating temperature : -40 to +85°C
• Package : MFP24(375mil)
Ordering number : EN6123B
CMOS IC
Single-Chip RDS
Signal-Processing System IC
• CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
• CCB is a registered trademark of Semiconductor Components Industries, LLC.
LC72722PM
No. 6123-2/18
Specifications
Absolute Maximum Ratings at Ta = 25°C, Vssd = Vssa = 0V
Parameter Symbol Pin Name Ratings Unit
Maximum supply voltage Vddmax Vddd, Vdda -0.3 to +7.0 V
Maximum input voltage
Vin1max CL, DI, CE, SYR, T1, T2, T3, T4, T5, T6, T7, SYNC -0.3 to +7.0 V
Vin2max XIN -0.3 to Vddd+0.3 V
Vin3max MPXIN, CIN -0.3 to Vdda+0.3 V
Maximum output voltage
Vo1max DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 -0.3 to +7.0 V
Vo2max XOUT -0.3 to Vddd+0.3 V
Vo3max FLOUT -0.3 to Vdda+0.3 V
Maximum output current
Io1max DO, T3, T4, T5, T6, T7 +6.0 mA
Io2max XOUT, FLOUT +3.0 mA
Io3max SYNC, RDS-ID +20.0 mA
Allowable power dissipation Pdmax (Ta≤85°C) 175 mW
Operating temperature Topr -40 to +85 °C
Storage temperature Tstg -55 to +125 °C
Allowable Operating Ranges at Ta = -40 to 85°C, Vssd = Vssa = 0V
Parameter Symbol Pin Name Conditions Ratings Unit
min typ max
Supply voltage Vdd1 Vddd, Vdda 4.5 5.0 5.5 V
Vdd2 Vddd Serial data hold voltage 2.0 V
Input high-level
voltage VIH CL, DI, CE, SYR, T1, T2 0.7Vddd 6.5 V
Input low-level voltage VIL CL, DI, CE, SYR, T1, T2 0 0.3Vddd V
Output voltage VO DO, SYNC, RDS-ID, T3,
T4, T5, T6, T7
6.5 V
Input amplitude
VIN1 MPXIN f=57±2kHz 50 mVrms
VIN2 100% modulation composite 100 mVrms
VXIN XIN 400 1500
mVrms
Guaranteed crystal
Oscillator frequencies XTAL XIN, XOUT CI≤120Ω (XS=0 ) 4.332 MHz
CI≤70Ω (XS=1) 8.664 MHz
Crystal oscillator
frequency
deviation TXtal XIN, XOUT fo=4.332MHz, 8.664MHz ±100 ppm
Data setup time tSU DI, CL 0.75 μs
Data hold time tHD DI, CL 0.75 μs
Clock low level time tCL CL 0.75 μs
Clock high level time tCH CL 0.75 μs
CE wait time tEL CE, CL 0.75 μs
CE setup time tES CE, CL 0.75 μs
CE hold time tEH CE, CL 0.75 μs
CE high-level time tCE CE 20 ms
Data latch change
time tLC 1.15 μs
Data output time tDC DO,CL Differs depending on the value
of the pull-up resistor used.
0.46 μs
tDH DO,CE
0.46 μs
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
C onditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
LC72722PM
No. 6123-3/18
Electrical Characteristics at Ta = -40 to 85°C, Vssd = Vssa = 0V
Parameter Symbol Pin Name Conditions Ratings Unit
min typ max
Input resistance
RMPXIN MPXIN-Vssa f=57kHz 43.0 kΩ
Rcin CIN-Vssa f=57kHz 100.0 kΩ
Internal feedback
resistance
Rf XIN 1.0 MΩ
Center frequency fc FLOUT 56.5 57.0 57.5 kHz
-3dB band width BW-3dB FLOUT 2.5 3.0 3.5 kHz
Gain Gain MPXIN-FLOUT f=57kHz 28 31 34 dB
Stop band
Attenuation
Att1 FLOUT Δf=±7kHz 30 dB
Att2 FLOUT f<45kHz, f>70kHz 40 dB
Att3 FLOUT f<20kHz 50 dB
Reference voltage
output
Vref Vref Vdda=5.0V 2.5 V
Hysteresis VHIS CL, DI, CE, SYR, T1, T2 0.1Vddd V
Out put low-level
voltage
VOL1 DO, T3, T4, T5, T6, T7 I=2mA 0.5 V
VOL2 SYNC, RDS-ID I=8mA 0.5 V
Input high-level
current
I IIH1 CL, DI, CE, SYR, T1, T2 VI= Vddd 5.0
μA
I IIH2 XIN VI=Vddd 2.0 11.0
μA
Input low-level
current
I IIL1 CL, DI, CE, SYR, T1, T2 VI=0V 5.0
μA
I IIL2 XIN VI=0V 2.0 11.0
μA
Output off leakage
current
I IOFF DO, SYNC, RDS-ID, T3,
T4, T5, T6, T7
VO=6.5V 5.0
μA
Current drain Idd Vddd, Vdda 9 mA
LC72722PM
No. 6123-4/18
Package Dimensions
unit:mm
3045C
Pin Assignment
SANYO : MFP24(375mil)
112
24 13
1.27
15.2
0.35
10.5
7.9
(0.62)
2.35max
0.1 (2.15)
0.65
0.15
VREF
MPXIN
Vdda
Vssa
FLOUT
CIN
T1
T2
T3 (RDCL)
T4 (RDDA)
T5 (RSFT)
XOUT
LC72722PM
Top view
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SYR
CE
DI
CL
DO
RDS-ID
SYNC
T7 (CORREC/ARI-ID/TA/BEO)
T6 (ERROR/57K/TP/BE1)
Vssd
Vddd
XIN
LC72722PM
No. 6123-5/18
Block Diagram
Vdda
Vssa
MPXIN
REFERENCE
VOLTAGE
ANTIALIASING
FILTER
VREF
57kHz
BPF
(SCF) SMOOTHING
FILTER
-
+
FLOUT CIN
VREF
PLL
(57kHz) CLOCK
RECOVERY
(1187.5Hz)
DATA
DECODER
Vddd
+5.0V
Vssd
RDS-ID
SYNC/EC
CONTROLLER SYNC
SYR
CCB
TEST
DO
CL
DI
CE
T1
T2
T3 to T7
RAM
(24 BLOCK DATA)
ERROR
CORRECTION
(SOFT DECISION)
MEMORY
CONTROL OSC/DIVIDER
CLK (4.332MHz)
XIN XOUT
SYNC
DETECT-1 SYNC
DETECT-2
+5.0V
LC72722PM
No. 6123-6/18
Pin Functions
Pin No. Pin name Function I/O Pin circuit
1 VREF Reference voltage output (Vdda/2) Output
2 MPXIN Baseband (multiplexed) signal input Input
5 FLOUT Subcarrier output (filter output) Output
7 CIN Subcarrier input (comparator input) Input
3 Vdda Analog system power supply (+5V) − −
4 Vssa Analog system ground − −
12 XOUT Crystal oscillator output (4.332/8.664MHz) Output
13 XIN Crystal oscillator input (external reference signal input)
Input
7 T1 Test input (This pin must always be connected to ground.)
8 T2
Test input (standby control)
0:Normal operation, 1:Standby state
(crystal oscillator stopped)
9 T3(RDCL) Test I/O (RDS clock output)
I/O*
10 T4(RDDA) Test I/O (RDS data output)
11 T5(RSFT) Test I/O (soft-decision control data output)
16 T6
(ERROR/57K/BE1) Test I/O (error status, regenerated carrier, error block count)
17 T7
(CORREC/ARI-ID/BE0)
Test I/O
(error correction status, SK detection, error block count)
18 SYNC Block synchronization detection output
19 RDS-ID RDS detection output Output
20 DO Data output
21 CL Clock input
Data input
Chip enable Input
22 DI
23 CE
24 SYR Synchronization and RAM address reset (active high)
14 Vddd Digital system pow er supply (+5V) − −
15 Vssd Digital system ground − −
Note : * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user
applications.
Serial data interface (CCB)
Vdda
Vdda
Vdda
Vddd
VREF
Vssa
Vssa
Vssd
Vssa
XOUT
XIN
Vssd
Vssd
S
Vssd
S
Vssd
LC72722PM
No. 6123-7/18
CCB output data format
1. Each block of output data consists of 32 bits (4 bytes), of which 2 bytes are RDS data and 2 bytes are flag data.
2. Any number of 32 -bi t s o utp ut data bl o cks can be output consecutively.
3. When there is no data that can be read out in the internal memory, the system outputs blocks of all-zero data
consecutively.
4. If data readout is inter rupted, the next rea d ope rat i o n starts with the 32-bit data block whose readout was interrupted.
However, if only the last bit is remaining to be read, it will not be possible to re-read that whole block.
5. The check bits (10 bits) are not output.
6. The data valid (OWD) must not be referred to.
7. When the first leading bits are not “1010”, the read in data is in invalid, and read operation is cancelled.
(1) Offset word detection flag (1bit) : OWD
OWD Offset word detection
1 Detected
0 Not detected (protection function operating)
(2) Offset word information flag (3bit) : B0 to B2
B
2 B
1 B
0 Offset word
0 0 0 A
0 0 1 B
0 1 0 C
0 1 1 C’
1 0 0 D
1 0 1 E
1 1 0 Unused
1 1 1 Unused
DI
DO
B
0
0
1010O
W
D
R
F
1
R
F
0
A
R
I
S
Y
C
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
B
2E
2E
1E
0D
9D
8D
7D
6D
5D
4D
3D
2D
1D
0
B
1B
0R
E
0110110
B
1B
2B
3A
0A
1A
2A
3
CCB address 6C
Output data / first bit Last bit
(8) RDS data
(7) Error information flags
(6) Synchronization established flag
(5) ARI(SK) detection flag
(4) RAM data remaining flags
(3) Consecutive RAM read out possible flag
(2) Offset word information flags
(1) Offset word detection flag
Fixed pattern (1010)
LC72722PM
No. 6123-8/18
(3) Consecutive RAM read out possible flag (1bit) : RE
RE RAM data information
1 The next data to be read out is in RAM
0 This data item is the last item in RAM, ant the next data is not present.
(4) RAM data remaining flag (2bits) : RF0,RF1
RF1 RF0 Remaining data in RAM (number of blocks)
0 0 1 to 7
0 1 8 to 15
1 0 16 to 23
1 1 24
Caution : This value is only meaningful when RE is 1. When RE is 0, there is no data in RAM, even if RF is 00.
If a synchronization reset was applied using SYR, then the backward protection block data that was written to memory
is also counted in this value.
(5) ARI(SK) detection flag (1bit) : ARI
ARI SK signal
1 Detected
0 Not detected
(6) Synchronization established flag (1bit) : SYC
SYC Synchronization detection
1 Synchronized
0 Not synchronized
Caution : This flag indicates the synchronization state of the circuit at the point when the data block being output was received.
On the other hand, the SYNC pin (pin18) output indicates the current synchronization state of the circuit.
(7) Error information flags (3bits) : E0 to E2
E
2 E
1 E
0 Number of bits corrected
0 0 0 0 (no errors)
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 Correction not possible
1 1 1 Unused
Caution : If the number of errors exceeds the value of the EC0 to EC2 setting (see the section on the CCB input format),
the error information flags will be set to the “Correction not possible” value.
(8) RDS data (16bits) : D0 to D15
This data is output with the MSB first ant the LSB last.
Caution : When error correction was not possible, the input data is output without change.
LC72722PM
No. 6123-9/18
CCB Input data format
(1) Synchronization protection (forward pro tection) method setting (4bits) : FS0 to FS3
FS3 = 0 : If offset words in the correct order could not be detected continuously during the number of blocks
specified by FS0 to FS2, take that to be a lost synchronizatio n sate.
FS3 = 1 : If blocks with uncorrectable errors were received consecutively during the number of blocks specified by
FS0 to FS2, take that to be a lost synchronization state.
F
S
0
F
S
1
F
S
2 Condition for detecting lost synchronization
0 0 0 If 3 consecutive blocks matching the FS3 condition are received.
1 0 0 If 4 consecutive blocks matching the FS3 condition are received.
0 1 0 If 5 consecutive blocks matching the FS3 condition are received.
1 1 0 If 6 consecutive blocks matching the FS3 condition are received.
0 0 1 If 8 consecutive blocks matching the FS3 condition are received.
1 0 1 If 10 consecutive blocks match ing the FS3 conditio n are received.
0 1 1 If 12 consecutive blocks match ing the FS3 conditio n are received.
1 1 1 If 16 consecutive blocks match ing the FS3 conditio n are received.
Initial value : FS0 = 0, FS1 = 1, FS2 = 0, FS3 = 0
(2) Synchronization detection method setting (1bit) : BS
BS Synchronization detection conditions
0 If during 3 blocks, 2 blocks of offset words were detected in the correct order.
1 If the offset words were detected in the correct order in 2 consecutive blocks.
Initial value : BS = 0
DI
B
0
0
B
1
1
B
2
0
B
3
1
A
0
0
A
1
1
A
2
1
A
3
0
[1] CCB address 6A
F
S
0
F
S
1
F
S
2
F
S
3
B
S
S
Y
R
O
W
E
E
C
0
E
C
1
E
C
2
E
C
3
E
C
4
C
T
0
(12) Circuit control
(5) Error correction method setting
(4) RAM write control
(3) Synchronization and RAM address reset
(2) Synchronization detection method setting
(1) Synchronization protection method setting
IN1 data, first bit
DI
B
0
1
B
1
1
B
2
0
B
3
1
A
0
0
A
1
1
A
2
1
A
3
0
[2] CCB address 6B
C
T
1
S
P
0
S
P
1
X
S
P
L
0
P
L
1
P
T
0
P
T
1
P
T
2
T
S
0
T
S
1
T
S
2
(11) Test mode settings
(10) Output pin settings
(9) RDS/RBDS selection
(8) Demodulation circuit phase control
(7) Crystal oscillator frequency selection
(12) Circuit control
IN2 data, first bit
R
M
T
S
3
Caution : The bits labeled with an asterisk must be set to 0.
(6) Intermittent DO output setting
LC72722PM
No. 6123-10/18
(3) Synchronization and RAM address reset (1bit) : SYR
SYR Synchronization detection circuit RAM
0 Normal operation (reset cleared) Normal write (See the description of the OWE bit)
1 Forced to the unsynchronized state
(synchron ization reset)
After the reset is cleared, start writing from the data prior
to the establishment of synchro nization, i.e. the data in
b
ackward protection.
Initial value : SYR = 0
Caution : 1. To apply a synchronization reset, set SYR to 1 temporarily using CCB, and then set it back to 0 again using CCB.
The circuit will start synchronization capture operation at the point SYR is set to 0.
2. The SYR pin (pin24) also provides an identical reset control operation. Applications can use either method.
However, the control method that is not used must be set to 0 at all times.
Any pulse with a width of over 250 ns will suffice.
3. A reset must be applied immediately after the reception channel is changed.
If a reset is not applied, reception data from the previous channel may remain in on-chip memory.
4. Data read out after a synchronization reset is read out starting with the backward protection block data preceding
the establishment of synchronization.
(4) RAM write control (1bit) : OWE
OWE RAM write condition s
0 Only data for which synchronization had been established is written.
1 Data for which synchronization not has been established (unsynchronized data) is also
written. (However, this applies when SYR = 0.)
Initial value : OWE = 0
(5) Error correction method setting (5bits) : EC0 to EC4
Initial values : EC0 = 0, EC1 = 1, EC2 = 0, EC3 = 0, EC4 = 1
Caution : 1. If soft-decision A or soft-decision B is specified, soft-decision control will be performed even if the number
of bits corrected is set to 0 (error detection only). With these settings, data will be output for blocks with no errors.
2. As opposed to soft-decision B, the soft-decision A setting suppresses soft decision error correction.
(6) Intermittent DO output setting
SP0 SP1 DO output state
0 0
DO goes low when one or more blocks of data are written to memory.
1 0
DO goes low when 4 or more blocks of data are written to memory.
0 1
DO goes low when 8 or more blocks of data are written to memory.
1 1
DO goes low when 12 or more blocks of data are written to memory.
Initial values : SP0 = 0, SP1 = 0
E
C
0
E
C
1
E
C
2 Number of bits corrected
0 0 0 0 (error detection only)
1 0 0 1 or fewer bits
0 1 0 2 or fewer bits
1 1 0 3 or fewer bits
0 0 1 4 or fewer bits
1 0 1 5 or fewer bits
0 1 1 Illegal value
1 1 1 Illegal value
E
C
3
E
C
4Soft-decision setting
00 MODE0 Hard decision
10 MODE1 Soft decision A
01 MODE2 Soft decision B
1 1 Illegal value
LC72722PM
No. 6123-11/18
(7) Crystal oscillator frequency selection (1bit) : XS
XS = 0 : 4.332MHz (Initial value : XS = 0)
XS = 1 : 8.664MHz
(8) Demodulation circuit phase control (2bits) : PL0, PL1
PL0 PL1 Demodulation circuit phase control
0 0/1
< Normal operat i on > when ARI presence or absence is unclear.
1 0 If the circuit determines that the ARI signal is absent : 90° phase
1 If the circuit determines that the ARI signal is present : 0° phase
Initial values : PL0 = 0, PL1 = 1
Caution : 1. When PL0 is 0 (normal operation), the IC detects the presence or absence of the ARI signal and reproduces
the RDS data by automatically controlling the demodulation phase with respect to the reproduced carrier.
However, the initial phase following a synchronization reset is set by PL1.
2. If PL0 is set to 1, the demodulation circuit phase is locked according to the PL1 setting at either 90° (PL1 = 0) or
0° (PL1 = 1), allowing RDS data to be reproduced. When ARI is not present, PL1 should be set to 0, since the
RDS data is reproduced by detecting at a phase of 90° with respect to the reproduced carrier. When ARI is present,
PL1 should be set to 1, since detection is at 0°. In cases where the ARI presence is known in advance, more stable
reproduction can be achieved by fixing the demodulation phase in this manner.
(9) RDS/RBDS(MMBS) selection (1bit) : RM
RM RBDS Decoding method
0 None
Only RDS data is decoded correctly (Offset word E is not detected.)
1 Provided RDS and MMBS data is decoded correctly (Offset word E is also detected.)
Initial value : RM=0
(10) Output pin settings (3bits) : PT0 to PT2
These bits control the T3, T4, T5, T6, T7, SYNC, and RDS-ID pins
MODE P
T
0
P
T
1
P
T
2
T3 T4 T5 T6 T7
RDCL RDDA RSFT ERROR 57K TP BE1 CORREC ARI-ID TA BE0
0 0 0 0 − − − − − − − − − −
1 1 0 0 −− − − − − − −
−
2 0 1 0 − − − − −
3 1 1 0 − − − − −
4 0 0 1 − − − − −
− − −
5 1 0 1 − − −
− − −
−
6 0 1 1 − − − − −
7 1 1 1 − − − − −
− : open, , : Output enabled ( = reve rse pola rity)
Initial value : PT0 = 1, PT1 = 1, PT2 = 0 (Mode 3)
Caution : 1. When PT2 is set to 1, the polarity of the T6(ERROR/57K/TP), T7(CORREC/ARI-ID/TA), SYNC,
and RDS-ID pins changes to active high.
2. The output pins (T3 to T7, SYNC, and RDS-ID) are all open-drain pins, and require external pull-up resistors
to output data.
Mode1 (PT2 = 0) Pin T6 (TP)
TP = 0 detected High (1)
TP = 1 detected Low (0)
TP = Traffic program code
LC72722PM
No. 6123-12/18
Mode1 (PT2 = 0) Pin T7 (TA)
TA = 0 detected High (1)
TA = 1 detected Low (0)
TA = Traffic announcement code
Mode2 (PT2 = 0) Pin T7 (ARI-ID)
No SK High (1)
SK present Low (0)
Mode3 (PT2 = 0) Pin T6 (ERROR) Pin T7 (CORREC)
Correction not possible Low (0) Low (0)
Errors corrected High (1) Low (0)
No errors High (1) High (1)
Mode = 4 Pin T6 (BE1) Pin T7 (BE0)
Number of error blocks (B)
B=0 Low (0) Low (0)
1 ≤ B ≤ 20 Low (0) Hig h (1 )
20 < B ≤ 40 High (1) Low (0)
40 < B ≤ 48 High (1) High (1)
These pins indicate the number of blocks in a set of 48 blocks that had errors before correction.
The output polarity of these pins is fixed at the values listed in the table.
Mode (PT2 = 0) The SYNC pin
0 to 2 When synchronized : Low (0), When unsynchronized: High (1)
3 When synchronized : Goes high for a fixed peri od (42 1
μ
s) at the
start of a block and then goes low.
When unsynchronized : High (1)
Caution : The output indicates the synchronization state for the previous block.
When PT2 = 0 The RDS-ID pin
No RDS High (1)
RDS present Low (0)
(11) Test mode settings (4bits) : TS0 to TS3
Initial values : TS0 = 0, TS1 = 0, TS2 = 0, TS3 = 0
(Applications must set these bits to the above v alues.)
Notes : The T1 and T2 pins (pins 7 and 8) are related to test mode as follows.
Pin T1 Pin T2 IC operation Notes
0 0 Normal operating mode These states are user settable
0 1 Standby mode (crystal oscillator stopped)
1 0/1 IC test mode Users cannot use this state
The T1 pin must be tied to VSS (0V).
(12) Circuit control (2 bits) : CT0 and CT1
Item Control
CT0 RSFT control
When set to 1, sof
t
-decision control data (RSFT) is
easier to generate.
CT1 RDS-ID detection condition When set to 1, the RDS-ID detection cond itions are
made more restrictive.
Initial value : CT0 = 0, CT1 = 0
LC72722PM
No. 6123-13/18
RDCL / RDDA / RSFT and ERROR / CORREC / SYNC output timing
(1) Timing 1
Note : When PT2 = 0, RDDA and RSFT must be acquired on the falling edge of RDCL.
(2) Timing 2 (mode 3, PT2 = 0)
Input data
Error crrection
SYNC output
ERROR output
CORREC output
Sync NG Sync OK
Tp1 Tp1
Sync OK Sync OK Sync OK Sync OK Sync NG Sync NG
Data
corrected No
errors No
errors Data
corrected
Uncorrectable
Uncorrectable
17 μs
421 μs 421 μs
Tp2
Tp1
17 μs
RDCL output
RSFT output
RDDA output
LC72722PM
No. 6123-14/18
Serial Data Input and Output Methods
Data is input and output using the CCB (Computer Control Bus), which is Our audio IC serial bus format.
This IC adopts an 8-bit address CCB format.
I/O mode
(LSB) Address (MSB) Comment
B0 B1 B2 B3 A0 A1 A2 A3
[1] IN1 (6A) 0 1 0 1 0 1 1 0
Control data input mode, also referred to as
“ serial data input ” mode.
16bit data input mode
[2] IN2 (6B) 1 1 0 1 0 1 1 0
[3] OUT (6C) 0 0 1 1 0 1 1 0
Data output mode
The data for multiple blocks can be
output sequentially in this mode.
CE
CL
DI
DO
B0 B1 B2 B3 A0 A1 A2 A3
First Data IN1/2
First Data OUT
First Data OUT
1
1
2
1
2
2
I/O mode determined
For the CL normal high state
For the CL normal low state
LC72722PM
No. 6123-15/18
(1) Serial data input (IN1 / IN2)
tSU, tHD, tEL, tES, tEH ≥ 0. 7 5μs tLC < 1.15μs tCE < 20 ms
CL : Normal high
CL : Normal low
(2) Serial data output (OUT)
tSU, tHD, tEL, tES, tEH ≥ 0. 7 5μs tDC, tDH < 0.46μs tCE < 20 ms
CL : Normal high
CL : Normal low
Cautions : 1. Since the DO pin is an n-channel open-drain output, the transition times (tDC, tDH) will differ with the value of
the pull-up resistor used.
2. The CE, CL, DI, and DO pins can be connected to the corresponding pins on other ICs that use the CCB interface.
(However, we recommend connecting the DO and CE pins separately if the number of available microcontroller
ports allows it.)
3. Serial data I/O becomes possible after the crystal oscillator starts oscillation.
tSU tHD
tEL tES tEH
tLC
tCE
B0 B1 B2 B3 A0 A1 A2 A3 FS0
CT1 FS1
0FS2
SP0 FS3
SP1 EC3
TS0 EC4
TS1 CT0
TS2 0
TS3
CE
CL
DI
Internal data
tSU tHD
tEL tES tEH
tDC tDC
tCE
B0 B1 B2 B3 A0 A1 A2 A3
1 0 1 0 D3 D2 D1 D0
CE
CL
DI
DO
tDH
tSU tHD
tEL tES tEH
tLC
tCE
B0 B1 B2 B3 A0 A1 A2 A3 FS1
0
FS0
CT1 FS2
SP0 FS3
SP1 EC3
TS0 EC4
TS1 CT0
TS2 0
TS3
CE
CL
DI
tSU tHD
tDC tDC
B0 B1 B2 B3 A0 A1 A2 A3
1 0 1 0 D3 D2 D1 D0
CE
CL
DI
DO
tDH
tEL tES tEH
tCE
Internal data
LC72722PM
No. 6123-16/18
(3) Serial data timing
CL : Normal high
CL : Normal low
Parameter Symbol Conditions min typ max Unit
Data setup time tSU DI, CL 0.75 μs
Data hold time tHD DI, CL 0.75 μs
Clock low level time tCL CL 0.75 μs
Clock high level time tCH CL 0.75 μs
CE wait time tEL CE, CL 0.75 μs
CE setup time tES CE, CL 0.75 μs
CE hold time tEH CE, CL 0.75 μs
CE high leve l time tCE CE 20 ms
Data latch transition time tLC 1.15 μs
Data output time tDC DO, CL Differs with the value of the pull-up
resistor used. 0.46 μs
tDH DO, CE 0.46 μs
tCE
VIH VIL
VIL
VIH VIL tEH
tDH
tLC
tES
tDC tDC
tEL
Old
Old
New
New
tCL
tCH
tSU tHD
VIH
VIL
VIH
VIL VIH
VIL
VIL
CE
CL
DI
DO
tCE
VIH VIL
VIH
VIL
tEH
tDH
tLC
tES
tDC
tEL
tCL tCH
tSU tHD
VIH
VIL
VIH
VIL
VIH
VIL
VIH
CE
CL
DI
DO
Internal data latch
Internal data latch
LC72722PM
No. 6123-17/18
DO pin operation
This IC incorporates a RAM data buffer that can hold up to 24 blocks of data. At the point when one block of data is
written to this RAM, the IC issues a read request by switching the DO pin from high to low.
The DO pin always goes high for a fixed period (Tdo = 265 μs) after a readout and CE goes low. When all the data in
the data buffer has been read out, the DO pin is held in the high state until a new block of data has been written to the
RAM. If there is data that has not yet been read remaining in the data buffer, the DO pin goes low after the Tdo time has
elapsed.
After a synchronization reset, the DO pin is held high until synchronization is established. It goes low at the point the IC
synchronizes.
When the DO pin is high following the 265 μs period (Tdo) after data is read out.
Here, the buffer is in the empty state, i.e. the state where new data has not been written. After this, when the DO pin
goes low, applications are guaranteed to be able to read out that data without it being overwritten by new data if they
start a readout operation within 480 ms of DO going low.
When DO goes low 265 μs after data is read out
Here, there is data that has not been read out remaining in the data buffer. In this case, applications are guaranteed to
be able to read out that data without it being overwritten by new data if they start a readout operation within 20 ms
of DO going low. (Note that this is the worst case condition.)
Notes : 1. Although an application can determine whether or not there is data remaining in the buffer by checking the DO level
with the above timing, checking the RE and RF flags in the serial data is a preferable method.
2. Applications are not limited to reading out one block of data at a time, but rather can read out multiple blocks of data
continuously as described above. When using this method, if an application references the RE and RF flags in the data
while reading out data, it can determine the amount of data remaining. However, the length of the period for data readout
(the period the CE pin remains high) must be kept under 20 ms.
3. If the DO pin is shared with other ICs that use the CCB interface, the application must identify which IC issued the
readout request. One method is to read out data from the LC72722PM and either check whether meaningful data has
been read (if the LC72722PM is not requesting a read, data consisting of all zeros will be read out) or check whether the
DO level goes low within the 256 μs following the completion of the read (if the DO pin goes low, then the request was
from another IC).
CE pin
DO pin (Last data)-1 Last data New data
T
Tdo
DO check (Tdo < T)
CE pin
DO pin (Last data)-2 (Last data)-1 Last data
T
Tdo
DO check (Tdo < T)
LC72722PM
No. 6123-18/18
Sample Application circuit
Caution : 1. Determine the value of the DO pin pull-up resistor based on the required serial data transfer speed.
2. If the SYR pin is unused, it must be connected to ground.
PS
+
124
VREF SYR SYR
223
MPXIN CE
322
Vdda DI
421
Vssa CL
520
FLOUT DO
619
CIN RDS-ID
718
T1 SYNC
12 13
XOUT XIN
10 μF
MPXIN
Vdda
Vssa
8T2
Vssd 9T3
NC NC
NC
NC
NC
10 T4
11 T5
Vssd Vssd
330 pF
560 pF
22 pF 22 pF
17
T7
16
T6
Vssd
Vssd
Vddd
0.1 μF
15
Vssd
14
Vddd
0.1 μF
Vssa
4.332 MHz
DI
CE
CL
DO
Vddd
10 kΩ
Vddd
10 kΩRDS-ID
SYNC
Vddd
10 kΩ
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries,LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for
any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture ofthe
part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
