
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20019I Page 3 Rev. 09-25-07
DATASHEET
TABLE OF CONTENTS
Chapter 1 GENERAL DESCRIPTION.....................................................................................................5
Chapter 2 PIN CONFIGURATIONS........................................................................................................6
Chapter 3 DESCRIPTION OF PIN FUNCTIONS....................................................................................8
Chapter 4 PROTOCOL DESCRIPTION ...............................................................................................11
4.1 NETWORK PROTOCOL............................................................................................................................11
4.2 DATA RATES.............................................................................................................................................11
4.3 NETWORK RECONFIGURATION.............................................................................................................11
4.4 BROADCAST MESSAGES........................................................................................................................12
4.5 EXTENDED TIMEOUT FUNCTION...........................................................................................................12
4.5.1 Response Time...................................................................................................................................12
4.5.2 Idle Time .............................................................................................................................................12
4.5.3 Reconfiguration Time..........................................................................................................................13
4.6 LINE PROTOCOL......................................................................................................................................13
4.6.1 Invitations To Transmit........................................................................................................................13
4.6.2 Free Buffer Enquiries..........................................................................................................................13
4.6.3 Data Packets.......................................................................................................................................13
4.6.4 Acknowledgements.............................................................................................................................14
4.6.5 Negative Acknowledgements..............................................................................................................14
Chapter 5 SYSTEM DESCRIPTION.....................................................................................................15
5.1 MICROCONTROLLER INTERFACE..........................................................................................................15
5.1.1 High Speed CPU Bus Timing Support ................................................................................................18
5.2 TRANSMISSION MEDIA INTERFACE ......................................................................................................19
5.2.1 Backplane Configuration.....................................................................................................................19
5.2.2 Differential Driver Configuration..........................................................................................................20
5.2.3 Programmable TXEN Polarity.............................................................................................................20
Chapter 6 FUNCTIONAL DESCRIPTION.............................................................................................23
6.1 MICROSEQUENCER.................................................................................................................................23
6.2 INTERNAL REGISTERS............................................................................................................................24
6.2.1 Interrupt Mask Register (IMR).............................................................................................................24
6.2.2 Data Register......................................................................................................................................24
6.2.3 Tentative ID Register ..........................................................................................................................25
6.2.4 Node ID Register.................................................................................................................................25
6.2.5 Next ID Register..................................................................................................................................25
6.2.6 Status Register....................................................................................................................................25
6.2.7 Diagnostic Status Register..................................................................................................................26
6.2.8 Command Register.............................................................................................................................26
6.2.9 Address Pointer Registers ..................................................................................................................26
6.2.10 Configuration Register.....................................................................................................................26
6.2.11 Sub-Address Register .....................................................................................................................26
6.2.12 Setup 1 Register..............................................................................................................................26
6.2.13 Setup 2 Register..............................................................................................................................27
6.3 INTERNAL RAM ........................................................................................................................................35
6.3.1 Sequential Access Memory.................................................................................................................35
6.3.2 Access Speed.....................................................................................................................................35
6.4 SOFTWARE INTERFACE..........................................................................................................................35
6.4.1 Selecting RAM Page Size...................................................................................................................36
6.4.2 Transmit Sequence.............................................................................................................................37
6.4.3 Receive Sequence..............................................................................................................................38
6.5 COMMAND CHAINING..............................................................................................................................39
6.5.1 Transmit Command Chaining .............................................................................................................40
6.5.2 Receive Command Chaining ..............................................................................................................40
6.6 RESET DETAILS .......................................................................................................................................41
6.6.1 Internal Reset Logic............................................................................................................................41
6.7 INITIALIZATION SEQUENCE....................................................................................................................41
6.7.1 Bus Determination...............................................................................................................................41
6.8 IMPROVED DIAGNOSTICS ......................................................................................................................42
6.8.1 Normal Results:...................................................................................................................................43