©2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8333 Rev. 1.0.3 27
FOD8333 — Input LED Drive, 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection, Isolated Fault Sensing,
Active Miller Clamp, and Automatic Fault Reset
As shown in Figure 55, the gate driver output is
influenced by signals from the photodetector circuitry,
the UVLO comparator, and the DESAT signals. Under
no-fault condition, normal operation resumes while the
supply voltage is above the UVLO threshold and the
output of the photodetector drives the MOSFETs of the
output stage. The logic circuitry of the output stage
ensures that the push-pull devices are never turned ON
simultaneously. When the output of the photodetector is
HIGH, output VO is pulled to HIGH state by turning on
the PMOS. When the output of the photodetector is
LOW, VO is pulled to LOW state by turning on the
50XNMOS.
When VDD supply goes below VUVLO, which is the
designated ULVO threshold at the comparator, VO is
pulled to LOW state regardless of photodetector output.
When VO is HIGH and desaturation is detected, VO turns
off slowly as it is pulled LOW by the 1XNMOS device.
The input to the fault-sense circuitry is latched to HIGH
state and turns on the LED2. The fault-sense signal
remains in HIGH state until LED1 is switched from LOW
to HIGH. When VO goes below 2 V, the 50XNMOS
device turns on, clamping the IGBT gate firmly to VSS.
3. Desaturation Protection, FAULT Output and
FAULT RESET
Desaturation detection protects the IGBT in short circuit
by monitoring the collector-emitter voltage of the IGBT
when it’s turned on. When the DESAT pin voltage goes
above the threshold voltage, a short-circuit condition is
detected and the driver output stage executes a “soft”
IGBT turn-off and is eventually driven LOW. This
sequence is illustrated in Figure 56. The FAULT open-
collector output is triggered active LOW to report a
desaturation error. The gate driver output is muted for
minimum of 20 µs. All input LED signals are ignored
during the mute period to allow the driver to completely
soft shutdown the IGBT. The fault mechanism is reset
automatically after the tDESAT(MUTE) (see Figure 56).
During OFF state of the IGBT, or if VO is LOW, the fault
sense circuitry is disabled to prevent false fault signals.
The DESAT comparator should be disabled for a short
period (blanking time) before the IGBT turns on to allow
the collector voltage to fall below the DESAT threshold.
This blanking period protects against false triggering of
the DESAT while the IGBT is turning on. The blanking
time is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT
capacitor (capacitor between DESAT and VE pin). The
nominal blanking time can be calculated using external
capacitance (CBLANK), FAULT threshold voltage
(VDESAT), and DESAT charge current (ICHG):
tBLANK = CBLANK x VDESAT / ICHG (2)
With a recommended 100 pF DESAT capacitor, the
nominal blanking time is:
100 pF x 6.5 V / 250 µA = 2.6 µs
4. Soft Turn-Off
The soft turn-off feature ensures the safe shutdown of
the IGBT under fault condition. The gate-driver voltage
VO turns off the IGBT in a controlled slow manner. This
reduces the voltage spike on the collector of the IGBT.
Without this, the IGBT would see a heavy spike on the
collector, resulting in a permanent damage to the device
when it’s turned off immediately. The VO is pulled to
LOW slowly in 4 µs.
5. Under-Voltage Lockout (UVLO)
Under-Voltage detection prevents the application of
insufficient gate voltage to the IGBT. This could be
dangerous, as it would drive the IGBT out of saturation
and into the linear operation where losses are very high
and the IGBT quickly overheats. This feature ensures
proper operation of the IGBTs. The output voltage, VO,
remains LOW irregardless of the inputs, as long as the
supply voltage, VDD – VE, is less than VUVLO+ during
power up. When the supply voltage falls below VUVLO- ,
VO goes LOW, as illustrated in Figure 57.
6. Active Miller Clamp Function
An active Miller clamp feature allows the sinking of the
Miller current to ground during a high-dV/dt situation.
Instead of driving the IGBT gate to a negative supply
voltage to increase the safety margin, the device has a
dedicated VCLAMP pin to control the Miller current.
During turn-off, the gate voltage of the IGBT is monitored
and the VCLAMP output is activated when the gate
voltage goes below 2 V (relative to VSS).
The Miller clamp NMOS transistor is then turned on and
provides a low resistive path for the Miller current, which
helps prevent a self-turn-on due to the parasitic Miller
capacitor in power switches. The clamp voltage is VSS +
2.5 V, typical for a Miller current up to 1100 mA.
In this way, the VCLAMP function does not affect the turn-
off characteristic. It helps to clamp the gate to the low
level throughout the turn-off time. During turn-on, where
the input of the driver is activated, the VCLAMP function is
disabled or opened.