PLR152/S1 - Everlight Electronic Co., Ltd.

EVERLIGHT ELECTRONICS CO., LTD. http://www.everlight.com Rev 1.1 Page: 1 of 7

Device NO: DPL-152-002 Prepared Date:04-23-2004 Prepared By: Chin-Chia Hsu

Technical Data Sheet

Photo link Light Receiver Unit

PLR152 Series

Features

1. High PD sensitivity optimized for red light

2. Data Rate up to 16Mbps at least (NRZ signal)

3. Low power consumption for extended battery

life

4. Built-in threshold control for improved noise

Margin

5. Good ESD protection: up to 8KV

6. Receiver sensitivity: up to –27dBm (Min.)

7. Pb Free

Descriptions

The optical receiver is packaged with custom optic

data link interface, integrated on a proprietary CMOS

PDIC process.

The unit functions by converting optical signals into

electric ones with data rate up to 16Mbps at least.

The unit is operated at 5V and the signal output

interface is TTL compatible with high performance at

low power consumption.

Applications

1. Digital Optical Data-Link

2. Dolby AC-3 Digital Audio Interface

EVERLIGHT ELECTRONICS CO., LTD. http://www.everlight.com Rev 1.1 Page: 2 of 7

Device NO: DPL-152-002 Prepared Date:04-23-2004 Prepared By: Chin-Chia Hsu

PLR152 Series

Package Dimensions

0.50±0.05

A'

5.70±0.1

Front View Side View

2.20±0.1

4.95±0.1

0.25±0.03

2.48

0.90

12.45Max.

7.50

6.60

5.08

2.54

2

31

R0.65

A

1.50

PIN FUNCTION:

3.Vcc

2.GND

1.Vout

Rear View

R1.40

AT

Notes: 1.All dimensions are in mm.

2.General Tolerance: Pin length tolerance is ±0.25 mm

others are ±0.10 mm

3.Leadframe Material: Alloy C194

4.Plating Thickness: Tin Layer>2um

5.It must be placed a 0.47uF capacitor in the between of Vcc and GND within 2mm.

6.Device Selection Table:

Device Name Pin Length A1 (mm)

PLR152 12.55±0.25

PLR152/S1 7.50±0.25

PLR152/S2 5.22±0.25

PLR152/S3 10.20±0.25

EVERLIGHT ELECTRONICS CO., LTD. http://www.everlight.com Rev 1.1 Page: 3 of 7

Device NO: DPL-152-002 Prepared Date:04-23-2004 Prepared By: Chin-Chia Hsu

PLR152 Series

Absolute Maximum Ratings( Ta = 25℃)

Parameter Symbol Rating Unit

Supply Voltage Vcc 6 V

Output Voltage Vout Vcc+0.3 V

Storage Temperature Tstg -40 to 85 ℃

Operating Temperature Topr -20 to 70 ℃

Soldering Temperature Tsol 260* ℃

* Soldering time ≤ 10 s.

Electro-Optical Characteristics(Ta=-10~70℃，Vcc=5±0.25V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Power supply voltage Vcc - 4.75 5.00 5.25 V

Peak sensitivity wavelength λp - - 650 - nm

Maximum receiver power Pc,max Refer to Fig.1 - - -14

dBm

Minimum receiver power Pc,min Refer to Fig.1 -27 - -

dBm

Dissipation current Icc Refer to Fig.2 - 4 12

mA

High level output voltage VOH Refer to Fig.3 2.4 4.8 - V

Low level output voltage VOL Refer to Fig.3 - 0.2 0.4

V

Rise time tr Refer to Fig.3 10 20

ns

Fall time tf Refer to Fig.3 15 20

ns

Propagation delay Low to High tpLH Refer to Fig.3 - - 120 ns

Propagation delay High to Low tpHL Refer to Fig.3 - - 120 ns

Pulse Width Distortion ∆tw Refer to Fig.3 -30 - +30 ns

Refer to Fig.3，Pc=-14dBm - 1 30 ns

Jitter ∆tj Refer to Fig.3，Pc=-24dBm - - 30 ns

Transfer rate T NRZ signal

0.1 - 16

Mb/s

EVERLIGHT ELECTRONICS CO., LTD. http://www.everlight.com Rev 1.1 Page: 4 of 7

Device NO: DPL-152-002 Prepared Date:04-23-2004 Prepared By: Chin-Chia Hsu

PLR152 Series

Measuring Method

*Fig.1 Measuring Method of Maximum and Minimum Input Power that Receiver Unit Need

Control Circuit

Standard Transmitter unit

Optical Power Meter

Standard plastic

optic fiber cable

PLR152 Receiver U n it

*Fig.2 Measuring Method of Dissipation Current

Vin

Standard Transmitter Unit

Signal

Input

16 Mbps NRZ "0101" successive signal input

Vcc GND

Standard plastic optic fiber cable

PLR152 Receiver Unit

5V

A

GND

0.47uF

Vcc Vout

47uH

EVERLIGHT ELECTRONICS CO., LTD. http://www.everlight.com Rev 1.1 Page: 5 of 7

Device NO: DPL-152-002 Prepared Date:04-23-2004 Prepared By: Chin-Chia Hsu

PLR152 Series

*Fig.3 Measuring Method of Output Voltage, Pulse and Jitter

Output

Vin

Standard Transmitter Unit

Input

Signal

Input

tw = TPHL-TPLH

tj2tj1

50%

50% CH2

T

TPLH PHL

0.1uF

Vcc GND

CH1

Standard plastic optic fiber cable

5V

A

GND

Vcc Vout

4.7uH 0.47uF

PLR152 Receiver Unit

16 Mbps NRZ "0101" suc ce ssive signa l input

Application Circuit

L2:47uH

C1:0.47uF

Vout

5V

L2

Vcc GND

C1

Receiver Unit

Note: For having good coupling, the C1 capacitor must be placed within 2mm

EVERLIGHT ELECTRONICS CO., LTD. http://www.everlight.com Rev 1.1 Page: 6 of 7

Device NO: DPL-152-002 Prepared Date:04-23-2004 Prepared By: Chin-Chia Hsu

PLR152 Series

RELIABILITY TEST ITEMS

Test Sample Size Number (n)

No. Item Test Condition

Hour/Cycle (Piece) Failure (c)

1 Soldering Heat 260℃±5℃ 10 seconds 22 n=22, c=0

2 High Temp. Storage Ta=100℃ 1000hrs 22 n=22, c=0

3 Low Temp. Storage Ta=-55℃ 1000hrs 22 n=22, c=0

High Temp. &

4 Humid. Test Ta=85℃, RH=85% 1000hrs 22 n=22, c=0

-40℃ ~~~~ 85℃

5 Temperature Cycle (30min) (5min) (30min) 300cycle 22 n=22, c=0

-10℃ ~~~~ 100℃

6 Thermal Shock (5min) (10sec) (5min) 300cycle 22 n=22, c=0

7 DC Operating Life Vcc=5V, Ta=25℃ 1000hrs 22 n=22, c=0

EVERLIGHT ELECTRONICS CO., LTD. http://www.everlight.com Rev 1.1 Page: 7 of 7

Device NO: DPL-152-002 Prepared Date:04-23-2004 Prepared By: Chin-Chia Hsu

PLR152 Series

Application Notes: PLR152 Series PCB layout for motherboard integration

To achieve better jitter and low input optical power performances, several PCB

layout guidelines must be followed. These guidelines ensure the most reliable

PLR152 POF performance for the motherboard integration. Failed to implement

these PCB guidelines may affect the PLR152 jitter and low input power

performances.

1. Careful decoupling of the power supplies is very important. Place a 0.47uf surface mount

(size 805 or smaller) capacitor as close as (less than 2cm) to the POF Vdd and Gnd leads. The

0.47uf act as a low impedance path to ground for any stray high frequency transient noises.

2. To reduce the digital noises form the digital IC on the motherboard, the planar capacitance

formed by an isolated Vcc and Gnd planes is critical. The POF device must be mounted directly

on these two planes to reduce the lead parasitic inductance.

3. The isolated Vdd and Gnd planes must be connected to the main Vcc and Gnd (digital)

planes at a single point using ferrite beads. The beads are used to block the high frequency noises

from the digital planes while still allowing the DC connections between the planes

E

VERLIGHT ELECTRONICS CO., LTD. Tel: 886-2-2267-2000, 2267-9936

Office: No 25, Lane 76, Sec 3, Chung Yang Rd, Fax:886-2-2269-8114, 2267-6189, 2267-6306

Tucheng, Taipei 236, Taiwan, R.O.C http://www.everlight.com