FEATURES
0.3 INCH (7.62 mm ) DIGIT HEIGHT.
FOUR-DIGIT,RIGHT HAND DECIMAL.
WIDE SUPPLY VOLTAGE OPERATION.
SERIAL DATA INPUT.
CONSTANT CURRE NT DRIV ERS.
CONTINUOUS BRIGHTNESS CONTROL.
OUTPUT AVAILABLE FOR TWO EXTERNAL LEDS.
WIDE VIEWING ANGLE.
TTL COMPAT IBLE.
DESCRIPTION
The LTM-8328PKR-04 is a 0.3 inch (7.62mm) digit
display. It has a built-in M5450 MOS IC that contains
serial data input and 35 bit shift control. The MOS IC
produced with N-channel silicon gate technology. This
device utilizes bright red LED chips, which are made
from GaP on a transparent GaP substrate. Have black
face with diffusion tape.
DEVICE
PART NO DESCRIPTION
Bright red
LTM-8328PKR-04
FOUR DIGIT R.H.D.P,
WITH I.C DRIVER
PACKAGE DIMENSIO NS
NOTES: All dimensions are in millimeters. Tolerances are ±0.25mm(0.01“) unless otherwise noted.
PIN CONNECTION
NO. CONNECTION NO. CONNECTION
1EXT LED16 V
DD
2 EXT LED2 7 DIMMER
3 DATA ENABLE 8 GND
4 DATA SERIAL 9 VLED
5CLOCK
SERIAL DATA INPUT SEQUENCE
BIT DIGIT SEGMENT BIT DIGIT SEGMENT
11 A 183 B
21 B 193 C
31 C 203 D
41 D 213 E
51 E 223 F
61 F 233 G
71 G 243 DP
81 DP254 A
92 A 264 B
10 2 B 27 4 C
11 2 C 28 4 D
12 2 D 29 4 E
13 2 E 30 4 F
14 2 F 31 4 G
15 2 G 32 4 DP
16 2 DP 33 LED1
17 3 A 34 LED2
ABSOL UTE MAXIMUM RATING AT TA=25oC
PARAMETER SYMBOL MIN. MAX. UNIT
Supply Voltage VDD -0.3 12 V
Input Voltage VI-0.3 12 V
Off State Output Volt ag e VO(off) 12 V
LED Supply Voltage VLED 2.8 3.5 V
Power Dissipation of IC PD(IC) 335 mW
Supply Current IDD 8.5 mA
Operating Temperatur e
Range TOP -20 +60 0C
Storage Te mp er ature Range Tstg -20 +60 0C
Solder Tem per at ur e:
inch Below Seating Plane for 3 Seconds at 2600C
NOTE:1.All Voltages are with respect to VSS(GND).
2.Power dissipation of IC is given by PD =( VLED - VF) • (IF) • (NO. of Segments)
+ (8.5mA)
• (VDD)
* VF is LED forward voltage.
RECOMMENDED OPERATING CONDITION AT TA=25oC
PARAMETER SYMBOL MIN. TYP. MAX. UNIT TEST CONDITION
Supply Voltage VDD 4.75 11 V
Input Voltage
Logical “0” Level
Logical “1” Level
Logical “1” Level VI-0.3
2.2
VDD-2
0.8
VDD
VDD
V
V
V
±10uA Input Bias
4.75V< VDD<5.25V
V
DD > 5.25V
Brightness Input Current IB00.75mA
Brightness Input Voltage VB3 4.3 V Input Current
=750uA
Off State Voltage VO(off) 11 V
Ouput Sink Current
Segment Off
Segment On
Input Clock Frequency FCLOCK 0
3
6
10
0.5
uA
mA
mA
MHZ
IB=0uA
IB=100uA
IB=200uA
Ouput Matching IO±20 %
ELECTRICAL OPTIC AL CHARACTERISTICS AT TA=25oC
PARAMETER SYMBOL MIN. TYP. MAX. UNIT TEST CONDITION
Average Luminous Intensity Iv 79 155 ucd IB=0.4mA
Peak Emission Wavelength p697 nm IB=0.4mA
Spectral Line Hal f-Width ! 90 nm IB=0.4mA
Domina nt Waveleng th d638 nm IF=20mA
Luminous Intensity Matching Ratio Iv-m 2:1 IB=0.4mA
FUNCTION AL DESCRIPTION
Serial data transfer from the data source to the display driver is accomplished with 2
signals serial data and clock. Using a format of a leading “1” following by the 35 data bits
allows data transfer without an additional load signal. The 35 data bits are latched after the
36th bit is completed, thus providing non-multiplexed, direct drive to the display. Outputs
change only if the serial data bits differ from the previous time.
Brightness of display is determined by control the 0utput current of LED display. A 1nF
capacitor should be connected to brightness control, Pin 7 to prevent possible oscillations.
The output current is typically 25 times greater than the current into Pin 7 which is set by an
external variable resistor. There is an internal limiting resistor of 400Ω nominal value.
Figure 1 shows the input data format. A start bit of logical “1” proceed the 35 bits of data. At
the 36th clock, a LOAD signal is generated synchronously with the high state of the clock,
which loads the 35 bits of the shift registers into the latches. At the low state of the clock a
RESET signal is generated which clears all the shift registers for the next set of data. The
shift registers are static master-slave configuration. There is no clear for portion of the first
register, thus allowing continuous operation.
There must be a complete set of 36 clocks or the shift registers won’t clear. When power
is first applied to the chip an internal power ON reset signal is generated which reset all
registers and all latched. The ATART bit and first clock return the chip on its normal
operation. Bit 1 is the first following the start bit and it will appear on the Figure 2 shows the
timing relationship between data clock, and DATA ENABLE. A maximum clock frequency of
0.5 MHz is assumed.
FIGURE.1 Input Data Format
FIGURE.2 Timi ng Rel ationship
