S-8243AADFT-TB-G - Seiko Instruments

S-8243A/B Series

www.sii-ic.com

BATTERY PROTECTION IC

FOR 3-SERIAL OR 4-SERIAL CELL PACK

Seiko Instruments Inc. 1

The S-8243A/B Series is a protection IC for lithium-ion rechargeable battery. The S-8243A Series protects 3-series, the S-8243B

Series protects 4-series cell pack from the overcharge, overdischarge, overcurrent voltages. This IC has a high-accuracy battery

protection circuit and a battery monitor amplifier, and also a voltage regulator w hich operates the microcomputer or gas gauge IC.

Combining this IC and a microcomputer or a gas gauge IC allow s to display the amount of charge remained in a battery .

 Features

(1) High-accuracy voltage detection for each cell

• Overcharge detection voltage n (n = 1 to 4)

3.9 V to 4.4 V (50 mV step) Accuracy ±25 mV

• Hysteresis voltage n (n = 1 to 4) of overcharge detection

−0.10 V to −0.40 V (50 mV step) or 0 V Accuracy ±50 mV

(Overcharge release voltage n (= Overcharge detection voltage n + Hysteresis voltage n) can be selected within

the range 3.8 V to 4.4 V.)

• Overdischarge detection voltage n (n = 1 to 4)

2.0 V to 3.0 V (100 mV step) Accuracy ±80 mV

• Hysteresis voltage n (n = 1 to 4) of overdischarge detection

0.15 V to 0.70 V or 0 V (50 mV step) Accuracy ±100 mV

(Overdischarge release voltage n (

Overdischarge detection voltage n + Hysteresis voltage n) can be selected

within the range 2.0 V to 3.4 V.)

(2) Three-level overcurrent protection including protection for short-circuiting

• Overcurrent detection voltage 1 0.05 V to 0.3 V (50 mV step) Accuracy ±25 mV

• Overcurrent detection voltage 2 0.5 V Accuracy ±100 mV

• Overcurrent detection voltage 3 VDD / 2 Accuracy ±15 %

(3) Delay times for overcharge detection, overdischarge detection and overcurrent detection 1 can be set by external

capacitors. (Delay times for overcurrent detection 2 and 3 are fixed internally.)

(4) Charge/discharge operation can be controlled through the control pins.

(5) High-accuracy battery monitor amp GAMP = VBATTERY × 0.2 ±1.0%

(6) Voltage regulator VOUT = 3.3 V ±2.4 % (3 mA max.)

(7) High input-voltage device Absolute maximum rating: 26 V

(8) Wide operating voltage range 6 V to 18 V

(9) Wide operating temperature range: −40°C to +85°C

(10) Low current consumption

• Operation mode 120 μA max.

• Power down mode 0.1 μA max.

(11) Lead-free, Sn 100%, halogen-free*1

*1. Refer to “ Product Name Structure” for details.

 Applications

• Lithium-ion rechargeable battery packs

• Lithium polymer rechargeable battery packs

 Package

• 16-Pin TSSOP

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

 Block Diagrams

1. S-8243A Series

Battery protection

VC3

VC2

VC1

VDD

DOP

COP

VMP

VREG

VBATOUT

200 nA

CTL1

CTL2

CTL3

1.4 MΩ

1 MΩ

5 MΩ

CTL4

VREG

Delay

control

RVCM,RVSM

DOP,COP,

Delay

Batter y mo nitor amp

Voltage

regulator

1.4 MΩ

660 kΩ

440 kΩ

CCT

VSS

CDT

Battery

selection

Remark1. Diodes in the figure are parasitic diodes.

2. Numerical values are typical values.

Figure 1

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 3

2. S-8243B Series

Battery protection

VC3

VC2

VC1

VDD

DOP

COP

VMP

VREG

VBATOUT

200 nA

CTL1

CTL2

CTL3

1.4 MΩ

1 MΩ

5 MΩ

CTL4

VREG

Delay

control

RVCM, RVSM

DOP, COP,

Delay

Battery monitor amp

Voltage

regulator

1.4 MΩ

660 kΩ

440 kΩ

CCT

VSS

CDT

Battery

selection

Remark1. Diodes in the figure are parasitic diodes.

2. Numerical values are typical values.

Figure 2

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

 Product Name Structure

1. Product Name

S-8243 x xx FT - TB − x

Environmental code

U : Lead-f ree (Sn 100% ), halogen-free

G : Lead-free (for details, please contact our sales office)

IC direction in tape specifications*1

Package name (abbreviation)

FT: 16-Pin TSSOP

Serial code*2

Sequentially set from AA to ZZ

Product series name

A : 3-cell

B : 4-cell

*1. Refer to the tape specif ications at the end of this book.

*2. Refer to the “3. Product Name List”.

2. Package

Drawing Code

Package Name Package Tape Reel

Environmental code = G FT016-A-P-SD FT016-A-C-SD FT016-A-R-SD

16-Pin TSSOP Environmental code = U FT016-A-P-SD FT016-A-C-SD FT016-A-R-S1

3. Product Name List

Table 1 S-8243A Series (For 3-Serial Cell)

Product name / Item Overcharge

detection voltage

]

Hysteresis voltage for

overcharge detection

]

Overdischarge

detection voltage

]

Hysteresis voltage for

overdischarge detection

]

Overcurrent

detection voltage1

IOV1

]

0 V battery

charging

function

S-8243AACFT-TB-x 4.350

0.025 V

−

0.15

0.05 V 2.40

0.08 V 0.20

0.10 V 0.20

0.025 V Available

S-8243AADFT-TB-x 4.350

0.025 V

−

0.35

0.05 V 2.40

0.08 V 0 V 0.20

0.025 V Available

Table 2 S-8243B Series (For 4-Serial Cell)

Product name / Item Overcharge

detection voltage

]

Hysteresis voltage for

overcharge detection

]

Overdischarge

detection voltage

]

Hysteresis voltage for

overdischarge detection

]

Overcurrent

detection voltage1

IOV1

]

0 V battery

charging

function

S-8243BADFT-TB-x 4.350

0.025 V

−

0.25

0.05 V 2.40

0.08 V 0 V 0.25

0.025 V Available

S-8243BAEFT-TB-x 4.350

0.025 V

−

0.15

0.05 V 2.40

0.08 V 0.20

0.10 V 0.20

0.025 V Available

S-8243BAFFT-TB-x 4.250

0.025 V

−

0.25

0.05 V 2.40

0.08 V 0 V 0.20

0.025 V Available

S-8243BAHFT-TB-x 4.315

0.025 V

−

0.20

0.05 V 2.00

0.08 V 0.15

0.10 V 0.20

0.025 V Available

Remark 1. Change in the detection voltage is available in products other than listed above. Cont act our sales office.

2. x: G or U

3. Please select products of environmental code = U for Sn 100%, halogen-free products.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 5

 Pin Configuration

16-Pin TSSOP

Top view

VDD

DOP

COP

VMP

VC1

VC2

VC3

VSS

VREG

CTL1

CTL2

CTL3

CTL4

VBATOUT

CCT

CDT

Figure 3

Table 3 Pin description (S-8243A Series)

Pin No. Symbol Description

1 VDD

Input pin for positive power supply, Connection pin for battery 1’s positive voltage

2 DOP Connection pin for discharge control FET gate (CMOS output)

3 COP Connection pin for charge control FET gate (Nch open drain output)

4 VMP Pin for voltage detection between VDD-VMP pin (Pin for overcurrent detection)

5 VC1 No connection

6 VC2

Connection pin for battery 1’s negative voltage, for battery 2’s positive voltage

7 VC3

Connection pin for battery 2’s negative voltage, for battery 3’s positive voltage

8 VSS

Input pin for negative power supply, Connection pin for battery 3’s negative voltage

9 CDT

Connection pin to capacitor for overdischarge detection delay, for overcurrent detection delay 1

10 CCT Connection pin to capacitor for overcharge detection delay

11 VBATOUT Output pin for battery voltage and offset voltage

12 CTL4 Pin for selecting output from VBATOUT pin

13 CTL3 Pin for selecting output from VBATOUT pin

14 CTL2 Control pin for charge / discharge FET

15 CTL1 Control pin for charge / discharge FET

16 VREG Output pin for voltage regulator (3.3 V)

Table 4 Pin description (S-8243B Series)

Pin No. Symbol Description

1 VDD Input pin for positive power supply, Connection pin for battery 1’s positive voltage

2 DOP

Connection pin for discharge control FET gate (CMOS output)

3 COP

Connection pin for charge control FET gate (Nch open drain output)

4 VMP

Pin for voltage detection between VDD-VMP pin (Pin for overcurrent detection)

5 VC1

Connection pin for battery 1’s negative voltage, for battery 2’s positive voltage

6 VC2 Connection pin for battery 2’s negative voltage, for battery 3’s positive voltage

7 VC3 Connection pin for battery 3’s negative voltage, for battery 4’s positive voltage

8 VSS Input pin for negative power supply, Connection pin for battery 4’s negative voltage

9 CDT Connection pin to capacitor for overdischarge detection delay, for overcurrent detection delay 1

10 CCT

Connection pin to capacitor for overcharge detection delay

11 VBATOUT

Output pin for battery voltage and offset voltage

12 CTL4

Pin for selecting output from VBATOUT pin

13 CTL3

Pin for selecting output from VBATOUT pin

14 CTL2

Control pin for charge / discharge FET

15 CTL1

Control pin for charge / discharge FET

16 VREG

Output pin for voltage regulator (3.3 V)

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

 Absolute Maximum Ratings

Table 5 (Ta = 25°C unless otherwise specified)

Item Symbol Applied Pins Absolute Maximum Ratings Unit

Input voltage VDD VDS − V

SS−0.3 to VSS+26 V

Input voltage VIN VC1, VC2, VC3, CCT,

CDT VSS−0.3 to VDD+0.3 V

VMP pin Input voltage VMP VMP VSS−0.3 to VSS+26 V

DOP pin output voltage VDOP DOP VSS−0.3 to VDD+0.3 V

COP pin output voltage VCOP COP VSS−0.3 to VSS+26 V

VREG pin output voltage VOUT VREG VSS−0.3 to VDD+0.3 V

CTL1 pin input voltage VCTL1 CTL1 VSS−0.3 to VDD+0.3 V

CTL2 to CTL4 pin input voltage VCTLn CTL2, CTL3, CTL4 VSS−0.3 to VOUT+0.3 V

Cell voltage output voltage VBATOUT VBATOUT VSS−0.3 to VOUT+0.3 V

− 300 (When not mounted on board) mW

Power dissipation PD − 1100*1 mW

Operation ambient temperature Topr − −40 to +85 °C

Storage temperature Tstg − −40 to +125 °C

*1. When mounted on board

[Mounted board]

(1) Board size : 114.3 mm × 76.2 mm × t1.6 mm

(2) Board name : JEDEC STANDARD51-7

Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical

damage. These values must therefore not be exceeded under any conditions.

0 50 100

150

800

400

Power Dissipation (P

) [mW]

Ambient Temperature (Ta) [°C]

1000

600

200

1200

Figure 4 Pow er Dissipation of Package (When Mounted on Board)

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 7

 Electrical Characteristics

1. S-8243A Series

Table 6 (1 / 2) (Ta

25°C unless otherwise specified)

Item Symbol Conditions Min. Typ. Max. Unit Test circuit

BATTERY PROTECTION

Overcharge detection voltage n

n=1, 2, 3 V

CUn

3.9 V to 4.4 V, 50 mV Step V

CUn

−

0.025 V

CUn

0.025 V 4

Hysteresis voltage n of overcharge

detection

= 1, 2, 3 V

HCn

−

0.10 V to

−

0.40 V, and 0 V V

HCn

−

0.05 V

HCn

0.05 V 4

Overdischarge detection voltage

= 1, 2, 3 V

DLn

2.0 V to 3.0 V, 100 mV Step V

DLn

−

0.08 V

DLn

0.08 V 4

Hysteresis voltage n of

Overdischarge detection

= 1, 2, 3 V

HDn

0.15 V to 0.70 V, and 0 V V

HDn

−

0.10 V

HDn

0.10 V 4

Overcurrent detection voltage 1 V

IOV1

0.05 V to 0.3 V, 50 mV Step

VM voltage based on V

IOV1

−

0.025 V

IOV1

0.025 V 4

Overcurrent detection voltage 2 V

IOV2

VM voltage based on V

0.40 0.50 0.60 V 4

Overcurrent detection voltage 3 V

IOV3

−

0.425 V

0.5 V

0.575 V 4

Temperature coefficient for

detection and release voltage

COE1

Ta =

−

C to

−

1.0 0 1.0 mV/

C 4

Temperature coefficient for

overcurrent detection voltage

COE2

Ta =

−

C to

−

0.5 0 0.5 mV/

C 4

0 V BATTERY CHARGING FUNCTION

(The 0 V battery function is either "0 V battery charging is allowed." or "0 V battery charging is inhibited."

depending upon the product type.)

0 V battery charge starting charger

voltage V

0CHA

0 V battery charging available

−

0.8 1.5 V 7

0 V battery charge inhibition battery

voltage V

0INH

0 V battery charging unavailable 0.4 0.7 1.1 V 7

INTERNAL RESISTANCE

Internal resistance between

VMP and VDD R

VDM

V1 = V2 = V3 = 3.5 V 500 1100 2400 k

Internal resistance between

VMP and VSS R

VSM

V1 = V2 = V3 = 1.8 V 300 700 1500 k

VOLTAGE REGULATOR

Output voltage V

OUT

= 14 V, I

OUT

= 3 mA 3.221 3.300 3.379 V 2

Line regulation

OUT1

= 6 V

→

18 V, I

OUT

= 3 mA

−

5 15 mV 2

Load regulation

OUT2

= 14 V, I

OUT

= 5

→

3 mA

−

15 30 mV 2

BATTERY MONITOR AMP

Input offset voltage n

= 1, 2, 3 V

OFFn

V1 = V2 = V3 = 3.5 V 60 165 270 mV 3

Voltage gain n

= 1, 2, 3 GAMPn V1 = V2 = V3 = 3.5 V 0.2

0.99 0.2 0.2

1.01

−

INPUT VOLTAGE, OPERATING VOLTAGE

Operating voltage between

and V

DSOP

−

18 V 4

CTL1 input voltage for High V

CTL1H

−

0.8

−

V 6

CTL1 input voltage for Low V

CTL1L

−

0.2 V 6

CTLn input voltage for High

n = 2, 3, 4 V

CTLnH

−

OUT

0.9

−

OUT

V 3, 6

CTLn input voltage for Low

n = 2, 3, 4 V

CTLnL

−

OUT

0.1 V 3, 6

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

Table 6 (2 / 2)

Item Symbol Remarks Min. Typ. Max. Unit Test circuit

INPUT CURRENT

Current consumption at not

monitoring V

BATOUT

OPE

V1 = V2 = V3 = 3.5 V, V

= V

−

65 120

A 1

Current consumption at power down I

PDN

V1 = V2 = V3 = 1.5 V, V

= V

− −

0.1

A 1

Current for VCn at not monitoring

BATOUT

(n = 2, 3) I

VCnN

V1 = V2 = V3 = 3.5 V

−

0.3 0 0.3

A 3

Current for VC2 at monitoring of

BATOUT

VC2

V1 = V2 = V3 = 3.5 V

−

2.0 7.2

A 3

Current for VC3 at monitoring of

BATOUT

VC3

V1 = V2 = V3 = 3.5 V

−

1.0 4.0

A 3

Current for CTL1 at Low I

CTL1L

V1 = V2 = V3 = 3.5 V, V

CTL1

= 0 V

−

0.4

−

0.2

−

A 5

Current for CTLn at High

n = 2,3,4 I

CTLnH

CTLn

= V

OUT

−

2.5 5

A 9

Current for CTLn at Low

n = 2,3,4 I

CTLnL

CTLn

= 0 V

−

2.5

−

A 9

OUTPUT CURRENT

Leak current COP I

COH

COP

= 24 V

−

0.1

A 9

Sink current COP I

COL

COP

= V

0.5 V 10

−

A 9

Source current DOP I

DOH

DOP

= V

−

0.5 V 10

−

A 9

Sink current DOP I

DOL

DOP

= V

0.5 V 10

−

A 9

Source current V

BATOUT

VBATH

BATOUT

= V

−

0.5 V 100

−

A 9

Sink current V

BATOUT

VBATL

BATOUT

= V

0.5 V 100

−

A 9

Applied to S-8243AACFT and S-8243AADFT

Item Symbol Conditions Min. Typ. Max. Unit Test circuit

DELAY TIME

Overcharge detection delay time t

= 0.1

F 0.5 1.0 1.5 s 5

Overdischarge detection delay time t

= 0.1

F 50 100 150 ms 5

Overcurrent detection delay time 1 t

lOV1

= 0.1

F 5 10 15 ms 5

Overcurrent detection delay time 2 t

lOV2

−

1.5 2.5 4.0 ms 4

Overcurrent detection delay time 3 t

lOV3

−

100 300 600

s 4

*1.

Temperature coefficient for detection and release voltage is applied to overcharge detection voltage n, overcharge release voltage n, overdischarge

detection voltage n, and overdischarge release voltage n.

*2.

Temperature coefficient for overcurrent detection voltage is applied to over current detection voltage 1 and 2.

*3.

Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in

production.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 9

2. S-8243B Series

Table 7 (1 / 2) (Ta

25°C unless otherwise specified)

Item Symbol Conditions Min. Typ. Max. Unit Test circuit

DETECTION VOLTAGE

Overcharge detection voltage n

n = 1, 2, 3, 4 V

CUn

3.9 V to 4.4 V, 50 mV Step V

CUn

−

0.025 V

Cun

CUn

0.025 V 4

Hysteresis voltage n of overcharge

detection

n = 1, 2, 3, 4 V

HCn

−

0.10 V to

−

0.40 V, and 0 V V

HCn

−

0.05 V

HCn

0.05 V 4

Overdischarge detection voltage

n = 1, 2, 3, 4 V

DLn

2.0 V to 3.0 V, 100 mV Step V

DLn

−

0.08 V

DLn

0.08 V 4

Hysteresis voltage n of

overdischarge detection

n = 1, 2, 3, 4 V

HDn

0.15 V to 0.70 V, and 0 V V

HDn

−

0.10 V

HDn

0.10 V 4

Overcurrent detection voltage 1 V

IOV1

0.05 V to 0.3 V, 50 mV Step

VM voltage based on V

IOV1

−

0.025 V

IOV1

0.025 V 4

Overcurrent detection voltage 2 V

IOV2

VM voltage based on V

0.40 0.50 0.60 V 4

Overcurrent detection voltage 3 V

IOV3

−

0.425 V

0.5 V

0.575 V 4

Temperature coefficient for

detection and release voltage

COE1

Ta =

−

C to

−

1.0 0 1.0 mV/

C 4

Temperature coefficient for

overcurrent detection voltage

COE2

Ta =

−

C to

−

0.5 0 0.5 mV/

C 4

0 V BATTERY CHARGING FUNCTION

(The 0 V battery function is either "0 V battery charging is allowed." or "0 V battery charging is inhibited.

depending upon the product type.)

0 V battery charge starting charger

voltage V

0CHA

0 V battery charging allowed

−

0.8 1.5 V 7

0 V battery charge inhibition battery

voltage V

0INH

0 V battery charging inhibited 0.4 0.7 1.1 V 7

INTERNAL RESISTANCE

Internal resistance between

VMP and VDD R

VDM

V1 = V2 = V3 = V4 = 3.5 V 500 1100 2400 k

Internal resistance between

VMP and VSS R

VSM

V1 = V2 = V3 = V4 = 1.8 V 300 700 1500 k

VOLTAGE REGULATOR

Output voltage V

OUT

= 14V, I

OUT

= 3 mA 3.221 3.300 3.379 V 2

Line regulation

OUT1

= 6 V

→

18 V, I

OUT

= 3 mA

−

5 15 mV 2

Load regulation

OUT2

= 14 V, I

OUT

= 5

→

3 mA

−

15 30 mV 2

BATTERY MONITOR AMP

Input offset voltage n

n = 1, 2, 3, 4 V

OFFn

V1 = V2 = V3 = V4 = 3.5 V 60 165 270 mV 3

Voltage gain n

n = 1, 2, 3, 4 GAMPn V1 = V2 = V3 = V4 = 3.5 V 0.2

0.99 0.2 0.2

1.01

⎯

INPUT VOLTAGE, OPERATING VOLTAGE

Operating voltage between

and V

DSOP

−

18 V 4

CTL1 input voltage for High V

CTL1H

−

0.8

−

V 6

CTL1 input voltage for Low V

CTL1L

−

0.2 V 6

CTLn input voltage for High

n = 2, 3, 4 V

CTLnH

−

OUT

0.9

−

OUT

V 3, 6

CTLn input voltage for Low

n = 2, 3, 4 V

CTLnL

−

OUT

0.1 V 3, 6

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

Table 7 (2 / 2)

Item Symbol Remarks Min. Typ. Max. Unit Test circuit

INPUT CURRENT

Current consumption at not

monitoring V

BATOUT

OPE

V1 = V2 = V3 = V4 = 3.5 V, V

= V

−

65 120

A 1

Current consumption at power down I

PDN

V1 = V2 = V3 = V4 = 1.5 V, V

= V

−

0.1

A 1

Current for VCn at not monitoring

BATOUT

(n = 2, 3) I

VCnN

V1 = V2 = V3 = V4 = 3.5 V

−

0.3 0 0.3

A 3

Current for VC1 at monitoring of

BATOUT

VC1

V1 = V2 = V3 = V4 = 3.5 V

−

3.2 10.4

A 3

Current for VC2 at monitoring of

BATOUT

VC2

V1 = V2 = V3 = V4 = 3.5 V

−

2.0 7.2

A 3

Current for VC3 at monitoring of

BATOUT

VC3

V1 = V2 = V3 = V4 = 3.5 V, V

CTL1

= 0 V

−

1.0 4.0

A 3

Current for CTL1 at Low I

CTL1L

V1 = V2 = V3 = V4 = 3.5 V, V

CTL1

= 0 V

−

0.4

−

0.2

−

A 5

Current for CTLn at High

n = 2, 3, 4 I

CTLnH

CTLn

= V

OUT

−

2.5 5

A 9

Current for CTLn at Low

n = 2, 3, 4 I

CTLnL

CTLn

= 0 V

−

2.5

−

A 9

OUTPUT CURRENT

Leak current COP I

COH

COP

= 24 V

−

0.1

A 9

Sink current COP I

COL

COP

= V

0.5 V 10

−

A 9

Source current DOP I

DOH

DOP

= V

−

0.5 V 10

−

A 9

Sink current DOP I

DOL

DOP

= V

0.5 V 10

−

A 9

Source current V

BATOUT

VBATH

BATOUT

= V

−

0.5 V 100

−

A 9

Sink current V

BATOUT

VBATL

BATOUT

= V

0.5 V 100

−

A 9

Applied to S-8243BAEFT, S-8243BAFFT, S-8243BAHFT

Item Symbol Conditions Min. Typ. Max. Unit Test circuit

DELAY TIME

Overcharge detection delay time t

= 0.1

F 0.5 1.0 1.5 s 5

Overdischarge detection delay time t

= 0.1

F 50 100 150 ms 5

Overcurrent detection delay time 1 t

lOV1

= 0.1

F 5 10 15 ms 5

Overcurrent detection delay time 2 t

lOV2

−

1.5 2.5 4.0 ms 4

Overcurrent detection delay time 3 t

lOV3

−

100 300 600

s 4

Applied to S-8243BADFT

Item Symbol Conditions Min. Typ. Max. Unit Test circuit

DELAY TIME

Overcharge detection delay time t

= 0.1

F 0.5 1.0 1.5 s 5

Overdischarge detection delay time t

= 0.1

F 55.5 111 222 ms 5

Overcurrent detection delay time 1 t

lOV1

= 0.1

F 3.31 6.62 13.2 ms 5

Overcurrent detection delay time 2 t

lOV2

−

1.5 2.5 4.0 ms 4

Overcurrent detection delay time 3 t

lOV3

−

100 300 600

s 4

*1.

Temperature coeffi cient for detection and release voltage is applied to overcharge detection vol tage n, overcharge release vol tage n, overdischarge

detection voltage n, and overdischarge release voltage n.

*2.

Temperature coefficient for overcurrent detection voltage is applied to over current detection voltage 1 and 2.

*3.

Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in

production.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 11

 Test Circuits

In this chapter test methods are explained for the case of S-8243B series, which is designed for 4-serial cell pack. For the

case of S-8243A series, which is designed for 3-serial cell, voltage source V2 should be shorted, V3 should be read as V2,

and V4 as V3.

1. Current consumption (Test circuit 1)

Current consumption at not monitoring VBATOUT, IOPE, is a current measured at the VSS pin when V1 = V2 = V3 = V4 =

3.5 V and VMP = VDD. Current consumption at power down, IPDN, is a current measured at the VSS pin when V1 = V2 =

V3 = V4 = 1.5 V and VMP = VSS.

2. Voltage regulator (Test circuit 2)

Output voltage of the regulator VOUT is a voltage measured at the VREG pin when VDD = VMP = 14 V and IOUT = 3 mA.

Line regulation of the voltage regulator ΔVOUT1 is defined by the equation ΔVOUT1 = VOUT2−VOUT1 where VOUT1 is the

output voltage when VDD = VMP = 6 V and IOUT = 3 mA, and VOUT2 is the output voltage when VDD = VMP = 18 V and IOUT

= 3 mA.

Load regulation of the regulator is defined by the equation ΔVOUT2 = VOUT3−VOUT where VOUT3 is the output voltage when

VDD = VMP = 14 V and IOUT = 5 μA.

3. Battery monitor amp and pin current for VC1 to VC3 (Test circuit 3)

Voltage gain of the battery monitor amp for each cell is defined by the input offset voltage and the measurement result

provided from the VBATOUT pin for the combination of the CTL3 pin and CTL4 pin expressed by the following table at

the condition where V1 = V2 = V3 = V4 = 3.5 V. Pin current for VC1 to VC3, IVCn and IVCnN are at the same time

measured.

Table 8

CTL3 pin status CTL4 pin status VBATOUT pin output VCn (n = 1, 2, 3) pin current

VCTL3H min. VCTL4H min. VOFF1 I

VC1 at VC1 pin

VCTL3H min. Open VBAT1

−

VCTL3H min. VCTL4L max. VOFF2 I

VC2 at VC2 pin

Open VCTL4H min. VBAT2

−

Open Open VOFF3 I

VC3 at VC3 pin

Open VCTL4L max. VBAT3

−

VCTL3L max. VCTL4H min. VOFF4 I

VCnN at VCn pin (n = 1, 2, 3)

VCTL3L max. Open VBAT4

−

Voltage gain of the battery monitor amp for each cell is calculated by the equation

GAMPn = (VBATn−VOFFn) / Vn (n = 1 to 4)

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

4. Overcharge detection voltages, overcharge detection hysteresis, overdischarge detection

voltages, overdischarge detection hysteresis, and overcurrent detection voltages (Test circuit 4)

4. 1 Overcharge detection vo ltag es, hysteresis voltages, and overdischarge detection voltages

In the following VMP = VDD and the CDT pin is open.

The COP pin and the DOP pin should provide “Low”, w hich is a voltage equal to VDD × 0.1 V or lower, in the condition

that V1 = V2 = V3 = V4 = 3.5 V.

The overcharge detection voltage VCU1 is defined by the voltage at which COP pin voltage becomes “High”, which is

a voltage equal to VDD × 0.9 V or higher, when the voltage V1 is gradually increased from the starting condition V1

= 3.5 V. The overcharge release voltage VCL1 is defined by the voltage at wh ich COP pin voltage becomes “Low”

when the voltage V1 is gradually decreased. The hysteresis voltage of the overcharge detection VHC1 is then defined

by the difference between the overcharge detection voltage V CU1 and the overcharge release voltage VCL1.

The overdischarge detection voltage VDL1 is defined by the voltage at which DOP pin voltage becomes “High” when

the voltage V1 is gradually decreased from the starting condition V1 = 3.5 V. The overdischarge release voltage

VDU1 is defined by the voltage at wh ich DOP pin voltage becomes “Low” w hen the voltage V1 is gradually increased.

The hysteresis of the overdischarge detection voltage VHD1 is then defined by the difference between the

overdischarge release voltage VDU1 and the overdischarge detection voltage VDL1.

Other overcharge detection voltage VCUn, hysteresis voltage of overcharge detection VHCn, overdischarge detection

voltage VDLn, and hysteresis of the overdischarge detection voltage VHDn ( for n = 2 to 4) are defined in the same

manner as in the case for n = 1.

4. 2 Overcurrent detection voltages

Starting condition is V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and the CDT pin is open. T he DOP pin voltage thus

provides “Low”

The overcurrent detection voltage 1, VIOV1 is defined by the voltage difference VDD − VMP at which the DOP pin

voltage becomes “High” when the voltage of VMP pin is decreased.

Starting condition for measuring the overcurrent detection voltage 2 and 3 is V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD

and the CDT pin voltage VCDT = VSS . The DOP pin voltage thus provides “Low”.

The overcurrent detection voltage 2, VIOV2 is defined by the voltage difference VDD−VMP at which the DOP pin voltage

becomes “High” when the voltage of VMP pin is decreased.

The overcurrent detection delay time 2, tIOV2 is a time needed for the DOP pin to become “High” from “Low” w hen the

VM pin voltage is changed quickly to VIOV2 min.−0.2 V from the starting condition VMP = VDD.

The overcurrent detection voltage 3, VIOV3 is defined by the voltage of the VM pin at which the DOP pin voltage

becomes “High” when the voltage of VMP pin is decreased at the speed 10 V / ms.

The overcurrent detection delay time 3, tIOV3 is a time needed for the DOP pin to become “High” from “Low” w hen the

VM pin voltage is changed quickly to VIOV3 min.−0.2 V from the starting condition VMP = VDD.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 13

5. CTL1 pin current, overcharge detection delay, overdischarge detection delay, and overcurrent

detection delay 1 (Test circuit 5)

Starting condition is V1 = V2 = V3 = V4 = 3.5 V and VMP = VDD.

Current that flows between the CT L1 pin and VSS is the CTL1 pin current ICTL1L.

The overcharge detection delay time tCU is a time needed for the COP pin voltage to change from “Low” to “High” just

after the V1 voltage is rapidly increased from 3.5 V to 4.5 V.

The overdischarge detection delay time tDL is a time needed for the DOP pin voltage to change from “Low” to “High” just

after the V1 voltage is rapidly decreased from 3.5 V to 1.5 V.

The overcurrent detection delay time 1 is a time needed for the DOP pin voltage to change from “Low” to “High” just after

the VMP pin voltage is decreased from VDD to VDD−0.35 V when V1 = 3.5 V.

6. Input voltages for CTL1 and CTL2 (Test circuit 6)

Starting condition is V1 = V2 = V3 = V4 = 3.5 V.

Pin voltages of the COP and the DOP should be “High” when VCTL1 = VCTL1H min. and CTL2 is OPEN.

Pin voltages of the COP and the DOP should be “Low” when VCTL1 = VCTL1L max. and CTL2 is OPEN.

Pin voltage of the COP is “High” and the pin voltage of the DOP is “Low” when VCTL1 = VCTL1L max. and VCTL2 = VCTL2H

min.

Pin voltage of the COP is “Low” and the pin voltage of the DOP is “High” when VCTL1 = VCTL1L max. and VCTL2 = VCTL2L

max.

7. 0 V battery charge starting charger voltage and 0 V battery charge inhibition battery voltage (Test

circuit 7)

One of the 0 V battery charge starting charger voltage and 0 V battery charge inhibition battery voltage is

applied to each product according to the 0V battery charging function.

Starting condition is V1 = V2 = V3 = V4 = 0 V for a product in which 0 V battery charging is available.

The COP pin voltage should be lower than V0CHA max.−1 V when the VMP pin voltage VMP = V0CHA max.

Starting condition is V1 = V2 = V3 = V4 = V0INH for a product in which 0 V battery charging is inhibited.

The COP pin voltage should be higher than VMP−1 V when the VMP pin voltage VMP = 24 V.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

8. Internal resistance (Test circuit 8)

The resistance between VDD and VMP is RVDM and is calculated by the equation RVDM = VDD / IVDM w here IVDM is a VMP

pin current after VMP is changed to VSS from the starting condition V1 = V2 = V3 = V4 = 3.5 V and VMP = VDD.

The resistance between VSS and VMP is RVSM and is calculated by the equation RVSM = VDD / IVSM w here IVSM is a VMP

pin current at the condition V1 = V2 = V3 = V4 = 1.8 V and VMP = VDD.

9. Pin current for CTL2 to CTL4, COP, DOP, VBATOUT (Test circuit 9)

Starting condition is V1 = V2 = V3 = V4 = 3.5 V.

Pin current for CTL2 at “High” is ICTL2H and is obtained by setting VCTL2 = VOUT.

Pin current for CTL2 at “Low” is ICTL2L and is obtained by setting VCTL2 = VSS.

Pin current for CTL3 and CTL4 can be obtained in the same manner as in the CTL2.

Pin current for COP at “High” is ICOH and is obtained by setting V1 = V2 = V3 = V4 = 6 V, VMP = VDD, and VCOP = VDD. And

pin current for COP at “Low” is ICOL and is obtained by setting V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and VCOP = 0.5 V.

Pin current for DOP at “Low” is IDOL and is obtained by setting V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and VDOP = 0.5 V.

And pin current for COP at “High” is ICOH and is obtained by setting V1 = V2 = V3 =V4 = 3.5 V, VMP = VDD−1 V, and VDOP

= VDD−0.5 V.

Pin current for VBATOUT at “High” is IVBATH and is obtained by setting CTL3 and CTL4 are open and VBATOUT =

VOFF3−0.5 V. And pin current for VBATOUT at “Low” is IVBATL and is obtained by setting VBATOUT = VOFF3+0.5 V.

C1=1 μF

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

VREG 16

CDT 9

CCT 10

CTL4 12

CTL2 14

CTL1 15

CTL3 13

C1=1 μF IOUT

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

VREG 16

CDT 9

CCT 10

CTL4 12

CTL2 14

CTL1 15

CTL3 13

Test circuit 1 Test circuit 2

C1=1 μF

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

VREG 16

CDT 9

CCT 10

CTL4 12

CTL2 14

CTL1 15

CTL3 13

R1=1 MΩ

C1=1 μF

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

VREG 16

CDT 9

CCT 10

CTL4 12

CTL2 14

CTL1 15

CTL3 13

Test circuit 3 Test circuit 4

Figure 5 (1 / 2)

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 15

C2=0.1 μF

C1=1 μF C3=0.1 μF

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

VREG 16

CDT 9

CCT 10

CTL4 12

CTL2 14

CTL1 15

CTL3 13

C1=1 μF

R1=1 MΩ

V8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

VREG 16

CDT 9

CCT 10

CTL4 12

CTL2 14

CTL1 15

CTL3 13

Test circuit 5 Test circuit 6

R1=1 MΩ

C1=1 μF

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

VREG 16

CDT 9

CCT 10

CTL4 12

CTL2 14

CTL1 15

CTL3 13

C1=1 μF

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

VREG 16

CDT 9

CCT 10

CTL4 12

CTL2 14

CTL1 15

CTL3 13

Test circuit 7 Test circuit 8

C1=1 μF

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

VREG 16

CDT 9

CCT 10

CTL4 12

CTL2 14

CTL1 15

CTL3 13

Test circuit 9

Figure 5 (2 / 2)

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

 Operation

1. Battery protection circuit

Remark Refer to “ Battery Protection IC Connection Example”.

Battery protection protects batteries from overcharge and overdischarge, and also protects external FETs from

overcurrent.

1. 1 Normal status

When all of the battery voltages are in the range from VDLn to VCUn and the discharge current is lower than a specified

value (the VMP pin voltage is lower than VIOV1), the charging and discharging FETs are turned on.

1. 2 Overcharge status

When any one of the battery voltages becomes higher than VCUn and the state continues for tCU or longer, the COP

pin becomes high impedance and is pulled up to EB+ pin voltage by an external resistor, and the charging FET is

turned off to stop charging. The overcharge status is released when one of the following two conditions holds.

(a) All battery voltages become lower than VCUn + VHCn.

(b) VDD−VMP>VIOV1 (A load is connected, and discharging starts.)

1. 3 Overdischarge status

When any one of the battery voltages becomes low er than VDLn and the state continues for tDL or longer, the DOP pin

voltage becomes VDD level, and the discharging FET is turned off to stop discharging. This is the overdischarge

status.

1. 4 Power down status

After stopping discharging due to overdischarge status, the S-8243 enters power dow n status. In this status, almost

all circuits of the S-8243 are stopped to save current consumption. The current consumption becomes lower than

IPDN. In the power dow n status, the VMP pin is pulled dow n to VSS level by the internal RVSM resistor. In pow er dow n

status, output pin voltages are fixed at the following levels.

(a) COP High-Z (Charging FET is turned off)

(b) DOP VDD (Discharging FET is turned off)

(d) VBATOUT VSS (Battery voltage monitor amp circuit is off)

The power down status is released when the following condition holds.

(a) VMP>VIOV3 (A charger is connected, and charging starts.)

The overdischarging status is released when the following condition holds.

(a) All of the battery voltages are VDLn or higher, and the VMP pin voltage is VDD / 2 or higher. (A charger is

connected.)

1. 5 Overcurrent status

The S-8243 has three overcurrent detection levels (VIOV1, VIOV2 and VIOV3) and three overcurrent detection delay

times (tIOV1, tIOV2 and tIOV3) corresponding to each overcurrent detection levels. When the discharging current

becomes higher than a specified value (the voltage between VDD and VMP is greater than VIOV1) and the state

continues for tIOV1 or longer, the S-8243 enters the overcurrent status in which the DOP pin voltage becomes VDD

level to turn off the discharging FET to stop discharging, the COP pin becomes high impedance and is pulled up to

EB+ pin voltage by an external resistor to turn off the charging FET to stop charging, and the VMP pin is pulled up to

VDD voltage by the internal resistor RVDM. Operation of two other overcurrent detection levels (VIOV2 and V IOV3) and

overcurrent detection delay times (tIOV2 and tIOV3) is the same as that for VIOV1 and tIOV1.

The overcurrent status is released when the following condition holds.

(a) VMP> {VIOV3 / (1−VIOV3) × 3 / 5−2 / 5} × RVDM (A load is released, and the impedance between the EB− and

EB+ pin becomes higher. )

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 17

1. 6 0 V battery charging function

Regarding the charging of a self-discharged battery (0 V battery) the S-8243 has two functions from which one

should be selected.

(a) 0 V battery charging is allowed (0 V battery charging is available)

When a charger voltage is higher than V0CHA, 0 V battery can be charged.

(b) 0 V battery charging is forbidden (0 V battery charging is impossible)

When one of the battery voltages is lower than V0INH, 0 V battery can not be charged.

Caution When the VDD pin voltage is lower than minimum of VDSOP, the operation of S-8243 series is not

guaranteed.

1. 7 Delay time setting

Overcharge detection delay times (tCU1 to tCU4) are determined by the external capacitor at the CCT pin.

Overdischarge detection delay times (tDL1 to tDL4) and overcurrent detection delay time 1 (tIOV1) are determined by the

external capacitor at CDT pin. Overcurrent detection delay time 2,3 (tIOV2, tIOV3) are fixed internally.

S-8243AAC, S-8243AAD, S-8243BAE, S-8243BAF, S-8243BAH

min. typ. max.

tCU [s] = Delay factor ( 5 10 15 ) × CCT [μF]

tDL [ms] = Delay factor ( 500 1000 1500 ) × CDT [μF]

tIOV1 [ms] = Delay factor ( 50 100 150 ) × CDT [μF]

S-8243BAD min. typ. max.

tCU [s] = Delay factor ( 5 10 15 ) × CCT [μF]

tDL [ms] = Delay factor ( 555 1110 2220 ) × CDT [μF]

tIOV1 [ms] = Delay factor ( 33.1 66.2 132 ) × CDT [μF]

2. Voltage regulator circui t

Built-in voltage regulator can be used to drive a micro computer, etc. The voltage regulator supplies voltage of 3.3 V (3

mA maximum) and an external capacitor is needed.

Caution In the pow er down status the voltage regulator output is pulled dow n to the VSS level by an internal

resistor.

3. Battery monitor amp circuit

Battery monitor amp sends information of the batteries to a microcomputer. The battery monitor amp output is

controlled and selected by CTL3 and CTL4 pins to give the following two voltages.

(a) VBATn = GAMPn × VBATTERYn + VOFFn where GAMPn is the n-th voltage gain of the amp, VBATTERYn is the n-th

battery voltage, and VOFFn is the n-th offset voltage of the amp.

(b) N-th offset voltage VOFFn

Each battery voltage VBATTERYn (n = 1 to 4) is thus calculated by following equation.

VBATTERYn = (VBATn − VOFFn) / GAMPn (n = 1, 2, 3, 4)

After the state of CTL3 and CTL4 are changed, a time between 25 μs and 250 μs is needed for the battery monitor

amp to become stable.

Caution In the power down status the battery monitor amp output is the VSS level.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

4. CTL pins

The S-8243 has four control pins. The CTL1 and CTL2 pins are used to control the COP and DOP pin output voltages.

CTL1 takes precedence over CTL2. CT L2 takes precedence over the battery protection circuit. The CTL3 and CT L4

pins are used to control the VBATOUT pin output voltage.

Table 9 CTL1 and CTL2 Mode

Input Output

CTL1 pin CTL2 pin External discharging FET External charging FET

High High OFF OFF

High Open OFF OFF

High Low OFF OFF

Open High OFF OFF

Open Open OFF OFF

Open Low OFF OFF

Low High Normal*1 OFF*2

Low Open Normal*1 Normal*1

Low Low OFF Normal*1

*1. States are controlled by voltage detection circuit.

*2. Off state is brought after the overcharge detection delay time tCU.

Table 10 CTL3 and CTL4 Mode

Input Output

CTL3 pin CTL4 pin V BATOUT (A series) VBATOUT (B series)

High High V1 Offset V1 Offset

High Open V1 × 0.2 + V1 Offset V1 × 0.2 + V1 Offset

High Low Don’t use. V2 Offset

Open High Don’t use. V2 × 0.2 + V2 Offset

Open*1 Open*1 V2 Offset V3 Offset

Open Low V2 × 0.2 + V2 Offset V3 × 0.2 + V3 Offset

Low High V3 Offset V4 Offset

Low Open V3 × 0.2 + V3 Offset V4 × 0.2 + V4 Offset

Low Low Don’t use. Don’t use.

*1. CTL3 and CTL4 pins should be open when a microcomputer is not used.

Caution Please note unexpected behavior might occur when electrical potential difference between the

CTL pin (“L” lev el) aMSS is generated through the e xternal filter (RVSS and C VSS) as a result of input

voltage fluctuations.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 19

 Timing Charts

1. Overcharge detection, Over discharge detection

(n = 1 to 4)

VCUn

VDUn

VDLn

VCLn

Battery voltage

High-Z

VEB+

VSS

COP pin voltage

VIOV1

VSS

VMP pin

voltage

VDD

DOP pin voltage

VSS

Charger connected

Load connected

Status*2

Overcharge detection

delay time (tCU) Overdischarge detection

delay time (tDL)

VBAT

VSS

VBATOUT pin

voltage*1

VOUT

VSS

VREG pin voltage

VDD

High-Z

<1> <2> <1> <4> <1><3>

VIOV3

*1. State depends on CTL3 and CTL4 input levels. Refer to Figure 9.

*2. <1>: Normal status, <2>: Overcharge status, <3>: Overdischarge status, <4>: Power down status

Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger.

Figure 6

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

2. Overcurrent detection

Battery

voltage

DOP pin

voltage

High-Z

COP pin

voltage

High-Z

VMP pin

voltage V

IOV3

IOV2

IOV1

Load connected

RETURN

OUT

VBATOUT

pin voltage

VREG pin

voltage V

OUT

BAT

<1> <2>

<1> <1>

<2> <1> <2>

Status

Charger connected

Overcurrent detection

delay time 1 ( t

IOV1

) Overcurrent detection

delay time 3 ( t

IOV3

)

Overcurrent detection

delay time 2 ( t

IOV2

)

*1. VRETURN = VDD / 6 (typ.)

*2. State depends on CTL3 and CTL4 input levels. Refer to Figure 9.

*3. <1>: Normal status, <2>: Overcurrent status

Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger.

Figure 7

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 21

3. CTL1, CTL2 pin voltage

COP pin

Voltage

VSS

VOUT

VSS

VBATOUT

pin Voltage*2

VDD

VSS

VREG pin

Voltage VOUT

VBAT

VDD

DOP pin

Voltage

VSS

VDD VDD VDD VDD VDD VDD

Normal

VDD

High-Z

Normal

VDD

VSS

CTL1 pin

Voltage VOUT

OPEN

VDD

VSS

VOUT

OPEN

CTL2 pin

Voltage

High-Z Hi

h-Z High-Z High-Z Hi

h-Z High-Z

VEB+

*1. State depends on each battery voltage and the VMP pin voltage.

*2. State depends on CTL3 and CTL4 input levels. Refer to Figure 9.

Figure 8

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

4. CTL3, TL4 pin voltage

VOFF

COP pin

voltage

VSS

VOUT

VSS

VDD

VSS

VREG pin

voltage

VOUT

VBAT

VDD

DOP pin

voltage

VSS

(1) (1)

(1)

(1) (1) (1) (1) (1) (1) (1) (1) (1)

VDD

VSS

CTL3 pin

voltage

VOUT

OPEN

VDD

VSS

VOUT

OPEN

CTL4 pin

voltage

VOUT

VSS

S-8243A

(3-serial cell)

VBATOUT

pin voltage

VBAT

S-8243B

(4-serial cell)

VBATOUT

pin voltage

(1)

VOFF

V1 offset

0.2 V2 offset V2

0.2

V2 offset

V3 offset

0.2

V3 offset

V1 offset

0.2 V2 offset

0.2

V2 offset V3 offset V4

0.2

Don’t

use Don’t

use

Don’t

use

Don’t

use

V3 offset V4 offset

V4 offset

(1)

VEB+

*1. State depends on CTL1 and CTL2 and each battery voltage and the VMP pin voltage. Refer to Figure 6 to 8.

Figure 9

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 23

 Battery Protection IC Connection Example

1. S-8243A Series

RVSS

CTL1

RVMP

RDOP

EB-

EB+

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

CTL4 12

VREG 16

CCT 10

CTL2 14

CTL1 15

CTL3 13

CDT 9

CVC3

CVC2

S-8243A

CVSS

RVC3

RVC2

Microcomputer

CCDT

CCCT

CVREG

RVBAT

RCTL4

RCTL3

RCTL2

RCTL1

Charging FET Discharging FET

RCOP

Figure 10

Table 11 Constants for External Components

No. Part Typ. Range Unit

1 RVC2 1 0.51 to 1*1 kΩ

2 RVC3 1 0.51 to 1*1 kΩ

3 RVSS 10 2.2 to 10*1 Ω

4 RDOP 5.1 2 to 10 kΩ

5 RCOP 1 0.1 to 1 MΩ

6 RVMP 5.1 1 to 10 kΩ

7 RCTL1 1 1 to 100 kΩ

8 RCTL2 1 1 to 10 kΩ

9 RCTL3 1 1 to 10 kΩ

10 RCTL4 1 1 to 10 kΩ

11 RVBAT 0 0 to 100 kΩ

12 CVC2 0.047 0.047 to 0.22*1 μF

13 CVC3 0.047 0.047 to 0.22*1 μF

14 CVSS 4.7 2.2 to 10*1 μF

15 CCCT 0.1 More than 0.01 μF

16 CCDT 0.1 More than 0.02 μF

17 CVREG 4.7 0.68 to 10 μF

*1. Please set up a filter constant to be RVSS × CVSS ≥ 22 μF • Ω and to be

RVC2 × CVC2 = RVC3 × CVC3 = RVSS × CVSS.

Caution1. No resistance should be inserted in the power supply pin VDD.

2. The above constants are subject to change without prior notice.

3. It has not been confirmed whether the operation is normal or not in circuits other than the above

example of connection. In addition, the example of connection shown above and the constant will

not guarantee successful operation. Perform thorough evaluation using the actual application to set

the constant.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

2. S-8243B Series

RVSS

CTL1

Charging FET

Discharging FET

RVMP

RDOP

EB-

EB+

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

CTL4 12

VREG 16

CCT 10

CTL2 14

CTL1 15

CTL3 13

CDT 9

CVC3

CVC2

CVC1 S-8243B

CVSS

RVC3

RVC2

Microcomputer

CCDT

CCCT

CVREG

RVBAT

RCTL4

RCTL3

RCTL2

RCTL1

RVC1

RCOP

Figure 11

Table 12 Constants for External Components

No. Part Typ. Range Unit

1 RVC1 1 0.51 to 1*1 kΩ

2 RVC2 1 0.51 to 1*1 kΩ

3 RVC3 1 0.51 to 1*1 kΩ

4 RVSS 10 2.2 to 10*1 Ω

5 RDOP 5.1 2 to 10 kΩ

6 RCOP 1 0.1 to 1 MΩ

7 RVMP 5.1 1 to 10 kΩ

8 RCTL1 1 1 to 100 kΩ

9 RCTL2 1 1 to 10 kΩ

10 RCTL3 1 1 to 10 kΩ

11 RCTL4 1 1 to 10 kΩ

12 RVBAT 0 0 to 100 kΩ

13 CVC1 0.047 0.047 to 0.22*1 μF

14 CVC2 0.047 0.047 to 0.22*1 μF

15 CVC3 0.047 0.047 to 0.22*1 μF

16 CVSS 4.7 2.2 to 10*1 μF

17 CCCT 0.1 More than 0.01 μF

18 CCDT 0.1 More than 0.02 μF

19 CVREG 4.7 0.68 to 10 μF

*1. Please set up a filter constant to be RVSS × CVSS ≥ 22 μF • Ω and to be

RVC1 × CVC1 = RVC2 × CVC2 = RVC3 × CVC3 = RVSS × CVSS.

Caution1. No resistance should be inserted in the power supply pin VDD.

2. The above constants are subject to change without prior notice.

3. It has not been confirmed whether the operation is normal or not in circuits other than the above

example of connection. In addition, the example of connection shown above and the constant will

not guarantee successful operation. Perform thorough evaluation using the actual application to set

the constant.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 25

 Precautions

• Pay attention to the operating conditions for input/output voltage and load current so that the power loss in the IC does

not exceed the package power dissipation.

• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic

protection circuit.

• Seiko Instruments Inc. shall not be responsible for any patent infringement by products including the S-8243 series, the

method of using the S-8243 series in such products, the product specifications or the country of destination thereof.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

 The Example of Application Circuit

1. S-8243A Series

CTL1

−

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

CTL4 12

VREG 16

CCT 10

CTL2 14

CTL1 15

CTL3 13

CDT 9

S-8243A

VREG

SMBus

VREG

LED1

LED2

LED3

LED4

LED5

DISP

VOUT

ESCL

ESCD

SMBC

SMBD

HDQ

SR2

SR1

SRCVSS

RB1

THON

VCELL1

CTL4

CTL3

CTL2

REG

VCC

Bq2063

S-24C

GND

SDA

SCL

VCC

Figure 12

2. S-8243B Series

CTL1

EB+

8 VSS

7 VC3

6 VC2

5 VC1

3 COP

2 DOP

4 VMP

1 VDD

VBATOUT 11

CTL4 12

VREG 16

CCT 10

CTL2 14

CTL1 15

CTL3 13

CDT 9

S-8243B

VREG

SMBus

VREG

LED1

LED2

LED3

LED4

LED5

DISP

VOUT

ESCL

ESCD

SMBC

SMBD

HDQ

SR2

SR1

SRCVSS

RB1

THON

VCELL1

CTL4

CTL3

CTL2

REG

VCC

Bq2063

S-24C

GND

SDA

SCL

VCC

Figure 13

Caution The above connection example will not guarantee successful operation. Perform thorough evaluation

using the actual application.

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 27

 Characteristics (Typical Data)

1. Current consumption

100

120

0 4 8 12 16 20 24

VDD [V]

S-8243BAF IOPE − VDD

IOPE [μA]

100

120

−

20 0 20406080

Ta [°C]

S-8243BAF IOPE − Temp

IOPE [μA]

0.00

0.02

0.04

0.06

0.08

0.10

0 4 8 12 16 20 24

S-8243BAF

VDD [V]

IPDN − VDD

IPDN [μA]

0.00

0.02

0.04

0.06

0.08

0.10

S-8243BAF

020406080

−

20 Ta [°C]

IPDN − Temp

IPDN [μA]

2. Overcharge detection/release voltage, overdischarge detection/release voltage, overcurrent

detection voltages, and delay times

4.225

4.230

4.235

4.240

4.245

4.250

4.255

4.260

4.265

4.270

4.275

S-8243BAF

0 20 40 60 80

−40 −20 Ta [°C]

VCU

−

Temp

VCU [V]

3.95

3.97

3.99

4.01

4.03

4.05

S-8243BAF

020406080

−

20 Ta [°C]

VCL − Temp

VCL [V]

2.300

2.325

2.350

2.375

2.400

2.425

2.450

2.475

2.500

S-8243BAF

0 20 40 60 80

−40 −20 Ta [°C]

VDU − Temp

VDU [V]

2.32

2.34

2.36

2.38

2.40

2.42

2.44

2.46

2.48

S-8243BAF

0 20 40 60 80

−40 −20 Ta [°C]

VDL − Temp

VDL [V]

0.175

0.180

0.185

0.190

0.195

0.200

0.205

0.210

0.215

0.220

0.225

10 12 14 16

S-8243BAF

VDD [V]

VIOV1 − VDD

VIOV1 [V]

0.175

0.180

0.185

0.190

0.195

0.200

0.205

0.210

0.215

0.220

0.225

S-8243BAF

0 20 40 60 80

−40 −20 Ta [°C]

VIOV1 − Temp

VIOV1 [V]

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

−0.60

−0.55

−0.50

−0.45

−0.40

10 12 14 16

S-8243BAF

VDD [V]

VIOV2 − VDD

VIOV2 [V]

VDD Reference

−0.60

−0.55

−0.50

−0.45

−0.40

−

20 020406080

Ta [°C]

VIOV2 [V]

S-8243BAF VIOV2 − Temp

VDD Reference

0.425

0.450

0.475

0.500

0.525

0.550

0.575

10 12 14 16

S-8243BAF

VDD [V]

VIOV3 − VDD

VIOV3 / VDD

0.425

0.450

0.475

0.500

0.525

0.550

0.575

Ta [°C]

S-8243BAF VIOV3 − Temp

VIOV3 / VDD

−40 −20 0 20 40 60 80

0 0.2 0.4 0.6 0.8 1.0

S-8243BAF

CCT [μF]

tCU − CCT

tCU [s]

0.0

0.5

1.0

1.5

2.0

2.5

−40 −20 0 20 40 60 80

Ta [°C]

tCU [s]

S-8243BAF tCU − Temp

CCT = 0.1 μF

500

1000

1500

0 0.2 0.4 0.6 0.8 1.0

S-8243BAF

CDT [μF]

tDL − CDT

tDL [ms]

100

150

200

250

−40 −20 020406080

Ta [°C]

tDL [ms]

S-8243BAF tDL − Temp

CDT = 0.1 μF

100

150

0 0.2 0.4 0.6 0.8 1.0

S-8243BAF

CDT [μF]

tIOV1 − CDT

tIOV1 [ms]

−40 −20 0 20 40 60 80

Ta [°C]

tIOV1 [ms]

S-8243BAF tIOV1 − Temp

CDT = 0.1 μF

1.5

2.0

2.5

3.0

3.5

4.0

−40 −20 020406080

Ta [°C]

tIOV2 [ms]

S-8243BAF

tIOV2 − Temp

100

200

300

400

500

600

−40 −20 0 20 40 60 80

Ta [°C]

tIOV3 [μs]

S-8243BAF

tIOV3 − Temp

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

Rev.3.0_00 S-8243A/B Series

Seiko Instruments Inc. 29

3. COP / DOP pin current

0.00

0.02

0.04

0.06

0.08

0.10

0 4 8 12 16 20 24

S-8243BAF

VCOP [V]

ICOH − VCOP

ICOH [μA]

0 3.5 7.0 10.5 14.0

S-8243BAF

VCOP [V]

ICOL − VCOP

ICOL [mA]

−5

−4

−3

−2

−1

0 1.8 3.6 5.4 7.2

S-8243BAF

VDOP [V]

IDOH − VDOP

IDOH [mA]

0 3.5 7.0 10.5 14.0

S-8243BAF

VDOP [V]

IDOL − VDOP

IDOL [mA]

4. Voltage regulator

3.0

3.1

3.2

3.3

3.4

3.5

3.6

−40 −20 0 20 40 60 80

Ta [°C]

VOUT [V]

S-8243BAF VOUT − Temp

2.3

2.8

3.3

3.8

04812162024

IOUT = 5 μA

100 μA

3 mA

10 mA

S-8243BAF

VDD [V]

VOUT − VDD

VOUT [V]

VDD = 0→24 V, Ta = 25° C

0.0

1.0

2.0

3.0

4.0

0 20 40 60 80 100

VDD = 6 V

14 V

18 V 10 V

IOUT [mA]

VOUT − IOUT

VOUT [V]

V1 = V2 = V3 = V4 = VBAT

S-8243BAF

0.0

1.0

2.0

3.0

4.0

0 20 40 60 80 100

85°C

Ta = −40°C

25°C

IOUT [mA]

VOUT − IOUT

VOUT [V]

S-8243BAF

BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK

S-8243A/B Series Rev.3.0_00

Seiko Instruments Inc.

5. Battery monitor amp

150

155

160

165

170

175

180

1 2 3 4 5

VOFF3

S-8243BAF

VBAT [V]

VOFF − VBAT

VOFF [mV]

V1 = V2 = V3 = V4 = VBAT

VOFF4

VOFF2 VOFF1

150

155

160

165

170

175

180

−40 −20 020406080

Ta [°C]

VOFF [mV]

S-8243BAF VOFF − Temp

VOFF3 VOFF4

VOFF2 VOFF1

0.198

0.199

0.200

0.201

0.202

1 2 3 4 5

GAMP

S-8243BAF

GAMP4

GAMP3

GAMP2 GAMP1

VBAT [V]

GAMP − VBAT

V1 = V2 = V3 = V4 = VBAT

0.198

0.199

0.200

0.201

0.202

−40 −20 0 20 40 60 80

Ta [°C]

GAMP

GAMP − Temp

S-8243BAF

GAMP4

GAMP3

GAMP2 GAMP1

0.17±0.05

5.1±0.2

0.22±0.08

0.65

No.

TITLE

SCALE

UNIT mm

Seiko Instruments Inc.

No. FT016-A-P-SD-1.1

FT016-A-P-SD-1.1

TSSOP16-A-PKG Dimensions

4.0±0.1

2.0±0.1

ø1.5+0.1

-0

ø1.6±0.1

8.0±0.1

4.2±0.2

6.5 +0.4

-0.2

0.3±0.05

1.5±0.1

(7.2)

No.

TITLE

SCALE

UNIT mm

Seiko Instruments Inc.

No. FT016-A-C-SD-1.1

FT016-A-C-SD-1.1

TSSOP16-A-Carrier Tape

Feed direction

No.

TITLE

SCALE

UNIT mm

17.4±1.0

Seiko Instruments Inc.

No. FT016-A-R-SD-2.0

FT016-A-R-SD-2.0

TSSOP16-A- Reel

QTY. 2,000

Enlarged drawing in the central part

2±0.5

ø13±0.2

ø21±0.8

21.4±1.0

17.4 +2.0

-1.5

No.

TITLE

SCALE

UNIT mm

17.4±1.0

Seiko Instruments Inc.

No. FT016-A-R-S1-1.0

FT016-A-R-S1-1.0

TSSOP16-A- Reel

QTY. 4,000

Enlarged drawing in the central part

2±0.5

ø13±0.2

ø21±0.8

21.4±1.0

17.4 +2.0

-1.5

www.sii-ic.com

• The information described herein is subject to change without notice.

• Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein

whose related industrial properties, patents, or other rights belong to third parties. The application circuit

examples explain typical applications of the products, and do not guarantee the success of any specific

mass-production design.

• When the products described herein are regulated products subject to the Wassenaar Arrangement or other

agreements, they may not be exported without authorization from the approp riate governmental authority.

• Use of the information described herein for other purposes and/or reproduction or copying without the

express permissi on of Seiko Instruments Inc. is strictly prohibited.

• The products described herein cannot be used as part of any device or equipment affecting the human

body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus

installed in airplanes and other vehicle s, without prior written permission of Seiko Instruments Inc.

• The products described herein are not designed to be radiation -p roof.

• Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the

failure or malfunction of semiconductor products may occur. The user of these products should therefore

give thorough consideration to safety design, including redundancy, fire-prevention measures, and

malfunction prevention, to prevent any accidents, fires, or comm unity damage that may ensue.