Rev: 1.13 5/2003 1/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
190 MHz–100 MHz
3.3 V VDD
3.3 V and 2.5 V I/O
TQFP, BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipelined
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC standard 100-lead TQFP or 119-Bump BGA package
Functional Description
Applications
The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS84018/32/36A is
available in a JEDEC standard 100-lead TQFP or 119-Bump
BGA package.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV
. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (pin 14 in the TQFP and
bump 5R in the BGA). Holding the FT mode pin/bump low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipelined mode, activating the rising-edge-triggered
Data Output Register.
SCD Pipelined Reads
The GS84018/32/36A is an SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS84018/32/36A operates on a 3.3 V power supply and
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (VDDQ) pins are used to de-couple output noise
from the internal circuit.
–190 –180 –166 –150 –100
Pipeline
3-1-1-1
tCycle
tKQ
IDD
5.3 ns
3.0 ns
200 mA
5.5 ns
3.0 ns
185 mA
6.0 ns
3.5 ns
170 mA
6.6 ns
3.8 ns
155 mA
10 ns
4.5 ns
105 mA
Flow
Through
2-1-1-1
tKQ
tCycle
IDD
7.5 ns
8.5 ns
125 mA
8 ns
9 ns
115 mA
8.5 ns
10 ns
105 mA
10 ns
12 ns
100 mA
12 ns
15 ns
80 mA
Rev: 1.13 5/2003 2/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
GS84018A 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQB
DQB
VSS
VDDQ
DQB
DQB
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
VSS
VDDQ
VDDQ
VSS
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
VSS
VDDQ
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
A
E1
E2
NC
NC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADV
A
A
A
256K x 18
Top View
DQPA
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC 10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 1.13 5/2003 3/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
GS84032A 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC
DQC
VSS
VDDQ
DQC
DQC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
VSS
VDDQ
VDDQ
VSS
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
VSS
VDDQ
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
A
E1
E2
BD
BC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADV
A
A
A
128K x 32
Top View
DQB
NC
DQB
DQB
DQB
DQA
DQA
DQA
DQA
NC
DQC
DQC
DQC
DQD
DQD
DQD
NC
DQC
NC 10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 1.13 5/2003 4/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
GS84036A 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC
DQC
VSS
VDDQ
DQC
DQC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
VSS
VDDQ
VDDQ
VSS
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
VSS
VDDQ
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
A
E1
E2
BD
BC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADV
A
A
A
128K x 36
Top View
DQB
DQPB
DQB
DQB
DQB
DQA
DQA
DQA
DQA
DQA
DQC
DQC
DQC
DQD
DQD
DQD
DQPD
DQC
DQPC
10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 1.13 5/2003 5/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
TQFP Pin Description
Symbol Type Description
A0, A1I Address field LSBs and Address Counter preset Inputs
A I Address Inputs
DQA
DQB
DQC
DQD
I/O Data Input and Output pins
BW I Byte Write—Writes all enabled bytes; active low
BA, BBI Byte Write Enable for DQA, DQB Data I/’s; active low
BC, BDI Byte Write Enable for DQC, DQD Data I/Os; active low
CK I Clock Input Signal; active high
GW I Global Write Enable—Writes all bytes; active low
E1, E3I Chip Enable; active low
E2I Chip Enable; active high
GI Output Enable; active low
ADV I Burst address counter advance enable; active low
ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low
ZZ I Sleep Mode control; active high
FT I Flow Through or Pipeline mode; active low
LBO I Linear Burst Order mode; active low
VDD I Core power supply
VSS I I/O and Core Ground
VDDQ I Output driver power supply
NC - No Connect
Rev: 1.13 5/2003 6/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
GS84018A Pad Out
119-Bump BGA—Top View
1234567
AVDDQ A A ADSP AAV
DDQ
BNC E2AADSCAE
3NC
CNC A A VDD AANC
DDQBNC VSS NC VSS DQPANC
ENC DQBVSS E1VSS NC DQA
FVDDQ NC VSS G VSS DQAVDDQ
GNC DQBBBADV NC NC DQA
HDQBNCVSS GW VSS DQANC
JVDDQ VDD NC VDD NC VDD VDDQ
KNC DQBVSS CK VSS NC DQA
LDQBNC NC NC BADQANC
MVDDQ DQBVSS BW VSS NC VDDQ
NDQBNC VSS A1VSS DQANC
PNC DQPBVSS A0VSS NC DQA
RNC A LBO VDD FT ANC
TNC A A NC A A ZZ
UVDDQ NC NC NC NC NC VDDQ
Rev: 1.13 5/2003 7/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
GS84032A Pad Out
119-Bump BGA—Top View
1234567
AVDDQ A A ADSP AAV
DDQ
BNC E2AADSCAE
3NC
CNC A A VDD AANC
DDQCNC VSS NC VSS NC DQB
EDQCDQCVSS E1VSS DQBDQB
FVDDQ DQCVSS G VSS DQBVDDQ
GDQCDQCBCADV BBDQBDQB
HDQCDQCVSS GW VSS DQBDQB
JVDDQ VDD NC VDD NC VDD VDDQ
KDQDDQDVSS CK VSS DQADQA
LDQDDQDBDNC BADQADQA
MVDDQ DQDVSS BW VSS DQAVDDQ
NDQDDQDVSS A1VSS DQADQA
PDQDNC VSS A0VSS NC DQA
RNC A LBO VDD FT ANC
TNC NC A A A NC ZZ
UVDDQ NC NC NC NC NC VDDQ
Rev: 1.13 5/2003 8/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
GS84036A Pad Out
119-Bump BGA—Top View
1234567
AVDDQ A A ADSP AAV
DDQ
BNC E2AADSCAE
3NC
CNC A A VDD AANC
DDQCDQPCVSS NC VSS DQPBDQB
EDQCDQCVSS E1VSS DQBDQB
FVDDQ DQCVSS G VSS DQBVDDQ
GDQC2 DQCBCADV BBDQBDQB2
HDQCDQCVSS GW VSS DQBDQB
JVDDQ VDD NC VDD NC VDD VDDQ
KDQDDQDVSS CK VSS DQADQA
LDQDDQDBDNC BADQADQA
MVDDQ DQDVSS BW VSS DQAVDDQ
NDQDDQDVSS A1VSS DQADQA
PDQDDQPDVSS A0VSS DQPADQA
RNC A LBO VDD FT ANC
TNC NC A A A NC ZZ
UVDDQ NC NC NC NC NC VDDQ
Rev: 1.13 5/2003 9/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
BGA Pin Description
Symbol Type Description
A0, A1I Address field LSBs and Address Counter Preset Inputs
A I Address Inputs
DQA
DQB
DQC
DQD
I/O Data Input and Output pins
BA, BB, BC, BDI Byte Write Enable for DQA, DQB, DQC, DQD I/O’s; active low
CK I Clock Input Signal; active high
BW I Byte Write—Writes all enabled bytes; active low
GW I Global Write Enable—Writes all bytes; active low
E1, E3I Chip Enable; active low
E2I Chip Enable; active high
GI Output Enable; active low
ADV I Burst address counter advance enable; active low
ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low
ZZ I Sleep Mode control; active high
FT I Flow Through or Pipeline mode; active low
LBO I Linear Burst Order mode; active low
VDD I Core power supply
VSS I I/O and Core Ground
VDDQ I Output driver power supply
NC - No Connect
Rev: 1.13 5/2003 10/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
GS84018/32/36A Block Diagram
A1
A0 A0
A1
D0
D1 Q1
Q0
Counter
Load
DQ
DQ
Register
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
E1
G
ZZ Power Down
Control
Memory
Array
36 36
4
A
QD
E3
E2
DQx0–DQx9
Note: Only x36 version shown for simplicity.
1
FT
Rev: 1.13 5/2003 11/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Byte Write Truth Table
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Mode Pin Functions
Mode Name Pin
Name State Function
Burst Order Control LBO L Linear Burst
H or NC Interleaved Burst
Output Register Control FT L Flow Through
H or NC Pipeline
Power Down Control ZZ L or NC Active
H Standby, IDD = ISB
Function GW BW BABBBCBDNotes
Read H H X X X X 1
Read HLHHHH1
Write byte AHL LHHH2, 3
Write byte BHLHLHH2, 3
Write byte CH L H H L H 2, 3, 4
Write byte DHLHHHL2, 3, 4
Write all bytesHLLLLL2, 3, 4
Write all bytesLXXXXX
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Rev: 1.13 5/2003 12/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
Synchronous Truth Table
Operation Address
Used
State
Diagram
Key5
E1E2ADSP ADSC ADV W3DQ4
Deselect Cycle, Power Down None X H X X L X X High-Z
Deselect Cycle, Power Down None X L F L X X X High-Z
Deselect Cycle, Power Down None X L F H L X X High-Z
Read Cycle, Begin Burst External R L T L X X X Q
Read Cycle, Begin Burst External R L T H L X F Q
Write Cycle, Begin Burst External W L T H L X T D
Read Cycle, Continue Burst Next CR X X H H L F Q
Read Cycle, Continue Burst Next CR H X X H L F Q
Write Cycle, Continue Burst Next CW X X H H L T D
Write Cycle, Continue Burst Next CW H X X H L T D
Read Cycle, Suspend Burst Current X X H H H F Q
Read Cycle, Suspend Burst Current H X X H H F Q
Write Cycle, Suspend Burst Current X X H H H T D
Write Cycle, Suspend Burst Current H X X H H T D
Notes:
1. X = Don’t Care, H = High, L = Low.
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.13 5/2003 13/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
First Write First Read
Burst Write Burst Read
Deselect
R
W
CRCW
X
X
WR
R
WR
XX
X
Simple Synchronous OperationSimple Burst Synchronous Operation
CR
R
CW CR
CR
Simplified State Diagram
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
Rev: 1.13 5/2003 14/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
First Write First Read
Burst Write Burst Read
Deselect
R
W
CRCW
X
X
WR
R
WR
X
X
X
CR
R
CW CR
CR
W
CW
W
CW
Simplified State Diagram with G
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.13 5/2003 15/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Rec-
ommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of
time, may affect reliability of this component.
Note:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ VDDQ ≤ 2.375 V
(i.e., 2.5 V I/O) and 3.6 V ≤ VDDQ ≤ 3.135 V (i.e., 3.3 V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < VDD+2 V with a pulse width not to exceed 20% tKC.
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 4.6 V
VDDQ Voltage in VDDQ Pins –0.5 to VDD V
VCK Voltage on Clock Input Pin –0.5 to 6 V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V
IIN Input Current on Any Pin +/–20 mA
IOUT Output Current on Any I/O Pin +/–20 mA
PDPackage Power Dissipation 1.5 W
TSTG Storage Temperature –55 to 125 oC
TBIAS Temperature Under Bias –55 to 125 oC
Recommended Operating Conditions
Parameter Symbol Min. Typ. Max. Unit Notes
Supply Voltage VDD 3.135 3.3 3.6 V
I/O Supply Voltage VDDQ 2.375 2.5 VDD V1
Input High Voltage VIH 1.7 — VDD +0.3 V2
Input Low Voltage VIL –0.3 — 0.8 V 2
Ambient Temperature (Commercial Range Versions) TA02570°C3
Ambient Temperature (Industrial Range Versions) TA–40 25 85 °C3
Rev: 1.13 5/2003 16/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
Note: This parameter is sample tested.
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
4. For x18 configuration, consult factory.
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter Symbol Test conditions Typ. Max. Unit
Control Input Capacitance CIVDD = 3.3 V 34pF
Input Capacitance CIN VIN = 0 V 45pF
Output Capacitance COUT VOUT = 0 V 67pF
Package Thermal Characteristics
Rating Layer Board Symbol TQFP Max BGA Max Unit Notes
Junction to Ambient (at 200 lfm) single RΘJA 40 38 °C/W 1,2,4
Junction to Ambient (at 200 lfm) four RΘJA 24 21 °C/W 1,2,4
Junction to Case (TOP) RΘJC 95°C/W 3,4
20% tKC
VSS-2.0V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKC
VDD+-2.0V
50%
VDD
VIL
Rev: 1.13 5/2003 17/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ.
4. Device is deselected as defined by the Truth Table.
AC Test Conditions
Parameter Conditions
Input high level 2.3 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level 1.25 V
Output reference level 1.25 V
Output load Fig. 1& 2
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –1 uA 1uA
ZZ Input Current IINZZ
VDD ≥ VIN ≥ VIH
0V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
300 uA
Mode Pin Input Current IINM
VDD ≥ VIN ≥ VIL
0V ≤ VIN ≤ VIL
–300 uA
–1uA
1 uA
1 uA
Output Leakage Current IOL Output Disable,
VOUT = 0 to VDD –1 uA 1 uA
Output High Voltage VOH IOH = –4 mA, VDDQ = 2.375 V 1.7 V
Output High Voltage VOH IOH = –4 mA, VDDQ = 3.135 V 2.4 V
Output Low Voltage VOL IOL = 4 mA 0.4 V
DQ
VT = 1.25 V
50Ω30pF*DQ
2.5 V
Output Load 1 Output Load 2
225Ω
225Ω
5pF*
* Distributed Test Jig Capacitance
Rev: 1.13 5/2003 18/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
Operating Currents
Parameter Test Conditions Symbol
-190 -180 -166 -150 -100
Unit
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Operating
Current
Device Selected;
All other
inputs
≥VIH or ≤ VIL
Output open
IDD
Pipeline 200 210 185 195 170 180 155 165 105 115 mA
IDD
Flow
Through
125 135 115 125 105 115 100 110 80 90 mA
Standby
Current
ZZ ≥ VDD –
0.2 V
ISB
Pipeline 20 30 20 30 20 30 20 30 20 30 mA
ISB
Flow
Through
20 30 20 30 20 30 20 30 20 30 mA
Deselect
Current
Device
Deselected;
All other
inputs
≥ VIH or ≤ VIL
IDD
Pipeline 35 45 35 45 30 40 30 40 20 30 mA
IDD
Flow
Through
20 30 20 30 20 30 15 25 15 25 mA
Rev: 1.13 5/2003 19/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
AC Electrical Characteristics
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Parameter Symbol -190 -180 -166 -150 -100 Unit
Min Max Min Max Min Max Min Max Min Max
Pipeline
Clock Cycle Time tKC 5.3 — 5.5 — 6.0 — 6.7 — 10 — ns
Clock to Output Valid tKQ — 3.0 — 3.0 — 3.5 — 3.8 — 4.5 ns
Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
Clock to Output in Low-Z tLZ11.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
Flow
Through
Clock Cycle Time tKC 8.5 — 9.0 — 10.0 — 12.0 — 15.0 — ns
Clock to Output Valid tKQ — 7.5 — 8.0 — 8.5 — 10.0 — 12.0 ns
Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns
Clock to Output in Low-Z tLZ13.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns
Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.3 — ns
Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
Clock to Output in High-Z tHZ11.5 3.0 1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns
G to Output Valid tOE — 3.0 — 3.2 — 3.5 — 3.8 — 5 ns
G to output in Low-Z tOLZ10—0—0—0—0—ns
G to output in High-Z tOHZ1— 3.0 — 3.2 — 3.5 — 3.8 — 5 ns
Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 2.0 — ns
Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
ZZ setup time tZZS25—5—5—5—5—ns
ZZ hold time tZZH21—1—1—1—1—ns
ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — ns
Rev: 1.13 5/2003 20/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
Pipeline Mode Timing
Begin Read A Cont Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect
tHZ
tKQXtKQ
tLZtH
tS
tOHZtOE
tH
tS
tH
tS
tH
tS
tH
tS
tHtS
tS
tH
tS
tHtS
tH
tS
Burst ReadBurst ReadSingle Write
tKCtKC
tKLtKL
tKH
Single WriteSingle Read
tKH
Single Read
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3)
ABC
Deselected with E1
E1 masks ADSP
E2 and E3 only sampled with ADSP and ADSC
ADSC initiated read
CK
ADSP
ADSC
ADV
A0–An
GW
BW
Ba–Bd
E1
E2
E3
G
DQa–DQd
Rev: 1.13 5/2003 21/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
Flow Through Mode Timing
Begin Read A Cont Cont1 Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont2 Deselect
tHZ
tKQX
tKQ
tLZ
tH
tS
tOHZtOE
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKCtKC
tKLtKL
tKHtKH
ABC
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
E2 and E3 only sampled with ADSC
ADSC initiated read
Deselected with E1
Fixed High
CK
ADSP
ADSC
ADV
A0–An
GW
BW
Ba–Bd
E1
E2
E3
G
DQa–DQd
Rev: 1.13 5/2003 22/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
CK
ADSP
ADSC
tH tKH tKL
tKC
tS
ZZ tZZR
tZZH
tZZS
~
~
~
~~
~~
~~
~~
~
Snooze
Sleep Mode Timing Diagram
Rev: 1.13 5/2003 23/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
GS84018/32/36A Output Driver Characteristics
-80
-60
-40
-20
0
20
40
60
-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
I Out (mA)
3.6V PD LD 3.3V PD LD 3.1V PD LD 3.1V PU LD 3.3V PU LD 3.6V PU LD
Pull Up Drivers
Pull Down Drivers
VDDQ
VOut
I Out
VSS
Rev: 1.13 5/2003 24/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
TQFP Package Drawing
D1
D
E1
E
Pin 1
b
e
c
L
L1
A2
A1
Y
θ
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Symbol Description Min. Nom. Max
A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45
b Lead Width 0.20 0.30 0.40
c Lead Thickness 0.09 0.20
D Terminal Dimension 21.9 22.0 22.1
D1 Package Body 19.9 20.0 20.1
E Terminal Dimension 15.9 16.0 16.1
E1 Package Body 13.9 14.0 14.1
e Lead Pitch 0.65
L Foot Length 0.45 0.60 0.75
L1 Lead Length 1.00
Y Coplanarity 0.10
θLead Angle 0°7°
Rev: 1.13 5/2003 25/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
Package Dimensions—119-Pin BGA
N
P
A
B
Pin 1
Corner
K
E
F
CT
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
G
SD
1234567
Package Dimensions—119-Pin BGA
Unit: mm
Symbol Description Min. Nom. Max
A Width 13.8 14.0 14.2
B Length 21.8 22.0 22.2
C Package Height (including ball) - 2.40
D Ball Size 0.60 0.75 0.90
E Ball Height 0.50 0.60 0.70
F Package Height (excluding balls) 1.46 1.70
G Width between Balls 1.27
K Package Height above board 0.80 0.90 1.00
N Cut-out Package Width 12.00
P Foot Length 19.50
R Width of package between balls 7.62
S Length of package between balls 20.32
T Variance of Ball Height 0.15
Bottom View
R
Top View
Side View
Rev: 1.13 5/2003 26/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
Ordering Information for GSI Synchronous Burst RAMS
Org Part Number1Type Package Speed2
(MHz/ns) TA3Status
256K x 18 GS84018AT-190 Pipeline/Flow Through TQFP 190/7.5 C
256K x 18 GS84018AT-180 Pipeline/Flow Through TQFP 180/8 C
256K x 18 GS84018AT-166 Pipeline/Flow Through TQFP 166/8.5 C
256K x 18 GS84018AT-150 Pipeline/Flow Through TQFP 150/10 C
256K x 18 GS84018AT-100 Pipeline/Flow Through TQFP 100/12 C
128K x 32 GS84032AT-190 Pipeline/Flow Through TQFP 190/7.5 C
128K x 32 GS84032AT-180 Pipeline/Flow Through TQFP 180/8 C
128K x 32 GS84032AT-166 Pipeline/Flow Through TQFP 166/8.5 C
128K x 32 GS84032AT-150 Pipeline/Flow Through TQFP 150/10 C
128K x 32 GS84032AT-100 Pipeline/Flow Through TQFP 100/12 C
128K x 36 GS84036AT-190 Pipeline/Flow Through TQFP 190/7.5 C
128K x 36 GS84036AT-180 Pipeline/Flow Through TQFP 180/8 C
128K x 36 GS84036AT-166 Pipeline/Flow Through TQFP 166/8.5 C
128K x 36 GS84036AT-150 Pipeline/Flow Through TQFP 150/10 C
128K x 36 GS84036AT-100 Pipeline/Flow Through TQFP 100/12 C
256K x 18 GS84018AT-190I Pipeline/Flow Through TQFP 190/7.5 I
256K x 18 GS84018AT-180I Pipeline/Flow Through TQFP 180/8 I
256K x 18 GS84018AT-166I Pipeline/Flow Through TQFP 166/8.5 I
256K x 18 GS84018AT-150I Pipeline/Flow Through TQFP 150/10 C
256K x 18 GS84018AT-100I Pipeline/Flow Through TQFP 100/12 C
128K x 32 GS84032AT-190I Pipeline/Flow Through TQFP 190/7.5 I
128K x 32 GS84032AT-180I Pipeline/Flow Through TQFP 180/8 I
128K x 32 GS84032AT-166I Pipeline/Flow Through TQFP 166/8.5 I
128K x 32 GS84032AT-150I Pipeline/Flow Through TQFP 150/10 C
128K x 32 GS84032AT-100I Pipeline/Flow Through TQFP 100/12 C
128K x 36 GS84036AT-190I Pipeline/Flow Through TQFP 190/7.5 I
128K x 36 GS84036AT-180I Pipeline/Flow Through TQFP 180/8 I
128K x 36 GS84036AT-166I Pipeline/Flow Through TQFP 166/8.5 I
128K x 36 GS84036AT-150I Pipeline/Flow Through TQFP 150/10 C
128K x 36 GS84036AT-100I Pipeline/Flow Through TQFP 100/12 C
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AT-8T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode.
Each device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.13 5/2003 27/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
256K x 18 GS84018AB-190 Pipeline/Flow Through BGA 190/7.5 C
256K x 18 GS84018AB-180 Pipeline/Flow Through BGA 180/8 C
256K x 18 GS84018AB-166 Pipeline/Flow Through BGA 166/8.5 C
256K x 18 GS84018AB-150 Pipeline/Flow Through BGA 150/10 C
256K x 18 GS84018AB-100 Pipeline/Flow Through BGA 100/12 C
128K x 32 GS84032AB-190 Pipeline/Flow Through BGA 190/7.5 C
128K x 32 GS84032AB-180 Pipeline/Flow Through BGA 180/8 C
128K x 32 GS84032AB-166 Pipeline/Flow Through BGA 166/8.5 C
128K x 32 GS84032AB-150 Pipeline/Flow Through BGA 150/10 C
128K x 32 GS84032AB-100 Pipeline/Flow Through BGA 100/12 C
128K x 36 GS84036AB-190 Pipeline/Flow Through BGA 190/7.5 C
128K x 36 GS84036AB-180 Pipeline/Flow Through BGA 180/8 C
128K x 36 GS84036AB-166 Pipeline/Flow Through BGA 166/8.5 C
128K x 36 GS84036AB-150 Pipeline/Flow Through BGA 150/10 C
128K x 36 GS84036AB-100 Pipeline/Flow Through BGA 100/12 C
256K x 18 GS84018AB-190I Pipeline/Flow Through BGA 190/7.5 I
256K x 18 GS84018AB-180I Pipeline/Flow Through BGA 180/8 I
256K x 18 GS84018AB-166I Pipeline/Flow Through BGA 166/8.5 I
256K x 18 GS84018AB-150I Pipeline/Flow Through BGA 150/10 C
256K x 18 GS84018AB-100I Pipeline/Flow Through BGA 100/12 C
128K x 32 GS84032AB-190I Pipeline/Flow Through BGA 190/7.5 I
128K x 32 GS84032AB-180I Pipeline/Flow Through BGA 180/8 I
128K x 32 GS84032AB-166I Pipeline/Flow Through BGA 166/8.5 I
128K x 32 GS84032AB-150I Pipeline/Flow Through BGA 150/10 C
128K x 32 GS84032AB-100I Pipeline/Flow Through BGA 100/12 C
128K x 36 GS84036AB-190I Pipeline/Flow Through BGA 190/7.5 I
128K x 36 GS84036AB-180I Pipeline/Flow Through BGA 180/8 I
128K x 36 GS84036AB-166I Pipeline/Flow Through BGA 166/8.5 I
128K x 36 GS84036AB-150I Pipeline/Flow Through BGA 150/10 C
128K x 36 GS84036AB-100I Pipeline/Flow Through BGA 100/12 C
Org Part Number1Type Package Speed2
(MHz/ns) TA3Status
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AT-8T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode.
Each device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.13 5/2003 28/28 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS84018/32/36AT/B-190/180/166/150/100
Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content Page /Revisions;Reason
GS84018/32/36 Rev 1.02c 5/1999;
GS84018/32/36A 1.00First Release
8/1999D
Format/Typos • Document/Continued changing to new format.
Content • First Datasheet for this part.
GS84018/32/36A1.00 8/
1999;GS84018/32/36A1.01 9/
1999E
Format/Typos
• Took “E” out of 840HE...in Core and Interface Voltages.
• Pin outs/New small caps format.
• Timing Diagrams/New format.
• Block Diagrams/New small caps format.
Content
• Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to
DQB3.
• Pin Description/Rearranged Address Inputs to match order on
TQFP Pinout.
• TQFP Package Diagram/Corrected Dimension D Max from
20.1 to 22.1.
GS84018/32/36A1.01 9/
1999E;GS84018/32/36A1.02
• Fixed Ordering information and speed bins.
• Took out Fine Pitch BGA Package. Package change in
progress.
GS84018/32/36A1.0210-11/
1999;GS84018/32/36A1.032/
2000G
Format
• New GSI Logo
• Took “Pin” out of heading for consistency.
GS84018/32/36A1.032/2000G;
84018A_r1_04 Content • Corrected all part order numbers
84018A_r1_04; 84018A_r1_05 Content • Updated pin descriptions table
84018A_r1_05; 84018A_r1_06 Content • Updated BGA pin description table to meet JEDEC standard
84018A_r1_06; 84018A_r1_07 Content/Format
• Added “non-A” speed bins to Operating Currents table, AC
Electrical Characteristics table, and Ordering Information
table
• Updated format to fit Technical Documentation standards
84018A_r1_07; 84018A_r1_08 Content/Format
• Updated font
• Corrected IDD for 150 MHz and 100 MHz on page 1 and page
18
84018A_r1_08; 84018A_r1_09 Content
• Updated table on page 1
• Updated Operating Currents table on page 18
• Updated Electrical Characteristics table on page 19
84018A_r1_09, 84018A_r1_10 Content • Reduced IDD by 20 mA in table on page 1 and Operating
Currents table
84018A_r1_10; 84018A_r1_11 Content • Corrected incorrect package type in ordering information table
84018A_r1_11; 84018A_r1_12 Content • Removed 200 MHz references from entire datasheet
84018A_r1_12; 84018A_r1_13 Content • Updated format
• Added 190 MHz speed bin
